A voltage stabilizing circuit

Abstract

The embodiment of the present application provides a kind of voltage stabilizing circuit.The voltage stabilizing circuit includes: error operational amplifier, power tube, resistance network and feedback regulating circuit;Power tube is used to receive power supply voltage, and generates output voltage, and the output voltage is output by the resistance network;The error operational amplifier is used to receive reference voltage and the output voltage, and generates the first control signal of control terminal of the power tube;The feedback regulating circuit is used to receive the output voltage, and generates the second control signal of control terminal of the power tube;When the output voltage changes, the second control signal changes ahead of the first control signal, and the second control signal makes the current flowing into the control terminal of the power tube change to quickly adjust the output voltage to preset voltage value.The technical scheme provided by the embodiment of the present application reduces the output voltage undershoot.

Description

[Technical Field]

[0001] This invention relates to the field of analog circuit technology, and more particularly to a voltage regulator circuit. [Background Technology]

[0002] Low dropout regulator (LDO) circuits are widely used in the field of integrated circuits. An LDO circuit typically includes an error amplifier, a power transistor, and a grounding resistor (the grounding resistor can also be replaced by any other device or circuit with resistive characteristics). The output voltage generated by the power transistor is input to the error amplifier to adjust the gate voltage of the power transistor, thereby regulating the change in the output voltage.

[0003] Because the bias current of the error op-amp is a fixed current, the differential pair transconductance gm of the error op-amp is constant. The loop bandwidth UGB ≈ gm / C. If the capacitance C is constant, the loop bandwidth UGB is constant. In this case, if a large value of loop bandwidth is required, a large value of transconductance gm is required. This will lead to a large bias current of the error op-amp, thereby increasing the power consumption of the chip. Furthermore, the loop bandwidth is limited by the loop stability.

[0004] In a system-on-a-chip (SoC), the LDO circuit powers both the digital circuitry and the flash memory. The digital circuitry operates at clock frequencies up to 100MHz. During the switching process, there are rapid transitions from light to heavy loads. Traditional LDO circuits require a large external capacitor for voltage regulation. Without this external capacitor, the LDO circuit's loop bandwidth is fixed. When the load current increases from light to heavy, the power transistor Mp cannot provide current to the load quickly enough. The initial gate discharge current of the error amplifier is quite small. Without additional current, the LDO circuit's output voltage undershoot will be substantial, easily triggering the power-on-reset (POR) circuit and causing malfunctions in the chip. [Summary of the Invention]

[0005] In view of this, embodiments of the present invention provide a voltage regulator circuit to solve the problem of output voltage undershoot in voltage regulator circuits.

[0006] On one hand, embodiments of the present invention provide a voltage regulator circuit, including: an error operational amplifier, a power transistor, a resistor network, and a feedback regulation circuit;

[0007] A power transistor is used to receive a power supply voltage and generate an output voltage, which is output through the resistor network.

[0008] The error operational amplifier is used to receive the reference voltage and the output voltage, and generate a first control signal to control the control terminal of the power transistor.

[0009] The feedback regulation circuit is used to receive the output voltage and generate a second control signal to control the control terminal of the power transistor.

[0010] When the output voltage changes, the second control signal changes before the first control signal. The second control signal causes the current flowing into the control terminal of the power transistor to change so as to quickly adjust the output voltage to a preset voltage value.

[0011] On the other hand, embodiments of the present invention provide a voltage regulator circuit, including an error operational amplifier, a power transistor, and a resistor network. The first terminal of the power transistor is connected to a power supply voltage, and the second terminal of the power transistor is connected to the resistor network to generate an output voltage. The first terminal of the error operational amplifier is connected to a reference voltage, and the second terminal of the error operational amplifier is connected to the output voltage. The output terminal of the error operational amplifier is connected to the control terminal of the power transistor. The voltage regulator circuit also includes a feedback adjustment circuit.

[0012] The feedback regulation circuit includes a feedback path, a voltage response circuit, and a current response circuit; the first end of the feedback path is electrically connected to the output voltage, the second end of the feedback path is connected to the voltage response circuit, the other end of the voltage response circuit is electrically connected to the input end of the current response circuit, the output end of the current response circuit is electrically connected to the control end of the power transistor, and the current response circuit pulls up or pulls down the control end of the power transistor.

[0013] In the technical solution provided by the embodiments of the present invention, the voltage regulator circuit includes an error operational amplifier, a power transistor, a resistor network, and a feedback adjustment circuit. When the output voltage changes, since the second control signal generated by the feedback adjustment circuit can change before the first control signal generated by the error operational amplifier, the second control signal generated by the feedback adjustment circuit can quickly adjust the current at the control terminal of the power transistor to quickly adjust the output voltage of the power transistor, thereby reducing the output voltage undershoot. [Attached Image Description]

[0014] Figure 1 This is a schematic diagram of a voltage regulator circuit provided in an embodiment of the present invention;

[0015] Figure 2 This is a schematic diagram of a feedback adjustment circuit provided in an embodiment of the present invention;

[0016] Figure 3 This is a schematic diagram of another feedback adjustment circuit provided in an embodiment of the present invention;

[0017] Figure 4 This is a schematic diagram of another feedback adjustment circuit provided in an embodiment of the present invention;

[0018] Figure 5 This is a schematic diagram of another feedback adjustment circuit provided in an embodiment of the present invention;

[0019] Figure 6 This is a schematic diagram of another feedback adjustment circuit provided in an embodiment of the present invention;

[0020] Figure 7 This is a schematic diagram of another feedback adjustment circuit provided in an embodiment of the present invention;

[0021] Figure 8 This is a schematic diagram of another feedback adjustment circuit provided in an embodiment of the present invention;

[0022] Figure 9 This is a schematic diagram of another feedback adjustment circuit provided in an embodiment of the present invention;

[0023] Figure 10 This is a schematic diagram of another feedback adjustment circuit provided in an embodiment of the present invention;

[0024] Figure 11 This is a schematic diagram of another feedback adjustment circuit provided in an embodiment of the present invention;

[0025] Figure 12 This is a schematic diagram of another feedback adjustment circuit provided in an embodiment of the present invention;

[0026] Figure 13 This is a schematic diagram of another feedback adjustment circuit provided in an embodiment of the present invention;

[0027] Figure 14 This is a schematic diagram of another voltage regulator circuit provided in an embodiment of the present invention;

[0028] Figure 15 This is a schematic diagram of another voltage regulator circuit provided in an embodiment of the present invention;

[0029] Figure 16 This is a schematic diagram of another voltage regulator circuit provided in an embodiment of the present invention;

[0030] Figure 17 This is a schematic diagram of another voltage regulator circuit provided in an embodiment of the present invention;

[0031] Figure 18 This is a schematic diagram of another voltage regulator circuit provided in an embodiment of the present invention;

[0032] Figure 19 This is a schematic diagram of another voltage regulator circuit provided in an embodiment of the present invention;

[0033] Figure 20 This is a schematic diagram of another voltage regulator circuit provided in an embodiment of the present invention;

[0034] Figure 21 This is a schematic diagram of another voltage regulator circuit provided in an embodiment of the present invention.

Detailed Implementation Methods

[0035] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0037] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0038] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0039] Figure 1 This is a schematic diagram of a voltage regulator circuit provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the voltage regulator circuit includes: an error operational amplifier 1, a power transistor 2, a resistor network 3, and a feedback adjustment circuit 4. The power transistor 2 is electrically connected to the error operational amplifier 1, the resistor network 3, and the feedback adjustment circuit 4. The power transistor 2 receives the power supply voltage and generates an output voltage Vout, which is output through the resistor network 3. The error operational amplifier 1 receives a reference voltage and the output voltage, and generates a first control signal to control the control terminal of the power transistor 2. The feedback adjustment circuit 4 receives the output voltage and generates a second control signal to control the control terminal of the power transistor 2. When the output voltage changes, the second control signal changes before the first control signal, causing a change in the current flowing into the control terminal of the power transistor 2 to quickly adjust the output voltage to a preset voltage value. In other words, the power transistor 2 is also used to change the current flowing into the control terminal under the control of the second control signal to quickly adjust the output voltage to a preset voltage value. The control terminal of the power transistor 2 is the gate.

[0040] like Figure 1 As shown, the first terminal of power transistor 2 is connected to the power supply voltage VDD, and the second terminal of power transistor 2 is connected to the resistor network 3 to generate an output voltage. The first terminal of error operational amplifier 1 is connected to the reference voltage VREF, the second terminal of error operational amplifier 1 is connected to the output voltage, the output terminal of error operational amplifier 1 is connected to the control terminal of power transistor 2, and error operational amplifier 1 is also connected to the power supply voltage VDD. It should be noted that the output voltage received by error operational amplifier 1 can be the voltage between power transistor 2 and resistor network 3, or if the resistor network is composed of multiple resistive components, the voltage input to the error operational amplifier can be the corresponding voltage after the output voltage is divided. However, the divided voltage is also a representation of the output voltage, so in this embodiment of the invention, it is referred to as the output voltage. In the subsequent connection of the feedback regulation circuit 4, the output voltage can also be treated in this way.

[0041] like Figure 1 As shown, the second terminal of the error operational amplifier 1 is connected to the output voltage through a resistor network 3. The first terminal of the resistor network 3 is electrically connected to the second terminal of the power transistor 2, and the second terminal of the resistor network 3 is electrically connected to a low-voltage terminal. The resistor network 3 may include at least one resistor; that is, the number of resistors in the resistor network 3 can be one or more. For example, at least one resistor may include resistors R1 and R2 connected in series. Resistor R1 is electrically connected to the second terminal of the power transistor 2, and resistor R2 is electrically connected to a low-voltage terminal, such as ground GND1. In practical applications, the resistor network 3 can also adopt other structures. For example, different numbers of resistors can be electrically connected in different ways to form different resistor networks 3; it can also be a MOSFET, a diode-connected MOSFET, or other components, as long as they have resistive properties.

[0042] like Figure 1 As shown, the node between resistor network 3 and power transistor 2 is the output terminal of the voltage regulator circuit, and the output voltage of this terminal is Vout. Resistor network 3 outputs the output voltage to error operational amplifier 1. Error operational amplifier 1 compares the output voltage with the reference voltage VREF and outputs a first control signal. The output voltage from resistor network 3 to error operational amplifier 1 is the feedback voltage Vf. Error operational amplifier 1 can generate a first control signal that can control the control terminal of power transistor 2 according to the magnitude of feedback voltage Vf, thereby controlling the output voltage Vout of power transistor 2 to achieve the purpose of keeping the output voltage constant.

[0043] like Figure 1As shown, in one possible implementation, the feedback regulation circuit 4 receives the output voltage Vout and generates a second control signal based on Vout to control the control terminal of the power transistor 2. In another possible implementation, the feedback regulation circuit 4 receives the output voltage Vf and generates a second control signal based on Vf to control the control terminal of the power transistor 2; this case is not specifically shown in the figure. When the output voltage Vout changes, since the second control signal changes before the first control signal, the second control signal can quickly adjust the current at the control terminal of the power transistor 2 to quickly adjust the output voltage of the power transistor 2, thereby reducing the output voltage undershoot.

[0044] Figure 2 This is a schematic diagram of a feedback regulation circuit provided in an embodiment of the present invention, as shown below. Figure 2 As shown, the feedback regulation circuit includes a feedback path 5, a voltage response circuit 6, and a current response circuit 7. Feedback path 5 is electrically connected to the voltage response circuit 6 and the power transistor 2, and the current response circuit 7 is also electrically connected to the voltage response circuit 6 and the power transistor 2. Feedback path 5 transmits the changing output voltage to the voltage response circuit 6, which generates a response voltage based on the changing output voltage. The current response circuit 7 receives the response voltage to generate a response current, and the control terminal of the power transistor 2 receives the response current to change the output voltage.

[0045] like Figure 2 As shown, the first end of the feedback path 5 is electrically connected to the output voltage, the second end of the feedback path 5 is connected to the voltage response circuit 6, the other end of the voltage response circuit 6 is electrically connected to the input end of the current response circuit 7, the output end of the current response circuit 7 is electrically connected to the control end of the power transistor 2, and the current response circuit 7 pulls up or pulls down the control end of the power transistor 2.

[0046] like Figure 2 As shown, the voltage response circuit 6 includes a first feedback transistor 61, a second feedback transistor 62, and a first current source 63. The current response circuit 7 includes a control circuit 71 and a first switching transistor 72. The first terminal of the first current source 63 is electrically connected to the power supply voltage VDD. The second terminal of the first current source 63 is electrically connected to the first terminal of the second feedback transistor 62. The second terminal of the second feedback transistor 62 is electrically connected to the first terminal of the first feedback transistor 61. The second terminal of the first feedback transistor 61 is electrically connected to the low-voltage terminal. The first terminal of the feedback path 5 is electrically connected to the first node between the first feedback transistor 61 and the second feedback transistor 62. The second terminal of the feedback path 5 is electrically connected to the output terminal of the voltage regulator circuit. The control terminal of the first switching transistor 72 is electrically connected to the second node between the first current source 63 and the second feedback transistor 62. The output terminal of the first switching transistor 72 is electrically connected to the input terminal of the control circuit 71. The output terminal of the control circuit 71 is electrically connected to the control terminal of the power transistor 2.

[0047] like Figure 2 As shown, when the voltage regulator circuit changes from light load to heavy load, the load current needs to increase. However, power transistor 2 cannot provide a sufficiently large load current to the load quickly enough, so the output voltage Vout decreases. Feedback path 5 receives the output voltage Vout and inputs voltage V0 to the first node between the first feedback transistor 61 and the second feedback transistor 62, making the voltage of the first node V0. Since the voltage V0 of the first node is less than the initial operating voltage of the second feedback transistor 62, the second feedback transistor 62 changes rapidly, causing the voltage V1 of the second node to decrease accordingly. The decreased voltage V1 causes the output current of the first switching transistor 72 to change. The control circuit 71 controls the output current supplied to power transistor 2 based on the changing current output by the first switching transistor 72. If power transistor 2 is a P-type transistor, for example, a P-type metal-oxide-semiconductor (PMOS) transistor, then control circuit 71 rapidly pulls down the gate of power transistor 2, thereby increasing the output current of power transistor 2. If power transistor 2 is an N-type transistor, for example, an N-type metal-oxide-semiconductor (NMOS) transistor, then control circuit 71 rapidly pulls up the gate of power transistor 2, thereby increasing the output current of power transistor 2. The increased output current of power transistor 2 leads to an increase in the output voltage Vout, thus achieving the purpose of regulating the output voltage Vout.

[0048] Therefore, in the voltage regulator circuit of this embodiment, the added feedback adjustment circuit can quickly adjust the output voltage Vout undershoot caused by the transition from light load to heavy load, and the adjustment of the output voltage Vout is faster compared to a voltage regulator circuit with only an error operational amplifier. By changing the current at the control terminal of power transistor 2, power transistor 2 is quickly pulled up and then pulled down, which further stabilizes Vout more quickly.

[0049] Figure 3 This is a schematic diagram of another feedback regulation circuit provided in an embodiment of the present invention, as shown below. Figure 3 As shown, in Figure 2 Based on this, if power transistor 2 is a P-type transistor, for example, a PMOS transistor, then the current response circuit 7 includes a pull-down circuit 73. The pull-down circuit 73 is used to generate an increased response current based on the decreased response voltage. The increased response current pulls down the voltage at the control terminal of power transistor 2 to control the output voltage Vout to increase.

[0050] exist Figure 2 In the circuit, the current response circuit 7 includes a control circuit 71, for example, Figure 2 The control circuit 71 includes Figure 3The pull-down circuit 73 is connected to the output of the first switching transistor 72. The first terminal of the pull-down circuit 73 is connected to the control terminal of the power transistor 2. The second terminal of the pull-down circuit 73 is connected to the low voltage terminal. Figure 3 Taking the power transistor 2 as a PMOS transistor and the low voltage terminal as ground terminal GND1, the first terminal of the pull-down circuit 73 is electrically connected to the control terminal of the PMOS transistor, and the second terminal of the pull-down circuit 73 is electrically connected to the ground terminal GND1.

[0051] like Figure 3 As shown, when the regulated voltage changes from light load to heavy load, the output voltage Vout decreases. The output current of the first switching transistor 72 should cause the pull-down circuit 73 to pull down the gate of the PMOS transistor significantly, thereby reducing the Vg of the PMOS transistor and increasing the |Vgs| voltage of the PMOS transistor. The output current of the PMOS transistor increases, so as to input a large current to resistors R1 and R2, thereby increasing the output voltage Vout.

[0052] Figure 4 This is a schematic diagram of another feedback regulation circuit provided in an embodiment of the present invention, as shown below. Figure 4 As shown, in Figure 2 Based on this, if power transistor 2 is an N-type transistor, for example, an NMOS transistor, then the current response circuit 7 includes a pull-up circuit 74 and a pull-down circuit 73. The pull-down circuit 73 is used to generate an increased first response current based on the decreased response voltage; the pull-up circuit 74 is used to generate an increased second response current based on the first response current. The increased second response current pulls up the voltage at the control terminal of power transistor 2 to control the output voltage Vout to increase.

[0053] exist Figure 2 In the circuit, the current response circuit 7 includes a control circuit 71, for example, Figure 2 The control circuit 71 includes Figure 4 The pull-up circuit 74 and pull-down circuit 73 are configured such that the input terminal of the pull-down circuit 73 is electrically connected to the output terminal of the first switching transistor 72, the first terminal of the pull-down circuit 73 is electrically connected to the control terminal of the pull-up circuit 74, the second terminal of the pull-down circuit 73 is electrically connected to the low voltage terminal, the first terminal of the pull-up circuit 74 is electrically connected to the power supply voltage VDD, and the second terminal of the pull-up circuit 74 is electrically connected to the control terminal of the power transistor 2. Figure 4 In the example of the power transistor 2, which is an NMOS transistor, and the low voltage terminal is grounded at GND1, the second terminal of the pull-up circuit 74 is electrically connected to the control terminal of the NMOS transistor, and the second terminal of the pull-down circuit 73 is electrically connected to grounded at GND1.

[0054] like Figure 4As shown, when the regulated voltage changes from light load to heavy load, the output voltage Vout decreases. The output current of the first switching transistor 72 should cause the pull-up circuit 74 to generate a relatively large pull-up on the gate of the NMOS transistor, thereby increasing the Vg of the NMOS transistor and thus increasing the Vgs voltage of the NMOS transistor. The output current of the NMOS transistor increases, so as to input a large current to resistors R1 and R2, thereby increasing the output voltage Vout.

[0055] In embodiments of the present invention, such as Figures 2 to 4 As shown, the first feedback transistor 61 may include a MOSFET, a diode connected in diode configuration, an output transistor of a current mirror, or a resistor, etc., to prevent the feedback voltage V0 from being directly grounded; the second feedback transistor 62 should be able to change rapidly according to the changes in the feedback voltage V0. When the feedback voltage V0 decreases, it can quickly pull down the voltage V1. The combination of the first switching transistor 72 and the pull-down circuit 73 can quickly pull down the gate of the PMOS transistor, and the combination of the first switching transistor 72, the pull-down circuit 73, and the pull-up circuit 74 can quickly pull up the gate of the NMOS transistor. Figures 2 to 4 As shown, the voltage regulator circuit includes a first current source 63, a second feedback transistor 62, and a first feedback transistor 61, which keeps the DC operating point of the first switching transistor 72 within its fast operating range.

[0056] Figure 5 This is a schematic diagram of another feedback regulation circuit provided in an embodiment of the present invention, as shown below. Figure 5 As shown, in Figure 3 Based on this, the pull-down circuit 72 includes a sixth current mirror 75. The input terminal of the sixth current mirror 75 is electrically connected to the output terminal of the first switching transistor 72, and the output terminal of the sixth current mirror 75 is electrically connected to the control terminal of the power transistor 2. Figure 5 Taking the PMOS transistor as an example, the output terminal of the sixth current mirror 75 is electrically connected to the control terminal of the PMOS transistor.

[0057] Figure 6 This is a schematic diagram of another feedback regulation circuit provided in an embodiment of the present invention, as shown below. Figure 6 As shown, in Figure 4 Based on this, the pull-down circuit 72 includes a sixth current mirror 75, and the pull-up circuit 74 includes a seventh current mirror 76. The input terminal of the sixth current mirror 75 is electrically connected to the output terminal of the first switching transistor 72, the output terminal of the sixth current mirror 75 is electrically connected to the input terminal of the seventh current mirror 76, and the output terminal of the seventh current mirror 76 is electrically connected to the control terminal of the power transistor 2. Figure 6 Taking the NMOS transistor as an example, the output terminal of the seventh current mirror 76 is electrically connected to the control terminal of the NMOS transistor.

[0058] Figure 7 This is a schematic diagram of another feedback regulation circuit provided in an embodiment of the present invention, as shown below. Figure 7 As shown, in Figure 2 Based on this, the first current source 63 is the first current mirror 64, the first feedback tube 62 is the output transistor of the second current mirror 65, the second feedback tube 62 is the output transistor of the third current mirror 66, the output terminal of the first current mirror 65 is electrically connected to the second feedback tube 62, the input terminal of the first current mirror 65 is electrically connected through the first terminal of the output transistor of the fourth current mirror 67 to form a third node, the second terminal of the output transistor of the fourth current mirror 67 is electrically connected to the first terminal of the output transistor of the fifth current mirror 68, and the second terminal of the output transistor of the fifth current mirror 68 is electrically connected to the low voltage terminal. Figure 7 Taking the ground terminal GND1 as an example, the second terminal of the output transistor of the fifth current mirror 68 is electrically connected to the ground terminal GND1.

[0059] Figure 8 This is a schematic diagram of another feedback regulation circuit provided in an embodiment of the present invention, as shown below. Figure 8 As shown, in Figure 7 Based on this, the control circuit 71 includes a sixth current mirror 75. The input terminal of the sixth current mirror 75 is electrically connected to the output terminal of the first switching transistor 72, and the output terminal of the sixth current mirror 75 is electrically connected to the control terminal of the power transistor 2. Figure 8 Taking the PMOS transistor as an example, the output terminal of the sixth current mirror 75 is electrically connected to the control terminal of the PMOS transistor. Figure 3 The pull-down circuit 73 in the middle is Figure 8 The sixth current mirror 75.

[0060] Figure 9 A schematic diagram of another feedback regulation circuit provided in an embodiment of the present invention is shown below. Figure 9 As shown, in Figure 7 Based on this, the control circuit 71 includes a sixth current mirror 75 and a seventh current mirror 76. The input terminal of the sixth current mirror 75 is electrically connected to the output terminal of the first switching transistor 72, the output terminal of the sixth current mirror 75 is electrically connected to the input terminal of the seventh current mirror 76, and the output terminal of the seventh current mirror 76 is electrically connected to the control terminal of the power transistor 2. Figure 9 Taking the NMOS transistor as an example, the output of the seventh current mirror 76 is electrically connected to the control terminal of the NMOS transistor. Figure 4 The pull-down circuit 73 in the middle is Figure 9 The sixth current mirror 75 in the middle, Figure 4 The pull-up circuit 74 in the middle is Figure 9 The seventh current mirror 76.

[0061] In embodiments of the present invention, such as Figures 5 to 9As shown, the first current source, first feedback transistor, second feedback transistor, pull-up circuit, and pull-down circuit can all employ current mirrors to ensure that at least a portion of the feedback regulation circuit remains in the linear or subthreshold region. This causes the transistor's output current to change exponentially with the gate-source voltage. This exponentially changing current effectively pulls up or down the power transistor's gate, allowing the feedback regulation circuit to quickly respond to changes in the output voltage Vout and thus rapidly adjust the output voltage Vout. Furthermore, the aforementioned circuit configuration provides resistor matching.

[0062] Figure 10 A schematic diagram of another feedback regulation circuit provided in an embodiment of the present invention is shown below. Figure 10 As shown, in Figure 8 Based on this, a second switch 69 is connected between the second node and the third node. The voltage at the second node is voltage V1, and the voltage at the third node is voltage V2.

[0063] To maintain the DC operating point of the first switching transistor 72 without deviation or with very small deviation, V2 and V1 should be equal. A second switching transistor 69 is provided at the control terminal and output terminal of the first current mirror. The second switching transistor 69 is kept on so that V2 = V1, thereby reducing the DC operating point deviation of the feedback regulation circuit, solving the circuit mismatch problem, and improving the ability to reduce the output voltage undershoot.

[0064] like Figure 10 As shown, the voltage regulator circuit also includes a voltage regulator module 80, a third feedback transistor, and a fourth feedback transistor. The third feedback transistor is the output transistor of the eighth current mirror 81, and the fourth feedback transistor is the output transistor of the ninth current mirror 82. The input terminal of the voltage regulator module 80 is electrically connected to the control terminal of the second switching transistor 69 and the first terminal of the output transistor of the eighth current mirror 81. The second terminal of the output transistor of the eighth current mirror 81 is electrically connected to the first terminal of the output transistor of the ninth current mirror 82. The second terminal of the output transistor of the ninth current mirror 82 is electrically connected to the low voltage terminal.

[0065] like Figure 10 As shown, a voltage regulator module 80 and a third feedback transistor can be set in the voltage regulator circuit, so that the voltage at the control terminal of the second switching transistor 69 is maintained at a stable voltage.

[0066] like Figure 10 As shown, to achieve circuit matching, a fourth feedback transistor (e.g., the ninth current mirror 82) can be set in the voltage regulator circuit. The voltage regulator module 80 is connected to the third feedback transistor (e.g., the eighth current mirror 81) and then to the fourth feedback transistor (e.g., the ninth current mirror). In this way, the third feedback transistor is matched with the second feedback transistor, and the fourth feedback transistor is matched with the first feedback transistor, thereby reducing the problems caused by circuit mismatch.

[0067] like Figure 10 As shown, the voltage regulator module 80 includes a fourth transistor and a fifth transistor. The first terminal of the fourth transistor is electrically connected to the power supply voltage. The control terminal and the second terminal of the fourth transistor are electrically connected to the first terminal of the fifth transistor. The control terminal and the second terminal of the fifth transistor are electrically connected to the first terminal of the output transistor of the eighth current mirror. The control terminal of the fifth transistor is also connected to the control terminal of the second switching transistor. The voltage regulator module 80 uses a diode-connected MOSFET, wherein the fourth transistor is matched with the first current mirror, and the fifth transistor is matched with the second switching transistor.

[0068] Figure 11 A schematic diagram of another feedback regulation circuit provided in an embodiment of the present invention is shown below. Figure 11 As shown, in Figure 9 Based on this, a second switch 69 is connected between the second node and the third node. The voltage at the second node is voltage V1, and the voltage at the third node is voltage V2.

[0069] like Figure 11 As shown, the voltage regulator circuit also includes a voltage regulator module 80, a third feedback transistor, and a fourth feedback transistor. The third feedback transistor is the output transistor of the eighth current mirror 81, and the fourth feedback transistor is the output transistor of the ninth current mirror 82.

[0070] right Figure 11 Descriptions of the second switching transistor 69, the voltage regulator module 80, the third feedback transistor, and the fourth feedback transistor can be found in [reference needed]. Figure 10 The description in the text will not be repeated here.

[0071] Figure 12 A schematic diagram of another feedback regulation circuit provided in an embodiment of the present invention is shown below. Figure 12 As shown, in Figure 3 Based on this, the feedback regulation circuit also includes a first shunt circuit 83, which is connected in parallel with the pull-down circuit 73. The first shunt circuit 83 is used to reduce the current output by the pull-down circuit 73 when it is effective. Figure 12 As shown, the control terminal of the first shunt circuit 83 is electrically connected to the first mode control terminal MODLE1, the first terminal of the first shunt circuit 83 is electrically connected to the input terminal of the pull-down circuit 73, and the second terminal of the first shunt circuit 83 is electrically connected to the low voltage terminal.

[0072] Figure 13 A schematic diagram of another feedback regulation circuit provided in an embodiment of the present invention is shown below. Figure 13 As shown, in Figure 4 Based on this, the feedback regulation circuit also includes a first shunt circuit 83, which is connected in parallel with the pull-down circuit 73. When the first shunt circuit 83 is active, it reduces the current output by the pull-down circuit 73. Figure 13As shown, the control terminal of the first shunt circuit 83 is electrically connected to the first mode control terminal MODLE1, the first terminal of the first shunt circuit 83 is electrically connected to the input terminal of the pull-down circuit 73, and the second terminal of the first shunt circuit 83 is electrically connected to the low voltage terminal.

[0073] like Figure 12 and Figure 13 As shown, pull-down circuit 73 is the sixth current mirror, and pull-up circuit 74 is the seventh current mirror.

[0074] In embodiments of the present invention, such as Figure 12 As shown, to reduce power consumption when no adjustment is needed and enable rapid response when adjustment is required, a first shunt circuit 83 is provided in parallel with the pull-down circuit 73 (e.g., the sixth current mirror) in the voltage regulator circuit. The first shunt circuit 83 is connected to the first mode control terminal MODEL1. When it is necessary to reduce the power consumption of the feedback adjustment circuit, the first shunt circuit 83 is turned on to make it effective, so that the output current of the first switching transistor 72 flows into the first shunt circuit 83 and the pull-down circuit 73 (e.g., the sixth current mirror), thereby reducing the output current of the pull-down circuit 73 (e.g., the sixth current mirror). The reduced current has virtually no effect on the gate of the PMOS transistor, so the feedback adjustment circuit does not affect the normal voltage regulator circuit, and at the same time, it can reduce power consumption. Similarly, as Figure 13 As shown, since the current output of the pull-down circuit 73 (e.g., the sixth current mirror) decreases, the current output of the pull-up circuit 74 (e.g., the seventh current mirror) also decreases. The reduced current has virtually no effect on the gate of the NMOS transistor. Therefore, the feedback regulation circuit does not affect the normal voltage regulator circuit and can reduce power consumption.

[0075] In embodiments of the present invention, such as Figure 12 As shown, when the feedback adjustment circuit needs to operate, the first mode control terminal MODEL1 shuts down the first shunt circuit 83. At this time, the first shunt circuit 83 is not working, causing the output current generated by the first switching transistor 72 to flow into the pull-down circuit 73 (e.g., the sixth current mirror), thus enabling a large current to quickly pull down the gate of the PMOS transistor. Similarly, as... Figure 13 As shown, when the feedback adjustment circuit needs to work, the first mode control terminal MODEL1 turns off the first shunt circuit 83. At this time, the first shunt circuit 83 does not work, so that the output current generated by the first switching transistor 72 flows into the pull-down circuit 73 (e.g., the sixth current mirror). At this time, the current flowing into the pull-up circuit 74 (e.g., the seventh current mirror) increases, so that the large current can quickly pull up the gate of the NMOS transistor.

[0076] Figure 14 A schematic diagram of another voltage regulator circuit provided in an embodiment of the present invention is shown below. Figure 14 As shown, in Figure 1 In addition to the above, the voltage regulator circuit also includes a current source supply circuit, which is electrically connected to the feedback regulation circuit 4 or the error operational amplifier 1. The current source supply circuit is used to supply current to the feedback regulation circuit 4 or the error operational amplifier 1. The current source supply circuit has multiple current source branches, and at least one current source branch can be selected to change the current flowing into the feedback regulation circuit 4 or the error operational amplifier 1.

[0077] Specifically, such as Figure 14 As shown, the current source supply circuit is connected between the power supply voltage VDD and the low voltage terminal and supplies power to the feedback regulation circuit 4 or the error operational amplifier 1. The current source supply circuit includes a power supply current mirror 91, the input of which is connected to multiple parallel control switches 92. Each control switch 92 is connected to a corresponding sub-circuit current source, and the control terminal of at least one control switch 92 is electrically connected to the second mode control terminal MODLE2. The output of the power supply current mirror 91 is electrically connected to the input transistors of the eighth current mirror 81, the fourth current mirror 67, and the third current mirror 66.

[0078] In one possible implementation, Figure 10 Based on this, the voltage regulator circuit includes a current source supply circuit. For example... Figure 14 As shown, the voltage regulator circuit includes two sub-current sources: a first sub-current source IB1 and a second sub-current source IB2. The first sub-current source IB1 is directly connected to the input of the power supply current mirror 91 and continuously supplies current to it, thus maintaining the feedback regulation circuit in a low-power state. The second sub-current source IB2 is connected to the power supply current mirror 91 via a control switch 92, and the control terminal of the control switch 92 is controlled by the second mode control terminal MODEL2. For example, the control switch 92 can be a fifth switching transistor. In another possible implementation, the first sub-current source IB1 is also connected to the input of the power supply current mirror 91 via the control switch 92.

[0079] To reduce power consumption when no adjustment is needed and enable rapid response when adjustment is required, an adjustable current source circuit is included in the voltage regulator circuit. When it is necessary to reduce the power consumption of the feedback adjustment circuit, the control switch 92 (e.g., the fifth switching transistor) is turned off under the control of the second mode control terminal MODEL2. The second sub-current source IB2 cannot supply current to the power supply current mirror 91, thus reducing the current supplied to the power supply current mirror 91. This, in turn, reduces the current supplied to the subsequent working sub-circuits of the feedback adjustment circuit, thereby reducing power consumption. When the feedback adjustment circuit needs to operate, the control switch 92 (e.g., the fifth switching transistor) is turned on under the control of the second mode control terminal MODEL2. The second sub-current source IB2 can supply current to the power supply current mirror 91, increasing the current in the power supply current mirror 91 to the current required for normal operation, thereby enabling control of the output voltage.

[0080] In this embodiment of the invention, in Figure 11 Based on this, the voltage regulator circuit may also include a current source supply circuit. This case is not specifically shown; for a detailed description of the current source supply circuit in this embodiment, please refer to [link to relevant documentation]. Figure 14 The description of the current source circuit in the previous section will not be repeated here.

[0081] Figure 15 A schematic diagram of another voltage regulator circuit provided in an embodiment of the present invention is shown below. Figure 15 As shown, in Figure 10 Based on this, the voltage regulator circuit also includes a current source supply circuit and a first shunt circuit 83. The current source supply circuit is connected between the power supply voltage VDD and the low-voltage terminal. The current source supply circuit includes a power supply current mirror 91, the input of which is connected to multiple parallel control switches 92. Each control switch 92 is connected to a corresponding sub-circuit current source, and the control terminal of at least one control switch 92 is electrically connected to the mode control terminal MODLE. The control terminal of the first shunt circuit 83 is electrically connected to the mode control terminal MODLE through an inverter NOT. The first terminal of the first shunt circuit 83 is electrically connected to the input of the pull-down circuit 73, and the second terminal of the first shunt circuit 83 is electrically connected to the low-voltage terminal. For a detailed description of the current source supply circuit, please refer to [link to relevant documentation]. Figure 14 For a detailed description of the first shunt circuit 83, please refer to the description in [the original text]. Figure 12 The description in the previous section will not be repeated here. The first shunt branch 83 and the adjustable current source supply circuit can share a single mode control terminal in the manner described above, or they can share two mode control terminals. It is preferable to use the method of sharing a single mode control terminal, which can save the number of control terminals, save wiring, and simplify the circuit.

[0082] To reduce power consumption and minimize the impact on the normal voltage regulator circuit, and to ensure a fast response when the feedback regulation circuit is operating, the following measures will be taken: Figure 12The scheme of controlling the first shunt circuit 83 and Figure 14 The scheme combines the current source supply circuit of the control circuit, and in order to save external pin circuits or simplify the layout and wiring, the mode control terminal of the two schemes can be shared. That is, the current source supply circuit and the first shunt circuit 83 are controlled by a mode control terminal MODEL. The first shunt circuit 83 can be electrically connected to the mode control terminal MODEL through an inverter.

[0083] For example, both control switch 92 and the first shunt circuit 83 are high-level conducting, MODLE=0 is the low-power mode, and MODLE=1 is the normal operating mode. When MODLE=0, control switch 92 is not conducting, and the control signal input to the control terminal of the first shunt circuit 83 after passing through the inverter is 1, so the first shunt circuit 83 is conducting. When MODLE=1, control switch 92 is conducting, and the control signal input to the control terminal of the first shunt circuit 83 after passing through the inverter is 0, so the first shunt circuit 83 is not conducting. This achieves... Figure 12 and Figure 14 The proposed solution.

[0084] It should be noted that if control switch 92 is high and the first shunt circuit 83 is low, or if control switch 92 is low and the first shunt circuit 83 is high, the control terminal of the first shunt circuit 83 can be directly connected to the mode control terminal MODLE, thus eliminating the need for an inverter. For example, if control switch 92 is high and the first shunt circuit 83 is low, when MODLE = 0, control switch 92 is not turned on, and the first shunt circuit 83 is turned on; when MODLE = 1, control switch 92 is turned on, and the first shunt circuit 83 is not turned on. This achieves the same effect as using an inverter.

[0085] In this embodiment of the invention, in Figure 11 Based on this, the voltage regulator circuit may also include a current source supply circuit and a first shunt circuit 83. This case is not specifically shown; for a detailed description of the current source supply circuit and the first shunt circuit 83 in this embodiment, please refer to [link to relevant documentation]. Figure 15 The description of the current source circuit and the first shunt circuit 83 in the previous section will not be repeated here.

[0086] Figure 16 This is a schematic diagram of another voltage regulator circuit provided in an embodiment of the present invention. The following is a description of its structure in conjunction with... Figure 16 Through a specific example, Figures 1 to 15 The provided voltage regulator circuit is described in detail. For example... Figure 16As shown, the first current mirror 4 includes a sixth switch MA11 and a seventh switch MA12; the eighth current mirror 81 includes an input transistor MA3 and an output transistor MA5; the fourth current mirror 67 includes an input transistor MA3 and an output transistor MA7; the third current mirror 66 includes an input transistor MA3 and an output transistor MA9; the ninth current mirror 82 includes an input transistor MA4 and an output transistor MA6; the fifth current mirror 68 includes an input transistor MA4 and an output transistor MA8; the second current mirror 65 includes an input transistor MA4 and an output transistor MA10; the sixth current mirror 75 includes an input transistor MA13 and an output transistor MA14; the voltage regulator module includes a fourth transistor Ms5 and a fifth transistor Ms6; the feedback path includes a feedback capacitor CT; the first shunt circuit 83 includes a third switch MS1 and a first transistor MS3; the power supply current mirror 91 includes a sixth switch MA1 and a seventh switch MA2; and the two control switches 92 include a fifth switch MS8 and an eighth switch MS7.

[0087] like Figure 16 As shown, the first terminal of the sixth switch MA11 and the first terminal of the seventh switch MA12 are both electrically connected to the power supply voltage VDD. The control terminals of the sixth switch MA11 and the seventh switch MA12 are both electrically connected to the third node. The second terminal of the sixth switch MA11 is electrically connected to the third node, and the second terminal of the seventh switch MA12 is electrically connected to the second node.

[0088] like Figure 16 As shown, the control terminal of the second switch MS4 is electrically connected to the control terminal of the fifth transistor Ms6, the input terminal of the second switch MS4 is electrically connected to the third node, and the output terminal of the second switch MS4 is electrically connected to the second node.

[0089] like Figure 16As shown, the first terminal and control terminal of input transistor MA3 are electrically connected and both are connected to the second terminal of the seventh switch MA2. The control terminal of input transistor MA3 is also electrically connected to the control terminals of output transistors MA5, MA7, and MA9. The second terminal of input transistor MA3 is electrically connected to the first terminal and control terminal of input transistor MA4. The first terminal of output transistor MA5 is electrically connected to the second terminal and control terminal of the fifth transistor Ms6, and the second terminal of output transistor MA5 is electrically connected to the first terminal of output transistor MA6. The first terminal of output transistor MA7 is electrically connected to the second terminal and control terminal of the sixth switch MA11, and the second terminal of output transistor MA7 is electrically connected to the first terminal of output transistor MA8. The first terminal of output transistor MA9 is electrically connected to the second node, and the second terminal of output transistor MA9 is electrically connected to the first node. The first terminal and control terminal of input transistor MA4 are electrically connected, and the control terminal of input transistor MA4 is also electrically connected to the control terminals of output transistors MA6, MA8, and MA10. The second terminals of output transistors MA6, MA8, and MA10 are all electrically connected to the low-voltage terminal.

[0090] like Figure 16 As shown, the control terminal of the first switch Ms0 is electrically connected to the second node, the input terminal of the first switch Ms0 is electrically connected to the power supply voltage VDD, and the output terminal of the first switch Ms0 is electrically connected to the first terminal of the third switch MS1.

[0091] like Figure 16 As shown, the control terminals of the input transistor MA13 and the output transistor MA14 are electrically connected to the first terminal of the input transistor MA13, and the second terminal of the input transistor MA13 is electrically connected to the low voltage terminal; the first terminal of the output transistor MA14 is electrically connected to the control terminal of the power transistor Mp, and the second terminal of the output transistor MA14 is electrically connected to the low voltage terminal.

[0092] like Figure 16 As shown, the first terminal of the fourth transistor Ms5 is electrically connected to the power supply voltage VDD, the control terminal and the second terminal of the fourth transistor Ms5 are electrically connected to the first terminal of the fifth transistor Ms6, the control terminal and the second terminal of the fifth transistor Ms5 are electrically connected to the first terminal of the output transistor MA5 of the eighth current mirror, and the control terminal of the fifth transistor is also connected to the control terminal of the second switching transistor Ms4.

[0093] like Figure 16As shown, the control terminal of power transistor Mp is electrically connected to the first terminal of output transistor MA14. The first terminal of power transistor Mp is electrically connected to the power supply voltage VDD. The second terminal of power transistor Mp is electrically connected to resistor R1. Resistor R1 is electrically connected to resistor R2. Resistor R2 is electrically connected to the low-voltage terminal. The second terminal of power transistor Mp and resistor R1 are connected to the output terminal of the voltage regulator circuit, and the output voltage of the voltage regulator circuit is Vout. The first terminal of feedback capacitor CT is electrically connected to the first node, and the second terminal of feedback capacitor CT is electrically connected to the output terminal of the voltage regulator circuit. The control terminal VGP of power transistor Mp is represented by a dashed line because VGP is also connected to and controlled by the error operational amplifier. Power transistor Mp is a PMOS transistor.

[0094] like Figure 16 As shown, the control terminal of the third switch MS1 is electrically connected to the mode control terminal MODEL through the inverter NOT. The first terminal of the third switch MS1 is electrically connected to the output terminal of the first switch MS0. The second terminal of the third switch MS1 is electrically connected to the first terminal of the first transistor MS3. The second terminal of the first transistor MS3 is electrically connected to the low voltage terminal. The control terminal of the first transistor MS3 is electrically connected to the first terminal.

[0095] like Figure 16 As shown, a second transistor MS2 is also disposed between the output terminal of the first switching transistor Ms0 and the input terminal of the sixth current mirror. Specifically, the second transistor MS2 is disposed between the output terminal of the first switching transistor Ms0 and the first terminal of the input transistor MA13. The control terminal of the second transistor MS2 is electrically connected to the power supply voltage VDD. To further achieve circuit matching, the second transistor MS2 is disposed between the first switching transistor Ms0 and the input transistor MA13. The second transistor MS2 can be set to be normally on, so that the third switching transistor MS1 is matched with the second transistor MS2, and the first transistor MS3 is matched with the input transistor MA13. For example, the first transistor MS3 can be a diode-connected MOSFET.

[0096] like Figure 16 As shown, the control terminals of the sixth switch MA1 and the seventh switch MA2 are electrically connected to the first terminal of the eighth switch MS7. The first terminals of the sixth switch MA1 and the seventh switch MA2 are both connected to the power supply voltage VDD. The second terminal of the sixth switch MA1 is electrically connected to the first terminal of the eighth switch MS7, and the second terminal of the seventh switch MA2 is electrically connected to the first terminal of the input transistor MA3.

[0097] like Figure 16As shown, the control terminal of the fifth switch MS8 is electrically connected to the mode control terminal MODEL, the first terminal of the fifth switch MS8 is electrically connected to the first terminal of the eighth switch MS7, and the second terminal of the fifth switch MS8 is electrically connected to the second sub-circuit current source IB2; the control terminal of the eighth switch MS7 is electrically connected to the power supply voltage VDD, and the second terminal of the eighth switch MS7 is electrically connected to the first sub-circuit current source IB1. The eighth switch MS7 is normally on, and it is matched with the fifth switch MS8.

[0098] Figure 17 This is a schematic diagram of another voltage regulator circuit provided in an embodiment of the present invention. The following is a description of its structure in conjunction with... Figure 17 Through a specific example, Figures 1 to 15 The provided voltage regulator circuit is described in detail. For example... Figure 17 As shown, with Figure 16 Compared to the structure, Figure 17 and Figure 16 The difference lies in the fact that this voltage regulator circuit includes a seventh current mirror 76, which comprises an input transistor MA15 and an output transistor MA16. The control terminals of the input transistor MA15 and the output transistor MA16 are electrically connected to the first terminal of the output transistor MA14, and the second terminal of the input transistor MA15 is electrically connected to the first terminal of the output transistor MA14. The first terminal of the input transistor MA15 is electrically connected to the power supply voltage VDD. The first terminal of the output transistor MA16 is electrically connected to the power supply voltage VDD, and the second terminal of the output transistor MA16 is electrically connected to the control terminal of the power transistor Mp. The power transistor Mp is an NMOS transistor. Figure 17 For descriptions of the remaining structures, please refer to Figure 16 The description in the text will not be repeated here.

[0099] In embodiments of the present invention, such as Figures 1 to 17 As shown, the voltage regulator circuit is an LDO circuit.

[0100] In the technical solution provided by this invention, the voltage regulator circuit includes an error operational amplifier, a power transistor, a resistor network, and a feedback adjustment circuit. When the output voltage changes, the second control signal generated by the feedback adjustment circuit changes before the first control signal generated by the error operational amplifier. Therefore, the second control signal generated by the feedback adjustment circuit can quickly adjust the current at the control terminal of the power transistor to quickly adjust the output voltage of the power transistor, thereby reducing the output voltage undershoot. Because the output voltage undershoot is reduced in this invention, the POR circuit of the voltage regulator circuit is not triggered and reset, allowing the chip to operate normally.

[0101] In related technologies, LDO circuits without external capacitors typically employ Miller compensation technology. This technology keeps the dominant pole internal, resulting in a loop bandwidth UGB ≈ gm / C. Here, gm is the differential-pair transconductance of the error op-amp, and C is the Miller compensation capacitor. Since the bias current of the error op-amp is fixed, its differential-pair transconductance gm remains constant. Because the loop bandwidth UGB ≈ gm / C, if the Miller compensation capacitor C is constant, the loop bandwidth remains constant. Therefore, the loop bandwidth of the LDO circuit remains unchanged under different loads. Under heavy loads, the constant bandwidth of the LDO circuit leads to a deterioration in loop response. If the loop bandwidth needs to be increased, the Miller compensation capacitor C must be decreased. However, the Miller compensation capacitor C cannot be made infinitely small, and this poses a challenge to loop stability design. If the loop bandwidth needs to be increased, the gm of the error op-amp needs to be increased, which requires an increased bias current for the error op-amp, leading to an increase in the static power consumption of the LDO circuit.

[0102] To address the aforementioned technical problems, embodiments of the present invention provide a voltage regulator circuit. Figure 18 A schematic diagram of another voltage regulator circuit provided in an embodiment of the present invention is shown below. Figure 18 As shown, in Figure 1 Based on this, the voltage regulator circuit also includes an output current sensing circuit 93 and a reference current circuit 94. The output current sensing circuit 93 is electrically connected to the power transistor Mp and the error operational amplifier 1, and the reference current circuit 94 is electrically connected to the error operational amplifier 1. The output current sensing circuit 93 is used to sense the output current of the power transistor Mp and generate a sensing current that varies with the output current. The reference current circuit 94 provides a reference current to the error operational amplifier 1, and the reference current varies with the sensing current to adjust the transconductance of the error operational amplifier 1.

[0103] For example, the reference current may include a first reference current Ibias and a second reference current. The reference current circuit 94 provides a fixed first reference current Ibias to the error operational amplifier 1, and the output current sensing circuit 93 outputs a second reference current to the error operational amplifier 1. The second reference current can change with the change of the sensing current generated by the output current sensing circuit 93. The reference current flowing into the error operational amplifier 1 is the result of the combined action of the first reference current circuit and the second reference current. Therefore, the reference current changes with the change of the sensing current.

[0104] like Figure 18As shown, the input terminal of the output current sensing circuit 93 is electrically connected to the second terminal of the power transistor Mp, and the output terminal of the reference current circuit 94 is electrically connected to the current input terminal of the error operational amplifier 1. (Note: In the schematic diagram, the reference current circuit 94 is placed between the error operational amplifier and the low voltage terminal. Alternatively, the reference current circuit 94 can be placed between the power supply voltage and the error operational amplifier. This is just an example; the method and position can be adjusted according to the design. See [link to specific details]). Figure 21 (As shown in the circuit example), the output terminal of the output current sensing circuit 93 is electrically connected to the input terminal of the reference current circuit 94. One end of the output current sensing circuit 93 is also connected to the power supply voltage VDD, and the other end of the output current sensing circuit 93 is also connected to the low voltage terminal EP1. The power transistor Mp is a PMOS transistor, or, in practical applications, the power transistor M can also be an NMOS transistor Mn, which is not shown in the figure.

[0105] Furthermore, such as Figure 18 As shown, the voltage regulator circuit also includes a Miller compensation capacitor C. The first terminal of the Miller compensation capacitor C is electrically connected to the error operational amplifier 1, and the second terminal of the Miller compensation capacitor C is electrically connected to the second terminal of the power transistor Mp.

[0106] In this embodiment of the invention, since UGB≈gm / C, gm is determined by the differential circuit output of the error operational amplifier 1, and gm is related to the reference current of the error operational amplifier 1, an output current sensing circuit 93 is set in the voltage regulator circuit. The output current sensing circuit 93 can change according to the change of the output current (load current IL) and generate a sensing current that changes with the output current. When the load current IL increases, the sensing current increases accordingly, and the reference current changes with the change of the sensing current. The output current sensing circuit 93 also increases the reference current input to the error operational amplifier 1, thereby increasing the reference current flowing into the error operational amplifier 1. gm is related to the flowing reference current. When the Miller compensation capacitor C is constant, the loop bandwidth increases when gm increases. In other words, since the bias current of the error operational amplifier 1 is a variable current, an additional variable current is added to the original fixed bias current. This variable current samples the current of the power transistor M (Mp or Mn) through the output current sensing circuit 93. The variable current is proportional to the load current IL. The differential pair transconductance gm of the error operational amplifier 1 is also proportional to the variable current. Therefore, the larger the output load current, the larger the variable current, and the larger the differential pair transconductance gm of the operational amplifier. Since the loop bandwidth UGB≈gm / C, if the Miller compensation capacitor C is constant, the larger the output load current, the larger the loop bandwidth. Therefore, under different loads, the loop bandwidth of the LDO circuit will change proportionally with the load current IL. Under large loads, the increased bandwidth of the LDO circuit leads to a better loop response, thus making it suitable for the needs of large load applications.

[0107] Figure 19A schematic diagram of another voltage regulator circuit provided in an embodiment of the present invention is shown below. Figure 19 As shown, in Figure 18 Based on this, the voltage regulator circuit also includes a first current boosting circuit 95. The first current boosting circuit 95, when effective, increases the output current of the output current sensing circuit 93, thereby further increasing the current flowing into the error operational amplifier, increasing the transconductance gm, and further improving the loop response. Optionally, the first current boosting circuit 95 may be disposed within the output current sensing circuit 93.

[0108] like Figure 19 As shown, the control terminal of the first current boosting circuit 95 is electrically connected to the mode control terminal MODEL. The mode control terminal MODEL can control the output current of the output current sensing circuit 93 by controlling the first current boosting circuit 95. The mode control terminal MODEL controls the current input from the output current sensing circuit 93 to the error operational amplifier 1 by controlling the on / off state of the first current boosting circuit 95. When the control signal of the mode control terminal MODEL is a low-power signal, the first current boosting circuit 95 is not turned on, which reduces the overall output current of the output current sensing circuit 93, thereby reducing the power consumption of the entire voltage regulator circuit. When the control signal of the mode control terminal MODEL is in normal mode or high-load mode, the first current boosting circuit 95 is turned on, which increases the overall output current of the current sensing circuit 93, allowing the voltage regulator circuit to operate normally. Moreover, the reference current can be increased, improving the transconductance and speeding up the circuit response. The output current of the current sensing circuit 93 to the error operational amplifier 1 is the second reference current.

[0109] Figure 20 A schematic diagram of another voltage regulator circuit provided in an embodiment of the present invention is shown below. Figure 20 As shown, in Figure 19 Based on this, the control terminal of the reference current circuit 94 is electrically connected to the mode control terminal MODEL.

[0110] like Figure 20 As shown, the reference current circuit 94 is controlled by the mode control terminal MODEL to increase or decrease the first reference current Ibias. When the control signal of the mode control terminal MODEL is a low-power signal, the first reference current Ibias output by the reference current circuit 94 decreases, which reduces the overall current of the error operational amplifier 1, thereby reducing the power consumption of the entire voltage regulator circuit. When the control signal of the mode control terminal MODEL is in normal mode or high-load mode, the first reference current Ibias output by the reference current circuit 94 increases, which increases the overall current of the error operational amplifier 1, and the voltage regulator circuit operates normally.

[0111] like Figure 20As shown, the voltage regulator circuit can simultaneously control the first current boosting circuit 95 and the reference current circuit 94. Furthermore, to simplify the circuit and reduce the number of external terminals, the first current boosting circuit 95 and the reference current circuit 94 can share the mode control terminal MODEL. If the control methods of the first current boosting circuit 95 and the reference current circuit are the same, both the first current boosting circuit 95 and the reference current circuit 94 can be directly electrically connected to the mode control terminal MODEL; if the control methods of the first current boosting circuit 95 and the reference current circuit 94 are different, either the first current boosting circuit 95 or the reference current circuit 94 can be electrically connected to the mode control terminal MODEL via an inverter.

[0112] Figure 21 This is a schematic diagram of another voltage regulator circuit provided in an embodiment of the present invention. The following is a description of its structure in conjunction with... Figure 21 Through a specific example, Figures 18 to 20 The provided voltage regulator circuit is described in detail. For example... Figure 21 As shown, the error operational amplifier 1 includes transistors M5 to M8, the output current sensing circuit 93 includes transistors MB1 to MB13, and the reference current circuit 94 includes transistors M1, M2, the first sub-current source IB and the second sub-current source K*IB, transistors M3 and M4 (transistors M3 and M4 form a current mirror).

[0113] The first current boosting circuit 95 includes a fourth switch MS11 and a third transistor MS22. The control terminal of the fourth switch MS11 is electrically connected to the mode control terminal MODEL, the second terminal of the fourth switch MS11 is electrically connected to the first terminal of the third transistor MS22, and the second terminal of the third transistor MS22 is electrically connected to the low voltage terminal. Further, the first terminal of the fourth switch MS11 is electrically connected to the first terminal of transistor MB3, and the control terminal of the third transistor MS22 is electrically connected to the first terminal of transistor MB6.

[0114] like Figure 21 As shown, the control terminal of transistor M5 is electrically connected to the node between resistors R1 and R2. The first terminal of transistor M5 is electrically connected to the second terminal of the fourth transistor M4, and the second terminal of transistor M5 is electrically connected to the first terminal of transistor M7. The control terminal of transistor M6 is electrically connected to the reference voltage VREF. The first terminal of transistor M6 is electrically connected to the second terminal of the fourth transistor M4, and the second terminal of transistor M6 is electrically connected to the first terminal of transistor M8. The control terminal of transistor M7 is electrically connected to the second terminal of transistor M5 and the control terminal of transistor M8, and the second terminal of transistor M7 is electrically connected to the low-voltage terminal. The control terminal of transistor M8 is electrically connected to the control terminal of transistor M7. The first terminal of transistor M8 is electrically connected to the second terminal of transistor M6, and the second terminal of transistor M8 is electrically connected to the low-voltage terminal.

[0115] like Figure 21As shown, the control terminal of transistor M1 is electrically connected to the mode control terminal MODEL, the first terminal of transistor M1 is electrically connected to the second terminal of transistor M3, and the second terminal of transistor M1 is electrically connected to the second sub-current source K*IB. The control terminal of transistor M2 is electrically connected to the power supply voltage VDD, the first terminal of transistor M2 is electrically connected to the second terminal of transistor M3, and the second terminal of transistor M2 is electrically connected to the first sub-current source IB. The control terminal of transistor M3 is electrically connected to both the second terminal of transistor M3 and the control terminal of transistor M4, and the first terminal of transistor M3 is electrically connected to the power supply voltage VDD. The first terminal of transistor M4 is electrically connected to the power supply voltage VDD. The first sub-current source IB and the second sub-current source K*IB are also electrically connected to the low voltage terminal.

[0116] like Figure 21As shown, the control terminal of transistor MB1 is electrically connected to the control terminal of transistor MB2, the first terminal of transistor MB1 is electrically connected to the power supply voltage VDD, and the second terminal of transistor MB1 is electrically connected to the second terminal of transistor MB4. The first terminal of transistor MB2 is electrically connected to the power supply voltage VDD, and the second terminal of transistor MB2 is electrically connected to the control terminal of transistor MB2 and the first terminal of transistor MB3. The control terminal of transistor MB3 is electrically connected to the power supply voltage VDD, and the second terminal of transistor MB3 is electrically connected to the first terminal of transistor MB4. The control terminal of transistor MB4 is electrically connected to the first terminal of transistor MB6, and the second terminal of transistor MB4 is electrically connected to a low-voltage terminal. The control terminal of transistor MB5 is electrically connected to the first terminal of transistor MB6, the first terminal of transistor MB5 is electrically connected to the second terminal of transistor MB7, and the second terminal of transistor MB5 is electrically connected to a low-voltage terminal. The control terminal of transistor MB6 is electrically connected to the control terminal of transistor MB11, the first terminal of transistor MB6 is electrically connected to the second terminal of transistor MB8, and the second terminal of transistor MB6 is electrically connected to a low-voltage terminal. The control terminal of transistor MB7 is electrically connected to the second terminal of transistor MB7, and the first terminal of transistor MB7 is electrically connected to the second terminal of transistor MB13. The control terminal of transistor MB8 is electrically connected to the control terminal of transistor MB10, and the first terminal of transistor MB8 is electrically connected to the second terminal of transistor MB13. The control terminal of transistor MB9 is electrically connected to the control terminal of transistor MB10, and the first terminal of transistor MB9 is electrically connected to the first terminal of transistor MB10. The second terminal of transistor MB9 is electrically connected to the first terminal of transistor MB11. The control terminal of transistor MB10 is electrically connected to the second terminal of transistor MB10, the first terminal of transistor MB10 is electrically connected to the second terminal of power transistor Mp, and the second terminal of transistor MB10 is electrically connected to the first terminal of transistor MB12. The control terminal of transistor MB11 is electrically connected to the first terminal of transistor MB11, and the second terminal of transistor MB11 is electrically connected to the low-voltage terminal. The control terminal of transistor MB12 is electrically connected to the second terminal of transistor MB8, and the second terminal of transistor MB12 is electrically connected to the low-voltage terminal. The control terminal of transistor MB13 is electrically connected to the control terminal of power transistor Mp, and the first terminal of transistor MB13 is electrically connected to the power supply voltage VDD.

[0117] The first terminal of the Miller compensation capacitor C is electrically connected to the second terminal of transistor M6 and the first terminal of transistor M8. The second terminal of the Miller compensation capacitor C is electrically connected to the second terminal of power transistor Mp.

[0118] like Figure 21 As shown, the current output from the second terminal of transistor M4 in the reference current circuit 94 is the first reference current Ibias, and the current output from the output terminal of the output current sensing circuit 93 is the second reference current. The reference current obtained by the combined action of the first reference current Ibias and the second reference point current flows into the error operational amplifier 1.

[0119] like Figure 21 As shown, in the output current sensing circuit 93, transistors MB5 to MB12 form a current mirror group, making VB = Vout, which realizes the current replication of current mirror M5 by transistor MB4. Here, VB is the voltage of the connection node between transistors MB7 and MB13. When the load current IL increases, the adjustment current Ifb through transistor MB1 also increases, thereby increasing the current flowing into error operational amplifier 1, which in turn increases the loop gain.

[0120] like Figure 21 As shown, the fourth switch MS11 and the third transistor MS22 form the first current boosting circuit 95. When MODEL is 0, transistors MB11 and MB22 are not turned on, so the current Ifb through transistor MB2 decreases, thereby reducing power consumption; when MODEL is 1, transistors MB11 and MB22 are turned on, the current Ifb through transistor MB2 increases, the circuit can operate normally while increasing transconductance and improving response speed.

[0121] like Figure 21 As shown, transistor MB3 is matched with the fourth switch MS11, and transistor MB3 is always on.

[0122] like Figure 21 As shown, the first sub-current source IB and the second sub-current source K*IB constitute the reference current circuit. When MODEL is 0, transistor M1 is not turned on, thus reducing the current in each branch of the reference current circuit and reducing power consumption; when MODEL is 1, transistor M1 is turned on, the current in the reference current circuit increases, and the circuit works normally.

[0123] like Figure 21 As shown, the current ratio of the third transistor MS22 to the transistor MB4 is M:1, the current ratio of the transistor M1 to the transistor MB2 is K:1, and the current ratio of the transistor MB13 to the transistor Mp is 1:N. By setting appropriate values ​​for K, M, and N, a trade-off between loop response and power consumption is ensured.

[0124] The first shunt circuit 83 may or may not shunt the current from the previous stage, and the first current booster circuit 95 may or may not provide current to the previous stage, but their structures are basically similar. For the first shunt circuit 83, being effective means reducing the current flowing into the pull-down circuit, such as when the corresponding transistor is turned on; for the first current booster circuit 95, being effective means increasing the current flowing into the reference current circuit, such as when the corresponding transistor is turned on. The control methods for the first sub-current source IB and the second sub-current source K*IB are the same as those described above for the first sub-current source IB1 and the second sub-current source IB2. These current control methods can be combined in various ways, such as... Figure 16 , Figure 17 and Figure 21 In addition to the specific circuit shown in the diagram, the first current boosting circuit 95 can be combined with... Figure 16 and Figure 17 In this context, the control method of the first sub-current source IB and the second sub-current source K*IB can also be applied to... Figure 16 and Figure 17 In the middle, it can also be Figure 21 The methods in the middle are all applicable Figure 16 and Figure 17 Medium-range, with multiple combinations that can be freely configured according to specific needs.

[0125] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A voltage regulator circuit, characterized in that, include: Error operational amplifier, power transistor, resistor network and feedback regulation circuit; A power transistor is used to receive a power supply voltage and generate an output voltage, which is output through the resistor network. The error operational amplifier is used to receive the reference voltage and the output voltage, and generate a first control signal to control the control terminal of the power transistor. The feedback regulation circuit is used to receive the output voltage and generate a second control signal to control the control terminal of the power transistor. When the output voltage changes, the second control signal changes before the first control signal. The second control signal causes the current flowing into the control terminal of the power transistor to change so as to quickly adjust the output voltage to a preset voltage value. The feedback regulation circuit includes: a feedback path, a voltage response circuit, and a current response circuit; The feedback path is used to transmit the changing output voltage to the voltage response circuit, which generates a response voltage according to the changing output voltage. The current response circuit is used to receive the response voltage to generate a response current, and the control terminal of the power transistor is used to receive the response current to change the output voltage; The power transistor is a P-type transistor, and the current response circuit includes a pull-down circuit. The pull-down circuit is used to generate an increased response current based on the decreased response voltage. The increased response current pulls down the voltage at the control terminal of the power transistor to control the output voltage to increase; or, The power transistor is an N-type transistor, and the current response circuit includes a pull-up circuit and a pull-down circuit. The pull-down circuit is used to generate an increased first response current in response to the reduced response voltage; The pull-up circuit is used to generate an increased second response current based on the first response current. The increased second response current pulls up the voltage at the control terminal of the power transistor to control the output voltage to increase.

2. The voltage regulator circuit according to claim 1, characterized in that, The voltage regulator circuit also includes an output current sensing circuit, which is used to sense the output current of the power transistor and generate a sensing current that varies with the output current. The voltage regulator circuit also includes a reference current circuit, which provides a reference current to the error operational amplifier. The reference current changes with the change of the sensed current to adjust the transconductance of the error operational amplifier.

3. The voltage regulator circuit according to claim 1, characterized in that, The voltage regulator circuit further includes a current source supply circuit, which provides current to the feedback regulation circuit or the error operational amplifier. The current source supply circuit has multiple current source branches, and at least one of the current source branches can be selected to change the current flowing into the feedback regulation circuit or the error operational amplifier.

4. The voltage regulator circuit according to claim 1 or 3, characterized in that, The feedback regulation circuit further includes a first shunt circuit, which is connected in parallel with the pull-down circuit; the first shunt circuit is used to reduce the current output by the pull-down circuit when effective.

5. The voltage regulator circuit according to claim 4, characterized in that, The voltage regulator circuit further includes a first current boosting circuit, which, when effective, increases the output current of the output current sensing circuit.

6. A voltage regulator circuit, comprising an error operational amplifier, a power transistor, and a resistor network, wherein a first terminal of the power transistor is connected to a power supply voltage, and a second terminal of the power transistor is connected to the resistor network to generate an output voltage; a first terminal of the error operational amplifier is connected to a reference voltage, a second terminal of the error operational amplifier is connected to the output voltage, and the output terminal of the error operational amplifier is connected to the control terminal of the power transistor; characterized in that, The voltage regulator circuit also includes a feedback adjustment circuit; The feedback regulation circuit includes a feedback path, a voltage response circuit, and a current response circuit; the first end of the feedback path is electrically connected to the output voltage, the second end of the feedback path is connected to the voltage response circuit, the other end of the voltage response circuit is electrically connected to the input end of the current response circuit, the output end of the current response circuit is electrically connected to the control end of the power transistor, and the current response circuit pulls up or pulls down the control end of the power transistor. The power transistor is a P-type transistor, and the current response circuit includes a pull-down circuit. The pull-down circuit is used to generate an increased response current based on the decreased response voltage. The increased response current pulls down the voltage at the control terminal of the power transistor to control the output voltage to increase; or, The power transistor is an N-type transistor, and the current response circuit includes a pull-up circuit and a pull-down circuit. The pull-down circuit is used to generate an increased first response current in response to the reduced response voltage; The pull-up circuit is used to generate an increased second response current based on the first response current. The increased second response current pulls up the voltage at the control terminal of the power transistor to control the output voltage to increase.

7. The voltage regulator circuit according to claim 6, characterized in that, The voltage response circuit includes a first feedback transistor, a second feedback transistor, and a first current source; the current response circuit includes a control circuit and a first switching transistor. The first terminal of the first current source is electrically connected to the power supply voltage, the second terminal of the first current source is electrically connected to the first terminal of the second feedback tube, the second terminal of the second feedback tube is electrically connected to the first terminal of the first feedback tube, and the second terminal of the first feedback tube is electrically connected to the low voltage terminal. The first end of the feedback path is electrically connected to the first node between the first feedback tube and the second feedback tube, and the second end of the feedback path is electrically connected to the output terminal of the voltage regulator circuit. The control terminal of the first switching transistor is electrically connected to the second node between the first current source and the second feedback transistor, the output terminal of the first switching transistor is electrically connected to the input terminal of the control circuit, and the output terminal of the control circuit is electrically connected to the control terminal of the power transistor.

8. The voltage regulator circuit according to claim 7, characterized in that, The control circuit includes a pull-down circuit, the input terminal of which is electrically connected to the output terminal of the first switching transistor, the first terminal of which is electrically connected to the control terminal of the power transistor, and the second terminal of which is electrically connected to a low-voltage terminal; or, the control circuit includes a pull-up circuit and a pull-down circuit, the input terminal of which is electrically connected to the output terminal of the first switching transistor, the first terminal of which is electrically connected to the control terminal of the pull-up circuit, the second terminal of which is electrically connected to a low-voltage terminal, the first terminal of which is electrically connected to the power supply voltage, and the second terminal of which is electrically connected to the control terminal of the power transistor.

9. The voltage regulator circuit according to claim 8, characterized in that, The feedback adjustment circuit includes a first shunt circuit; the control terminal of the first shunt circuit is electrically connected to the first mode control terminal, the first terminal of the first shunt circuit is electrically connected to the input terminal of the pull-down circuit, and the second terminal of the first shunt circuit is electrically connected to the low voltage terminal.

10. The voltage regulator circuit according to claim 8, characterized in that, The voltage regulator circuit further includes a current source supply circuit, which is connected between the power supply voltage and the low voltage terminal and supplies power to the feedback adjustment circuit or the error operational amplifier. The current source supply circuit includes a power supply current mirror, the input terminal of which is connected to a plurality of parallel control switches, each of which is connected to a corresponding sub-circuit current source, and the control terminal of at least one of the control switches is electrically connected to the second mode control terminal.

11. The voltage regulator circuit according to claim 8, characterized in that, The voltage regulator circuit also includes an output current sensing circuit, the input terminal of which is electrically connected to the second terminal of the power transistor. The voltage regulator circuit also includes a reference current circuit, the output terminal of which is electrically connected to the current input terminal of the error operational amplifier, and the output terminal of the output current sensing circuit is electrically connected to the input terminal of the reference current circuit.

12. The voltage regulator circuit according to claim 7, characterized in that, The first current source is a first current mirror, the first feedback transistor is the output transistor of the second current mirror, the second feedback transistor is the output transistor of the third current mirror, the output terminal of the first current mirror is electrically connected to the second feedback transistor, the input terminal of the first current mirror is electrically connected through the first terminal of the output transistor of the fourth current mirror to form a third node, the second terminal of the output transistor of the fourth current mirror is electrically connected to the first terminal of the output transistor of the fifth current mirror, and the second terminal of the output transistor of the fifth current mirror is electrically connected to the low voltage terminal. The control circuit includes a sixth current mirror, the input terminal of which is electrically connected to the output terminal of the first switching transistor, and the output terminal of which is electrically connected to the control terminal of the power transistor. Alternatively, the control circuit includes a sixth current mirror and a seventh current mirror, the input terminal of which is electrically connected to the output terminal of the first switching transistor, the output terminal of which is electrically connected to the input terminal of the seventh current mirror, and the output terminal of the seventh current mirror is electrically connected to the control terminal of the power transistor.

13. The voltage regulator circuit according to claim 12, characterized in that, A second switching transistor is connected between the second node and the third node.

14. The voltage regulator circuit according to claim 12, characterized in that, The feedback regulation circuit further includes a first shunt circuit, which includes a third switch and a first transistor. The control terminal of the third switch is electrically connected to the mode control terminal. The first terminal of the third switch is electrically connected to the output terminal of the first switch. The second terminal of the third switch is electrically connected to the first terminal of the first transistor. The second terminal of the first transistor is electrically connected to the low voltage terminal.

15. The voltage regulator circuit according to claim 12, characterized in that, A second transistor is also provided between the output terminal of the first switching transistor and the input terminal of the sixth current mirror.

16. The voltage regulator circuit according to claim 11, characterized in that, The voltage regulator circuit further includes a first current boosting circuit, which includes a fourth switching transistor and a third transistor. The control terminal of the fourth switching transistor is electrically connected to the mode control terminal, the second terminal of the fourth switching transistor is electrically connected to the first terminal of the third transistor, and the second terminal of the third transistor is electrically connected to the low voltage terminal.

17. The voltage regulator circuit according to claim 16, characterized in that, The control terminal of the reference current circuit is electrically connected to the mode control terminal.

18. The voltage regulator circuit according to claim 13, characterized in that, The voltage regulator circuit also includes a third feedback transistor and a fourth feedback transistor, a fourth transistor and a fifth transistor, wherein the third feedback transistor is the output transistor of the eighth current mirror, and the fourth feedback transistor is the output transistor of the ninth current mirror. The first terminal of the fourth transistor is electrically connected to the power supply voltage, the control terminal and the second terminal of the fourth transistor are electrically connected to the first terminal of the fifth transistor, the control terminal and the second terminal of the fifth transistor are electrically connected to the first terminal of the output transistor of the eighth current mirror, and the control terminal of the fifth transistor is also connected to the control terminal of the second switching transistor. The second terminal of the output transistor of the eighth current mirror is electrically connected to the first terminal of the output transistor of the ninth current mirror, and the second terminal of the output transistor of the ninth current mirror is electrically connected to the low voltage terminal.

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