Method for free rtos to access pcie device under virtual machine

Abstract

The application relates to a method for accessing a PCIe device under a FreeRTOS, which comprises the following steps: reading a PCIe configuration file when the FreeRTOS is initialized; scanning the PCIe device; reading a PCIe capbilitilites register; configuring a BAR space by reading BAR0 / 1 information, and obtaining an IO space address range; reading msix capabilities, and configuring msi / msix interrupts by a vpci_irq_base attribute in a PCIe bus description file; and realizing PCIe basic functions including IO access of the PCIe device, sending and receiving of the msix interrupts by a driver. The application can enable the FreeRTOS running on a virtual machine to perform PCIe device scanning, interrupt registration, IO reading and writing and other access operations on the PCIe device.

Description

Technical Field

[0001] This invention relates to the field of FreeRTOS access function optimization technology under virtual machines, and a method for FreeRTOS to access PCIe devices under virtual machines. Background Technology

[0002] FreeRTOS is a real-time operating system. In the IoT field, the main chip has a low clock speed and requires low power consumption. The peripherals that communicate with the system are mostly low-speed devices such as I2C, SPI, and UART, and generally do not communicate with high-speed PCIe devices.

[0003] However, in the industrial control field, the main chip has a high clock frequency and can accept higher power consumption. FreeRTOS will run in a virtual environment (Hypervisor), and there will be a large demand for communication between FreeRTOS and physical PCIe devices, as well as communication between FreeRTOS and virtual PCIe devices created by the Hypervisor.

[0004] Currently, FreeRTOS running in a virtual machine does not support PCIe drivers and cannot scan or access PCIe devices. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a method for FreeRTOS to access PCIe devices under a virtual machine, comprising the following steps:

[0006] Step S1: FreeRTOS reads the PCIe configuration file during initialization;

[0007] Step S2: Scan PCIe devices according to the attributes described in the configuration file;

[0008] Step S3: Read the PCIe configuration space information of the scanned PCIe devices;

[0009] Step S4: Obtain the I / O space address range to be mapped by using the BAR register information in the PCIe configuration space;

[0010] Step S5: Read the Capabilities information through the Capabilities pointer in the PCIe configuration space, and then read the msix capabilities. Combine this with the vpci_irq_base attribute in the PCIe bus description file in the PCIe configuration file in step S1 to configure the MSI / msix interrupt.

[0011] Step S6: Implement basic PCIe functions, including PCIe device I / O access and sending and receiving msix interrupts, through the API provided by the driver.

[0012] In step S1, the PCIe configuration file read includes a PCIe bus description, a PCIe device description, and PCIe capabilities attributes.

[0013] The configuration files involved in the PCIe bus description include:

[0014] pci_mmconfig_base indicates the address where the PCIe bus description file is located;

[0015] pci_mmconfig_end_bus indicates the number of buses supported by the PCIe bus;

[0016] pci_is_virtual indicates whether a virtualized PCIe device exists.

[0017] pci_domain represents the PCI bus domain;

[0018] num_pci_devices represents the total number of PCIe devices that FreeRTOS needs to recognize;

[0019] vpci_irq_base represents the starting interrupt number used by PCIe devices under FreeRTOS.

[0020] The configuration files involved in the PCIe device description include:

[0021] Type indicates the category of PCIe device, which is divided into bridge device, ordinary PCIe device and virtual PCIe device;

[0022] Domain indicates the domain in which the PCIe device resides;

[0023] bdf is used to identify PCIe devices;

[0024] caps_start indicates the starting position of the PCIe device's capability attribute;

[0025] num_caps represents the number of capabilities attributes contained in a PCIe device;

[0026] num_msi_vectors represents the number of MSI interrupts supported by a PCIe device;

[0027] msi_64bits indicates whether the PCIe device supports 64-bit MSI interrupts;

[0028] msi_maskable indicates whether the PCIe device's msi supports masks;

[0029] num_msix_vectors represents the number of msix interrupts supported by a PCIe device;

[0030] msix_regIOn_size represents the size of the PCIe device's msix regIOn.

[0031] msix_address represents the msix address of the PCIe device;

[0032] BAR_mask represents the BAR mask of the PCIe device.

[0033] The configuration files involved in the PCIe capabilities attributes include:

[0034] ID represents the type of PCIe capabilities;

[0035] Start is used to identify the PCIe capabilities address;

[0036] Len is used to identify the length of PCIe capabilities;

[0037] Flags are used to identify the writable attributes of PCIe capabilities.

[0038] Step S2 includes:

[0039] Step S21: Obtain the starting address of the PCIe device description file through the PCIe bus description file;

[0040] Step S22: Traverse all devices described in the PCIe device configuration file using the device start address described in the PCIe device configuration file, and find the corresponding PCIe device using the BDF information.

[0041] In step S3, after obtaining the register information, the capabilities attribute of the corresponding PCIe device is obtained through the caps_start and num_caps attributes in the PCIe device description file, thereby obtaining the capabilities information of the PCIe device.

[0042] The method for accessing PCIe devices under a virtual machine according to the present invention enables FreeRTOS running on a virtual machine to perform PCIe device scanning, interrupt registration, IO read and write, and other access operations to PCIe devices. Attached Figure Description

[0043] Figure 1This is a logic diagram illustrating the implementation of the FreeRTOS method for accessing PCIe devices under a virtual machine according to the present invention. Detailed Implementation

[0044] To gain a better understanding of the technical solution and beneficial effects of the present invention, the technical solution of the present invention and its beneficial effects are described in detail below with reference to the accompanying drawings.

[0045] Figure 1 The following is a logic diagram illustrating the implementation of the FreeRTOS method for accessing PCIe devices under a virtual machine according to the present invention: Figure 1 As shown, this invention enables FreeRTOS to access PCIe devices under a virtual machine by designing a configuration file that describes the attributes of PCIe devices and implementing a set of PCIe drivers.

[0046] The specific implementation steps are as follows:

[0047] 1. FreeRTOS reads the PCIe configuration file during initialization.

[0048] Because FreeRTOS uses physical addressing, it is only necessary to agree on the starting address of the PCIe configuration file; the PCIe configuration file should be a part of the virtual machine configuration file.

[0049] The configuration file includes a PCIe bus description, a PCIe device description, and PCIe capabilities attributes. Their respective formats and contents are as follows:

[0050] 1. PCIe bus description:

[0051] .platform_info={

[0052] .pci_mmconfig_base=0x0000000040000000,

[0053] .pci_mmconfig_end_bus=0xFF,

[0054] .pci_is_virtual=1,

[0055] .pci_domain=1,

[0056] .num_pci_devices=ARRAY_SIZE(config.pci_devices),

[0057] .vpci_irq_base=101,

[0058] }

[0059] Table 1: PCIe Bus Description Attributes

[0060]

[0061] 2. PCIe Device Description

[0062] / *PCIDevice:0000:00:05.0* /

[0063] {

[0064] .type=XXX_PCI_TYPE_BRIDGE,.domain=0x0,.bdf=0x28,.caps_start=0,.num_caps=8,

[0065] .num_msi_vectors=1, .msi_64bits=1, .msi_maskable=1,

[0066] .num_msix_vectors=1, .msix_regIOn_size=0x1000, .msix_address=0x1011400000,

[0067] .BAR_mask={0xffc00000,0xffffffff,0x00000000,0x00000000,0x00000000,0x00000000,},

[0068] },

[0069] Table 2: PCIe Device Description Attributes

[0070]

[0071] The msix file is an interrupt mechanism defined in PCIe sepcification.

[0072] mask is a code used for filtering or filtering.

[0073] 3. Introduction to PCIe capabilities attributes

[0074] / *PCIDevice:0000:00:05.0* /

[0075] {.id=PCI_CAP_ID_PM,.start=0x80,.len=8,.flags=XXX_PCICAPS_WR ITE},

[0076] {.id=PCI_CAP_ID_MSI,.start=0x90,.len=20,.flags=XXX_PCICAPS_WRITE},

[0077] {.id=PCI_CAP_ID_MSIX,.start=0xb0,.len=12,.flags=XXX_PCICAPS_WRITE},

[0078] {.id=PCI_CAP_ID_EXP,.start=0xc0,.len=60,.flags=XXX_PCICAPS_WRITE},

[0079] {.id=PCI_EXT_CAP_ID_ERR,.start=0x100,.len=64,.flags=0},

[0080] {.id=PCI_EXT_CAP_ID_TPH,.start=0x274,.len=2,.flags=0},

[0081] {.id=PCI_CAP_ID_EXP,.start=0x300,.len=16,.flags=0},

[0082] {.id=PCI_EXT_CAP_ID_L1SS,.start=0x900,.len=2,.flags=0},

[0083] Table 3: PCIe capabilities attribute description

[0084] Configuration file variables Variable meaning Id This ID is defined in the PCIe specification and represents the type of capabilities; it will not be elaborated further. Start Identifying the capability address Len Identify the length of the capability Flags Writable properties that identify capabilities

[0085] II. Scanning PCIe Devices (PCIe scan)

[0086] 1. The program can obtain the starting address of the PCIe device description file through the PCIe bus description file;

[0087] 2. The program can traverse all devices described in the configuration file by using the starting address of the PCIe device description configuration file and find the corresponding PCIe device through the BDF information.

[0088] III. Reading the PCIe capbilitilites register

[0089] The program can obtain the capabilities attributes of the corresponding PCIe device through the caps_start and num_caps attributes in the PCIe device description file, thereby obtaining the capabilities information of the PCIe device.

[0090] PCIe expands the PCI configuration space from 256 bytes to 4096 bytes. The PCIe configuration space can be divided into two parts: the 256-byte PCI-compatible configuration space and the PCIe extended configuration space.

[0091] The PCIe Capabilities List is divided into two parts: the PCI-compatible part and the PCIe extended part.

[0092] IV. Obtain the I / O space address range, etc., through BAR register information.

[0093] The specific configuration process includes:

[0094] Write 1 to the BAR address using a cfg write request;

[0095] Read the BAR using the cfg read request;

[0096] Based on the read BAR value, determine the request size and request type of BAR, and configure the software to perform a write (type 0) operation on the starting address of the programming device, that is, the starting address of the high-order programming device of the BAR register.

[0097] 5. Read the msix capabilities and configure the MSI / msix interrupts through the vpci_irq_base attribute in the PCIe bus description file.

[0098] VI. Implement basic PCIe functions such as PCIe device I / O access, sending and receiving msix interrupts, etc. through the program.

[0099] Therefore, this invention initializes the PCIe driver by reading the configuration file, enabling basic operations such as scanning PCIe devices, interrupt registration, and I / O access. This allows FreeRTOS running on a virtual machine to perform PCIe device scanning, interrupt registration, and I / O read / write operations. This invention can be implemented on various operating system platforms.

[0100] Although the present invention has been described using the above preferred embodiments, it is not intended to limit the scope of protection of the present invention. Any changes and modifications made by those skilled in the art to the above embodiments without departing from the spirit and scope of the present invention shall still fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be defined by the claims.

Claims

1. A method for accessing PCIe devices under FreeRTOS in a virtual machine, characterized in that, Includes the following steps: Step S1: FreeRTOS reads the PCIe configuration file during initialization. The PCIe configuration file includes a PCIe bus description, a PCIe device description, and PCIe capabilities attributes. Step S2: Scan PCIe devices according to the attributes described in the configuration file; Step S3: Read the PCIe configuration space information of the scanned PCIe devices; Step S4: Obtain the I / O space address range to be mapped by using the BAR register information in the PCIe configuration space; Step S5: Read the Capabilities information through the Capabilities pointer in the PCIe configuration space, and then read the msix capabilities. Combine the vpci_irq_base attribute in the PCIe bus description file in the PCIe configuration file in step S1 to configure the msi / msix interrupt, where vpci_irq_base represents the starting interrupt number used by the PCIe device under FreeRTOS. Step S6: Implement basic PCIe functions, including PCIe device I / O access and sending and receiving msix interrupts, through the API provided by the driver.

2. The method for accessing PCIe devices under a virtual machine using FreeRTOS as described in claim 1, characterized in that: In step S1, the PCIe configuration file read includes a PCIe bus description, a PCIe device description, and PCIe capabilities attributes.

3. The method for accessing PCIe devices under a virtual machine using FreeRTOS as described in claim 2, characterized in that: The configuration files involved in describing the PCIe bus include: pci_mmconfig_base indicates the address where the PCIe bus description file is located; pci_mmconfig_end_bus indicates the number of buses supported by the PCIe bus; pci_is_virtual indicates whether a virtualized PCIe device exists. pci_domain represents the PCI bus domain; num_pci_devices represents the total number of PCIe devices that FreeRTOS needs to recognize; vpci_irq_base represents the starting interrupt number used by PCIe devices under FreeRTOS.

4. The method for accessing PCIe devices under a virtual machine using FreeRTOS as described in claim 2, characterized in that: The configuration files involved in the PCIe device description include: Type indicates the category of PCIe device, which is divided into bridge device, ordinary PCIe device and virtual PCIe device; Domain indicates the domain in which the PCIe device resides; bdf is used to identify PCIe devices; caps_start indicates the starting position of the PCIe device's capability attribute; num_caps represents the number of capabilities attributes contained in a PCIe device; num_msi_vectors represents the number of MSI interrupts supported by a PCIe device; msi_64bits indicates whether the PCIe device supports 64-bit MSI interrupts; msi_maskable indicates whether the PCIe device's msi supports masks; num_msix_vectors represents the number of msix interrupts supported by a PCIe device; msix_regIOn_size represents the size of the PCIe device's msix regIOn. msix_address represents the msix address of the PCIe device; BAR_mask represents the BAR mask of the PCIe device.

5. The method for accessing PCIe devices under a virtual machine using FreeRTOS as described in claim 2, characterized in that: The configuration files involved in the PCIecapabilities attribute include: ID represents the type of PCIe capabilities; Start is used to identify the PCIe capabilities address; Len is used to identify the length of PCIe capabilities; Flags are used to identify the writable attributes of PCIe capabilities.

6. The method for accessing PCIe devices under a virtual machine using FreeRTOS as described in claim 1, characterized in that: Step S2 includes: Step S21: Obtain the starting address of the PCIe device description file through the PCIe bus description file; Step S22: Traverse all devices described in the PCIe device configuration file using the device start address described in the PCIe device configuration file, and find the corresponding PCIe device using the BDF information.

7. The method for accessing PCIe devices under a virtual machine using FreeRTOS as described in claim 1, characterized in that: In step S3, after obtaining the register information, the capabilities attribute of the corresponding PCIe device is obtained through the caps_start and num_caps attributes in the PCIe device description file, thereby obtaining the capabilities information of the PCIe device.

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