Resource allocation method and device, electronic equipment and storage medium

Abstract

A resource allocation method, device, electronic equipment and storage medium. The resource allocation method comprises: obtaining a target task, wherein the target task is divided into a plurality of stage sub-tasks executed in sequence, and the plurality of stages comprise a first stage; determining a first quantity of first virtual resources required for executing the sub-task of the first stage; and in response to a quantity of currently available physical resources in a graphics processor being greater than or equal to the first quantity, mapping a first quantity of first physical resources in the currently available physical resources to the first virtual resources to execute the sub-task of the first stage using the first physical resources. The resource allocation method can enable more thread bundles or threads to be executed in parallel, so that the pipeline is always in a working state, effectively masks and compensates for long delay operations, avoids the stalling of the pipeline, flexibly allocates limited storage resources, and improves the execution efficiency and parallelism of the processor.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a resource allocation method, a resource allocation apparatus, an electronic device, and a non-transitory computer-readable storage medium. BACKGROUND

[0002] A graphics processing unit (GPU) or general purpose graphics processing unit (GPGPU) can utilize a large number of threads to improve parallelism of operations, and the threads need to index corresponding data in a global memory. Since the global memory bandwidth is limited, a large number of access requests cannot be satisfied at the same time, and thus the process often causes a long delay operation, which causes an instruction pipeline to stall and wait. In order to reduce access to the global memory, the graphics processing unit or general purpose graphics processing unit provides various memory types and various memory hierarchy relationships to improve the execution efficiency of a kernel function.

[0003] For example, the graphics processing unit or general purpose graphics processing unit supports a register file, a local memory, a shared memory, a cache, and various types of memories. SUMMARY

[0004] At least one embodiment of the present disclosure provides a resource allocation method for a graphics processing unit, the resource allocation method comprising: obtaining a target task, wherein the target task is divided into a plurality of stage sub-tasks executed in sequence, and the plurality of stages include a first stage; determining a first number of first virtual resources required for executing a sub-task of the first stage; in response to a number of currently available physical resources in the graphics processing unit being greater than or equal to the first number, mapping the first number of first physical resources in the currently available physical resources to the first virtual resources, to execute the sub-task of the first stage using the first physical resources.

[0005] For example, in the resource allocation method provided by at least one embodiment of the present disclosure, determining a first number of first virtual resources required for executing a sub-task of the first stage comprises: obtaining a total number of virtual resources required for executing the target task, and allocating a corresponding continuous virtual address space according to the total number of virtual resources; and determining, from the continuous virtual address space, a continuous first number of the first virtual resources allocated to the sub-task of the first stage.

[0006] For example, in the resource allocation method provided by at least one embodiment of the present disclosure, the first quantity of the first physical resources in the currently available physical resources is mapped to the first virtual resource to perform the sub-tasks of the first stage using the first physical resources, including: determining the first quantity of the first physical resources from the currently available physical resources in the graphics processor; and establishing a one-to-one mapping relationship between the first virtual resource and the first physical resource.

[0007] For example, in the resource allocation method provided by at least one embodiment of the present disclosure, the plurality of stages further includes a second stage, and the sub-tasks of the second stage are executed after the sub-tasks of the first stage. The resource allocation method further includes: determining a second quantity of second virtual resources required for executing the sub-tasks of the second stage; and before the sub-tasks of the first stage are executed and the sub-tasks of the second stage are started to be executed, in response to the quantity of the currently available physical resources in the graphics processor being greater than or equal to the second quantity, mapping the second quantity of second physical resources in the currently available physical resources in the graphics processor to the second virtual resource to execute the sub-tasks of the second stage using the second physical resources.

[0008] For example, in the resource allocation method provided by at least one embodiment of the present disclosure, in response to the target task ending after the i-th stage of the sub-tasks of the plurality of stages is executed, the sub-tasks of each stage executed after the i-th stage of the sub-tasks are no longer executed and no longer apply for and allocate physical resources, and the virtual resources and the physical resources allocated for the first i stages of the sub-tasks are released, where i is a positive integer and less than or equal to the total number of the plurality of stages.

[0009] For example, the resource allocation method provided by at least one embodiment of the present disclosure further includes: grouping the instructions required for executing the sub-tasks of the plurality of stages according to instruction types.

[0010] For example, in the resource allocation method provided by at least one embodiment of the present disclosure, the grouping of the instructions required for executing the sub-tasks of the plurality of stages according to instruction types includes: preferentially executing the first type of instructions in at least one group, where the first type of instructions can make the target task end early.

[0011] For example, in the resource allocation method provided by at least one embodiment of the present disclosure, the grouping of the instructions required for executing the sub-tasks of the plurality of stages according to instruction types includes: preferentially executing the second type of instructions in at least one group, where the second type of instructions have a longer execution time.

[0012] For example, in the resource allocation method provided by at least one embodiment of the present disclosure, the virtual resources allocated to each stage of sub-tasks are continuous, and the physical resources mapped with the virtual resources allocated to each stage of sub-tasks are discontinuous.

[0013] For example, in the resource allocation method provided by at least one embodiment of the present disclosure, the physical resources include register file resources in the graphics processor.

[0014] At least one embodiment of the present disclosure provides a resource allocation apparatus for a graphics processor, comprising: an acquisition unit configured to acquire a target task, wherein the target task is divided into a plurality of stages of sub-tasks executed in sequence, and the plurality of stages include a first stage; a virtual resource determination unit configured to determine a first number of first virtual resources required for executing a sub-task of the first stage; and a first resource allocation unit configured to, in response to a number of currently available physical resources in the graphics processor being greater than or equal to the first number, map a first number of first physical resources in the currently available physical resources to the first virtual resources, so as to execute the sub-task of the first stage by using the first physical resources.

[0015] For example, in the resource allocation apparatus provided by at least one embodiment of the present disclosure, when the virtual resource determination unit performs the operation of determining the first number of first virtual resources required for executing the sub-task of the first stage, the operation includes: acquiring a total number of virtual resources required for executing the target task, and allocating a corresponding continuous virtual address space according to the total number of virtual resources; and determining the first number of continuous first virtual resources from the continuous virtual address space to be allocated to the sub-task of the first stage.

[0016] For example, in the resource allocation apparatus provided by at least one embodiment of the present disclosure, when the first resource allocation unit performs the operation of mapping the first number of first physical resources in the currently available physical resources to the first virtual resources, so as to execute the sub-task of the first stage by using the first physical resources, the operation includes: determining the first number of first physical resources from the currently available physical resources in the graphics processor; and establishing a one-to-one mapping relationship between the first virtual resources and the first physical resources.

[0017] For example, in the resource allocation apparatus provided by at least one embodiment of the present disclosure, the plurality of stages further includes a second stage, the sub-tasks of the second stage are executed after the sub-tasks of the first stage, and the resource allocation apparatus further includes a second resource allocation unit, which is configured to: determine a second quantity of second virtual resources required for executing the sub-tasks of the second stage; and before the sub-tasks of the first stage are executed and the sub-tasks of the second stage are started to be executed, in response to the quantity of the currently available physical resources in the graphics processor being greater than or equal to the second quantity, map a second quantity of second physical resources in the currently available physical resources to the second virtual resources, so as to execute the sub-tasks of the second stage by using the second physical resources.

[0018] For example, the resource allocation apparatus provided by at least one embodiment of the present disclosure further includes an instruction grouping unit, which is configured to group the instructions required for executing the sub-tasks of the plurality of stages according to instruction types.

[0019] An electronic device is provided in at least one embodiment of the present disclosure, including: a memory, which is non-transient and stores computer executable instructions; and a processor, which is configured to run the computer executable instructions, wherein the computer executable instructions, when run by the processor, implement the resource allocation method according to any embodiment of the present disclosure.

[0020] A non-transitory computer readable storage medium is provided in at least one embodiment of the present disclosure, wherein the non-transitory computer readable storage medium stores computer executable instructions, and the computer executable instructions, when executed by a processor, implement the resource allocation method according to any embodiment of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only related to some embodiments of the present disclosure, but not limit the present disclosure.

[0022] Figure 1 A structural schematic diagram of a general-purpose graphics processing unit (GPGPU);

[0023] Figure 2 A schematic flowchart of a resource allocation method provided by at least one embodiment of the present disclosure;

[0024] Figure 3 A schematic flowchart of a resource allocation method provided by at least one embodiment of the present disclosure;

[0025] Figure 4 A resource mapping relationship diagram provided by at least one embodiment of the present disclosure;

[0026] Figure 5 A schematic block diagram of a resource allocation apparatus provided for at least one embodiment of the present disclosure;

[0027] Figure 6 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure;

[0028] Figure 7 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0030] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning commonly understood by a person of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second” and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. The terms “include”, “contain” and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms “connect” or “connected” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper”, “lower”, “left”, “right” and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0031] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components.

[0032] Figure 1 A structural schematic diagram of a general-purpose graphics processing unit (GPGPU).

[0033] In parallel computing, a computing task is generally executed by multiple threads. For example, a general-purpose graphics processing unit (GPGPU) is a parallel computing device that is used to perform general-purpose computing tasks. Figure 1As shown, before these threads execute in the general-purpose graphics processor (or parallel computing processor), they are divided into multiple thread blocks in the thread block scheduling module. Then, the thread block distribution module distributes these thread blocks to various computing units (CUs) (e.g., streaming multiprocessors (SMs)). All threads within a thread block must be assigned to the same computing unit for execution. Simultaneously, thread blocks are further divided into minimum execution thread warps (or simply thread warps), each containing a fixed number (or less than this fixed number) of threads, for example, 32 threads. Multiple thread blocks can execute within the same computing unit or in different computing units.

[0034] Within each computing unit, the thread bundle scheduling / distribution module schedules and allocates thread bundles so that multiple computing cores (e.g., stream processors (SPs)) of that unit can run the thread bundles. Each computing core includes an arithmetic logic unit (ALU), a floating-point unit, etc. Depending on the number of computing cores in the computing unit, multiple thread bundles within a thread block can execute concurrently or in a time-sharing manner. Multiple threads within each thread bundle execute the same instructions. Instruction fetching, decoding, and issuing are all completed within the thread bundle scheduling / distribution module. Memory execution instructions are issued to shared caches (e.g., shared L1 caches) within the computing unit or further issued to a unified cache for read / write operations, etc.

[0035] like Figure 1 As shown, the register file is the most important part of on-chip memory, providing data access speeds that match the computing core. For example, unlike CPU (Central Processing Unit) cores which have only a few general-purpose registers, each streaming multiprocessor (SM) in a general-purpose graphics processor has a large number of register resources. The general-purpose graphics processor statically allocates these registers to each thread, and the large register file allows more threads to remain active simultaneously without the need for time-consuming context switching like in a CPU.

[0036] For example, in some scenarios, the execution of some tasks can be divided into multiple phases of sub-tasks executed in sequence. For example, in a computing task, multiple phases can include at least two phases, i.e., a first phase and a second phase, in the first phase, each pixel is subjected to a depth test, and in the second phase, further processing is performed according to the depth test result of each pixel to output a refraction result. For example, in the multiple phases of sub-tasks, the sub-task of a subsequent phase needs to be processed based on the calculation result of the sub-task executed before, and the sub-task of the subsequent phase can be executed only after the execution of the sub-task executed before is completed, for example, the subsequent sub-task can be executed only after the execution of the sub-task executed before is completed and other operations are performed.

[0037] Currently, when applying for a register file and other resources, for a complete task, the resources required by each phase need to be applied in one time, and the task can be executed only after the application of the resources of all the phases is completed. If the resources required by a task are very large, but the execution of the task is divided into multiple phases, part of the applied resources will not be used immediately, and these resources cannot be provided for use by other threads or thread bundles, thereby causing a large amount of hardware storage resources to be occupied, and affecting the execution efficiency and parallelism of the processor.

[0038] For example, assume that a task can be divided into three stages, i.e., the task can be divided into three-stage sub-tasks executed in sequence, which are the first stage phase0 sub-task, the second stage phase1 sub-task, and the third stage phase2 sub-task. The physical resources required by each stage sub-task are phase0_size, phase1_size, and phase2_size, respectively, and the total physical resources required by the execution of the task are total_size, where phase0_size+phase1_size+phase2_size>=total_size. Here, phase0_size+phase1_size+phase2_size>total_size means that the scheduling module will perform some resource optimization according to the physical resource release during the execution process. Before the task is executed, the total_size amount of physical resources needs to be applied at one time. If the amount of currently available physical resources in the general-purpose graphics processor is less than total_size, even if the size is greater than phase0_size, the first stage program of the current task cannot be executed in advance, and the task can only be executed after the total_size amount of physical resources are in place, so that the second stage and the third stage form a long delay, causing the pipeline to stop. Moreover, the physical resources applied for the second stage and the third stage need to wait for the completion of the execution of the previous sub-tasks before they can be executed, and for a long time, the physical resources are in an unused state, and the delay of the second stage and the third stage is long, so that other thread bundles cannot use these physical resources, which will lead to a large amount of occupation of limited physical resources, and the execution efficiency and parallelism of the processor will be greatly reduced.

[0039] Moreover, the current application for the register file resource is generally to directly use the physical address of the register, and the physical address needs to be continuous, so that the instruction can be conveniently addressed, and therefore a whole block of continuous physical address space with a quantity of total_size is required for the execution of the task when the resources are allocated, and the flexibility of resource allocation is low.

[0040] At least one embodiment of the present disclosure provides a resource allocation method, a resource allocation device, an electronic device, and a non-transitory computer-readable storage medium. The resource allocation method comprises: obtaining a target task, wherein the target task is divided into a plurality of stage sub-tasks executed in sequence, and the plurality of stages include a first stage; determining a first quantity of first virtual resources required for executing the first stage sub-task; and in response to the quantity of currently available physical resources in the graphics processor being greater than or equal to the first quantity, mapping a first quantity of first physical resources in the currently available physical resources to the first virtual resources to execute the first stage sub-task using the first physical resources.

[0041] In the resource allocation method provided by at least one embodiment of the present disclosure, the resources are managed in a manner combining virtual addresses and physical addresses, a first virtual resource and a first physical resource are allocated to a subtask in a first stage, and a mapping relationship between the first virtual resource and the first physical resource is established. When the task is executed, all physical resources required by each stage of the task do not need to be allocated to the task at one time, and only the physical resource required by the first stage needs to be allocated to the subtask and a mapping relationship between the physical resource and the corresponding virtual resource is established, so that the subtask in the first stage can start to execute. Since less physical resources are allocated at one time, more thread bundles or threads can be executed in parallel, so that the pipeline is always in a working state, long-delay operations are effectively masked and compensated, the pipeline is prevented from stopping, limited storage resources are flexibly allocated, and the execution efficiency and parallelism of the processor are improved.

[0042] The embodiments of the present disclosure will be described in detail below with reference to the drawings, but the present disclosure is not limited to these specific embodiments.

[0043] Figure 2 A schematic flowchart of a resource allocation method provided by at least one embodiment of the present disclosure.

[0044] For example, the resource allocation method is used in a general-purpose graphics processing unit (GPGPU) or a graphics processing unit (GPU), but the present disclosure is not limited thereto, and the resource allocation method can also be applied to other processors having similar architectures or principles to the graphics processing unit.

[0045] For example, the resource allocation method provided by at least one embodiment of the present disclosure is described in detail below by taking a graphics processing unit as an example, but it can be understood that the resource allocation method can also be applied to a general-purpose graphics processing unit or a processor having similar architectures or principles, and the specific process will not be described repeatedly.

[0046] For example, as shown in Figure 2 The resource allocation method provided by the embodiment of the present disclosure includes steps S10 to S30.

[0047] In step S10, a target task is acquired.

[0048] For example, the target task is divided into a plurality of subtasks executed in sequence, and the plurality of stages include a first stage.

[0049] For example, the target task is a task currently required to be executed by the graphics processing unit, such as a computing task.

[0050] For example, the target task can be divided into multiple stages of subtasks, and the multiple subtasks are executed in sequence. The concepts of "stage" and "subtask" can be referred to the foregoing, and will not be described here.

[0051] For example, the multiple stages include a first stage, and the subtask of the first stage can be a first subtask in execution order among the multiple subtasks, or the subtask of the first stage can also be any one of the multiple subtasks, and the disclosure does not limit this.

[0052] For example, the multiple stages can include a first stage, and of course, can also include a second stage, a third stage, and the like.

[0053] In step S20, a first quantity of first virtual resources required to execute the subtask of the first stage is determined.

[0054] For example, step S20 can include: obtaining a total quantity of virtual resources required to execute the target task, and allocating a corresponding continuous virtual address space according to the total quantity of virtual resources; and determining, from the continuous virtual address space, a first quantity of first virtual resources to be allocated to the subtask of the first stage.

[0055] For example, in at least one embodiment of the disclosure, a virtual address mapping manner is used to apply for physical resources, and the virtual resources applied for each target task must be continuous. For example, the target task includes N stages of subtasks, N is a positive integer, the sum of the quantities of resources required by the subtasks of the respective stages is calculated as a total quantity of virtual resources required to execute the target task, and a continuous virtual address space with a size of the total quantity of virtual resources is allocated as the virtual resources of the target task. For example, the continuous virtual address space includes total_size continuous virtual addresses, and total_size is the total quantity of virtual resources.

[0056] For example, a first quantity of first virtual resources is determined from the continuous virtual address space to be allocated to the subtask of the first stage, and the first virtual resources are also continuous.

[0057] In step S30, in response to the quantity of currently available physical resources in the graphics processor being greater than or equal to the first quantity, a first quantity of first physical resources in the currently available physical resources is mapped to the first virtual resources to execute the subtask of the first stage using the first physical resources.

[0058] For example, if the quantity of currently available physical resources in the graphics processor is greater than or equal to the first quantity, a first quantity of first physical resources is determined from the currently available physical resources in the graphics processor, and a one-to-one mapping relationship between the first virtual resources and the first physical resources is established to execute the subtask of the first stage using the first physical resources.

[0059] The one-to-one mapping relationship refers to, for example, the first virtual resource includes P virtual addresses, the first physical resource includes P physical addresses, P is a positive integer and represents the first quantity, and the P virtual addresses and the P physical addresses have a one-to-one mapping relationship.

[0060] For example, the virtual resource allocated for each stage of the subtask is continuous, and the physical resource that establishes a mapping relationship with the virtual resource allocated for each stage of the subtask can be discontinuous. For example, taking the first stage as an example, the P virtual addresses are continuous, and the P physical addresses corresponding to the P virtual addresses do not need to be continuous, thereby improving the flexibility of resource allocation.

[0061] For example, the physical resource includes a register file resource in the graphics processor. Of course, according to actual needs, the physical resource can also include other types of storage resources in the graphics processor.

[0062] In at least one embodiment of the present disclosure, even if the number of currently available physical resources in the graphics processor is less than the total number of physical resources required by the target task (equal to the total number of virtual resources), as long as the number of currently available physical resources in the graphics processor is greater than or equal to the first quantity, the mapping relationship between the first virtual resource and the first physical resource can be established, and the execution of the first stage of the subtask can be started, without waiting for the total physical resources required by all stages in the entire target task to be in place before executing the first stage of the subtask, thereby reducing unnecessary resource occupation, reducing one-time allocation of physical resources, allowing more thread bundles or threads to be executed in parallel, keeping the pipeline in a working state at all times, effectively masking long-latency operations, compensating for execution latency, avoiding pipeline stalls, flexibly allocating limited storage resources, improving the utilization efficiency of physical resources, and improving the execution efficiency and parallelism of the processor (especially the graphics processor).

[0063] For example, the plurality of stages further includes a second stage, and the subtask of the second stage is executed after the subtask of the first stage. For example, the subtask of the second stage performs corresponding processing based on the calculation result of the subtask of the first stage, for example, the subtask of the second stage can be executed only after the subtask of the first stage is executed and transferred to perform other operations. For example, there is no other subtask between the subtask of the second stage and the subtask of the first stage, that is, the subtask of the second stage is immediately adjacent to the subtask of the first stage in the execution order, or there is another subtask between the subtask of the second stage and the subtask of the first stage, and the present disclosure does not make specific limitations thereon.

[0064] Figure 3 A schematic flowchart of a resource allocation method provided by at least one embodiment of the present disclosure is provided.

[0065] As Figure 3As shown, the resource allocation method provided by at least one embodiment of the present disclosure further includes steps S40-S50.

[0066] In step S40, a second quantity of second virtual resources required for executing the subtask of the second stage is determined.

[0067] Similar to the process of obtaining the first virtual resources, for example, a continuous virtual address space with a size of the total quantity of virtual resources is pre-planned as the virtual resources of the target task, and the second quantity of second virtual resources is determined from the continuous virtual address space and allocated to the subtask of the second stage, for example, the second virtual resources are also continuous.

[0068] For example, in some examples, before the target task starts to execute, the total quantity of resources required by the target task and the quantity of resources required by each stage are informed to a scheduling module in the graphics processor, and the scheduling module allocates a continuous virtual address space with a size of the total quantity of virtual resources to the target task at one time, and at the same time, allocates the virtual resources required by the subtask of each stage.

[0069] For example, in other examples, the allocation of the virtual resources of each stage can also occur before the subtask of each stage starts to execute and after the subtask of the previous stage is executed. For example, after the subtask of the first stage is executed, the second virtual resources are allocated to the subtask of the second stage.

[0070] In step S50, before the subtask of the first stage is executed and the subtask of the second stage starts to execute, in response to the quantity of the physical resources currently available in the graphics processor being greater than or equal to the second quantity, the second quantity of second physical resources in the physical resources currently available in the graphics processor are mapped to the second virtual resources, so as to execute the subtask of the second stage by using the second physical resources.

[0071] For example, in at least one embodiment of the present disclosure, the allocation of the resources required by the subtask of the second stage is performed only after the subtask of the second stage experiences a waiting time (execution delay) of the execution time of the subtasks of the previous stages and actually starts to execute. At this time, the subtask of the second stage can start to execute when the execution condition (for example, data preparation is completed, a thread bundle is formed, etc.) is met, and if the quantity of the physical resources currently available in the graphics processor is greater than or equal to the second quantity, a mapping relationship between the second virtual resources and the second quantity of second physical resources allocated to the subtask of the second stage is established, the program of the second stage is executed, and the subtask of the second stage is completed.

[0072] For example, the currently available physical resources in the graphics processor can be understood as a resource pool, for example, when the physical resources are register file resources, the resource pool can include idle registers in a plurality of registers pre-allocated to a stream processor performing a target task, and the plurality of idle registers are shared by sub-tasks of a plurality of stages included in the target task. If the number of the plurality of idle registers is greater than or equal to the number of resources required by the sub-task of the current stage, the physical resource application, allocation and mapping of the stage can be performed, for example, including steps S20-S30 or steps S40-S50.

[0073] For example, the second number can also be 0, at this time, the sub-task of the second stage can continue to use the first physical resource to execute the sub-task of the second stage.

[0074] For example, in response to the end of the target task after the execution of the i-th sub-task of the plurality of stages, the sub-tasks of the stages after the i-th sub-task are no longer executed and no physical resources are applied and allocated, and the virtual resources and the physical resources allocated for the first i sub-tasks are released, where i is a positive integer and less than or equal to the total number of the plurality of stages.

[0075] For example, in some scenarios, for a target task, a depth test is first performed on each pixel in a first stage, and further processing is performed on each pixel according to the depth test result in a second stage to output a refraction result. If the depth test result of the first stage indicates that there is occlusion between the pixels, the calculation of the second stage is not needed to be performed, that is, the target task can end in advance, then the sub-task of the second stage and the sub-tasks of the stages after the second stage can no longer be executed, and physical resources are not needed to be applied and allocated, for example, the second physical resources and the mapping relationship between the second physical resources and the second virtual resources are not needed to be applied and established, and at the same time, the first virtual resources and the first physical resources allocated for the sub-task of the first stage are released for subsequent other tasks to continue to use.

[0076] Therefore, in the resource allocation method provided by at least one embodiment of the present disclosure, when some target tasks being executed can end in advance, since the physical resources are applied, allocated and mapped before the sub-tasks of each stage are executed, only a small amount of physical resources are allocated for the target task, which effectively compensates for the delay; and the target task does not need to wait for all the physical resources of all the stages to be in place, and the target task can be executed in advance after the physical resources of the first stage are in place (applied, allocated and mapped), if the program execution result is to end in advance, that is, the sub-tasks of some subsequent stages do not need to be executed, then other tasks executed after the target task can be executed in advance, which greatly improves the processing efficiency.

[0077] Figure 4 A mapping relationship diagram of resource allocation provided by at least one embodiment of the present disclosure.

[0078] As shown in Figure 4 , the target task includes three stages, i.e., a first stage phase0, a second stage phase1, and a third stage phase2, and the subtasks of the three stages are executed in sequence, for example, the subtask of the second stage can be executed after the subtask of the first stage is executed, and the subtask of the third stage can be executed after the subtask of the second stage is executed. Of course, the target task can also include a fourth stage and a fifth stage, which are not shown here.

[0079] The execution process of the resource allocation method provided by at least one embodiment of the present disclosure will be described in detail below in combination with Figure 4 .

[0080] For example, before the target task starts to be executed, a continuous virtual address space is applied according to the total virtual resource quantity required for executing the target task, and at the same time, an attempt is made to apply physical resources according to the total virtual resource quantity, if the quantity of available physical resources is less than the total virtual resource quantity, as long as the quantity of currently available physical resources in the graphics processor is greater than or equal to a first quantity N1 required for executing the subtask of the first stage phase0, the subtask of the first stage phase0 is allocated a first physical resource including N1 physical addresses, and a mapping relationship is established with a first virtual resource including N1 virtual addresses. After that, the subtask of the first stage can start to be executed.

[0081] For example, as shown in Figure 4 , the subtask of the first stage phase0 requires a first quantity N1 of physical resources, N1 continuous virtual addresses are determined from the continuous virtual address space as a first virtual resource, i.e., a, a+1,..., a+N1 in Figure 4 , and N1 physical addresses are determined from the currently available physical resources of the graphics processor, and a one-to-one mapping relationship is established between the N1 physical addresses and the N1 virtual addresses, N1 is a positive integer, and a represents a starting address. As shown in Figure 4 , the N1 virtual addresses are continuous, but the N1 physical addresses do not need to be continuous.

[0082] After the subtask of the first stage phase0 is executed and the subtask of the second stage phase1 starts to be executed, if the quantity of currently available physical resources in the graphics processor is greater than or equal to a second quantity N2 required for executing the subtask of the second stage phase1, the subtask of the second stage phase1 is allocated a second physical resource including N2 physical addresses, and a mapping relationship is established with a second virtual resource including N2 virtual addresses. After that, the subtask of the second stage can start to be executed.

[0083] For example, as shown in Figure 4As shown, executing the subtask of phase 1 in the second stage requires N2 physical resources. N2 consecutive virtual addresses (b, ..., b+N2) are determined from the contiguous virtual address space. Furthermore, N2 physical addresses are determined from the currently available physical resources in the graphics processor. A one-to-one mapping relationship is established between these N2 physical addresses and N2 virtual addresses, where N2 is a positive integer and b represents the starting address. For example... Figure 4 As shown, the N2 virtual addresses are contiguous, but the N2 physical addresses do not need to be contiguous.

[0084] Subsequently, after the subtasks of phase 1 in the second phase have been completed and before the subtasks of phase 2 in the third phase begin execution, if the number of currently available physical resources in the graphics processor is greater than or equal to the third number N3 required to execute the subtasks of phase 2 in the third phase, then a third physical resource consisting of N3 physical addresses is allocated to the subtasks of phase 2 in the third phase, and a mapping relationship is established with a third virtual resource consisting of N3 virtual addresses. For example, the third virtual resource is the third number of virtual resources required to execute the subtasks of the third phase, determined from the contiguous virtual address space allocated for the target task, where N3 is a positive integer. After this, the subtasks of the third phase can begin execution.

[0085] For example, such as Figure 4 As shown, executing the subtask of phase 2 in the third stage requires N3 physical resources. N3 consecutive virtual addresses (c, ..., c+N3) are determined from the contiguous virtual address space. Furthermore, N3 physical addresses are determined from the currently available physical resources of the graphics processor. A one-to-one mapping relationship is established between these N3 physical addresses and the N3 virtual addresses, where c represents the starting address. For example... Figure 5 As shown, the N3 virtual addresses are contiguous, but the N3 physical addresses do not need to be contiguous.

[0086] For any of the above stages, if the program finds that the target has been completed ahead of schedule, for example, after the subtask of the first stage is completed, the calculation result indicates that the subtasks of the second and third stages do not need to be executed, then the subsequent second and third stages do not need to request physical resources or be executed. At the same time, the first virtual resource and the first physical resource that have been requested will be released and made available for use by other subsequent tasks.

[0087] This embodiment significantly improves the utilization efficiency of physical resources (such as register resources), enhancing the parallelism and efficiency of the processor, especially the graphics processor. Furthermore, when executing programs requiring longer latency, only a smaller amount of physical resources need to be allocated in advance to allow this part of the task to execute ahead of time, effectively compensating for latency and keeping the pipeline constantly operational. This effectively masks long-latency operations, avoids pipeline stalls, and improves system performance. In addition, if the execution result of a subtask at a certain stage indicates that the target task has ended early, meaning that some subsequent subtasks no longer need to be executed, other tasks scheduled to execute after the target task can begin execution earlier, significantly improving processing efficiency.

[0088] In the resource allocation method provided in at least one embodiment of this disclosure, since the allocation and mapping of resources are completed in stages, each stage's subtask only needs to map the physical resources required by the current stage's subtask, which places higher demands on the processor's hardware and software design.

[0089] For a compiler, when executing subtasks at each stage, the instructions for those subtasks need to be grouped. For example, the instructions for executing the target task can be grouped according to different stages, so that the instructions for the first stage's subtasks are executed first, and then the instructions for the second stage's subtasks are executed. For example, each group here can include instructions for executing the subtasks of the corresponding stage.

[0090] For example, the resource allocation method provided in at least one embodiment of this disclosure further includes: grouping the instructions required to execute sub-tasks in multiple stages according to the instruction type.

[0091] For example, grouping instructions required to execute sub-tasks in multiple stages according to instruction type may include: assigning instructions of a first type among the instructions required to execute sub-tasks in multiple stages to at least one group for priority execution, for example, instructions of the first type that enable the target task to end early.

[0092] For example, based on the grouping of instructions for the above-mentioned target tasks according to different stages, the first type of instructions, such as depth-related instructions (depth instructions are used to calculate the sequencing depth of each site or region and display it on a standard display device) and pixel discard (shader fragment processing, discarding threads or pixels that do not meet the program conditions), can be placed in a group for priority execution.

[0093] For example, the group assigned to the first type of instruction could be a group of instructions that execute the sub-tasks of the first stage, and the group of instructions for the sub-tasks of the first stage belongs to the first or earlier group.

[0094] For example, the first type of instructions can include depth-related instructions or pixel discard-related instructions, which can cause the current thread bundle or thread to end early, so that subsequent instructions do not need to be executed, for example, sub-tasks of subsequent stages do not need to be executed, and the corresponding physical resources do not need to be applied for, allocated and mapped, thereby improving the utilization efficiency of physical resources and greatly improving the processing efficiency.

[0095] For example, grouping the instructions required for executing the sub-tasks of the plurality of stages according to the instruction types can include: preferentially executing the second type of instructions in the instructions required for executing the sub-tasks of the plurality of stages in at least one group, for example, the second type of instructions have a longer execution time.

[0096] For example, based on the grouping of the instructions of the target task according to different stages, some instructions with a longer execution time, such as sample instructions, data transfer instructions (such as load or store instructions) and the like, can be placed in the first or earlier group for preferential execution, for example, this group can be the group of instructions of the sub-tasks of the first stage that are executed first, or the group of instructions of the sub-tasks of the second stage that are executed earlier. Since the physical resources allocated at one time are less, more threads or thread bundles can be executed in parallel, thereby achieving the effect of compensating for the long latency.

[0097] For example, in at least one embodiment of the present disclosure, the software and the compiler also need to analyze the target task, so as to provide the hardware with the number of physical resources required by each stage. For example, the software and the compiler analyze the target task before the target task starts to execute, and inform the scheduling module in the graphics processor of the total resource quantity required by the target task and the resource quantity required by each stage, and the scheduling module allocates a continuous virtual address space with a size of the total virtual resource quantity to the target task at one time, and also allocates the virtual resources required by the sub-tasks of each stage.

[0098] In at least one embodiment of the present disclosure, the physical resources (such as register file resources) can be more flexibly managed, on the one hand to improve the utilization efficiency of the physical resources and increase the parallelism of the execution of threads or thread bundles, and on the other hand to ensure that a certain amount of physical resources can be reserved, so that the thread bundle that has started to execute can obtain sufficient physical resources at a certain time in the future in a certain way, thereby avoiding deadlock.

[0099] Corresponding to the above resource allocation method, at least one embodiment of the present disclosure also provides a resource allocation apparatus.

[0100] Figure 5 A schematic block diagram of a resource allocation apparatus provided by at least one embodiment of the present disclosure is shown.

[0101] For example, as shown in Figure 2 The resource allocation apparatus 100 comprises an obtaining unit 101, a virtual resource determining unit 102 and a first resource allocation unit 103.

[0102] For example, the resource allocation apparatus 100 is used for a graphics processor. The description of the graphics processor can refer to the description of the aforementioned resource allocation method, which will not be repeated here.

[0103] For example, the obtaining unit 101 is configured to obtain a target task, wherein the target task is divided into a plurality of stage sub-tasks executed in sequence, and the plurality of stages comprises a first stage.

[0104] For example, the virtual resource determining unit is configured to determine a first number of first virtual resources required for executing the sub-task of the first stage.

[0105] For example, the first resource allocation unit 103 is configured to, in response to the number of currently available physical resources in the graphics processor being greater than or equal to the first number, map a first number of first physical resources in the currently available physical resources to the first virtual resources, so as to execute the sub-task of the first stage using the first physical resources.

[0106] For example, when the virtual resource determining unit 102 executes the first number of first virtual resources required for executing the sub-task of the first stage, it comprises the following operations: obtaining a total number of virtual resources required for executing the target task, and allocating a corresponding continuous virtual address space according to the total number of virtual resources; determining a first number of first virtual resources from the continuous virtual address space to be allocated to the sub-task of the first stage.

[0107] For example, when the first resource allocation unit 103 executes the first number of first physical resources in the currently available physical resources to the first virtual resources, so as to execute the sub-task of the first stage using the first physical resources, it comprises the following operations: determining a first number of first physical resources from the currently available physical resources in the graphics processor; establishing a one-to-one mapping relationship between the first virtual resources and the first physical resources.

[0108] For example, the plurality of stages further comprises a second stage, and the sub-task of the second stage is executed after the sub-task of the first stage.

[0109] For example, the resource allocation apparatus further comprises a second resource allocation unit (not shown) configured to: determine a second number of second virtual resources required for executing the sub-tasks of the second stage; and in response to the number of the physical resources currently available in the graphics processor being greater than or equal to the second number before the sub-tasks of the first stage are completed and the sub-tasks of the second stage are started, map a second number of second physical resources from the physical resources currently available to the second virtual resources to execute the sub-tasks of the second stage using the second physical resources.

[0110] For example, in response to the target task being completed after the execution of the i-th sub-task of the plurality of stages, the sub-tasks of the stages executed after the i-th sub-task are no longer executed and no longer apply for and allocate physical resources, and the virtual resources and the physical resources allocated for the first i sub-tasks are released, where i is a positive integer and is less than or equal to the total number of the plurality of stages.

[0111] For example, the resource allocation apparatus further comprises an instruction grouping unit (not shown) configured to group the instructions required for executing the sub-tasks of the plurality of stages according to the instruction types.

[0112] For example, when the instruction grouping unit groups the instructions required for executing the sub-tasks of the plurality of stages according to the instruction types, the grouping comprises: allocating first type instructions required for executing the sub-tasks of the plurality of stages in at least one group to be executed preferentially, where the first type instructions can cause the target task to be completed in advance.

[0113] For example, when the instruction grouping unit groups the instructions required for executing the sub-tasks of the plurality of stages according to the instruction types, the grouping comprises: allocating second type instructions required for executing the sub-tasks of the plurality of stages in at least one group to be executed preferentially, where the second type instructions have a longer execution time.

[0114] For example, the virtual resources allocated for each of the sub-tasks of the stages are continuous, and the physical resources mapped to the virtual resources allocated for each of the sub-tasks of the stages are discontinuous.

[0115] For example, the physical resources comprise register file resources in the graphics processor.

[0116] For example, the acquisition unit 101, the virtual resource determination unit 102, and the first resource allocation unit 103 include code and programs stored in memory; the processor can execute the code and programs to implement some or all of the functions of the acquisition unit 101, the virtual resource determination unit 102, and the first resource allocation unit 103 as described above. For example, the acquisition unit 101, the virtual resource determination unit 102, and the first resource allocation unit 103 can be dedicated hardware devices used to implement some or all of the functions of the acquisition unit 101, the virtual resource determination unit 102, and the first resource allocation unit 103 as described above. For example, the acquisition unit 101, the virtual resource determination unit 102, and the first resource allocation unit 103 can be a circuit board or a combination of multiple circuit boards used to implement the functions described above. In the embodiments of this application, the circuit board or the combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-temporary memories connected to the processor; and (3) firmware executable by the processor and stored in memory.

[0117] It should be noted that the acquisition unit 101 is used to implement Figure 2 In step S10 shown, the virtual resource determination unit 102 is used to implement... Figure 2 In step S20 shown, the first resource allocation unit 103 is used to implement... Figure 2 The step S30 is shown. Therefore, a detailed description of the acquisition unit 101 can be found in the embodiments of the resource allocation method described above. Figure 2 The description of step S10 shown above, and the detailed explanation of the virtual resource determination unit 102, can be found in the embodiments of the resource allocation method described above. Figure 2 The description of step S20 shown above, and the detailed explanation of the first resource allocation unit 103, can be found in the embodiments of the resource allocation method described above. Figure 6 The relevant description of step S30 is shown below. Furthermore, the resource allocation device can achieve similar technical effects to the aforementioned resource allocation method, and will not be elaborated further here.

[0118] At least one embodiment of this disclosure also provides an electronic device. Figure 6 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0119] For example, such as Figure 7 As shown, the electronic device includes a processor 201, a communication interface 202, a memory 203, and a communication bus 204. The processor 201, communication interface 202, and memory 203 communicate with each other via the communication bus 204. The components such as the processor 201, communication interface 202, and memory 203 can also communicate with each other via a network connection. This disclosure does not limit the type and function of the network.

[0120] For example, the memory 203 is configured to store computer-executable instructions non-transitorily. When the processor 201 is configured to execute the computer-executable instructions, the computer-executable instructions are executed by the processor 201 to implement the resource allocation method according to any of the above-described embodiments. For the specific implementation of each step of the resource allocation method and the related explanations, please refer to the above-described embodiments of the resource allocation method, which will not be repeated here.

[0121] For example, the processor 201 executes the program stored in the memory 203 to implement the implementation manner of the resource allocation method, which is the same as the implementation manner mentioned in the above-described embodiment of the resource allocation method, which will not be repeated here.

[0122] For example, the communication bus 204 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or only one type of bus.

[0123] For example, the communication interface 202 is configured to implement the communication between the electronic device and other devices.

[0124] For example, the processor 201 and the memory 203 can be arranged at the server end (or cloud end).

[0125] For example, the processor 201 can control other components in the electronic device to perform the desired functions. The processor 201 can be a central processing unit (CPU), a network processing unit (NP), etc., and can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. The central processing unit (CPU) can be X86 or ARM architecture, etc.

[0126] For example, the memory 203 can include one or more computer program products in any combination, which can include various forms of computer readable storage media, such as volatile memory and / or non-volatile memory. For example, the volatile memory can include random access memory (RAM), cache memory, etc. The non-volatile memory can include read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer-executable instructions can be stored on the computer-readable storage medium, and the processor 201 can execute the computer-executable instructions to implement various functions of the electronic device. Various application programs and various data, etc. can also be stored in the storage medium.

[0127] For example, the detailed description of the process in which the electronic device performs resource allocation can refer to the related description in the embodiments of the resource allocation method, and the repeated parts will not be described again.

[0128] Figure 7 A schematic diagram of a non-transitory computer-readable storage medium is provided for at least one embodiment of the present disclosure. For example, as shown in FIG. 3, one or more computer-executable instructions 301 can be stored non-transitorily on a storage medium 300. For example, when the computer-executable instructions 301 are executed by a processor, one or more steps of the resource allocation method described above can be performed. ​

[0129] For example, the storage medium 300 can be applied in the electronic device and / or the resource allocation apparatus described above. For example, the storage medium 300 can include the memory 203 in the electronic device.

[0130] For example, the description of the storage medium 300 can refer to the description of the memory in the embodiments of the electronic device, and the repeated parts will not be described again.

[0131] Those skilled in the art can understand that the disclosed content of the present disclosure can have various modifications and improvements. For example, the various devices or components described above can be implemented by hardware, or by software, firmware, or a combination of some or all of the three.

[0132] In addition, although the present disclosure makes various references to certain units in the system according to the embodiments of the present disclosure, however, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0133] Flowcharts are used in the present disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the preceding or subsequent steps do not necessarily proceed in sequence. Instead, various steps can be processed in reverse order or simultaneously. Other operations can also be added to these processes.

[0134] Those of ordinary skill in the art can understand that all or part of the steps in the above method can be instructed by a computer program to relevant hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a magnetic disk, or an optical disk. Alternatively, all or part of the steps of the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in the form of hardware or in the form of a software functional module. The present disclosure is not limited to any specific form of combination of hardware and software. ​

[0135] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0136] The foregoing is a summary of the present disclosure and is not to be considered as limiting the disclosure's scope. Although several exemplary embodiments of the present disclosure have been described, it will be understood by those skilled in the art that many modifications can be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. It is to be understood that the above description is illustrative of the disclosure and should not be considered the limiting the particular embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the claims. The disclosure is defined by the claims and their equivalents.

Claims

1. A resource allocation method for a graphics processor, the resource allocation method comprising: Obtain a target task, wherein the target task is divided into multiple sub-tasks in multiple stages and executed sequentially. The multiple stages include a first stage. In the sub-tasks of the multiple stages, the sub-tasks of subsequent stages are processed based on the calculation results of the previously executed sub-tasks. The sub-tasks of subsequent stages are executed after the previously executed sub-tasks have been completed. Determine the first quantity of first virtual resources required to execute the sub-tasks of the first phase; In response to the number of currently available physical resources in the graphics processor being greater than or equal to the first number, the first number of the currently available physical resources is mapped to the first virtual resource to execute the sub-task of the first stage using the first physical resource; In response to the fact that the number of currently available physical resources in the graphics processor is less than the first number, it is determined that the subtask of the first stage will not be executed; The physical resources include the register file resources in the graphics processor; The resource allocation method further includes: Determine a second number of second virtual resources required to execute the subtask of the i-th stage, where i is a positive integer greater than 1 and less than or equal to the total number of the plurality of stages; Before the subtask of the (i-1)th stage is completed and the subtask of the ith stage begins to be executed, in response to the number of currently available physical resources in the graphics processor being greater than or equal to the second number, the second number of second physical resources currently available in the graphics processor are mapped to the second virtual resources so as to use the second physical resources to execute the subtask of the ith stage. In response to i being less than the total number of the plurality of stages, and after the execution of the subtask of the i-th stage, the execution result of the subtask of the i-th stage indicates the end of the target task. Subtasks of each stage executed after the subtask of the i-th stage will no longer be executed and will not request or allocate physical resources. At the same time, the virtual and physical resources allocated to all subtasks executed before the subtask of the i-th stage will be released.

2. The resource allocation method according to claim 1, wherein, Determine the first quantity of first virtual resources required to execute the subtasks of the first phase, including: Obtain the total number of virtual resources required to execute the target task, and allocate corresponding contiguous virtual address space according to the total number of virtual resources; The first number of consecutive first virtual resources are determined from the contiguous virtual address space and allocated to the subtasks of the first phase.

3. The resource allocation method according to claim 1, wherein, Mapping the first number of first physical resources from the currently available physical resources to the first virtual resources, so as to use the first physical resources to execute the sub-tasks of the first phase, includes: The first quantity of the first physical resources is determined from the currently available physical resources of the graphics processor; Establish a one-to-one mapping relationship between the first virtual resource and the first physical resource.

4. The resource allocation method according to any one of claims 1-3, further comprising: The instructions required to execute the sub-tasks of the multiple stages are grouped according to the instruction type.

5. The resource allocation method according to claim 4, wherein, The instructions required to execute the subtasks of the multiple stages are grouped according to the instruction type, including: The first type of instructions required to execute the sub-tasks of the multiple stages are assigned to at least one group for priority execution, wherein the first type of instructions enables the target task to end early.

6. The resource allocation method according to claim 4, wherein, The instructions required to execute the subtasks of the multiple stages are grouped according to the instruction type, including: The second type of instructions, which are required to execute the sub-tasks of the multiple stages, are assigned to at least one group for priority execution, wherein the second type of instructions have a longer execution time.

7. The resource allocation method according to any one of claims 1-3, wherein, The virtual resources allocated to the sub-tasks of each stage are contiguous, while the physical resources that establish a mapping relationship with the virtual resources allocated to the sub-tasks of each stage are discontinuous.

8. A resource allocation device for a graphics processor, the resource allocation device comprising: The acquisition unit is configured to acquire a target task, wherein the target task is divided into multiple sub-tasks in multiple stages and executed sequentially. The multiple stages include a first stage. In the sub-tasks of the multiple stages, the sub-tasks of subsequent stages are processed based on the calculation results of the previously executed sub-tasks. The sub-tasks of subsequent stages are executed after the previously executed sub-tasks have been completed. The virtual resource determination unit is configured to determine a first number of first virtual resources required to execute the sub-tasks of the first stage; The first resource allocation unit is configured to, in response to the number of currently available physical resources in the graphics processor being greater than or equal to the first number, map the first number of the first physical resources in the currently available physical resources to the first virtual resources to use the first physical resources to execute the sub-task of the first stage, and in response to the number of currently available physical resources in the graphics processor being less than the first number, determine not to execute the sub-task of the first stage. The physical resources include the register file resources in the graphics processor; The resource allocation device is further configured to: Determine a second number of second virtual resources required to execute the subtask of the i-th stage, where i is a positive integer greater than 1 and less than or equal to the total number of the plurality of stages; Before the subtask of the (i-1)th stage is completed and the subtask of the ith stage begins to be executed, in response to the number of currently available physical resources in the graphics processor being greater than or equal to the second number, the second number of second physical resources currently available in the graphics processor are mapped to the second virtual resources so as to use the second physical resources to execute the subtask of the ith stage. In response to i being less than the total number of the plurality of stages, and after the execution of the subtask of the i-th stage, the execution result of the subtask of the i-th stage indicates the end of the target task. Subtasks of each stage executed after the subtask of the i-th stage will no longer be executed and will not request or allocate physical resources. At the same time, the virtual and physical resources allocated to all subtasks executed before the subtask of the i-th stage will be released.

9. The resource allocation device according to claim 8, wherein, When the virtual resource determination unit determines the first number of first virtual resources required to execute the sub-task of the first stage, it includes performing the following operations: Obtain the total number of virtual resources required to execute the target task, and allocate corresponding contiguous virtual address space according to the total number of virtual resources; The first number of consecutive first virtual resources are determined from the contiguous virtual address space and allocated to the subtasks of the first phase.

10. The resource allocation device according to claim 8, wherein, When the first resource allocation unit performs the operation of mapping the first number of first physical resources from the currently available physical resources to the first virtual resources, so as to use the first physical resources to perform the sub-tasks of the first stage, it includes performing the following operations: The first quantity of first physical resources is determined from the currently available physical resources of the graphics processor; Establish a one-to-one mapping relationship between the first virtual resource and the first physical resource.

11. The resource allocation apparatus according to any one of claims 8-10, further comprising an instruction grouping unit, The instruction grouping unit is configured to group the instructions required to execute the sub-tasks of the multiple stages according to the instruction type.

12. An electronic device, comprising: Memory stores computer-executable instructions non-transiently; The processor is configured to run computer-executable instructions. The computer-executable instructions are executed by the processor to implement the resource allocation method according to any one of claims 1-7.

13. A non-transitory computer-readable storage medium, wherein, The non-transitory computer-readable storage medium stores computer-executable instructions that, when executed by a processor, implement the resource allocation method according to any one of claims 1-7.

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