A method for simulating radiation effects of SRAM type FPGA

Abstract

This invention discloses a radiation effect simulation method for SRAM-type FPGAs. It combines device-level and circuit-level modeling simulation to simulate the combined effects of total dose and single-event effects on the FPGA, analyzing the impact of various radiation effects on the FPGA's operating state. This method solves the problems of limited accelerator resources, difficulty in adjusting irradiated particle energy, and high economic costs. It helps to understand the changes in internal micro-parameters of the device and reveal the damage mechanism, enabling the evaluation of the device's radiation damage sensitivity. It provides technical support for FPGA radiation resistance evaluation and hardening design, and is economical and convenient. It can be used to evaluate the radiation resistance of devices, contributing to improved device reliability in aerospace engineering applications.

Description

Technical Field

[0001] This invention relates to a method for studying the radiation effects of electronic devices, specifically a method for simulating the radiation effects of an SRAM-type FPGA. Background Technology

[0002] With the rapid development of aerospace technology, the integration level of integrated circuits is becoming increasingly higher, and various electronic components are widely used in spacecraft. The complex space radiation environment poses serious radiation safety problems for electronic components and their circuits. Studying the space radiation effects of semiconductor devices and their circuits and improving their radiation resistance has become an important research direction in microelectronics both domestically and internationally in recent years. As a core control device for aerospace products, SRAM-type FPGAs are widely used in aerospace electronic products due to their high density, small size, low power consumption, and semi-custom characteristics. The performance of FPGAs directly affects the technical specifications and reliability of the entire electronic device. The radiation environment in space applications may cause FPGA performance degradation, and in severe cases, may lead to functional errors or even failures, causing serious malfunctions to spacecraft. Therefore, in-depth research on the space radiation effects of SRAM-type FPGAs is particularly important.

[0003] The space radiation effects of FPGA chips mainly include single-event effects and total dose effects. Ground-based irradiation tests are a common technique for studying the synergistic effects of total dose and single-event effects on devices, and can accurately assess the radiation resistance of devices. However, irradiation tests suffer from limited resources, high costs, and limited irradiation conditions, making it difficult to grasp changes in the device's internal micro-parameters and hindering the revelation of damage mechanisms. Furthermore, the limited resources of particle accelerators, the difficulty in adjusting irradiated particle energy, and high economic costs restrict related research. In contrast, studying radiation effects through simulation allows for flexible adjustment of irradiation conditions, linear energy transfer (LET), and other parameters. It enables the analysis of the influence of various radiation effects in SRAM-type FPGAs from the perspective of the device's internal micro-parameters, compensating for the limitations of accelerators and representing an effective technical approach.

[0004] Ground-based heavy ion accelerator irradiation tests are a commonly used technique for evaluating the single-event sensitivity of devices and can accurately assess the radiation resistance of devices. However, ground-based heavy ion accelerator tests have problems such as limited accelerator resources, difficulty in adjusting the energy of irradiated particles, and high economic costs. Summary of the Invention

[0005] Purpose of the invention: To address the aforementioned existing technologies, this invention proposes a radiation effect simulation method for SRAM-based FPGAs. This method can simulate the combined effects of total dose and single-event effects on the FPGA, analyze the impact of various radiation effects on the FPGA's operating state, and solve the problems of limited accelerator resources, difficulty in adjusting irradiated particle energy, and high economic costs.

[0006] Technical solution: A method for simulating radiation effects in an SRAM-based FPGA, comprising the following steps:

[0007] Step 1: Based on the size, structure and process parameters of the core unit MOS device in the FPGA, the MOS device is modeled in three dimensions using the semiconductor device simulation platform TCAD to obtain a three-dimensional structural model of the MOS device. The three-dimensional structural model is then meshed using a three-dimensional model meshing tool to generate a meshed device structure.

[0008] Step 2: Perform TCAD device simulation on the gridded device structure to obtain the transfer and output characteristic curves of the MOS device. Then compare it with the corresponding electrical characteristic curves in the product manual of the MOS device with the same process. Optimize and calibrate the channel layer thickness, barrier layer thickness, gate-drain spacing, P-type gate doping concentration or barrier layer composition process parameters of the device. Finally, make the TCAD device simulation results match the corresponding electrical characteristic curves in the device product manual.

[0009] Step 3: Based on the optimized model in Step 2, add a total dose effect simulation module, define the device oxide layer trap charge density and interface state charge density, perform total dose effect simulation on the MOS device, and obtain the electrical characteristic degradation of the device under different irradiation doses; then import the degraded transfer and output characteristic curve data into the device parameter extraction software to extract the SPICE parameters of the TCAD device after total dose irradiation.

[0010] Step 4: Add a single-event effect simulation module to the total dose effect simulation model constructed in Step 3, define the incident angle, incident depth, track radius, charge generation pulse characteristics and peak time parameters of the incident ions, perform single-event effect simulation on the MOS device, and obtain the single-event drain transient current value at different positions.

[0011] Step 5: Use the circuit-level simulation tool HSPICE to write a circuit netlist file, construct the equivalent circuit of the FPGA key module CLB, and replace the called MOS parameters in the circuit netlist file with the SPICE parameters extracted in step 3 to realize circuit-level modeling and simulation of the total dose effect of the FPGA.

[0012] Step 6: Fit the single-event drain transient current values ​​at different locations obtained in Step 4 using a double exponential model to obtain their rise time constant and fall time constant. Then, in the equivalent circuit established in Step 5, use an external current source as a fault injection into the drain of the off-state MOS transistor in the SRAM memory cell to realize the circuit-level simulation of the FPGA single-event effect.

[0013] Step 7: Based on the output voltages of different nodes obtained from the simulations in Steps 5 and 6, analyze the impact of total dose effect and single-event effect on the FPGA operating state.

[0014] Furthermore, in step 1, when performing mesh generation, the mesh is refined in the channel, doped region, and electrode boundary region of the MOS.

[0015] Furthermore, in step 5, the basic unit of the CLB is a SLICE, and each SLICE consists of a six-input lookup table, a carry-lookahead adder, and a rising-edge D flip-flop. Each six-input lookup table consists of 64 SRAM memory cells and 63 2-to-1 data selectors. An address is input through six input control bits to look up the corresponding content in the SRAM and then output it. The result of the six-input lookup table serves as one input to the carry-lookahead adder, and the carry output of the first adder serves as the carry input to the second adder. Changes in the result will affect the output of the second adder. The result of the carry-lookahead adder serves as the input signal to the rising-edge D flip-flop, and the CLK pulses and output results of the two D flip-flops are independent of each other.

[0016] Beneficial Effects: This invention proposes a radiation effect simulation method for SRAM-type FPGAs, which combines device-level modeling and simulation with circuit-level modeling and simulation. SPICE parameters are extracted from the MOS transistors after total dose irradiation and replaced in the circuit. This achieves simulation of the synergistic effect of total dose and single-event effects on the FPGA, analyzing the impact of various radiation effects on the FPGA's operating state. It solves the problems of limited accelerator resources, difficulty in adjusting irradiated particle energy, and high economic costs. It helps to understand the changes in internal micro-parameters of the device and reveal the damage mechanism, enabling the evaluation of the device's radiation damage sensitivity. This provides technical support for FPGA radiation resistance evaluation and hardening design, and is economical and convenient. It can be used to evaluate the radiation resistance of devices, helping to improve the reliability of devices in aerospace engineering applications. Attached Figure Description

[0017] Figure 1 This is a flowchart of the method of the present invention;

[0018] Figure 2 The diagram shows the structure of a MOS device, where (a) is a nmos cell structure and (b) is a pmos cell structure.

[0019] Figure 3 The figures show the transfer characteristic curves of MOS devices, where (a) represents an NMOS transistor and (b) represents a PMOS transistor.

[0020] Figure 4The output characteristic curves of the MOS devices are shown, where (a) is an NMOS transistor and (b) is a PMOS transistor.

[0021] Figure 5 Single-event transient current plot (LET = 5 MeV·cm) 2 / mg);

[0022] Figure 6 This is a structural diagram of the basic unit slice of a CLB;

[0023] Figure 7 This is a schematic diagram of a fault injection circuit in a circuit-level model simulation.

[0024] Figure 8 The waveform diagram of the rising edge D flip-flop D#1 outputting the F1 logic level toggling;

[0025] Figure 9 The waveform diagram shows the logic level of the output F2 of the rising edge D flip-flop D#2. Detailed Implementation

[0026] The invention will now be further explained with reference to the accompanying drawings.

[0027] like Figure 1 As shown, a method for simulating radiation effects in an SRAM-based FPGA includes the following steps:

[0028] Step 1: As Figure 2 The diagram shows the structural schematic of the MOS device, the core unit of an FPGA. Based on the dimensions and process parameters of the device to be simulated, a 3D model of the device is created using the semiconductor device simulation platform TCAD, resulting in the 3D structural model of the MOS device, the core unit of the FPGA. The specific steps for obtaining the parameters and creating the 3D model of the device to be simulated are as follows:

[0029] Step 1.1: Obtain the structure and process parameters from device process data or relevant literature, and establish a three-dimensional model containing information on device structure, structural dimensions, and doping concentration;

[0030] Step 1.2: Select the appropriate process materials for each component of the device to be simulated, so that the process materials set during simulation are the same as the actual process materials of that component;

[0031] Step 1.3: Set the device to be simulated in the following order to obtain the three-dimensional structural model of the device: substrate thickness, buffer layer thickness, channel layer thickness, barrier layer thickness, P-type gate thickness, electrode thickness, barrier layer composition, doping concentration of the P-type gate, and electrode contact; the overall device model structure has a lateral width of 0.1 μm, a vertical width of 0.1 μm, and a height of 0.2 μm; the substrate material used is Si, with a doping concentration of 1 × 10⁻⁶. 18 cm -3 .

[0032] Step 2: Use a 3D model meshing tool to mesh the 3D structural model obtained in Step 1, generating a meshed device structure that matches the actual device structure. Specifically, the mesh is refined at key locations such as channels, doped regions, and electrode boundaries. Fine meshing is performed near the gate oxide structure region, which significantly affects electrical parameters and radiation effects, using a step size of 0.02 nm or even lower. The remaining regions are meshed with a step size of 0.1-0.5 nm.

[0033] Step 3: Perform TCAD device simulation on the meshed device structure to obtain the transfer and output characteristic curves of the MOS device, such as... Figure 3 , Figure 4 As shown, the threshold voltage of NMOS is 0.3V, and the threshold voltage of PMOS is -0.3V. By comparing the corresponding electrical characteristic curves in the datasheets of MOS devices using the same process, the channel layer thickness, barrier layer thickness, gate-drain spacing, P-type gate doping concentration, or barrier layer composition process parameters of the device are optimized and calibrated. Ultimately, the TCAD device simulation results are made to match the corresponding electrical characteristic curves in the device datasheet. For example, if the curve does not reach a typical trend, the doping concentration of the device structure is changed to make the characteristic curve exhibit the typical trend of MOS.

[0034] Step 4: Based on the model obtained in Step 3, add a total dose effect simulation module, and define the oxide layer trap charge density as 7.5 × 10⁻⁶ using interface and inttrap statements. 11 cm -2 The density of the interface state charge is 3.1 × 10⁻⁶. 7 cm -2 Total dose effect simulation was performed on the MOS device to obtain the degradation of its electrical characteristics under different irradiation doses. Then, the degraded transfer and output characteristic curve data were imported into UTMOST4 software, and the basic parameters of the BSIM4 model were used for fitting to extract the SPICE parameters of the TCAD device after total dose irradiation.

[0035] Step 5: Add a single-event effect simulation module to the total dose effect simulation model constructed in Step 4 for co-simulation. Specifically, define the particle trajectory radius of the incident ion as 0.02 μm, the incident depth as penetrating the device, the incident angle as perpendicular, the peak time of the generated charge pulse as 4 ps, and the characteristic time of the charge pulse as 2 ps. Perform single-event effect simulation on the MOS device to obtain the single-event drain transient current values ​​at different locations. For example... Figure 5 As shown, LET = 5 MeV·cm 2 Single-particle drain transient current value at / mg.

[0036] Step 6: Use the circuit-level simulation tool HSPICE to create a circuit netlist file and construct the equivalent circuit of the FPGA's key module CLB (Configurable Logic Block). For example... Figure 6 As shown, the basic unit of the CLB is a SLICE, each consisting of a six-input lookup table (LUT), a carry-lookahead adder, and a rising-edge D flip-flop. Each six-input lookup table (LUT) is composed of 64 SRAM memory cells and 63 2-to-1 data selectors. An address is input via six input control bits to look up the corresponding content in the SRAM and then output it. The result of the six-input lookup table serves as one input to the carry-lookahead adder. The carry output of the first adder serves as the carry input to the second adder, and changes to the result affect the output of the second adder. The result of the carry-lookahead adder serves as the input signal to the rising-edge D flip-flop. The CLK pulses and output results of the two D flip-flops are independent of each other. The MOS parameters are replaced with the SPICE parameters extracted in step 4 in the circuit netlist file to achieve circuit-level modeling and simulation of the total dose effect on the FPGA.

[0037] Step 7: As Figure 7 The diagram shows a typical SRAM 6-transistor memory cell structure, mainly composed of four NMOS transistors and two PMOS transistors. Conventionally, M1 and M3 are called pull-down NMOS transistors, M2 and M4 are called pull-up PMOS transistors or load PMOS transistors, and M5 and M6 are called on-state NMOS transistors. M1 and M2, and M3 and M4, each form two inverters, which are connected end-to-end to form a bistable structure, storing two logically opposite pieces of information. The single-event drain transient current values ​​obtained in step 5 are fitted using a double exponential model to obtain their rise time constant and fall time constant. Then, in the equivalent circuit established in step 6, an AC current source is injected into the drain of the off-state MOS transistor in the SRAM memory cell (i.e., the IN node in the diagram), realizing circuit-level simulation of the FPGA single-event effect.

[0038] Step 8: Inject the single-event drain transient current value obtained in Step 5 into the drain of the off-state NMOS transistor (IN49) in SRAM#49. At this time, SRAM#49 will undergo a single-event flip. When SRAM#49 flips, the single-event error will propagate downwards, causing the data read by lookup table LUT#1 to change, and the output of LUT#1 will change from 0 to 1. When the logic level of the output Q4 of LUT#1 flips, the results of the accumulation output sum1 and carry output count1 of the next stage carry lookup amplifier ADD#1 in the device will also change. The value of the accumulation output sum1 changes from 1 to 0, and the value of the carry output count1 changes from 0 to 1. When the logic level of the accumulation output sum1 of ADD#1 flips, the value of the output F1 of the rising edge D flip-flop D#1 changes from 1 to 0. The logic level flip waveform is as follows. Figure 8 As shown; when the logic level of the accumulated output sum2 of ADD#2 toggles, the value of the output F2 of D flip-flop D#2 changes from 0 to 1 on the rising edge, and the logic level toggling waveform is as follows. Figure 9 As shown.

[0039] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for simulating radiation effects on an SRAM-based FPGA, characterized in that, Includes the following steps: Step 1: Based on the size, structure and process parameters of the core unit MOS device in the FPGA, the MOS device is modeled in three dimensions using the semiconductor device simulation platform TCAD to obtain a three-dimensional structural model of the MOS device. The three-dimensional structural model is then meshed using a three-dimensional model meshing tool to generate a meshed device structure. Step 2: Perform TCAD device simulation on the gridded device structure to obtain the transfer and output characteristic curves of the MOS device. Then compare it with the corresponding electrical characteristic curves in the product manual of the MOS device with the same process. Optimize and calibrate the channel layer thickness, barrier layer thickness, gate-drain spacing, P-type gate doping concentration or barrier layer composition process parameters of the device. Finally, make the TCAD device simulation results match the corresponding electrical characteristic curves in the device product manual. Step 3: Based on the optimized model in Step 2, add a total dose effect simulation module, define the device oxide layer trap charge density and interface state charge density, perform total dose effect simulation on the MOS device, and obtain the electrical characteristic degradation of the device under different irradiation doses; then import the degraded transfer and output characteristic curve data into the device parameter extraction software to extract the SPICE parameters of the TCAD device after total dose irradiation. Step 4: Add a single-event effect simulation module to the total dose effect simulation model constructed in Step 3, define the incident angle, incident depth, track radius, charge generation pulse characteristics and peak time parameters of the incident ions, perform single-event effect simulation on the MOS device, and obtain the single-event drain transient current value at different positions. Step 5: Use the circuit-level simulation tool HSPICE to write a circuit netlist file, construct the equivalent circuit of the FPGA key module CLB, and replace the called MOS parameters in the circuit netlist file with the SPICE parameters extracted in step 3 to realize circuit-level modeling and simulation of the total dose effect of the FPGA. Step 6: Fit the single-event drain transient current values ​​at different locations obtained in Step 4 using a double exponential model to obtain their rise time constant and fall time constant. Then, in the equivalent circuit established in Step 5, use an external current source as a fault injection into the drain of the off-state MOS transistor in the SRAM memory cell to realize the circuit-level simulation of the FPGA single-event effect. Step 7: Based on the output voltages of different nodes obtained from the simulations in Steps 5 and 6, analyze the impact of total dose effect and single-event effect on the FPGA operating state.

2. The radiation effect simulation method for SRAM-type FPGA according to claim 1, characterized in that, In step 1, when performing mesh generation, the mesh is refined in the MOS channel, doped region, and electrode boundary region.

3. The radiation effect simulation method for SRAM-type FPGA according to claim 1, characterized in that, In step 5, the basic unit of CLB is SLICE. Each SLICE consists of a six-input lookup table, a carry-lookahead adder, and a rising-edge D flip-flop. Each six-input lookup table consists of 64 SRAM memory cells and 63 2-to-1 data selectors. An address is input through 6 input control bits to look up the table, find the corresponding content in the SRAM, and then output it. The result of the six-input lookup table will be used as one input of the carry-lookahead adder. The carry output of the first adder will be used as the carry input of the second adder. Changes in the result will affect the output of the second adder. The result of the carry-lookahead adder will be used as the input signal of the rising-edge D flip-flop. The CLK pulses and output results of the two D flip-flops are independent of each other.

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