Integrated circuit layout for a filter and integrated circuit layout method

Abstract

An integrated circuit layout and an integrated circuit layout method for a filter are disclosed. The method includes determining an architecture of a target filter, including capacitors and first selected components; dividing a capacitor reserved region; disposing the first selected components in the capacitor reserved region and electrically connecting the first selected components to a plurality of first external nodes outside the capacitor reserved region through a plurality of first lines in a first metal layer; electrically connecting the first external nodes to a plurality of second lines in a second metal layer and disposed around the capacitor reserved region, respectively; and disposing the capacitors in the capacitor reserved region and above the first selected components. The capacitors have oppositely disposed first and second metal plates and are located in two of the second metal layer and at least one third metal layer above the second metal layer.

Description

Technical Field

[0001] The present invention relates to an integrated circuit layout and an integrated circuit layout method, and in particular to an integrated circuit layout and an integrated circuit layout method for a filter. Background Art

[0002] Filter is a mainstream circuit used to filter out high-frequency electronic noise or specific frequency electronic noise. Please refer to Figures 1 to 4 , which are respectively the first to fourth schematic diagrams of the existing filter circuit.

[0003] like Figures 1 to 4 As shown, filters used in integrated circuits are generally composed of resistors and capacitors, or transistors and capacitors. The transistors, resistors, and capacitors are selected to minimize their area to reduce wafer manufacturing costs. Currently, circuit designers are seeking to achieve even greater area savings and higher area utilization, considering cost structures.

[0004] Further references Figure 5 , which is the layout diagram of the existing filter circuit. Figure 5 As shown, this filter 5 employs a field-effect transistor 50 and a capacitor 52, wherein a plurality of metal wires ML1 of the field-effect transistor 50 are located in a first metal layer above the field-effect transistor 50, and a plurality of metal wires ML2 are located in a second metal layer above the field-effect transistor 50. The metal wires ML1 are connected to the metal wires ML2 via a dielectric layer V1 having vias, and the second metal layer is above the first metal layer, while the capacitor 52 is disposed next to the field-effect transistor 50. However, this layout requires reserving the usable area for both the field-effect transistor 50 and the capacitor 52. Furthermore, because the capacitor 52 only utilizes the metal plates MP2, MP3, and MP4 located in the upper metal layer, the space in the lower metal layer is not used, and thus optimal area utilization cannot be achieved.

[0005] Therefore, improving circuit layout to save area to achieve higher area utilization and overcome the above-mentioned defects has become one of the important issues that this industry wants to solve. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide an integrated circuit layout and an integrated circuit layout method for a filter, which can increase the area utilization of capacitors and reduce the coupling area of ​​external noise, in response to the shortcomings of the existing technology.

[0007] To solve the above-mentioned technical problems, one of the technical solutions adopted by the present invention is to provide an integrated circuit layout method for a filter, which includes: determining the architecture of a target filter, wherein the target filter includes a capacitor and a first optional component, and the first optional component is a first resistor or a first fin field-effect transistor; dividing a capacitor reservation area at a predetermined position in a circuit layout; disposing the first optional component in the capacitor reservation area and electrically connecting the first optional component to a plurality of first external nodes outside the capacitor reservation area through a plurality of first circuits located in a first metal layer; electrically connecting the first external nodes to a plurality of second circuits located in a second metal layer, wherein the second circuits are arranged around the capacitor reservation area and the second metal layer is above the first metal layer; disposing the capacitor in the capacitor reservation area and above the first optional component, wherein the capacitor has a first metal plate and a second metal plate arranged opposite to each other, and the first metal plate and the second metal plate are respectively located in two of the second metal layer and at least one third metal layer located above the second metal layer.

[0008] In order to solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide an integrated circuit layout for a filter, which includes a target filter, a plurality of first circuits and a plurality of second circuits. The target filter is arranged at a predetermined position in a circuit layout, and includes a capacitor and a first optional component, wherein the first optional component is a first resistor or a first transistor, and is arranged in a capacitor retention area. The plurality of first circuits are located in a first metal layer, and are respectively used to electrically connect the first optional component to a plurality of first external nodes outside the capacitor retention area. The plurality of second circuits are located in a second metal layer and are arranged around the capacitor retention area, and are respectively used to electrically connect the first external nodes, wherein the second metal layer is above the first metal layer. The capacitor is arranged in the capacitor retention area and above the first optional component, and the capacitor has a first metal plate and a second metal plate arranged relative to each other, and the first metal plate and the second metal plate are respectively located in the second metal layer and two of the at least one third metal layer above it.

[0009] One of the beneficial effects of the present invention is that the integrated circuit layout and integrated circuit layout method for the filter provided by the present invention can guide multiple external nodes of the first optional element and / or the second optional element to the periphery of the capacitor retention area through the wiring arranged in the first metal layer. Therefore, the capacitor is allowed to be arranged above the first optional element and the second optional element to utilize multiple unused metal layers. In addition to increasing the capacitor area utilization rate, it can also reduce the area used by the filter by approximately 50%, thereby reducing the wafer area cost and the external noise coupling area.

[0010] To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only for reference and explanation and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 4 They are the first to fourth schematic diagrams of existing filter circuits respectively.

[0012] Figure 5 This is a layout diagram of an existing filter circuit.

[0013] Figure 6 FIG. 1 is a flow chart of a method for layout of an integrated circuit for a filter according to a first embodiment of the present invention.

[0014] Figure 7A and Figure 7B 1 and 2 are respectively a first schematic top view and a second schematic top view of an integrated circuit layout for a filter according to a first embodiment of the present invention.

[0015] Figure 8 for Figure 7B , a side view schematically shown along section line AA.

[0016] Figure 9 FIG. 4 is a flow chart of an integrated circuit layout method for a filter according to a second embodiment of the present invention.

[0017] Figure 10A and Figure 10B 1 and 2 are respectively a first schematic top view and a second schematic top view of an integrated circuit layout for a filter according to a second embodiment of the present invention.

[0018] Figure 11 for Figure 10B , a side view schematically shown along section line BB.

[0019]

Explanation of symbols

[0020] 5: Filter

[0021] 7, 8: Integrated Circuit Layout

[0022] 50: Field Effect Transistor

[0023] 52, 700, 800: capacitors

[0024] 70, 80: Target filter

[0025] 702, 802: First FinFET

[0026] 804, 806: resistor

[0027] AA, BB: hatching

[0028] B1, B2: substrate

[0029] F1, F2, F3: Fins

[0030] L1: First Line

[0031] L2: Second Line

[0032] L3: Third Line

[0033] L4: The fourth line

[0034] M1: First metal layer

[0035] M2: Second metal layer

[0036] M3: The third metal layer

[0037] M30: Metal

[0038] M4: fourth metal layer

[0039] ML1, ML2: Metal wiring

[0040] MP11: First Metal Plate

[0041] MP12: Second Metal Plate

[0042] MP13: Third Metal Plate

[0043] MP2, MP3, MP4: Metal plate

[0044] N1: First external node

[0045] N2: Second external node

[0046] R1, R2: Capacitor reserved area

[0047] V1, V12, V12', V23, V34: dielectric layer DETAILED DESCRIPTION

[0048] The following is an explanation of the implementation methods of the "integrated circuit layout and integrated circuit layout method for filters" disclosed in the present invention through specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depicted according to actual dimensions. It is stated in advance. The following embodiments will further explain the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the scope of protection of the present invention. In addition, the term "or" used in this article may include any one or more combinations of the associated listed items depending on the actual situation.

[0049] [First embodiment]

[0050] See Figures 6 to 8 , Figure 6 is a flow chart of a method for layout of an integrated circuit for a filter according to a first embodiment of the present invention. Figure 7A and Figure 7B are respectively a first schematic top view and a second schematic top view of an integrated circuit layout for a filter according to a first embodiment of the present invention, Figure 8 for Figure 7B , a side view schematically shown along section line AA.

[0051] like Figure 6 As shown, the first embodiment of the present invention provides an integrated circuit layout method for a filter, which includes the following steps:

[0052] Step S60: Determine the architecture of the target filter.

[0053] refer to Figures 1 to 4 The composition of the existing filter circuit shown is Figure 7A In the integrated circuit layout 7, the target filter 70 may include a capacitor 700 and a first optional component, and the first optional component may be a resistor or a fin field effect transistor. Figure 7A and Figure 7B In the figure, the first fin field effect transistor 702 is taken as an example as the first optional component, which includes fins F1, F2 and a substrate B1 as shown in the figure.

[0054] Step S61: dividing a capacitor reservation area at a predetermined position in the circuit layout.

[0055] like Figure 7A As shown, the circuit layout 7 is divided into a capacitance retention area R1 in the top view.

[0056] Step S62 : disposing a first optional component in the capacitor reserved region, and electrically connecting the first optional component to a plurality of first external nodes outside the capacitor reserved region through a plurality of first circuits in the first metal layer.

[0057] by Figure 7A For example, the first fin field effect transistor 702 can be disposed in the capacitor retention region R1, and the first fin field effect transistor 702 is electrically connected to a plurality of first external nodes N1 outside the capacitor retention region R1 through a plurality of first lines L1 located in the first metal layer M1. These external nodes N1 are used to electrically connect to the source, drain, and gate of the first fin field effect transistor 702, respectively, and the number of the source, drain, and gate is not limited to Figure 7A Architecture. Figure 5 In contrast, in the embodiment of the present invention, the first external nodes N1 are further designed outside the capacitor reserved region R1. Moreover, from a top view, the shape of the capacitor reserved region R1 is substantially the same as the shape and size of the area to be occupied by the capacitor 700. Therefore, the capacitor reserved region R1 is not limited to Figure 7A The rectangle shown may also be a circle or a polygon.

[0058] Step S63 : electrically connecting the first external nodes to a plurality of second circuits in the second metal layer respectively.

[0059] like Figure 7A As shown, a plurality of second lines L2 in the second metal layer M2 are arranged around the capacitor retention area R1 and are electrically connected to the first external nodes N1 respectively, and the second metal layer M2 is above the first metal layer M1. In some embodiments, a portion of the second lines L2 can be arranged on the first side of the capacitor retention area R1 (e.g. Figure 7A The other part of the second lines L2 can be arranged on the second side of the capacitor retention area R1, for example Figure 7A The middle capacitor remains below region R1.

[0060] In addition, if Figure 7A 、 7B and Figure 8 As shown, each of the second lines L2 can be electrically connected to the corresponding first line L1 through the dielectric layer V12 having the via hole.

[0061] Step S64: placing a capacitor in the capacitor reserved area and above the first optional component.

[0062] like Figure 7B As shown, the capacitor 700 is in the capacitor retention region R1 and above the first FinFET 702 , and has a first metal plate MP11 and a second metal plate MP12 that are oppositely disposed.

[0063] According to different circuit design requirements, the first metal plate MP11 and the second metal plate MP12 can be respectively located on the second metal layer M2 and two of the multiple metal layers above it. Figure 8 As an example of the 1P4M process shown in FIG. 1 , the third metal layer M3 and the fourth metal layer M4 are disposed above the second metal layer M2. The first metal plate MP11 and the second metal plate MP12 are defined as the bottom layer and the top layer of the capacitor 700, respectively. Figure 8 , the first metal plate MP11 is disposed in the second metal layer M2, and the second metal plate MP12 is disposed in the fourth metal layer M4 and is electrically connected to the second metal plate MP12. However, the present invention does not limit the selection of the first metal plate MP11 and the second metal plate MP12. For example, the first metal plate MP11 and the second metal plate MP12 can be selected from the second metal layer M2 to the seventh metal layer (not shown) according to design requirements. In other words, the capacitor 700 can be disposed in the second metal layer M2 and multiple metal layers additionally disposed thereon, and the number thereof can be 1, 2, 3, 4, or 5. All metal plates or metals disposed in the second metal layer M2 to the seventh metal layer can be made of conductive metal plates, such as aluminum plates, steel plates, copper plates, unaltered steel plates, aluminum plates, etc.

[0064] The first metal plate MP11 can be electrically connected to the second metal plate MP12 via dielectrics V23 and V34 having conductive vias and metal M30. A third metal plate MP13 located on a third metal layer M3 is also disposed between the first and second metal plates MP11, MP12, and multiple gaps within the first, second, and third metal plates MP11, MP12, and MP13 are filled with dielectric material. In this configuration, the capacitor formed between the first and third metal plates MP11, MP13 can be connected in parallel with the capacitor formed between the second and third metal plates MP11, MP13. However, the configuration of the capacitor 700 provided in this embodiment is merely illustrative and is not intended to limit the present invention.

[0065] In addition, it should be noted that the first FinFET 702 as the first optional component is not higher than the first metal layer M1 to avoid occupying the available space of the capacitor 700 .

[0066] Therefore, if Figure 7B As shown, in the circuit layout 7 for the filter generated by the integrated circuit layout method provided by the present invention, the capacitor 700 is arranged on the first fin field effect transistor 702, and the first fin field effect transistor 702 guides the external nodes N1 to the periphery of the capacitor reserved area R1 through the first wirings L1, so that the capacitor 700 can use the second metal layer M2 to the fourth metal layer M4. Figure 5In terms of circuit layout, the filter capacitor does not reduce the number of metal layers required for excessive capacitance due to the wiring of the field-effect transistor, thereby reducing the capacitance per unit area. It can also reduce the area used by about 50%, thereby reducing wafer area cost and external noise coupling area.

[0067] [Second embodiment]

[0068] See Figures 9 to 11 , Figure 9 is a flow chart of an integrated circuit layout method for a filter according to a second embodiment of the present invention. Figure 10A and Figure 10B are respectively a first schematic top view and a second schematic top view of an integrated circuit layout for a filter according to a second embodiment of the present invention, Figure 11 for Figure 10B , a side view schematically shown along section line BB.

[0069] You can refer to it first Figures 1 to 4 as well as Figure 6 , the target filter 80 of this embodiment may further include a second optional component, which may also be a resistor or a fin field effect transistor. In the first embodiment, since the first optional component has adopted the first fin field effect transistor 702, this embodiment adopts resistors 804 and 806 as the second optional component. Therefore, Figure 10B As shown, the target filter 80 determined in step S60 may include a capacitor 800 , a first FinFET 802 , and resistors 804 and 806 .

[0070] like Figure 9 As shown, the integrated circuit layout method according to the second embodiment of the present invention may further include the following steps:

[0071] Step S90 : disposing the second optional component in the capacitor reserved area without overlapping the first optional component, and electrically connecting the second optional component to a plurality of second external nodes outside the capacitor reserved area through a plurality of third circuits in the first metal layer.

[0072] by Figure 10A For example, with Figure 7A Similar to the integrated circuit layout 8, the first FinFET 802 includes a fin F3 and a substrate B2, is disposed in the capacitor retention region R2, and is electrically connected to a plurality of first external nodes N1 outside the capacitor retention region R1 via a plurality of first lines L1 in the first metal layer M1.

[0073] On the other hand, the second optional component may include, for example, resistors 804 and 806, which are disposed in the capacitor retention region R2 and do not overlap with the first FinFET 802. The resistors 804 and 806 are electrically connected to a plurality of second external nodes N2 outside the capacitor retention region R2 via a plurality of third lines L3 disposed in the first metal layer M1. The layout of the resistors 804 and 806 is well known to those skilled in the art and will not be described in detail herein. Figure 10A exemplarily illustrates its structure and the connection relationship with the second external nodes N2.

[0074] and Figure 5 In contrast, in the embodiment of the present invention, the second external nodes N2 are further designed outside the capacitor reserved region R2. Moreover, from a top view, the shape of the capacitor reserved region R2 is substantially the same as the shape and size of the area to be occupied by the capacitor 800. Therefore, the capacitor reserved region R2 is not limited to Figure 10A The rectangle shown may also be a circle or a polygon.

[0075] Step S91 : electrically connecting the second external nodes to a plurality of fourth circuits located in the second metal layer respectively.

[0076] This embodiment and Figure 7A The similarities are omitted here. Figure 10A In the embodiment of the present invention, a plurality of fourth lines L4 in the second metal layer M2 are arranged around the capacitor reserved region R2 and are electrically connected to the second external nodes N2. It should be noted that the fourth lines L4 are arranged around the capacitor reserved region R2 and do not overlap with the second lines L2.

[0077] In some embodiments, a portion of the fourth lines L4 may be disposed on a first side of the capacitor retention region R2 (eg, Figure 10A The other part of the second lines L2 may be disposed on the second side of the capacitor retention area R2, for example Figure 10A The middle capacitor remains below region R2.

[0078] In addition, if Figure 10A 、 10B and Figure 11 As shown, each of the fourth lines L4 can be electrically connected to the corresponding third line L3 through the dielectric layer V12 ′ having the via hole.

[0079] Step S92: placing a capacitor above the second optional component.

[0080] like Figure 10BAs shown, capacitor 800 is disposed in capacitor retention region R2 and above first FinFET 802 and resistors 804 and 806. Similar to the first embodiment, the second optional component, such as resistors 804 and 806, should not be higher than the first metal layer M1.

[0081] Therefore, if Figure 10B As shown, in the circuit layout 8 for the filter generated by the integrated circuit layout method provided by the present invention, the capacitor 800 is arranged above the first fin transistor 802 and the resistors 804 and 806. In addition, the first fin transistor 802 guides the external nodes N1 to the periphery of the capacitor reserved area R2 through the first wirings L1, and the resistors 804 and 806 guide the external nodes N2 to the periphery of the capacitor reserved area R2 through the third wirings L3, so that the capacitor 700 can use the second metal layer M2 to the fourth metal layer M4. Therefore, relative to Figure 5 In terms of circuit layout, the filter capacitor does not reduce the number of metal layers required for excessive capacitance due to the wiring of the field-effect transistor, thereby reducing the capacitance per unit area. It can also reduce the area used by about 50%, thereby reducing wafer area cost and external noise coupling area.

[0082] [Beneficial Effects of Embodiments]

[0083] In summary, the integrated circuit layout and integrated circuit layout method for the filter provided by the present invention can guide multiple external nodes of the first optional element and / or the second optional element to the periphery of the capacitor reserved area through the wiring arranged in the first metal layer. Therefore, the capacitor is allowed to be arranged above the first optional element and the second optional element to utilize multiple unused metal layers. In addition to increasing the capacitor area utilization, it can also reduce the area used by the filter by approximately 50%, thereby reducing the wafer area cost and the external noise coupling area.

[0084] The contents disclosed above are only preferred feasible embodiments of the present invention and do not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the contents of the description and drawings of the present invention are included in the scope of the patent application of the present invention.

Claims

1. A method for layout of an integrated circuit for a filter, characterized in that: include: Determining a target filter structure, wherein the target filter includes a capacitor and a first optional component, and the first optional component is a first resistor or a first fin field effect transistor; dividing a capacitor reservation area at a predetermined position in a circuit layout; The first optional component is disposed in the capacitor reserved region, and the first optional component is electrically connected to a plurality of first external nodes outside the capacitor reserved region through a plurality of first circuits located in a first metal layer; electrically connecting the plurality of first external nodes to a plurality of second circuits located in a second metal layer, wherein the plurality of second circuits are disposed around the capacitor reserved area and the second metal layer is above the first metal layer; and The capacitor is arranged in the capacitor retention area and above the first optional element, wherein the capacitor has a first metal plate and a second metal plate arranged opposite to each other, and the first metal plate and the second metal plate are respectively located in two of the second metal layer and at least a third metal layer above it.

2. The integrated circuit layout method according to claim 1, wherein: The target filter further includes a second optional element. In response to the first optional element being the first resistor, the second optional element is a second fin field effect transistor. In response to the first optional element being the fin field effect transistor, the second optional element is a second resistor.

3. The integrated circuit layout method according to claim 2, wherein: Also includes: The second optional element is disposed in the capacitor reserved area without overlapping with the first optional element, and the second optional element is electrically connected to a plurality of second external nodes outside the capacitor reserved area through a plurality of third circuits located in the first metal layer; electrically connecting the plurality of second external nodes to a plurality of fourth circuits located in the second metal layer, respectively, wherein the plurality of fourth circuits are disposed around the capacitor reserved area and do not overlap with the plurality of second circuits; as well as The capacitor is disposed above the second optional component.

4. An integrated circuit layout for a filter, characterized in that include: A target filter is disposed at a predetermined position in a circuit layout and includes a capacitor and a first optional component, wherein the first optional component is a first resistor or a first transistor and is disposed in a capacitor reservation area; a plurality of first circuits located in a first metal layer, respectively used to electrically connect the first optional component to a plurality of first external nodes outside the capacitor reserved area; as well as A plurality of second lines are located in a second metal layer and are arranged around the capacitor reserved area, and are respectively used to electrically connect the plurality of first external nodes, wherein the second metal layer is above the first metal layer. The capacitor is arranged in the capacitor retention area and above the first optional element. The capacitor has a first metal plate and a second metal plate arranged opposite to each other, and the first metal plate and the second metal plate are respectively located in two of the second metal layer and at least one third metal layer above it.

5. The integrated circuit layout according to claim 4, wherein: The first optional component is no higher than the first metal layer.

6. The integrated circuit layout of claim 4, wherein: The target filter further includes a second optional element. In response to the first optional element being the first resistor, the second optional element is a second transistor. In response to the first optional element being the first transistor, the second optional element is a second resistor.

7. The integrated circuit layout according to claim 6, wherein: The second optional component is disposed in the capacitor retention area and does not overlap with the first optional component, and the integrated circuit layout further includes: a plurality of third lines located in the first metal layer, respectively used to electrically connect the second optional component to a plurality of second external nodes outside the capacitor reserved area; and A plurality of fourth lines are located in the second metal layer and are electrically connected to the plurality of second external nodes respectively, wherein the plurality of fourth lines are arranged around the capacitor reserved area and do not overlap with the plurality of second lines. Wherein, the capacitor is arranged above the second optional component.

8. The integrated circuit layout according to claim 7, wherein: The second optional element is no higher than the first metal layer.

9. The integrated circuit layout of claim 4, wherein: A portion of the plurality of second lines is disposed on a first side of the capacitor reservation area, and another portion of the plurality of second lines is disposed on a second side of the capacitor reservation area.

10. The integrated circuit layout according to claim 4, wherein: The number of the at least one third metal layer is 1, 2, 3, 4 or 5.

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