A method, apparatus, electronic device, and readable storage medium for layout data processing

Abstract

The present application relates to the field of integrated circuits, and discloses a layout data processing method, apparatus, device, and storage medium, including selecting a plurality of target chips from a chip combination arranged on a photomask to match a guard ring; the chip combination includes a plurality of different types of chips; obtaining the individual layout data of each target chip, the layout data of the guard ring, and the layout data of an identification layer; the identification layer includes a chamfer identification unit, the chamfer identification unit is correspondingly arranged with a chamfer protection body on the guard ring, and the projection of the chamfer identification unit on the chamfer protection body completely covers the chamfer protection body; exporting the individual layout data of each target chip, the layout data of the guard ring, and the layout data of the identification layer. The present application can solve the problem of splicing the guard ring with different chips, avoid repeatedly modifying the chip layout data, and facilitate modifying the layout data of a single chip; it is not limited by the chip area and can flexibly combine the MPW layout positions.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and particularly to a layout data processing method, apparatus, electronic device, and computer-readable storage medium. Background Art

[0002] During the dicing process of a chip, delamination or cracking is likely to occur. Delamination appears at the edge of the chip and gradually extends from the edge towards the inside. A chip seal ring is a ring between the chip and the dicing slot, surrounding the chip on all sides, which can effectively reduce the stress damage to the chip during dicing.

[0003] In the mask publishing for product R & D or verification, the seal ring is usually verified, which is particularly common in the new product R & D and tape-out (design completion) stage of MPW (Multi Project Wafer). When verifying an extremely large seal ring, the area of a single chip cannot fill the internal area of the seal ring, and multiple chips need to be spliced together. Currently, when processing layout data, the chip manufacturer (fab) first prepares the overall chip layout, then combines multiple different types of chips onto a single mask for layout, thereby forming a complete mask, and then combines the seal ring with the chips into a whole to obtain the layout data of the whole and gives the layout data to the mask factory. There are the following defects: multiple different chips need to be combined, and the combination is single; when the layout of a single chip is modified, since the chips are spliced, the overall chip layout is affected, and the layout designs of multiple chips need to be modified.

[0004] Therefore, how to solve the above technical problems should be the focus of attention of those skilled in the art. Summary of the Invention

[0005] The purpose of the present application is to provide a layout data processing method, apparatus, electronic device, and computer-readable storage medium to facilitate the processing of layout data.

[0006] To solve the above technical problems, the present application provides a layout data processing method, including:

[0007] Selecting a plurality of target chips from the chip combinations laid out on the mask to match the seal ring; the chip combinations include a plurality of different types of chips;

[0008] Obtaining the individual layout data of each of the target chips, the layout data of the seal ring, and the layout data of the identification layer; the identification layer includes a chamfer identification unit, the chamfer identification unit is correspondingly arranged with a chamfer protection body on the seal ring, and the projection of the chamfer identification unit on the chamfer protection body completely covers the chamfer protection body;

[0009] Export the individual layout data of each of the target chips, the layout data of the guard ring, and the layout data of the identification layer, wherein the individual layout data of each chip, the layout data of the guard ring, and the layout data of the identification layer are independent data.

[0010] Optionally, the shape of the chamfer identification unit in the identification layer is the same as the shape of the chamfer protection body on the guard ring.

[0011] Optionally, the shape of the chamfer identification unit is any one of a triangle, a quadrilateral, a pentagon, and a hexagon.

[0012] Optionally, before selecting multiple target chips from the chip combination arranged on the photomask to match the guard ring, it further includes:

[0013] Obtain the overall layout data of the chips arranged on the photomask to determine the chip combination.

[0014] Optionally, the overall layout data of the chips is GDS format layout data.

[0015] This application also provides a layout data processing device, including:

[0016] A chip selection module, configured to select multiple target chips from the chip combination arranged on the photomask to match the guard ring; the chip combination includes multiple different types of chips;

[0017] A data acquisition module, configured to acquire the individual layout data of each of the target chips, the layout data of the guard ring, and the layout data of the identification layer; the identification layer includes a chamfer identification unit, the chamfer identification unit is correspondingly arranged with the chamfer protection body on the guard ring, and the projection of the chamfer identification unit on the chamfer protection body completely covers the chamfer protection body;

[0018] A data export module, configured to export the individual layout data of each of the target chips, the layout data of the guard ring, and the layout data of the identification layer, wherein the individual layout data of each of the target chips, the layout data of the guard ring, and the layout data of the identification layer are independent data.

[0019] Optionally, it further includes:

[0020] A layout acquisition module, configured to acquire the overall layout data of the chips arranged on the photomask to determine the chip combination.

[0021] This application also provides an electronic device, including:

[0022] A memory, configured to store a computer program;

[0023] A processor for implementing the steps of any of the above layout data processing methods when executing the computer program.

[0024] The present application further provides a computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of any of the above layout data processing methods are implemented.

[0025] A layout data processing method provided by the present application includes: selecting a plurality of target chips from a chip combination arranged on a photomask to match a guard ring; the chip combination includes a plurality of different types of chips; obtaining the individual layout data of each of the target chips, the layout data of the guard ring, and the layout data of an identification layer; the identification layer includes a chamfer identification unit, the chamfer identification unit is correspondingly arranged with a chamfer protection body on the guard ring, and the projection of the chamfer identification unit on the chamfer protection body completely covers the chamfer protection body; exporting the individual layout data of each of the target chips, the layout data of the guard ring, and the layout data of the identification layer, wherein the individual layout data of each of the target chips, the layout data of the guard ring, and the layout data of the identification layer are independent data respectively.

[0026] It can be seen that an identification layer is added in the processing of the present application, the layout data of each target chip, the layout data of the guard ring, and the layout data of the identification layer are separately obtained, and each layout data is exported as independent data. Since the chips combined in the present application are processed separately, there is no need to modify the chip design, splice and combine the chips and the guard ring, and process the overall combination after splicing; and since the projection of the chamfer identification unit on the chamfer protection body completely covers the chamfer protection body, the graphics overlapping the chip and the chamfer protection body can be removed through data logical operations, solving the problem of splicing the guard ring with a plurality of chips of different sizes and shapes, and avoiding repeated modification of the chip layout and data. The layout data of each target chip is processed independently, which is convenient for modifying the layout data of any single target chip within the guard ring without affecting other chips, simplifies the processing process, and is not limited by the chip area, and can freely and flexibly combine the MPW layout positions.

[0027] In addition, the present application further provides a device, an electronic device, and a computer-readable storage medium having the above advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] To more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0029] Figure 1 Flowchart of a layout data processing method provided by an embodiment of the present application;

[0030] Figure 2 Schematic diagram of a guard ring provided by an embodiment of the present application;

[0031] Figure 3 Schematic diagram of an identification layer provided by an embodiment of the present application;

[0032] Figure 4 Schematic diagram of the splicing effect of an identification layer, each chip, and a guard ring provided by an embodiment of the present application;

[0033] Figure 5 Structural block diagram of a layout data processing device provided by an embodiment of the present application;

[0034] Figure 6 Structural block diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0035] In order to enable those skilled in the art to better understand the solutions of the present application, the following further elaborates on the present application in conjunction with the drawings and specific implementation manners. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope protected by the present application.

[0036] Many specific details are set forth in the following description in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described herein. Those skilled in the art can make similar generalizations without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0037] As described in the background art section, currently when processing layout data, the fab factory needs to combine multiple different types of chips and then give the overall layout data of the chips and the guard ring to the mask factory. There are the following defects: multiple different chips need to be combined, and the combination is single; when the layout of a single chip is modified, since the chips are spliced, the overall chip layout is affected, and the layout designs of multiple chips need to be modified.

[0038] In view of this, the present application provides a method for processing layout data. Please refer to Figure 1 , including:

[0039] Step S101: Select a plurality of target chips from the chip combination arranged on the photomask to match the guard ring; the chip combination includes multiple different types of chips.

[0040] The chips in the chip combination are all the chips when arranged on a single photomask. In the present application, the number of chips in the chip combination is not limited, which can be as few as several or as many as dozens or hundreds, depending on the specific situation.

[0041] After the target chips are spliced and combined, they match the size of the guard ring. The size of the guard ring is less than or equal to the size of the photomask and greater than the size of one chip. That is, the number of target chips is more than two and less than or equal to the number of all chips in the chip combination.

[0042] The process of selecting the target chips can refer to the prior art and will not be elaborated in detail in the present application.

[0043] Optionally, in an embodiment of the present application, before selecting a plurality of target chips from the chip combination arranged on the photomask to match the guard ring, it further includes:

[0044] Obtain the overall layout data of the chips arranged on the photomask to determine the chip combination.

[0045] Generally, the overall layout data of the chips is GDS format layout data. Of course, it can also be other forms of layout data, which are all within the protection scope of the present application.

[0046] Step S102: Obtain the individual layout data of each of the target chips, the layout data of the guard ring, and the layout data of the identification layer; the identification layer includes a chamfer identification unit, the chamfer identification unit is correspondingly arranged with the chamfer protection body on the guard ring, and the projection of the chamfer identification unit on the chamfer protection body completely covers the chamfer protection body.

[0047] There are two ways to obtain the individual layout data of the target chips.

[0048] As an implementable manner, the individual layout data of all chips in the chip combination can be obtained, and then the individual layout data of the target chips can be selected from the individual layout data of all chips. Among them, obtaining the individual layout data of all chips in the chip combination can be carried out either before selecting the target chips to match the guard ring or after selecting the target chips to match the guard ring.

[0049] As another implementable manner, directly obtain only the individual layout data of the target chips.

[0050] The schematic diagram of the protection ring is as shown in Figure 2 Figure 4. The protection ring 1 is provided with chamfered protection bodies 11 at four corners of the protection ring 1, and the chamfered protection bodies 11 are generally triangular in shape. The protection ring is a large integral ring structure.

[0051] The schematic diagram of the identification layer is as shown in Figure 3 Figure 5. The identification layer 2 includes four chamfered identification units 21, and each chamfered identification unit 21 corresponds to a chamfered protection body 11. The identification layer 2 is a virtual layer arranged in a certain way. After adding the identification layer 2, the schematic diagram of the splicing effect of each chip 3 and the protection ring 1 is as shown in Figure 4 Figure 6.

[0052] The projection of the chamfered identification unit on the chamfered protection body completely covers the chamfered protection body, that is, the area of the chamfered identification unit is greater than or equal to the area of the chamfered protection body. The purpose is to remove the overlapping graphics of the chip and the chamfered protection body on the protection ring through data logic operations to avoid process contamination.

[0053] Optionally, as an implementable manner, the shape of the chamfered identification unit in the identification layer is the same as the shape of the chamfered protection body on the protection ring. However, the present application does not limit this. As another implementable manner, the shape of the chamfered identification unit in the identification layer may also be different from the shape of the chamfered protection body on the protection ring.

[0054] The shape of the chamfered identification unit includes but is not limited to any one of a triangle, a quadrilateral, a pentagon, and a hexagon.

[0055] The determination processes of the single layout data of each chip, the layout data of the protection ring, and the layout data of the identification layer are well known to those skilled in the art and will not be elaborated here in detail.

[0056] Step S103: Export the single layout data of each of the target chips, the layout data of the protection ring, and the layout data of the identification layer, where the single layout data of each of the target chips, the layout data of the protection ring, and the layout data of the identification layer are independent data.

[0057] Suppose there are N (N≥2) different types of target chips for splicing and combination. In the prior art when determining the layout data, after splicing N target chips with the protection ring, the overall layout data is determined, and then this overall layout data is sent to the mask factory for processing. In this embodiment, however, the N target chips are processed separately to obtain N pieces of layout data regarding the target chips, and then the layout data of the protection ring and the identification layer are determined respectively. That is, in this embodiment, (N + 2) pieces of layout data are determined and exported.

[0058] Since the individual layout data of each chip, the layout data of the guard ring, and the layout data of the identification layer are independent data, they can be modified and processed independently, which is very convenient.

[0059] The individual layout data of the exported chips, the layout data of the guard ring, and the layout data of the identification layer are generally sent to the mask factory. Therefore, what the mask factory obtains are the individual layout data of each individual chip, the layout data of the guard ring, and the layout data of the identification layer. The layout data of the identification layer can be processed independently without the need to be jointly processed with other chips, and at the same time, it is more convenient to process the chip layout data.

[0060] In the process of this application, an identification layer is added. The layout data of each chip, the layout data of the guard ring, and the layout data of the identification layer are obtained separately, and each layout data is exported as independent data. Since the chips combined in this application are processed separately, there is no need to modify the chip design, splice and combine the chip and the guard ring, and process the overall combination; and since the projection of the chamfer identification unit on the chamfer protection body completely covers the chamfer protection body, the graphics overlapping the chip and the chamfer protection body can be removed through data logical operations, solving the problem of splicing the guard ring with multiple chips of different sizes and shapes, and avoiding repeated modification of the chip layout and data. The layout data of each target chip is processed independently, which is convenient for modifying the layout data of any single target chip within the guard ring, and does not affect the simplification of the processing of other chips. At the same time, it is not limited by the chip area and can freely and flexibly combine the MPW layout positions. And it can also minimize the impact on the layout typesetting and save the layout area.

[0061] The following introduces the layout data processing device provided by the embodiments of the present invention. The description of the layout data processing device below can be mutually referred to the layout data processing method described above. Please refer to Figure 5 , Figure 5 which is a structural block diagram of a layout data processing device provided by an embodiment of the present application. The device includes:

[0062] A chip selection module 100, configured to select multiple target chips from a chip combination arranged on a mask to match the guard ring; the chip combination includes multiple different types of chips;

[0063] A data acquisition module 200, configured to acquire the individual layout data of each of the target chips, the layout data of the guard ring, and the layout data of the identification layer; the identification layer includes a chamfer identification unit, the chamfer identification unit is correspondingly arranged with a chamfer protection body on the guard ring, and the projection of the chamfer identification unit on the chamfer protection body completely covers the chamfer protection body;

[0064] A data export module 300 is used to export the individual layout data of each of the target chips, the layout data of the guard ring, and the layout data of the identification layer. Among them, the individual layout data of each of the target chips, the layout data of the guard ring, and the layout data of the identification layer are independent data respectively.

[0065] The layout data processing device of this embodiment is used to implement the foregoing layout data processing method. Therefore, the specific implementation manners in the layout data processing device can be seen in the embodiment part of the layout data processing method in the foregoing text. For example, the chip selection module 100, the data acquisition module 200, and the data export module 300 are respectively used to implement steps S101, S102, and S103 in the above layout data processing method. Therefore, the specific implementation manners can refer to the descriptions of the corresponding individual embodiments and will not be elaborated here.

[0066] Optionally, the layout data processing device further includes:

[0067] A layout data acquisition module is used to acquire the overall layout data of the chips arranged on the photomask to determine the chip combination.

[0068] Next, the electronic device provided by the embodiment of the present invention will be introduced. The electronic device described below can be correspondingly referred to the layout data processing method described above. Please refer to Figure 6 , Figure 6 which is a structural block diagram of an electronic device provided by an embodiment of the present application, including:

[0069] A memory 11 is used to store a computer program;

[0070] A processor 12 is used to implement the steps of the layout data processing method described in any of the above embodiments when executing the computer program.

[0071] Next, the computer-readable storage medium provided by the embodiment of the present invention will be introduced. The computer-readable storage medium described below can be correspondingly referred to the layout data processing method described above.

[0072] The present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the layout data processing method described in any of the above embodiments are implemented.

[0073] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple. For the relevant parts, please refer to the description in the method part.

[0074] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods for each specific application to implement the described functions, but such implementation should not be considered as exceeding the scope of the present invention.

[0075] The steps of the methods or algorithms described in combination with the embodiments disclosed herein can be directly implemented by hardware, software modules executed by a processor, or a combination of the two. The software modules can be placed in a random access memory, internal memory, read-only memory, electrically programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disk, removable disk, or any other form of storage medium known in the art.

[0076] The above has introduced in detail a layout data processing method, apparatus, electronic device, and computer-readable storage medium provided by the present application. Specific examples are used herein to elaborate on the principles and implementation manners of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A layout data processing method, characterized in that, Including: Selecting a plurality of target chips from a chip combination arranged on a photomask to match a guard ring; The chip combination includes a plurality of different types of chips; Obtaining the individual layout data of each of the target chips, the layout data of the guard ring, and the layout data of an identification layer; the identification layer includes a chamfer identification unit, the chamfer identification unit is correspondingly arranged with a chamfer protection body on the guard ring, and the projection of the chamfer identification unit on the chamfer protection body completely covers the chamfer protection body; Exporting the individual layout data of each of the target chips, the layout data of the guard ring, and the layout data of the identification layer, wherein the individual layout data of each of the target chips, the layout data of the guard ring, and the layout data of the identification layer are independent data respectively.

2. The layout data processing method according to claim 1, wherein The shape of the chamfer identification unit in the identification layer is the same as the shape of the chamfer protection body on the guard ring.

3. The layout data processing method according to claim 1, wherein The shape of the chamfer identification unit is any one of a triangle, a quadrilateral, a pentagon, and a hexagon.

4. The layout data processing method according to any one of claims 1 to 3, characterized in that Before selecting a plurality of target chips from a chip combination arranged on a photomask to match a guard ring, it further includes: Obtaining the overall layout data of the chips arranged on the photomask to determine the chip combination.

5. The layout data processing method according to claim 4, wherein The overall layout data of the chips is GDS format layout data.

6. A layout data processing device, characterized in that, Including: A chip selection module, configured to select a plurality of target chips from a chip combination arranged on a photomask to match a guard ring; the chip combination includes a plurality of different types of chips; A data acquisition module, configured to obtain the individual layout data of each of the target chips, the layout data of the guard ring, and the layout data of an identification layer; the identification layer includes a chamfer identification unit, the chamfer identification unit is correspondingly arranged with a chamfer protection body on the guard ring, and the projection of the chamfer identification unit on the chamfer protection body completely covers the chamfer protection body; A data export module, configured to export the individual layout data of each of the target chips, the layout data of the guard ring, and the layout data of the identification layer, wherein the individual layout data of each of the target chips, the layout data of the guard ring, and the layout data of the identification layer are independent data respectively.

7. The layout data processing device according to claim 6, wherein It further includes: An overall layout data acquisition module, configured to obtain the overall layout data of the chips arranged on the photomask to determine the chip combination.

8. An electronic device, characterized in that, Including: A memory, configured to store a computer program; A processor, configured to implement the steps of the layout data processing method according to any one of claims 1 to 5 when executing the computer program.

9. A computer-readable storage medium, characterized in that, A computer program is stored on a computer-readable storage medium, and when the computer program is executed by a processor, the steps of the layout data processing method according to any one of claims 1 to 5 are implemented.

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