Macrocell layout method, apparatus, and computer readable storage medium

Abstract

The application discloses a macro cell layout method, equipment and computer readable storage medium, and relates to the technical field of integrated circuits. The macro cell layout method comprises the following steps: obtaining circuit netlist information to be laid out and a trained layout model; preprocessing the circuit netlist information to be laid out to obtain a current layout state; inputting the current layout state into the trained layout model to obtain a first to-be-placed position of a macro cell to be placed in the current layout state; updating the current layout state according to the first to-be-placed position to obtain a new current layout state, and inputting the new current layout state into the trained layout model again; after obtaining the first to-be-placed positions of all the macro cells to be placed in the circuit netlist information to be laid out, generating a corresponding macro cell layout result, and performing macro cell layout based on the macro cell layout result. The application solves the technical problem that the current macro cell layout method has poor layout effect.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and particularly relates to a macro cell layout method, equipment and computer readable storage medium. BACKGROUND

[0002] In the current chip design process, the physical design of a very large scale integrated circuit (VLSI) can be roughly divided into five stages of floor planning, placement, clock tree synthesis, routing and sign off. The main steps of floor planning include IO (Input / Output) layout, macro cell layout, power planning and physical cell placement.

[0003] In the existing method, the traditional method for macro cell layout mainly uses heuristic algorithms combined with two methods of representation and resolution. However, the macro cell positions obtained by the heuristic algorithms combined with the representation method are often relatively compact, which easily causes congestion; and the resolution method mixes and places the macro cells and standard cells together, which easily leads to a large number of overlaps between the macro cells, and the differences between the macro cells and the standard cells also make it difficult to legalize subsequently. Therefore, the layout effect of the existing macro cell layout method is poor. SUMMARY

[0004] The main purpose of the present application is to provide a macro cell layout method, which aims to solve the technical problem of poor layout effect of the existing macro cell layout method.

[0005] To achieve the above purpose, the present application provides a macro cell layout method, which comprises the following steps:

[0006] Obtaining circuit netlist information to be laid out and a trained layout model;

[0007] Pretreating the circuit netlist information to be laid out to obtain a current layout state;

[0008] Inputting the current layout state into the trained layout model to obtain a first to-be-placed position of a macro cell to be placed in the current layout state;

[0009] Updating the current layout state according to the first to-be-placed position to obtain a new current layout state, and performing the step of inputting the current layout state into the trained layout model to obtain a first to-be-placed position of a macro cell to be placed in the current layout state;

[0010] After obtaining the first placement position of all the macro cells to be placed in the circuit netlist information to be laid out, a corresponding macro cell layout result is generated, and macro cell layout is performed based on the macro cell layout result.

[0011] Optionally, the step of pre-processing the circuit netlist information to be laid out to obtain the current layout state comprises:

[0012] Macro cell feature information and macro cell connection information are obtained from the circuit netlist information to be laid out;

[0013] The preset layout area is divided to obtain each partition grid;

[0014] According to the macro cell feature information, the macro cell density of each partition grid is determined, and a macro cell density map of the preset layout area is generated according to the macro cell density;

[0015] According to the macro cell connection information, a macro cell line network hypergraph of the preset layout area is generated;

[0016] The macro cell feature information is feature-extracted to obtain macro cell node features;

[0017] The metadata of the circuit netlist information to be laid out is feature-extracted to obtain metadata features;

[0018] According to the macro cell feature information and a preset constraint condition, a real-time legal mask matrix of the preset layout area is determined;

[0019] The macro cell density map, the macro cell line network hypergraph, each macro cell node feature, the metadata features, and the real-time legal mask matrix are taken as the current layout state.

[0020] Optionally, the step of determining the real-time legal mask matrix of the preset layout area according to the macro cell feature information and a preset constraint condition comprises:

[0021] The placement feature information of the macro cell to be placed and the placement feature information of the macro cell already placed in the macro cell feature information are obtained;

[0022] According to the placement feature information and the placement feature information, a corresponding placement result of the macro cell to be placed in each partition grid is traversed based on a preset constraint condition, wherein the placement result includes that the macro cell to be placed overlaps with the macro cell already placed, the macro cell to be placed exceeds the preset layout area, and the macro cell to be placed is allowed to be placed;

[0023] The to-be-placed macro unit is overlapped with the placed macro unit, and a segmentation grid corresponding to the to-be-placed macro unit exceeding a preset layout area is marked as an illegal position;

[0024] The to-be-placed macro unit is overlapped with the placed macro unit, and a segmentation grid corresponding to the to-be-placed macro unit exceeding a preset layout area is marked as an illegal position;

[0025] Based on the illegal position and the legal position, a corresponding real-time legal mask matrix is constructed.

[0026] Optionally, the trained layout model includes a trained graph neural network, a trained convolutional neural network, and a trained policy network, and the step of inputting the current layout state into the trained layout model to obtain a first to-be-placed position of a to-be-placed macro unit in the current layout state includes:

[0027] The macro unit density graph is input into the trained convolutional neural network to obtain corresponding macro unit density features;

[0028] The macro unit node features and the macro unit line network supergraph are input into the trained graph neural network to obtain corresponding macro unit global node features, and to-be-placed node features in the macro unit global node features are determined;

[0029] The macro unit global node features are averaged to obtain corresponding global average features;

[0030] According to the macro unit global node features and the to-be-placed node features, attention node features are generated based on a preset multi-head attention mechanism;

[0031] The macro unit density features, the global average features, the attention node features, and the metadata features are spliced into macro unit composite features;

[0032] The macro unit composite features and the real-time legal mask matrix are input into the trained policy network to obtain a first to-be-placed position of a to-be-placed macro unit in the current layout state.

[0033] Optionally, the step of inputting the macro unit composite features and the real-time legal mask matrix into the trained policy network to obtain a first to-be-placed position of a to-be-placed macro unit in the current layout state includes:

[0034] The macro unit composite features are input into the trained policy network to obtain corresponding action probability distributions;

[0035] According to the real-time legal mask matrix, the action probability distributions are legalized to obtain legal probability distributions;

[0036] According to the legal probability distributions, a first to-be-placed position of a to-be-placed macro unit in the current layout state is determined.

[0037] Optionally, before the step of obtaining the circuit netlist information to be laid out and the trained layout model, comprising:

[0038] Obtaining a circuit netlist training set and an untrained layout model;

[0039] Preprocessing the circuit netlist training set to obtain a training layout state;

[0040] Inputting the training layout state into the untrained layout model to obtain a second placement position of a training macro cell in the training layout state;

[0041] Updating the training layout state according to the second placement position, obtaining a new training layout state, and performing the step of inputting the training layout state into the untrained layout model to obtain a second placement position of a training macro cell in the training layout state;

[0042] After obtaining the second placement position of all training macro cells in the circuit netlist training set, generating a corresponding training layout result;

[0043] Calling a preset layout tool to perform standard cell layout and global routing based on the training layout result to obtain a layout and routing result;

[0044] According to the layout and routing result and a preset reward function, a corresponding current reward value is calculated;

[0045] Based on the current reward value, the parameters of the untrained layout model are updated until the untrained layout model converges, obtaining a trained layout model.

[0046] Optionally, the step of calculating a corresponding current reward value according to the layout and routing result and a preset reward function comprises:

[0047] Inputting the layout and routing result into a pre-trained measurement model to measure the total bus length, congestion degree and timing of the layout and routing result;

[0048] According to the total bus length, the congestion degree and the timing, a current reward value corresponding to the layout and routing result is calculated based on a preset reward function.

[0049] Optionally, the untrained layout model includes an untrained graph neural network, an untrained convolutional neural network, an untrained policy network and an untrained value network, and the step of updating the parameters of the untrained layout model based on the current reward value until the untrained layout model converges to obtain a trained layout model comprises:

[0050] Obtaining a historical reward value and a fitted value of the value network;

[0051] According to the historical reward value, the current reward value and a preset discount factor, a long-term discounted reward is calculated;

[0052] According to the long-term discounted reward and the fitted evaluation value, a loss function value corresponding to the untrained policy network and the untrained evaluation network is calculated;

[0053] According to the loss function value, the untrained policy network, the untrained evaluation network, the untrained graph neural network and the untrained convolutional neural network are updated in parameters until the untrained layout model converges, and a trained layout model is obtained.

[0054] In addition, to achieve the above object, the application further provides a macro cell layout device, which comprises a memory, a processor and a computer program stored in the memory and executable on the processor, and the computer program implements the steps of the macro cell layout method according to any one of the above when executed by the processor.

[0055] In addition, to achieve the above object, the application further provides a computer readable storage medium, which stores a macro cell layout program, and the macro cell layout program implements the steps of the macro cell layout method according to any one of the above when executed by a processor.

[0056] The macro cell layout method, device and computer readable storage medium provided by the application, by obtaining the circuit netlist information to be laid out and the trained layout model, and then preprocessing the circuit netlist information to be laid out, the current layout state is obtained. Then input the current layout state into the trained layout model to obtain the first to-be-placed position of the macro cell to be placed in the current layout state; update the current layout state according to the first to-be-placed position, obtain a new current layout state, and execute the step of inputting the current layout state into the trained layout model to obtain the first to-be-placed position of the macro cell to be placed in the current layout state. In this way, all the macro cells to be placed in the circuit netlist information to be laid out can be placed according to the preset order through the trained layout model until the first to-be-placed position of all the macro cells to be placed in the circuit netlist information to be laid out is obtained. Then, the corresponding macro cell layout result is generated according to the first to-be-placed position of all the macro cells to be placed, and the macro cell layout is performed based on the macro cell layout result. In the application, the interaction between the current layout state representing the current macro cell layout state and the first to-be-placed position output by the trained layout model makes the macro cells to be placed in the optimal position according to the preset order, that is, the congestion caused by the relatively compact macro cell position is avoided. Moreover, by laying out the macro cells, the circuit cell overlap and legalization difficulty caused by the mixed placement of macro cells and standard cells are also avoided, the layout effect of the macro cells is effectively improved, and the final layout and routing effect is also improved. BRIEF DESCRIPTION OF DRAWINGS

[0057] Figure 1 The flowchart of the first embodiment of the macro cell layout method of the application;

[0058] Figure 2 The schematic diagram of the macro cell structure related to the embodiment;

[0059] Figure 3 The schematic diagram of the scene of generating the macro cell density map related to the embodiment of the application;

[0060] Figure 4 The schematic diagram of the placement of the macro cell in the embodiment of the application;

[0061] Figure 5 The schematic diagram of the construction scene of the real-time legalization mask matrix in the embodiment of the application;

[0062] Figure 6 The flowchart of the second embodiment of the macro cell layout method of the application;

[0063] Figure 7 The training scene diagram of the untrained layout model related to the embodiment of the application;

[0064] Figure 8 A schematic diagram of a macro cell layout device according to an embodiment of the application.

[0065] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0066] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0067] The term "and / or" in the present application is only used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone.

[0068] The terms "first" and "second" and the like in the specification and claims of the embodiments of the present application are used to distinguish different objects, and are not used to describe the specific order of the objects. For example, the first target object and the second target object are used to distinguish different target objects, and are not used to describe the specific order of the target objects.

[0069] In the embodiments of the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Rather, the use of the words "exemplary" or "for example" is intended to present relevant concepts in a concrete manner.

[0070] It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0071] In order to better describe the technical solutions of the present application, the macro cell layout method of the present application will be described in combination with some prior art as follows:

[0072] In the current chip design flow, the physical design of a very large scale integration (VLSI) circuit can be roughly divided into five stages: floorplanning, placement, clock tree synthesis, routing, and sign off. The main steps of floorplanning include IO (Input / Output) placement, macro cell placement, power planning, and physical cell placement. Among them, macro cell placement is a critical step, which greatly affects whether the timing of subsequent chip design can converge and whether physical verification can be met. Macro cell placement has always been a weak link in chip automatic design tools. In most previous chip designs, the number of macro cells is small, or even none. Even if the area of a macro cell is much larger than that of a standard cell, the total area ratio is very low. Back-end engineers place macro cells around the chip and fine-tune them according to some rules, which often results in a good macro cell placement result. In recent years, with the increasing demand for big data processing, storage modules have been added to chips, which has led to an increase in the number of macro cells and even made the area of a macro cell more than half of the chip area. Therefore, high-quality automatic macro cell placement is crucial for chip physical design.

[0073] In existing methods, traditional methods mainly use heuristic algorithms combined with representation methods. Representation methods use binary trees, linked lists, and other data structures to represent the solution of macro cell placement and compress the solution space. Heuristic algorithms optimize the solution by perturbation, and the result of macro cell placement can be obtained. However, the representation method represents relatively compact macro cell placement in order to reduce chip area. In actual physical design, the size of the chip is fixed, and the positions of macro cells do not have to be too compact. On the contrary, in order to prevent congestion, macro cells should maintain a certain distance between them. Another main method is the analytical method, which places macro cells and standard cells together. This will result in a lot of overlaps between macro cells, and the huge difference between macro cells and standard cells also makes it difficult to legalize. Therefore, the layout effect of existing macro cell placement methods is poor.

[0074] Therefore, an embodiment of the present application obtains the to-be-laid-out circuit netlist information and the trained layout model, and then pre-processes the to-be-laid-out circuit netlist information to obtain a current layout state. Then, the current layout state is input into the trained layout model to obtain a first to-be-placed position of a to-be-placed macro cell in the current layout state. The current layout state is updated according to the first to-be-placed position to obtain a new current layout state, and the step of inputting the current layout state into the trained layout model to obtain a first to-be-placed position of a to-be-placed macro cell in the current layout state is performed. In this way, all to-be-placed macro cells in the to-be-laid-out circuit netlist information can be placed according to a preset order through the trained layout model until the first to-be-placed position of all to-be-placed macro cells in the to-be-laid-out circuit netlist information is obtained. Then, a corresponding macro cell layout result is generated according to the first to-be-placed positions of all to-be-placed macro cells, and macro cell layout is performed based on the macro cell layout result. In the embodiment, the interaction between the current layout state representing the current macro cell layout state and the first to-be-placed position output by the trained layout model makes the to-be-placed macro cells placed in the optimal position according to the preset order, that is, congestion caused by the relatively compact macro cell position is avoided. Moreover, the present application performs layout for the macro cell, which also avoids the circuit cell overlapping and legalization difficulty caused by the mixed placement of the macro cell and the standard cell, effectively improves the layout effect of the macro cell, and further improves the final layout and routing effect.

[0075] Reference Figure 1 , Figure 1 FIG. 1 is a flowchart of a macro cell layout method according to a first embodiment of the present application.

[0076] As shown in FIG. 2, the first embodiment of the present application provides a macro cell layout method, which includes the following steps: Figure 1

[0077] Step S100, obtaining to-be-laid-out circuit netlist information and a trained layout model;

[0078] In the embodiment, it should be noted that the to-be-laid-out circuit netlist information is a netlist designed to achieve a desired function, wherein the netlist at least contains macro cell feature information and macro cell connection information, and can also include standard cell feature information. Exemplarily, the to-be-laid-out circuit netlist information includes a circuit cell (i.e., macro cell and standard cell) list and a wire net list , wherein represents a macro cell, the number of which is ; represents a standard cell, the number of which is ; represents a wire net, the number of which is ​It can be understood that at least two circuit units can be connected on a line net. The circuit netlist information to be laid out can further include a preset layout area, which is generally rectangular with a width and a height of In addition, the circuit netlist information to be laid out also includes process information of the circuit netlist to be laid out.

[0079] It should be noted in this embodiment that the trained layout model includes a trained graph neural network, a trained convolutional neural network, and a trained policy network. The trained graph neural network and the trained convolutional neural network are used to extract features of a current layout state corresponding to the circuit netlist information to be laid out, to obtain corresponding macro cell composite features. The trained policy network is used to output a first to-be-placed position of a to-be-placed macro cell in the current layout state according to the macro cell composite features and a real-time legal mask matrix in the current layout state. It can be understood that the trained layout model can be a model trained in advance or a model trained in real time.

[0080] In step S200, the circuit netlist information to be laid out is preprocessed to obtain a current layout state.

[0081] It should be noted in this embodiment that in order to facilitate the trained layout model to make a corresponding decision action (i.e., determine the first to-be-placed position of the to-be-placed macro cell) based on the circuit netlist information to be laid out, the circuit netlist information to be laid out needs to be preprocessed to obtain a current layout state representing a current macro cell layout state in the preset layout area. For example, the current layout state can include a macro cell density map, a macro cell line net hypergraph, node features of each macro cell, metadata features, a real-time legal mask matrix, and identification information of the to-be-placed macro cell. The preprocessing methods include segmenting the preset layout area, constructing a density map, constructing a line net hypergraph, feature extraction, generating a real-time legal mask matrix, and the like.

[0082] As an example, macro cell feature information and macro cell connection information can be obtained from the circuit netlist information to be laid out. A preset layout region is divided to obtain each partition grid. Then, according to the macro cell feature information, a macro cell density of each partition grid is calculated, and a macro cell density map of the preset layout region is generated according to the macro cell density. Then, according to the macro cell connection information, a macro cell line net hypergraph of the preset layout region can be generated. Further, feature extraction is performed on the macro cell feature information to obtain each macro cell node feature. Metadata features are obtained by performing feature extraction on metadata of the circuit netlist information to be laid out. Then, according to a preset constraint condition, the macro cell feature information, and identification information of a macro cell to be placed, a real-time legal mask matrix of the preset layout region is determined. Further, the macro cell density map, the macro cell line net hypergraph, each macro cell node feature, the metadata features, and the real-time legal mask matrix are taken as a current layout state.

[0083] As another example, the placement order of the macro cell to be placed can be to place in order from large to small in area, so as to avoid the problem that after the macro cell with small area is placed, the macro cell with large area cannot be placed. Of course, the macro cells are also divided into different area intervals according to the area size, so that the placement order of the macro cell to be placed can be to place in order from large to small in area interval.

[0084] In step S200, the circuit netlist information to be laid out is preprocessed to obtain a current layout state, including:

[0085] In step S210, macro cell feature information and macro cell connection information are obtained from the circuit netlist information to be laid out.

[0086] In step S220, a preset layout region is divided to obtain each partition grid.

[0087] In step S230, according to the macro cell feature information, a macro cell density of each partition grid is determined, and a macro cell density map of the preset layout region is generated according to the macro cell density.

[0088] In step S240, according to the macro cell connection information, a macro cell line net hypergraph of the preset layout region is generated.

[0089] In step S250, feature extraction is performed on the macro cell feature information to obtain each macro cell node feature.

[0090] In step S260, feature extraction is performed on metadata of the circuit netlist information to be laid out to obtain metadata features.

[0091] Step S270: Determine the real-time valid mask matrix of the preset layout region based on the macrocell feature information and preset constraints;

[0092] Step S280: The macrocell density map, the macrocell mesh hypergraph, the features of each macrocell node, the metadata features, and the real-time legal mask matrix are taken as the current layout state.

[0093] In this embodiment, it should be noted that a macrocell is a unit with a preset function, composed of elements such as flip-flops, logic units, and registers. Macrocell feature information includes its size, position, port list, and placement status (i.e., whether it is placed within a preset layout area). A macrocell is typically a rectangular block, with width and height that can be denoted as... Typically, macrocells have fixed width and height, but some macrocells have fixed area but variable width and height. The position coordinates of a macrocell (i.e., the position of its center point) can be denoted as ( The port list of a macrocell can represent... , where P （i,1） ,...,P （i,j） Let be the port of macrocell i. The port is a convex polygon, but during the macrocell placement phase, the port of a macrocell can be considered a point. Regarding the coordinates of the port, the first... The first macro unit Each port has an offset coordinate relative to the macrocell center. The offset coordinates describe the distribution of the ports on the macrocell. When the position of the macrocell is determined, the actual coordinates of the ports are... This can also be determined. For example, the formula for calculating the actual coordinates of a macrocell's port can be as follows:

[0094] ;

[0095] in, The x-coordinate of the macrocell's position coordinates. For the width of the macrocell, The x-coordinate of the port's offset coordinates. The ordinate of the macrocell's position coordinates. For the high of macrocells, The vertical coordinate is the offset coordinate of the port.

[0096] like Figure 2 As shown, Figure 2 This is a schematic diagram of the macrocell structure involved in this embodiment. Figure 2 There exists a port P10 on the macrocell M10, and the offset coordinates of port P10 with the center point of macrocell M10 as the origin are: When the position of the macro cell changes, the offset coordinates of the port change, and the width and height of the macro cell also change. The actual coordinates of the port can still be calculated by the formula.

[0097] In addition, it should be noted that the macro cell connection information is a line net list, which is used to describe the connection relationship between the macro cells. It can be understood that the essence of the line net list is also a port list. The line net list represents the line net through the port connects three macro cells.

[0098] As an example, the macro cell feature information and the macro cell connection information are obtained from the to-be-laid-out circuit net list information. A plurality of equal-sized partition grids are obtained by dividing the preset layout area. For example, the preset layout area can be divided into n*n partition grids. Then, according to the placement state of each macro cell in the macro cell feature information, the size and position of the already-placed macro cell with the placement state of already-placed are obtained. According to the size and position of each already-placed macro cell, the macro cell area of each partition grid is calculated. The macro cell area of each partition grid is divided by the area of the partition grid, and then the macro cell density of each partition grid can be obtained. Further, the macro cell density map of the preset layout area can be generated according to the macro cell density. For example, the macro cell density of each partition grid can be converted into a gray value, and then the macro cell density map of the preset layout area can be generated based on the gray value of each partition grid. See Figure 3 , Figure 3 is a scene diagram for generating a macro cell density map involved in the embodiment of the present application. Figure 3The feature information map Z10 representing the feature information of the macro cell is divided into a preset layout region Q10 of a plurality of partition grids, and a macro cell density gray scale map. The macro cell density of each partition grid in the preset layout region Q10 can be calculated through the feature information map Z10, and then the gray scale value of each partition grid in the preset layout region Q10 can be obtained by querying the mapping table of the preset macro cell density and the gray scale value. Thus, the macro cell density map corresponding to the preset layout region Q10 is constructed based on the gray scale value. Since the hypergraph is a generalization of the graph, one edge can connect any number of vertices. The line net usually connects a plurality of circuit cells, and therefore the connection relationship (i.e., the line net) between the macro cells can be more accurately described in the form of a hypergraph. Therefore, the macro cell line net hypergraph used to describe the line net in the preset layout region can be generated according to the macro cell connection information. Then, the macro cell feature information can be preliminarily feature-extracted by using a pre-trained encoding network to obtain the node features of each macro cell, and the metadata of the to-be-laid circuit netlist information can be feature-extracted by using a pre-trained metadata encoding network to obtain the metadata features. The metadata can include the basic data of the to-be-laid circuit netlist information, such as the number of line nets, the type (macro cell or standard cell) and the number of circuit cells, and the like.

[0099] In the embodiment, the real-time legal mask matrix of the preset layout region is determined according to the preset constraint condition, the macro cell feature information, and the identification information of the to-be-placed macro cell. The preset constraint condition is that the macro cells are not allowed to overlap, and the macro cells as a whole need to be in the preset layout region. The preset constraint condition can be expressed by the following formula:

[0100]

[0101] wherein, represents that the macro cell does not exceed the preset layout region in the horizontal direction, is the horizontal coordinate of the position coordinate of the macro cell, is the width of the macro cell, and W is the width of the preset layout region; represents that the macro cell does not exceed the preset layout region in the vertical direction, is the vertical coordinate of the position coordinate of the macro cell, is the height of the macro cell, and H is the height of the preset layout region. represents that there is no overlap between the macro cells.

[0102] As an example, the preset constraint condition can be implemented in the form of a mask matrix. The to-be-placed feature information of the to-be-placed macro unit and the placed feature information of the placed macro unit in the macro unit feature information can be obtained. Then, according to the to-be-placed feature information and the placed feature information, the corresponding placement results of the to-be-placed macro unit placed in each of the partition grids are traversed based on the preset constraint condition, wherein the placement results include that the to-be-placed macro unit overlaps with the placed macro unit, the to-be-placed macro unit exceeds the preset layout area, and the to-be-placed macro unit is allowed to be placed. Thus, the partition grids corresponding to the to-be-placed macro unit overlapping with the placed macro unit and the to-be-placed macro unit exceeding the preset layout area can be marked as illegal positions. The partition grids corresponding to the to-be-placed macro unit allowed to be placed can be marked as legal positions. Thus, all positions allowed for the current to-be-placed macro unit to be placed can be determined. Then, according to the illegal positions and the legal positions, a corresponding real-time legal mask matrix can be constructed, which is used to limit the first placement position of the to-be-placed macro unit under the preset constraint condition, so as to ensure that the first placement position is legal.

[0103] Finally, the macro unit density graph, the macro unit line net supergraph, the macro unit node features, the metadata features, and the real-time legal mask matrix can be used as the current layout state.

[0104] In step S270, the real-time legal mask matrix of the preset layout area is determined according to the macro unit feature information and the preset constraint condition, including:

[0105] In step S271, the to-be-placed feature information of the to-be-placed macro unit and the placed feature information of the placed macro unit in the macro unit feature information are obtained.

[0106] In step S272, according to the to-be-placed feature information and the placed feature information, the corresponding placement results of the to-be-placed macro unit placed in each of the partition grids are traversed based on the preset constraint condition, wherein the placement results include that the to-be-placed macro unit overlaps with the placed macro unit, the to-be-placed macro unit exceeds the preset layout area, and the to-be-placed macro unit is allowed to be placed.

[0107] In step S273, the partition grids corresponding to the to-be-placed macro unit overlapping with the placed macro unit and the to-be-placed macro unit exceeding the preset layout area are marked as illegal positions.

[0108] In step S274, the partition grids corresponding to the to-be-placed macro unit allowed to be placed are marked as legal positions.

[0109] In step S275, a corresponding real-time legal mask matrix is constructed based on the illegal positions and the legal positions.

[0110] It should be noted that, in the embodiment, when the to-be-placed macro unit is placed, the center point of the to-be-placed macro unit (i.e., the position corresponding to the position coordinate of the macro unit) can coincide with the center point of the segmentation grid. Of course, it can be understood that it can also be any position in the segmentation grid, but the to-be-placed macro unit needs to be placed at the same position of each segmentation grid. For example, referring to FIG. 1, the center point of the macro unit M11 is a circle, and the center point of the segmentation grid F11 is an X. When the macro unit M11 is placed, the center point of the macro unit M11 coincides with the center point of the segmentation grid F11. When the macro unit M11 is placed on other segmentation grids, the center point of the macro unit M11 also needs to coincide with the center point of the segmentation grid. Figure 4 , Figure 4 FIG. 1 is a schematic diagram of the placement of a macro unit in an embodiment of the present application. Figure 4 The circle in the middle is the center point of the macro unit M11, and the X is the center point of the segmentation grid F11. When the macro unit M11 is placed, the center point of the macro unit M11 coincides with the center point of the segmentation grid F11. When the macro unit M11 is placed on other segmentation grids, the center point of the macro unit M11 also needs to coincide with the center point of the segmentation grid.

[0111] As an example, the present application divides each macro unit into a to-be-placed macro unit and a placed macro unit according to the placement state of each macro unit in the macro unit feature information. Then, the to-be-placed feature information of the to-be-placed macro unit and the placed feature information of the placed macro unit are obtained. It can be understood that the feature information of the to-be-placed macro unit at least includes the size of the to-be-placed macro unit, and of course the feature information of the to-be-placed macro unit can also include the position of the to-be-placed macro unit, and the position coordinate corresponding to the position is a variable. The feature information of the placed macro unit at least includes the size and position of the to-be-placed macro unit. Then, the to-be-placed macro unit is placed in each segmentation grid in turn, and according to the to-be-placed feature information, the placed feature information, and a preset constraint condition, the placement result of the to-be-placed macro unit placed in each segmentation grid is determined, wherein the placement result includes that the to-be-placed macro unit overlaps the placed macro unit, the to-be-placed macro unit exceeds the preset layout area, and the to-be-placed macro unit is allowed to be placed. The segmentation grid corresponding to the to-be-placed macro unit overlapping the placed macro unit and the to-be-placed macro unit exceeding the preset layout area is marked as an illegal position. The segmentation grid corresponding to the to-be-placed macro unit allowed to be placed is marked as a legal position. Thus, a corresponding real-time legal mask matrix can be constructed based on the illegal position and the legal position. For example, the real-time legal mask matrix is a 0, 1 matrix corresponding to the segmentation grid in the preset layout area, 0 indicates that the position corresponding to the segmentation grid is legal, and the to-be-placed macro unit can be placed at the position, and 1 indicates that the position corresponding to the segmentation grid is illegal, and the to-be-placed macro unit cannot be placed at the position.

[0112] For example, referring to FIG. 1, the center point of the macro unit M11 is a circle, and the center point of the segmentation grid F11 is an X. When the macro unit M11 is placed, the center point of the macro unit M11 coincides with the center point of the segmentation grid F11. When the macro unit M11 is placed on other segmentation grids, the center point of the macro unit M11 also needs to coincide with the center point of the segmentation grid. Figure 5 , Figure 5 FIG. 1 is a schematic diagram of the placement of a macro unit in an embodiment of the present application. Figure 5The preset layout area Q10 includes a placed macro cell M0 and a to-be-placed macro cell M 2 The to-be-placed macro cell M 2 The preset layout area Q10 includes a placed macro cell M0 and a to-be-placed macro cell M 2 The to-be-placed macro cell M is sequentially placed in each of the divided grids to obtain a corresponding placement result, so as to determine whether the placement result corresponding to the divided grid is that the to-be-placed macro cell overlaps with the placed macro cell, the to-be-placed macro cell exceeds the preset layout area, or the to-be-placed macro cell is allowed to be placed. Therefore, a corresponding real-time legal mask matrix can be constructed.

[0113] In step S300, the current layout state is input into the trained layout model to obtain a first to-be-placed position of a to-be-placed macro cell in the current layout state.

[0114] In this embodiment, it should be noted that the trained layout model includes a trained graph neural network, a trained convolutional neural network, and a trained policy network. The trained graph neural network and the trained convolutional neural network are used to extract features of the current layout state corresponding to the to-be-laid-out circuit netlist information to obtain corresponding macro cell composite features. The trained policy network is used to output the first to-be-placed position of the to-be-placed macro cell in the current layout state according to the macro cell composite features and the real-time legal mask matrix in the current layout state. It can be understood that the trained layout model can be a model trained in advance or a model trained in real time.

[0115] Therefore, by inputting the current layout state into the trained layout model, the trained graph neural network and the trained convolutional neural network can be used to extract features of the current layout state and combine the features to obtain macro cell composite features corresponding to the current layout state. Then, a real-time legal mask matrix constructed based on the preset constraint condition and the macro cell feature information is obtained. Furthermore, the macro cell composite features and the real-time legal mask matrix are input into the trained policy network to obtain the first to-be-placed position of the to-be-placed macro cell.

[0116] In step S300, the trained layout model includes a trained graph neural network, a trained convolutional neural network, and a trained policy network. The step of inputting the current layout state into the trained layout model to obtain the first to-be-placed position of the to-be-placed macro cell in the current layout state includes:

[0117] In step S310, the macro cell density map is input into the trained convolutional neural network to obtain corresponding macro cell density features.

[0118] Step S320, inputting each of the macro unit node features and the macro unit line network supergraph into the trained graph neural network to obtain corresponding macro unit global node features, and determining a to-be-placed node feature in the macro unit global node features;

[0119] Step S330, averaging the macro unit global node features to obtain corresponding global average features;

[0120] Step S340, generating an attention node feature based on a preset multi-head attention mechanism according to the macro unit global node features and the to-be-placed node feature;

[0121] Step S350, concatenating the macro unit density feature, the global average feature, the attention node feature, and the metadata feature into a macro unit composite feature;

[0122] Step S360, inputting the macro unit composite feature and the real-time legal mask matrix into a trained strategy network to obtain a first to-be-placed position of the to-be-placed macro unit in the current layout state.

[0123] In the embodiment, the trained convolutional neural network is inputted with the macro unit density map, so that the trained convolutional neural network performs feature sampling analysis on the macro unit state based on the macro unit density map, and outputs a macro unit density feature representing the global distribution of the macro unit. Illustratively, the trained convolutional neural network is composed of a first convolutional layer, a second convolutional layer, a third convolutional layer, and a fully connected layer. The first convolutional layer outputs a convolutional channel of 32, a convolutional kernel size of 8, and a step size of 4; the second convolutional layer outputs a convolutional channel of 64, a convolutional kernel size of 4, and a step size of 2; the third convolutional layer outputs a convolutional channel of 32, a convolutional kernel size of 3, and a step size of 1; and the fully connected layer outputs a vector dimension of 496 with an input data size of 32*32*64. Illustratively, the trained convolutional neural network is inputted with the macro unit density map, and outputs a corresponding density feature map, and then the density feature map is simplified to obtain a density feature vector corresponding to the macro unit density map as the macro unit density feature.

[0124] Further, by converting the macro cell line network supergraph into a sparse adjacency matrix, inputting each macro cell node feature and the sparse adjacency matrix corresponding to the macro cell line network supergraph into the trained graph neural network, so that the trained graph neural network outputs corresponding macro cell global node features, and determining the to-be-placed node feature in the macro cell global node feature. Wherein the to-be-placed node feature is the node feature of the to-be-placed macro cell. Then the macro cell global node features can be averaged to obtain a global average feature representing the whole graph information feature of the preset layout area. Further, according to the macro cell global node feature and the to-be-placed node feature, based on the preset multi-head attention mechanism, the attention node feature is generated, so that the trained strategy network optimizes the to-be-placed macro cell based on the attention node feature. Then the macro cell density feature, the global average feature, the attention node feature and the metadata feature in the current layout state can be spliced into a macro cell composite feature. The macro cell composite feature can comprehensively represent the current layout state. Thus, the macro cell composite feature and the real-time legal mask matrix can be input into the trained strategy network to obtain a first to-be-placed position of the to-be-placed macro cell in the current layout state. It can be understood that the first to-be-placed position meets the real-time legal mask matrix, thereby satisfying the preset constraint condition.

[0125] In step S360, the macro cell composite feature and the real-time legal mask matrix are input into the trained strategy network to obtain a first to-be-placed position of the to-be-placed macro cell in the current layout state, including:

[0126] In step S361, the macro cell composite feature is input into the trained strategy network to obtain a corresponding action probability distribution.

[0127] In step S362, according to the real-time legal mask matrix, the action probability distribution is legalized to obtain a legal probability distribution.

[0128] In step S363, according to the legal probability distribution, a first to-be-placed position of the to-be-placed macro cell in the current layout state is determined.

[0129] In this embodiment, by inputting the macro cell composite feature into the trained strategy network, the trained strategy network outputs a corresponding action probability distribution. Then, according to the real-time legal mask matrix, the action probability distribution is legalized to obtain a legal probability distribution. Thus, the position corresponding to the action probability distribution does not satisfy the preset constraint condition. For example, the action probability distribution can be subtracted by the real-time legal mask matrix multiplied by the minimum number (tending to negative infinity), and then normalized to obtain the legal probability distribution. The softmax formula of the normalization processing is as follows:

[0130] .

[0131] wherein z ij is a probability of a to-be-placed macro cell being placed at a partition grid (i,j) in a preset layout region, and e is a natural constant.

[0132] Further, a first to-be-placed position of the to-be-placed macro cell in the current layout state can be determined according to the legal probability distribution. For example, the partition grid with the highest legal probability distribution can be directly taken as the first to-be-placed position of the to-be-placed macro cell in the current layout state.

[0133] At step S400, the current layout state is updated according to the first to-be-placed position, a new current layout state is obtained, and the step of inputting the current layout state into the trained layout model to obtain the first to-be-placed position of the to-be-placed macro cell in the current layout state is performed.

[0134] Since the first to-be-placed position of each to-be-placed macro cell is obtained, after the to-be-placed macro cell is placed at the first to-be-placed position, the previous current layout state cannot represent the layout state after the to-be-placed macro cell is placed. Therefore, the identification information of a new to-be-placed macro cell is obtained, and the current layout state is updated according to the identification information of the new to-be-placed macro cell and the first to-be-placed position to obtain a new current layout state. The step of inputting the current layout state into the trained layout model to obtain the first to-be-placed position of the to-be-placed macro cell in the current layout state is performed, so as to obtain the first to-be-placed position of the new to-be-placed macro cell, until the first to-be-placed positions of all to-be-placed macro cells in the to-be-laid-out circuit netlist information are obtained.

[0135] At step S500, after the first to-be-placed positions of all to-be-placed macro cells in the to-be-laid-out circuit netlist information are obtained, a corresponding macro cell layout result is generated, and macro cell layout is performed based on the macro cell layout result.

[0136] In this embodiment, after the first to-be-placed positions of all to-be-placed macro cells in the to-be-laid-out circuit netlist information are obtained, all to-be-placed macro cells can be placed at corresponding first to-be-placed positions in the preset layout region to obtain a corresponding macro cell layout result, and macro cell layout is performed based on the macro cell layout result.

[0137] In the first embodiment of the present application, a macro cell layout method is provided. By obtaining circuit netlist information to be laid out and a trained layout model, the circuit netlist information to be laid out is preprocessed to obtain a current layout state. Then the current layout state is input into the trained layout model to obtain a first to-be-placed position of a macro cell to be placed in the current layout state. The current layout state is updated according to the first to-be-placed position to obtain a new current layout state, and the step of inputting the current layout state into the trained layout model to obtain the first to-be-placed position of the macro cell to be placed in the current layout state is executed. In this way, all macro cells to be placed in the circuit netlist information to be laid out can be placed according to a preset order through the trained layout model until the first to-be-placed position of all macro cells to be placed in the circuit netlist information to be laid out is obtained. Then a corresponding macro cell layout result is generated according to the first to-be-placed positions of all macro cells to be placed, and macro cell layout is performed based on the macro cell layout result. In the embodiment, the interaction between the current layout state representing the current macro cell layout state and the first to-be-placed position output by the trained layout model makes the macro cells to be placed according to the preset order placed in the optimal position, that is, congestion caused by the relatively compact macro cell position is avoided. Moreover, the present application performs layout for macro cells, which also avoids circuit cell overlapping and legalization difficulty caused by mixed placement of macro cells and standard cells, effectively improves the layout effect of macro cells, and further improves the layout and routing effect obtained finally.

[0138] Reference Figure 6 , Figure 6 The flowchart of the second embodiment of the macro cell layout method of the present application is shown in FIG. 2.

[0139] As Figure 6 shown in FIG. 2, the second embodiment of the present application provides a macro cell layout method, which includes the following steps before the step of obtaining circuit netlist information to be laid out and a trained layout model:

[0140] Step A10, obtaining a circuit netlist training set and an untrained layout model;

[0141] Step A20, preprocessing the circuit netlist training set to obtain a training layout state;

[0142] Step A30, inputting the training layout state into the untrained layout model to obtain a second to-be-placed position of a training macro cell in the training layout state;

[0143] Step A40, updating the training layout state according to the second to-be-placed position to obtain a new training layout state, and executing the step of inputting the training layout state into the untrained layout model to obtain the second to-be-placed position of the training macro cell in the training layout state;

[0144] Step A50, after obtaining the second placement positions of all training macro cells in the circuit netlist training set, a corresponding training layout result is generated;

[0145] Step A60, a preset layout tool is called to perform standard cell layout and global routing based on the training layout result, and a layout and routing result is obtained;

[0146] Step A70, a corresponding current reward value is calculated according to the layout and routing result and a preset reward function;

[0147] Step A80, the untrained layout model is updated based on the current reward value until the untrained layout model converges, and a trained layout model is obtained.

[0148] In this embodiment, it should be noted that the circuit netlist training set includes a training netlist, and also includes a first macro cell solution placed by an engineer for the training netlist, and a second macro cell solution placed by an untrained layout model, and the label is a current reward value of a layout and routing result generated according to a preset reward function and based on the first macro cell solution and the second macro cell solution. The netlist at least contains macro cell feature information and macro cell connection information for training, and can also include standard cell feature information, a preset layout area, and circuit process information.

[0149] In this embodiment, it should also be noted that the untrained layout model includes an untrained graph neural network, an untrained convolutional neural network, and an untrained policy network. The untrained graph neural network and the untrained convolutional neural network are used to extract features of a training layout state corresponding to the circuit netlist training set, and obtain corresponding training macro cell composite features. The untrained policy network is used to output a second to-be-placed position of a training macro cell in the training layout state according to the training macro cell composite features and a training legal mask matrix in the training layout state.

[0150] The embodiment obtains a circuit netlist training set and an untrained layout model, pre-processes the circuit netlist training set to obtain a training layout state, inputs the training layout state into the untrained layout model to obtain a second to-be-placed position of a training macro cell in the training layout state, updates the training layout state according to the second to-be-placed position, obtains a new training layout state, and performs the steps of inputting the training layout state into the untrained layout model to obtain a second to-be-placed position of a training macro cell in the training layout state, and generating a corresponding training layout result after obtaining the second to-be-placed positions of all training macro cells in the circuit netlist training set. Then, a preset layout tool can be called to perform standard cell layout and global routing based on the training layout result to obtain a layout and routing result. Exemplarily, the preset layout tool can be Astro of Synopsys. Further, a corresponding current reward value can be calculated according to the layout and routing result and a preset reward function. The preset reward function includes at least one of a bus length item, a congestion degree item, and a timing item. Based on the current reward value and a preset loss function value, a corresponding loss function value is calculated, the untrained layout model is updated in parameters through back propagation according to the loss function value, and the untrained layout model converges to obtain a trained layout model. Therefore, the embodiment can further optimize the bus length, the congestion degree, or the timing of the macro cell layout result on the subsequent layout and routing process.

[0151] The step of calculating a corresponding current reward value according to the layout and routing result and a preset reward function in step A70 includes:

[0152] In step B10, the layout and routing result is input into a pre-trained measurement and calculation model to measure and calculate the bus length, the congestion degree, and the timing of the layout and routing result.

[0153] In step B20, a corresponding current reward value of the layout and routing result is calculated based on a preset reward function according to the bus length, the congestion degree, and the timing.

[0154] In the embodiment, it should be noted that the pre-trained measurement and calculation model is a model for measuring and calculating information such as the bus length, the congestion degree, and the timing of the layout and routing result.

[0155] The embodiment inputs the layout and routing result into a pre-trained measurement and calculation model to measure and calculate the bus length, the congestion degree, and the timing of the layout and routing result. Then, a corresponding current reward value of the layout and routing result is calculated based on a preset reward function according to the bus length, the congestion degree, and the timing.

[0156] Exemplarily, the preset reward function R = -a wirelenght - b congestion - g timing. Wherein a, b, g are weights set according to the requirements for bus length, congestion and timing. wirelenght is the bus length of the layout routing result, which can be half perimeter line length or Steiner tree dense line length. congestion is the congestion of the layout routing result, which can be characterized by rectangular line density. timing is the timing of the layout routing result, that is, the delay of the timing path, including total delay and worst delay.

[0157] Wherein, the untrained layout model in step A80 includes an untrained graph neural network, an untrained convolutional neural network, an untrained policy network and an untrained value network, the step of updating parameters of the untrained layout model based on the current reward value until the untrained layout model converges to obtain a trained layout model, includes:

[0158] Step C10, obtaining a historical reward value and a fitted value of the value network;

[0159] Step C20, calculating a long-term discounted reward according to the historical reward value, the current reward value and a preset discount factor;

[0160] Step C30, calculating a loss function value corresponding to the untrained policy network and the untrained value network according to the long-term discounted reward and the fitted value;

[0161] Step C40, updating parameters of the untrained policy network, the untrained value network, the untrained graph neural network and the untrained convolutional neural network according to the loss function value until the untrained layout model converges to obtain a trained layout model.

[0162] In this embodiment, the trained macro cell composite features output by the untrained graph neural network and the untrained convolutional neural network are input into the value network, so that a fitted value corresponding to the value network can be obtained. Then, a long-term discounted reward is calculated as a reward value of the untrained policy network and the untrained value network according to the historical reward value, the current reward value and a preset discount factor. Further, a loss function value corresponding to the untrained policy network and the untrained value network can be calculated according to the long-term discounted reward, the fitted value and a preset loss function. Parameters of the untrained policy network, the untrained value network, the untrained graph neural network and the untrained convolutional neural network are updated through back propagation according to the loss function value until the untrained layout model converges to obtain a trained layout model.

[0163] In the second embodiment of the present application, a circuit netlist training set and an untrained layout model are obtained; the circuit netlist training set is preprocessed to obtain a training layout state; the training layout state is input into the untrained layout model to obtain a second to-be-placed position of a training macro cell in the training layout state; the training layout state is updated according to the second to-be-placed position to obtain a new training layout state, and the step of inputting the training layout state into the untrained layout model to obtain a second to-be-placed position of a training macro cell in the training layout state is performed; after obtaining the second to-be-placed positions of all training macro cells in the circuit netlist training set, a corresponding training layout result is generated; a preset layout tool is called to perform standard cell layout and global routing based on the training layout result to obtain a layout and routing result; a corresponding current reward value is calculated according to the layout and routing result and a preset reward function; the untrained layout model is updated in parameters based on the current reward value until the untrained layout model converges to obtain a trained layout model. Thus, in this embodiment, the layout and routing result based on the training layout result and the preset reward function are used to calculate a corresponding current reward value, and then the untrained layout model is updated in parameters based on the current reward value, so that the optimization effect of the trained layout model on the subsequent layout and routing process can be ensured, and the layout effect of the macro cell is effectively improved.

[0164] As an example, refer to Figure 7 , Figure 7 is a training scene graph of the untrained layout model involved in the embodiment of the present application. As Figure 7As shown, the untrained placement model includes an untrained graph neural network edge-GNN, an untrained convolutional neural network CNN, an untrained policy network, and an untrained value network. The macro cell feature information node features in the circuit netlist training set are subjected to preliminary feature extraction by a node feature encoder node data encoder to obtain the node features of each training macro cell. The training metadata in the circuit netlist training set are subjected to feature extraction by a metadata encoder metadata encoder to obtain the training metadata features. The training layout state includes the node features of each training macro cell, the training metadata features, the training layout feature map, the training macro cell line network hypergraph, and the training legal mask matrix. The training layout feature map is input into the untrained convolutional neural network CNN to obtain the corresponding training layout feature map, and then the training layout feature map is subjected to flatten processing to obtain the training layout feature. The sparse adjacency matrix sparse-adj-matrix corresponding to each training macro cell node feature and the training macro cell line network hypergraph is input into the untrained graph neural network edge-GNN to obtain the corresponding training global node feature, and to determine the training to-be-placed node feature next-macro-index in the training global node feature. The training global node feature is subjected to mean processing to obtain the corresponding training global average feature. Based on the training global node feature and the training to-be-placed node feature next-macro-index, a training attention node feature is generated based on a preset multi-head attention mechanism multi-head attention. The training layout feature, the training global average feature, the training attention node feature, and the metadata feature are concatenated as a training macro cell composite feature. The training macro cell composite feature and the training legal mask matrix are input into the untrained policy network to output the corresponding action probability distribution action-probability, and then the second placement position of the training macro cell in the training layout state is determined based on the action probability distribution action-probability. In addition, the training global average feature is also input into a pre-training calculation network pretrain network to calculate the wire length wire-length, the line density density, and other information, and then the untrained value network value network calculates the corresponding fitting value value based on the training macro cell composite feature and a preset reward function.Further, a loss function value corresponding to the fitting value value and a preset loss function is calculated, and all neural networks in the untrained layout model are updated in parameters through back propagation according to the loss function value, until the untrained layout model converges, and the trained layout model is obtained.

[0165] As shown in Figure 8 , a structure diagram of a macro cell layout device is shown. Figure 8 As shown in

[0166] Exemplarily, the macro cell layout device can be a PC (Personal Computer), a tablet computer, a portable computer, a server or the like.

[0167] As shown in Figure 8 , the macro cell layout device can include a processor 1001 such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to realize the connection and communication between the components. The user interface 1003 can include a display screen (Display), an input unit such as a touch screen or a keyboard (Keyboard), and the optional user interface 1003 can further include a standard wired interface, a wireless interface. The network interface 1004 can optionally include a standard wired interface, a wireless interface (such as a Wi-Fi interface). The memory 1005 can be a high-speed RAM memory, or a non-volatile memory (Non-Volatile Memory) such as a disk memory. The memory 1005 can optionally be a storage device independent of the aforementioned processor 1001.

[0168] Those skilled in the art can understand that Figure 8 the device structure shown in the foregoing embodiments does not constitute a limitation on the macro cell layout device, and can include more or fewer components than shown, or combine certain components, or different component arrangements.

[0169] As shown in Figure 8 , the memory 1005 as a computer storage medium can include an operating system, a network communication module, a user interface module, and a macro cell layout application.

[0170] In the device shown in Figure 8 , the processor 1001 can be used to call the macro cell layout application stored in the memory 1005, and perform the operations of the macro cell layout method in the above embodiments.

[0171] In addition, an embodiment of the present application further provides a computer storage medium, wherein the computer storage medium stores a computer program, and the computer program is executed by a processor to implement the operations in the macro cell layout method provided by the above embodiment.

[0172] It should be noted that, in this document, the terms such as first and second are used only to distinguish one entity / operation / element from another entity / operation / element, and do not necessarily require or imply any such actual relationship or order between these entities / operations / elements; the terms "comprise", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or other elements inherent to such a process, method, article or system. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of another identical element in the process, method, article or system including the element.

[0173] For the device embodiment, since it is basically similar to the method embodiment, it is described more simply, and the relevant part can refer to the part of the description of the method embodiment. The device embodiment described above is only schematic, and the units described as separate components can or can not be physically separate. Some or all of the modules can be selected according to actual needs to achieve the purpose of the present application. Those skilled in the art can understand and implement it without creative labor.

[0174] The serial numbers of the above embodiments of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0175] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment method can be realized by means of software and the necessary general hardware platform, and of course it can also be realized by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as a ROM / RAM, a magnetic disk, an optical disk) as described above, and includes a plurality of instructions for making a terminal device (which can be a mobile phone, a computer, a server, a vehicle, or a network device, etc.) execute the macro cell layout method described in each embodiment of the present application.

[0176] The above merely preferred embodiments of the present application and are not intended to limit the patent scope of the present application, any equivalent structure or equivalent process transformation using the content of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A macrocell layout method, characterized by, The macro cell layout method comprises the following steps: Obtain the circuit netlist information to be laid out and the trained layout model; Preprocess the circuit netlist information to be laid out to obtain a current layout state; Input the current layout state into the trained layout model to obtain a first placement position of a macro cell to be placed in the current layout state; Update the current layout state according to the first placement position to obtain a new current layout state, and perform the step of inputting the current layout state into the trained layout model to obtain a first placement position of a macro cell to be placed in the current layout state; After obtaining the first placement position of all macro cells to be placed in the circuit netlist information to be laid out, generate a corresponding macro cell layout result, and perform macro cell layout based on the macro cell layout result; The step of preprocessing the circuit netlist information to be laid out to obtain a current layout state comprises: Obtain macro cell feature information and macro cell connection information from the circuit netlist information to be laid out, wherein the macro cell feature information comprises the size, position, port list and placement state of the macro cell, and the macro cell connection information is used to describe the connection relationship between macro cells; Divide the preset layout area to obtain each partition grid; Determine the macro cell density of each partition grid according to the macro cell feature information, and generate a macro cell density map of the preset layout area according to the macro cell density; Generate a macro cell line network hypergraph of the preset layout area according to the macro cell connection information; Extract features from the macro cell feature information to obtain macro cell node features; Extract features from the metadata of the circuit netlist information to be laid out to obtain metadata features, wherein the metadata comprises the number of line networks, the type and number of circuit units; Determine a real-time legal mask matrix of the preset layout area according to the macro cell feature information and a preset constraint condition; The macro cell density map, the macro cell line network hypergraph, each macro cell node feature, the metadata feature and the real-time legal mask matrix are taken as a current layout state; The trained layout model comprises a trained graph neural network, a trained convolutional neural network and a trained policy network, and the step of inputting the current layout state into the trained layout model to obtain a first placement position of a macro cell to be placed in the current layout state comprises: Input the macro cell density map into the trained convolutional neural network to obtain corresponding macro cell density features; Input each macro cell node feature and the macro cell line network hypergraph into the trained graph neural network to obtain corresponding macro cell global node features, and determine a to-be-placed node feature in the macro cell global node features; Average the macro cell global node features to obtain corresponding global average features; Generate attention node features based on a preset multi-head attention mechanism according to the macro cell global node features and the to-be-placed node features; Concatenate the macro cell density features, the global average features, the attention node features and the metadata features into macro cell composite features; Input the macro cell composite feature and the real-time legal mask matrix into a trained strategy network to obtain a first to-be-placed position of the to-be-placed macro cell in the current layout state.

2. The macrocell layout method of claim 1 wherein, The step of determining the real-time legal mask matrix of the preset layout region according to the macro cell feature information and a preset constraint condition comprises: obtaining to-be-placed feature information of the to-be-placed macro cell and placed feature information of the placed macro cell in the macro cell feature information; according to the to-be-placed feature information and the placed feature information, traversing a corresponding placement result of the to-be-placed macro cell placed in each of the partition grids based on a preset constraint condition, wherein the placement result comprises that the to-be-placed macro cell overlaps with the placed macro cell, the to-be-placed macro cell exceeds the preset layout region, and the to-be-placed macro cell is allowed to be placed; marking the partition grid corresponding to the to-be-placed macro cell overlapping with the placed macro cell and the to-be-placed macro cell exceeding the preset layout region as an illegal position; marking the partition grid corresponding to the to-be-placed macro cell allowed to be placed as a legal position; based on the illegal position and the legal position, constructing a corresponding real-time legal mask matrix.

3. The macrocell layout method of claim 1 wherein, The step of inputting the macro cell composite feature and the real-time legal mask matrix into a trained strategy network to obtain a first to-be-placed position of the to-be-placed macro cell in the current layout state comprises: inputting the macro cell composite feature into a trained strategy network to obtain a corresponding action probability distribution; according to the real-time legal mask matrix, performing legalization processing on the action probability distribution to obtain a legal probability distribution; determining a first to-be-placed position of the to-be-placed macro cell in the current layout state according to the legal probability distribution.

4. The macrocell layout method of any one of claims 1 to 3, wherein, Before the step of obtaining the circuit netlist information to be laid out and the trained layout model, comprising: obtaining a circuit netlist training set and an untrained layout model; preprocessing the circuit netlist training set to obtain a training layout state; inputting the training layout state into the untrained layout model to obtain a second to-be-placed position of a training macro cell in the training layout state; updating the training layout state according to the second to-be-placed position to obtain a new training layout state, and performing the step of inputting the training layout state into the untrained layout model to obtain a second to-be-placed position of a training macro cell in the training layout state; after obtaining the second to-be-placed positions of all the training macro cells in the circuit netlist training set, generating a corresponding training layout result; calling a preset layout tool to perform standard cell layout and global routing based on the training layout result to obtain a layout and routing result; according to the layout and routing result and a preset reward function, calculating a corresponding current reward value; based on the current reward value, updating parameters of the untrained layout model until the untrained layout model converges to obtain a trained layout model.

5. The macrocell layout method of claim 4 wherein, The step of calculating a corresponding current reward value according to the layout and routing result and a preset reward function comprises: inputting the layout and routing result into a pre-trained measurement model to measure a total bus length, a congestion degree, and a timing of the layout and routing result; According to the bus length, the congestion degree and the timing, a preset reward function is used to calculate a current reward value corresponding to the layout and routing result.

6. The macrocell layout method of claim 4 wherein, The untrained layout model includes an untrained graph neural network, an untrained convolutional neural network, an untrained policy network and an untrained value network. The untrained layout model is updated in parameters based on the current reward value until the untrained layout model converges, thereby obtaining a trained layout model. The step includes: a historical reward value and a fitted value of the value network are obtained; a long-term discounted reward is calculated according to the historical reward value, the current reward value and a preset discount factor; a loss function value corresponding to the untrained policy network and the untrained value network is calculated according to the long-term discounted reward and the fitted value; the untrained policy network, the untrained value network, the untrained graph neural network and the untrained convolutional neural network are updated in parameters according to the loss function value until the untrained layout model converges, thereby obtaining a trained layout model.

7. A macrocell layout device, characterized by The macro cell layout device includes a memory, a processor and a computer program stored on the memory and executable on the processor. When the computer program is executed by the processor, the steps of the macro cell layout method according to any one of claims 1 to 6 are implemented.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a macro cell layout program. When the macro cell layout program is executed by the processor, the steps of the macro cell layout method according to any one of claims 1 to 6 are implemented.

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