Display device and overcurrent detection method thereof

Abstract

A display device and an overcurrent detection method thereof. The display device includes a display panel driven based on a first gate clock and a second gate clock; a clock supply circuit including a first output terminal for output of the first gate clock and a second output terminal for output of the second gate clock, supplying one of a gate high voltage and a gate low voltage as a first test voltage to the first output terminal and the other of the gate high voltage and the gate low voltage as a second test voltage to the second output terminal within a first time interval immediately after system power is supplied to the clock supply circuit; a power generator generating the gate high voltage and the gate low voltage and supplying the gate high voltage and the gate low voltage to the clock supply circuit; and an overcurrent detector receiving a flag signal to identify an overcurrent from the power generator when the first output terminal and the second output terminal are short-circuited to each other within the first time interval in order to shut down the power generator.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a display apparatus and an overcurrent detection method thereof. BACKGROUND

[0002] When an overcurrent occurs in a display apparatus, the operation stability of the display apparatus is reduced. The overcurrent can occur due to various reasons such as a short defect between lines for supplying a driving signal to a display panel.

[0003] In a related art display apparatus, since an overcurrent is detected in a display driving for displaying an input image, there is a problem that the accuracy of detection is reduced because the time for detecting the overcurrent is short in a display apparatus driven at a high speed or having a high resolution. SUMMARY

[0004] To overcome the above-mentioned problems of the related art, the disclosure can provide a display apparatus and an overcurrent detection method thereof which secure a long time for detecting an overcurrent to improve the accuracy of overcurrent detection.

[0005] To achieve these objects and other advantages and according to the purpose of the disclosure, as embodied and broadly described herein, a display apparatus includes a display panel driven based on a first gate clock and a second gate clock, a clock supply circuit including a first output terminal for output of the first gate clock and a second output terminal for output of the second gate clock, supplying one of a gate high voltage and a gate low voltage to the first output terminal as a first test voltage and the other of the gate high voltage and the gate low voltage to the second output terminal as a second test voltage within a first time interval immediately after system power is supplied to the clock supply circuit, a power generator generating the gate high voltage and the gate low voltage and supplying the gate high voltage and the gate low voltage to the clock supply circuit, and an overcurrent detector receiving a flag signal to identify an overcurrent from the power generator to shut down the power generator when the first output terminal and the second output terminal are short-circuited to each other within the first time interval.

[0006] In another aspect of the present disclosure, an overcurrent detection method of a display apparatus includes the steps of generating a gate high voltage and a gate low voltage by using a power generator; supplying one of the gate high voltage and the gate low voltage as a first test voltage to a first output terminal for output of a first gate clock by using a clock supply circuit for a first time interval immediately after application of system power; supplying the other of the gate high voltage and the gate low voltage as a second test voltage to a second output terminal for output of a second gate clock by using the clock supply circuit for the first time interval; and receiving a flag signal to identify an overcurrent from the power generator by using an overcurrent detector when the first output terminal and the second output terminal are short-circuited to each other for the first time interval, thereby shutting down the power generator. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0008] Figure 1 is a diagram illustrating a display apparatus according to an embodiment of the present disclosure;

[0009] Figure 2 is a diagram schematically illustrating Figure 1 a sub-pixel illustrated in FIG. 1;

[0010] Figure 3 is a diagram schematically illustrating an overall circuit configuration including a safety circuit according to an embodiment of the present disclosure;

[0011] Figure 4 is a diagram illustrating a schematic configuration of a safety circuit according to a comparative example of the present disclosure;

[0012] Figure 5 is a diagram illustrating Figure 4 a driving waveform of the safety circuit of FIG. 1;

[0013] Figure 6 is a diagram illustrating a schematic configuration of a safety circuit according to an embodiment of the present disclosure;

[0014] Figure 7 is a diagram illustrating Figure 6 a detailed configuration of a power circuit included in the safety circuit of FIG. 1;

[0015] Figure 8 is a diagram illustrating Figure 6 a circuit configuration of a level shifter included in the safety circuit of FIG. 1;

[0016] Figure 9 a driving waveform of the safety circuit of Figure 7 and Figure 8 is a view illustrating a driving waveform of the safety circuit of

[0017] Figure 10 a driving waveform of the safety circuit of Figure 7 and Figure 8 is a view illustrating a driving waveform of the safety circuit of

[0018] Figure 11 is a view illustrating another circuit configuration of a level shifter included in the safety circuit of Figure 6

[0019] Figure 12 a driving waveform of the safety circuit of Figure 7 and Figure 11 is a view illustrating a driving waveform of the safety circuit of

[0020] Figure 13 a driving waveform of the safety circuit of Figure 7 and Figure 11 is a view illustrating a driving waveform of the safety circuit of DETAILED DESCRIPTION

[0021] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the present disclosure to those skilled in the art.

[0022] The display apparatus according to the present embodiment can be implemented as a television (TV), a video player, a personal computer (PC), a home theater, a car-mounted electronic device, or a smart phone, but is not limited thereto. The display apparatus according to the present embodiment can be implemented as a light emitting display apparatus, a quantum dot display (QDD) apparatus, or a liquid crystal display (LCD) apparatus. However, hereinafter, for convenience of description, a light emitting display apparatus, e.g., based on inorganic light emitting diodes or organic light emitting diodes, will be described.

[0023] Further, the light emitting display apparatus described below will be described as including, for example, an n-type or a p-type transistor, but is not limited thereto, and can be implemented as a type that collectively provides n-type and p-type. The transistor can be a three-terminal element including a gate, a source, and a drain. The source and the drain of the transistor can exchange between them based on a voltage applied thereto. Based on this, in the description below, one of the source and the drain will be described as a first electrode, and the other of the source and the drain will be described as a second electrode. ​

[0024] Figure 1 FIG. 1 is a diagram illustrating a display apparatus according to an embodiment of the disclosure. Figure 2 Figure 1 FIG. 2 is a diagram schematically illustrating a sub-pixel.

[0025] As Figure 1 Figure 2 As illustrated in FIGS. 1 and 2, the display apparatus according to the present embodiment can include a host system 110, a timing controller 120, a scan driver 130, a data driver 140, a display panel 150, and a power circuit 180. One or more of the timing controller 120, the scan driver 130, and the data driver 140 can be integrated into a single integrated circuit (IC) based on the implementation type of the display apparatus.

[0026] The host system 110 can output various timing signals along with video data supplied from the outside or video data stored in an internal memory. The host system 110 can supply the video data and the timing signals to the timing controller 120.

[0027] Based on the timing signals, the timing controller 120 can output a gate timing control signal GDC for controlling the operation timing of the scan driver 130 and a data timing control signal DDC for controlling the operation timing of the data driver 140. The timing controller 120 can supply image data DATA along with the data timing control signal DDC to the data driver 140. The timing controller 120 can be implemented in an IC type and can be mounted on a printed circuit board (PCB), but is not limited thereto.

[0028] The scan driver 130 can output a scan signal based on the gate timing control signal GDC supplied from the timing controller 120. The scan driver 130 can supply the scan signal to sub-pixels included in the display panel 150 through gate lines GL1 to GLm. The scan driver 130 can be implemented in an IC type, or can be directly disposed on the display panel 150 in a gate-in-panel (GIP) type, but is not limited thereto.

[0029] The data driver 140 can sample and latch the image data DATA based on the data timing control signal DDC supplied from the timing controller 120, and can map the latched data to a gamma compensation voltage to generate an analog data voltage. The data driver 140 can supply the data voltage to the sub-pixels included in the display panel 150 through data lines DL1 to DLn. The data driver 140 can be implemented in an IC type and can be mounted on the display panel 150 or the PCB, but is not limited thereto.

[0030] ​​The power circuit 180 can generate a first panel power EVDD having a high level and a second panel power EVSS having a low level based on a direct current (DC) input voltage supplied from the outside. The power circuit 180 can also generate a gate high voltage VGH and a gate low voltage VGL required to drive the scan driver 130 and a source voltage required to drive the data driver 140.

[0031] The display panel 150 can be supplied with a scan signal, a driving signal including a data voltage, the first panel power EVDD, and the second panel power EVSS to display an input image. Each of the sub-pixels of the display panel 150 can directly emit light. The display panel 150 can be manufactured based on a substrate such as glass, silicon resin, or polyimide having rigidity or ductility. Red, green, and blue sub-pixels can constitute one pixel, or red, green, blue, and white sub-pixels can constitute one pixel. In addition, the method in which a plurality of sub-pixels constitute one pixel can be variously modified. The sub-pixel SP can include a pixel circuit including a switching transistor, a driving transistor, a storage capacitor, and a light emitting diode.

[0032] Figure 3 FIG. 1 is a diagram schematically illustrating an overall circuit configuration including a safety circuit according to an embodiment of the disclosure.

[0033] Referring to Figure 3 The scan driver 130 can include a level shifter 135 and a gate shift register 131.

[0034] The level shifter 135 can generate a gate clock GCLK based on gate timing control signals GDC (e.g., a start signal VST, an on clock (OnCLK), and an off clock (Off CLK)) and a gate high voltage VGH and a gate low voltage VGL input from the power circuit 180. The gate clock GCLK can have different phases and can be supplied to the gate shift register 131 through different clock lines.

[0035] The gate shift register 131 can receive the gate clock GCLK from the level shifter 135 through a plurality of clock lines. The gate shift register 131 can receive the start signal VST from the timing controller 120 through a start line.

[0036] The gate shift register 131 can include a plurality of gate stages STG1 to STGm connected to each other in cascade and can generate scan signals SCAN1 to SCANm based on the gate clock GCLK and the start signal VST. Output terminals of the scan signals SCAN1 to SCANm can be connected to gate lines of the display panel and can supply the scan signals SCAN1 to SCANm to the gate lines.

[0037] In this embodiment, the safety circuit XY may include a level shifter 135 and a power circuit 180.

[0038] Safety circuit XY can detect short-circuit defects between the output terminals of level shifter 135 connected to the clock line. Short-circuit defects between the output terminals included in level shifter 135 can occur due to various reasons such as IC defects, short circuits caused by particles present during manufacturing, short circuits caused by panel cracks during assembly, and short circuits that occur during the packaging, movement, or installation of the device.

[0039] When a short circuit occurs between the output terminals included in the level shifter 135, overcurrent may flow in the power circuit 180. Whenever an overcurrent is detected, the power circuit 180 can generate a flag signal, and when the flag signal is repeatedly generated within a certain time period, the power circuit 180 can be shut down, thereby preventing abnormal operation of the device and ensuring operational stability.

[0040] Figure 4 This is a schematic diagram illustrating a comparative example of the safety circuit XY according to the present disclosure. Figure 5 This is an example Figure 4 A diagram showing the driving waveform of the safety circuit.

[0041] Reference Figure 4 In the safety circuit XY according to the comparative example, the level shifter 135 may include a first pulse generator 135A and a second pulse generator 135B, and the power circuit 180 may include a power generator 180A and an overcurrent detector 180B.

[0042] The first pulse generator 135A can generate a first pulse based on an on-clock and an off-clock input from the timing controller 120. The first pulse can be a first gating clock GCLKA shifted to a first phase as it oscillates between a gating high voltage VGH and a gating low voltage VGL. The rising edge of the first gating clock GCLKA can be synchronized with the rising edge of the on-clock, and the falling edge of the first gating clock GCLKA can be synchronized with the falling edge of the off-clock. The first gating clock GCLKA can be supplied to a first clock line via a first output terminal.

[0043] The second pulse generator 135B can generate a second pulse based on the on-clock and off-clock input from the timing controller 120. The second pulse can be a second gating clock GCLKB shifted to a second phase as it oscillates between the gating high voltage VGH and the gating low voltage VGL. The rising edge of the second gating clock GCLKB can be synchronized with the rising edge of the on-clock, and the falling edge of the second gating clock GCLKB can be synchronized with the falling edge of the off-clock. The second gating clock GCLKB can be supplied to a second clock line via a second output terminal.

[0044] The power generator 180A may include a boost converter containing a transistor Q1 and a flag signal generator that detects overcurrent flowing in the transistor Q1 to generate an overcurrent protection (OCP) flag signal. The boost converter can boost the input DC voltage in coordination with pulse-width modulation (PWM) operation of the transistor Q1, thus generating a gating high voltage VGH. When the drain voltage of the transistor Q1 is greater than a reference value, the flag signal generator can generate an OCP flag signal and supply the OCP flag signal to the overcurrent detector 180B.

[0045] The overcurrent detector 180B can shut down the power generator 180A based on the OCP flag signal.

[0046] The overcurrent detection and subsequent processing operations of the safety circuit XY will be briefly described below.

[0047] When the first output terminal of the first pulse generator 135A and the second output terminal of the second pulse generator 135B are short-circuited due to a defect (process (1)), a defective current path may appear from the high-voltage gate VGH terminal of the first pulse generator 135A to the low-voltage gate VGL terminal of the second pulse generator 135B, or a defective current path may appear from the high-voltage gate VGH terminal of the second pulse generator 135B to the low-voltage gate VGL terminal of the first pulse generator 135A (process (2)). Due to this defective current path, overcurrent may flow in the transistor Q1 of the power generator 180A and may generate an OCP flag signal (process (3)).

[0048] When the OCP flag signal is repeatedly input within a certain time period, the overcurrent detector 180B can shut down the power generator 180A ((4) process) and can stop the output of the gating high voltage VGH from the power generator 180A ((5) process).

[0049] In the safety circuit XY according to the comparative example described above, an overcurrent detection operation can be performed in the display driver used to display the input image. However, because the first gating clock GCLKA and the second gating clock GCLKB are in such a state... Figure 5In the display driver, the output has a phase difference of one on-clock cycle (or one off-clock cycle), so the time for a defective current path to form due to a short circuit between the first and second output terminals cannot be maintained for long and may be short. Figure 5 In this context, "DP" can represent the period during which a defective current path is formed when a short circuit occurs between the first output terminal and the second output terminal, and "NDP" can represent the period during which a defective current path is not formed even though a short circuit occurs between the first output terminal and the second output terminal.

[0050] like Figure 5 As illustrated, the period during which a defective current path is formed when a short circuit occurs between the first output terminal and the second output terminal can be the period during which one of the first gating clock GCLKA and the second gating clock GCLKB selects a high voltage VGH and the other selects a low voltage VGL. When both the first gating clock GCLKA and the second gating clock GCLKB select a high voltage VGH, no defective path will appear between the high voltage VGH and the low voltage VGL, even though a short circuit has occurred.

[0051] exist Figure 5 In this context, "DP" may be very short within a single conduction clock cycle. An OCP flag signal can be generated when the current flowing in transistor Q1 is higher than the OCP level. However, when the time for a defective current path to form due to a short circuit is short, the Q1 current flowing in transistor Q1 may struggle to reach the OCP level. (Refer to...) Figure 5 The Q1 current can increase in "DP" and decrease in "NDP". Since "DP" is not long enough for the Q1 current to reach the OCP level, the Q1 current cannot reach the OCP level and may decrease again.

[0052] As described above, in the safety circuit XY according to the comparative example above, because it is difficult to detect the overcurrent caused by the short circuit, subsequent actions such as shutting down may be delayed, and consequently, the stability of the device may be reduced.

[0053] Figure 6 This is a schematic diagram illustrating a configuration of a safety circuit XY according to an embodiment of the present disclosure.

[0054] Reference Figure 6 The safety circuit XY according to the embodiment may also include Figure 4 The comparative example does not include a clock supply circuit 135C, thus ensuring a long period of time for overcurrent detection. Figure 6 In the implementation method, with Figure 4Unlike the comparative example, when detecting overcurrent in a first time interval before display driving, the first time interval can be between the first and second pulses of the start signal VST, which is counted from the timing of applying system power. Display driving can begin from the second pulse of the start signal VST.

[0055] The clock supply circuit 135C may include a first output terminal for the output of a first gating clock GCLKA and a second output terminal for the output of a second gating clock GCLKB. In a first time interval immediately following the application of system power, the clock supply circuit 135C may supply one of a gating high voltage VGH and a gating low voltage VGL as a first test voltage to the first output terminal, and may supply the other of a gating high voltage VGH and a gating low voltage VGL as a second test voltage to the second output terminal. Therefore, the period during which a defect current path is formed when the first output terminal is short-circuited to the second output terminal can be extended to the first time interval. The first time interval may be longer than the first clock cycle of the first gating clock GCLKA or the second gating clock GCLKB, therefore, compared with... Figure 4 Compared to the comparative example, the time period used to detect overcurrent caused by a short circuit in the power circuit 180 can be increased.

[0056] Figure 7 This is an example Figure 6 A diagram showing the detailed configuration of the power circuit 180 included in the safety circuit XY.

[0057] Reference Figure 7 The power circuit 180 may include a power generator 180A and an overcurrent detector 180B.

[0058] The power generator 180A can boost the input DC voltage VI of the DC power supply to generate a gating high voltage VGH, and when the first and second output terminals of the clock supply circuit 135C are short-circuited to each other, the power generator 180A can detect the overcurrent flowing in transistor Q1 within a first time interval to generate an OCP flag signal. The power generator 180A may include a boost circuit for generating the gating high voltage VGH and a flag signal generator CMP for generating the OCP flag signal.

[0059] The boost circuit of the power generator 180A may include an inductor L connected between the DC power supply and node Nx, a transistor Q1 connected between node Nx and node SEN and alternately turned on or off based on a PWM control signal, a transistor Q2 connected between node Nx and node Ny and kept on based on a turn-on control signal, a switch controller PGM that generates PWM control signals and turn-on control signals to control the operation of transistors Q1 and Q2, a resistor R connected between node SEN and ground power supply GND, and a capacitor C connected between node Ny and ground power supply GND. Transistor Q2 can remain on, and transistor Q1 can be repeatedly turned on or off multiple times according to the PWM control signal; therefore, the input DC voltage VI can be boosted to the gate high voltage VGH.

[0060] The flag signal generator CMP of the power generator 180A compares the voltage of node SEN with a predetermined OCP level, and generates an OCP flag signal whenever the voltage of node SEN is higher than the OCP level. When the first and second output terminals of the clock supply circuit 135C are short-circuited to each other during a first time interval, overcurrent can flow in transistor Q1, and because the voltage of node SEN is higher than the OCP level when the overcurrent flows in transistor Q1, an OCP flag signal can be generated.

[0061] When the first and second output terminals of the clock supply circuit 135C are short-circuited to each other during a first time interval, the overcurrent detector 180B can receive an OCP flag signal from the power generator 180A to turn off the switch controller PGM of the power generator 180A. When the switch controller PGM is turned off, the output of the gating high voltage VGH from the power generator 180A can be stopped.

[0062] The overcurrent detector 180B can be implemented as a logic circuit. To increase the stability and reliability of the overcurrent detector 180B's operation, when the OCP flag signal is continuously input for the first time within the first time interval, the overcurrent detector 180B can self-restart. Then, after the restart operation is repeated for the second time, the power generator 180A can be turned off. The first number can be greater than the second number. In this embodiment, the first number can be 64 times and the second number can be 3 times, but the inventive concept is not limited to this.

[0063] Figure 8 This is an example Figure 6 A diagram showing the circuit configuration of the level shifter 135 included in the safety circuit XY.

[0064] Reference Figure 8The level shifter 135 may include a first pulse generator 135A, a second pulse generator 135B, and a clock supply circuit 135C.

[0065] The first pulse generator 135A can generate a first pulse based on a turn-on clock and a cut-off clock input from the timing controller 120. The first pulse can be a first gating clock GCLKA shifted to a first phase as it oscillates between a gating high voltage VGH and a gating low voltage VGL. The rising edge of the first gating clock GCLKA can be synchronized with the rising edge of the turn-on clock, and the falling edge of the first gating clock GCLKA can be synchronized with the falling edge of the cut-off clock (see [link to relevant documentation]). Figure 10 The first strobe clock GCLKA can be supplied to the first clock line through the first output terminal.

[0066] The first pulse generator 135A may include a first pull-up transistor TUA connected between an input terminal for selecting a high voltage VGH and a node NA, and turned on or off based on an on-time clock; and a first pull-down transistor TDA connected between a node NA and an input terminal for selecting a low voltage VGL, and turned on or off based on an off-time clock. When the first pull-up transistor TUA is on, the first pulse generator 135A may output a first pulse as the gate voltage VGH, and when the first pull-down transistor TDA is on, the first pulse generator 135A may output a first pulse as the gate voltage VGL.

[0067] The second pulse generator 135B can generate a second pulse based on the on-clock and off-clock inputs from the timing controller 120. The second pulse can be a second gating clock GCLKB shifted to a second phase as it oscillates between the gating high voltage VGH and the gating low voltage VGL. The rising edge of the second gating clock GCLKB can be synchronized with the rising edge of the on-clock, and the falling edge of the second gating clock GCLKB can be synchronized with the falling edge of the off-clock (see [link to relevant documentation]). Figure 10 The second strobe clock, GCLKB, can be supplied to the second clock line via the second output terminal.

[0068] The second pulse generator 135B may include a second pull-up transistor TUB connected between the input terminal for selecting the high voltage VGH and the node NB, and turned on or off based on an on-time clock; and a second pull-down transistor TDB connected between the node NB and the input terminal for selecting the low voltage VGL, and turned on or off based on an off-time clock. When the second pull-up transistor TUB is on, the second pulse generator 135B may output a second pulse as the high voltage VGH, and when the second pull-down transistor TDB is on, the second pulse generator 135B may output a second pulse as the low voltage VGL.

[0069] The clock supply circuit 135C may include a first output terminal CTA for the output of a first gating clock GCLKA and a second output terminal CTB for the output of a second gating clock GCLKB. During a first time interval immediately following the application of system power, the clock supply circuit 135C may supply one of a gating high voltage VGH and a gating low voltage VGL to the first output terminal CTA as a first test voltage (e.g., ...). Figure 9 and Figure 10 The second output terminal CTB can be supplied with either the gating high voltage VGH or the gating low voltage VGL as a second test voltage (e.g., VGL). Figure 9 and Figure 10 Therefore, the time period during which a defective current path is formed when the first output terminal CTA and the second output terminal CTB are short-circuited can be increased to the first time interval (see VGH). Figure 9 and Figure 10 (FT1).

[0070] For this purpose, during the first time interval, the clock supply circuit 135C can disconnect the electrical connection between node NA and the first output terminal CTA, and can also disconnect the electrical connection between node NB and the second output terminal CTB. Additionally, the clock supply circuit 135C can disconnect the electrical connection during the second time interval (see...). Figure 9 and Figure 10 FT2) connects node NA to the first output terminal CTA, and can connect node NB to the second output terminal CTB in the second time interval.

[0071] The clock supply circuit 135C may include a control voltage output circuit XGM, a first control transistor TA1, a second control transistor TB1, an inverter INV, a third control transistor TA2, and a fourth control transistor TB2.

[0072] The control voltage output circuit XGM can output a gating control voltage VG with a conduction level in a first time interval based on the start signal VST used to define a frame time, and can output a gating control voltage VG with a cutoff level in a second time interval following the first time interval.

[0073] The first control transistor TA1 can be connected between the first output terminal CTA and the input terminal for selecting the low voltage VGL, and can be turned on or off based on the selection control voltage VG. The first control transistor TA1 can be turned on during a first time interval based on the selection control voltage VG with an on level to supply the first test voltage VGL to the first output terminal CTA, and can remain off during a second time interval based on the selection control voltage VG with an off level.

[0074] The second control transistor TB1 can be connected between the second output terminal CTB and the input terminal for selecting the high voltage VGH, and can be turned on or off based on the selection control voltage VG. The second control transistor TB1 can be turned on during a first time interval based on the selection control voltage VG with an on level to supply the second test voltage VGH to the second output terminal CTB, and can remain off during a second time interval based on the selection control voltage VG with an off level.

[0075] The inverter INV can invert the gating control voltage VG with a conduction level to a gating control voltage VG with a cutoff level in a first time interval, and can invert the gating control voltage VG with a cutoff level to a gating control voltage VG with a conduction level in a second time interval.

[0076] The third control transistor TA2 can be connected between node NA and the first output terminal CTA, and can be turned on or off based on the output of inverter INV. The third control transistor TA2 can be turned off during a first time interval based on an inverted gating control voltage VG with a cutoff level to disconnect the electrical connection between node NA and the first output terminal CTA. In addition, it can be turned on during a second time interval based on an inverted gating control voltage VG with a conduction level to electrically connect node NA to the first output terminal CTA.

[0077] The fourth control transistor TB2 can be connected between node NB and the second output terminal CTB, and can be turned on or off based on the output of inverter INV. The fourth control transistor TB2 can be turned off during a first time interval based on an inverted gating control voltage VG with a cutoff level to disconnect the electrical connection between node NB and the second output terminal CTB. Conversely, it can be turned on during a second time interval based on an inverted gating control voltage VG with a conduction level to electrically connect node NB to the second output terminal CTB.

[0078] Figure 9 This illustrates the conditions under which overcurrent occurs. Figure 7 and Figure 8 The diagram shows the driving waveforms of the safety circuit XY. Figure 10 This illustrates the condition where no overcurrent occurs. Figure 7 and Figure 8 A diagram showing the driving waveform of the safety circuit.

[0079] Reference Figure 9 and Figure 10Within one frame immediately following the application of power, a first test voltage that selects the low voltage VGL can be supplied to the first output terminal CTA of the clock supply circuit 135C, and a second test voltage that selects the high voltage VGH can be supplied to the second output terminal CTB.

[0080] Therefore, as Figure 9 In the event of a short circuit between the first output terminal CTA and the second output terminal CTB, the defect current path between the high voltage VGH and the low voltage VGL is selected (see [reference]). Figure 8 The first time interval FT1, which is equal to the duration of one consecutive frame, can be formed within this first time interval FT1. The first time interval FT1 can be longer than one clock cycle of the first strobe clock GCLKA or the second strobe clock GCLKB. In other words, the first time interval FT1 can be longer than one on clock cycle (or one off clock cycle).

[0081] When the Q1 current flowing in transistor Q1 is higher than the OCP level, an OCP flag signal can be generated. According to this embodiment, because the time for a defective current path to form due to a short circuit is approximately one frame, the Q1 current flowing in transistor Q1 can easily reach the OCP level. Within the first time interval FT1, the OCP flag signal can be repeatedly generated whenever the Q1 current is higher than the OCP level. Furthermore, in Figure 9 In this process, the increase or decrease of the current of Q1 can be repeated in a certain cycle, and this can be based on the PWM operation of transistor Q1.

[0082] The overcurrent detector 180B can count the input of the OCP flag signal during the first time interval FT1 to increase the number of flag count signals FLAG_CNT. When the number of flag count signals FLAG_CNT is 64, the overcurrent detector 180B can generate an OCP shutdown signal OCP-SHDN. The flag count signal FLAG_CNT can be reset by the OCP shutdown signal OCP-SHDN, and the overcurrent detector 180B can self-restart.

[0083] The overcurrent detector 180B can perform a restart operation Restart_CNT three times, after which the power generator 180A can be shut down. When the power generator 180A is shut down, the output of the gating high voltage VGH from the power generator 180A can stop in the second time interval FT2, and the first gating clock GCLKA and the second gating clock GCLKB can maintain the ground voltage GND. As a result, the display drive can stop in the second time interval FT2.

[0084] In addition, such as Figure 10In the case where no short circuit occurs between the first output terminal CTA and the second output terminal CTB, the defect current path between the high voltage VGH and the low voltage VGL is selected (see [reference]). Figure 8 Therefore, the Q1 current may not reach the OCP level in the first time interval FT1, and the OCP flag signal may not be generated. In this case, the power generator 180A may not be turned off, and the high-voltage gate VGH may be output normally in the second time interval FT2. As a result, the first pulse generated by the first pulse generator 135A may be output as the first gate clock GCLKA in the second time interval FT2, and the second pulse generated by the second pulse generator 135B may be output as the second gate clock GCLKB. In addition, display driving may be performed in the second time interval FT2 based on the first gate clock GCLKA and the second gate clock GCLKB.

[0085] Figure 11 This is an example Figure 6 A diagram illustrating another circuit configuration of the level shifter included in the safety circuit XY. Figure 12 This illustrates the conditions under which overcurrent occurs. Figure 7 and Figure 11 The diagram shows the driving waveforms of the safety circuit XY. Figure 13 This illustrates the condition where no overcurrent occurs. Figure 7 and Figure 11 The diagram shows the driving waveforms of the safety circuit XY.

[0086] exist Figure 11 and Figure 12 In the configuration and operation of the level shifter 135, Figure 11 and Figure 12 The level shifter 135 may also include a first time regulator TMR in the clock supply circuit 135C, and therefore can be used with Figure 8 Different, and other configurations and operations can be basically the same as Figure 8 same.

[0087] exist Figure 12 and Figure 13 In this context, the time between the first and second pulses of the start signal VST can be defined as X-frame time, and the time between adjacent pulses following the second pulse can be defined as one frame time. In this case, X-frame time can be shorter than one frame time.

[0088] The first time regulator (TMR) can generate first time information based on an internal clock (internal CLK) that is shorter than the X-frame time and longer than one clock cycle of the first or second strobe clock. The first time information can be supplied to the control voltage output circuit XGM only during the first time interval FT1 of the X-frame time, and can be excluded from supplying the control voltage output circuit XGM during the second time interval FT2 of the X-frame time, excluding the first time interval FT1.

[0089] The control voltage output circuit XGM can output a gating control voltage VG with a conduction level in a first time interval FT1 that is shortened compared to the X frame time, based on the first time information and the start signal VST used to define the X frame time, and can output a gating control voltage VG with a cutoff level in a second time interval FT2 following the first time interval FT1.

[0090] When the time for applying the gating control voltage VG with a conduction level is shortened as described above, the starting timing of the second time interval FT2, which performs normal drive immediately after the application of system power under the condition that no overcurrent occurs, can be as follows: Figure 13 Earlier than in the middle, therefore, with Figure 9 In comparison, the time it takes for the screen to open normally can be reduced and user convenience can be increased.

[0091] In this embodiment, one of the gate high voltage and the gate low voltage can be supplied as a first test voltage to the first output terminal of the level shifter for the output of the first gate clock at a certain time before the display is driven (i.e., a relatively long period of time immediately after the system power is applied), and the other of the gate high voltage and the gate low voltage can be supplied as a second test voltage to the second output terminal of the level shifter for the output of the second gate clock.

[0092] Therefore, in this embodiment, a longer period of time for detecting overcurrent can be ensured when the first output terminal and the second output terminal are short-circuited to each other, thus improving the accuracy of overcurrent detection. Because the accuracy of overcurrent detection is improved in this embodiment, abnormal operation of the display device caused by overcurrent can be prevented, thereby enhancing the reliability and stability of the display device.

[0093] The effects of this disclosure are not limited to the examples above, and various other effects may be included in the specification.

[0094] While this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0095] Cross-reference to related applications

[0096] This application claims the benefit of Korean Patent Application No. 10-2021-0183729, filed on December 21, 2021, which is hereby incorporated by reference as fully set forth herein.

Claims

1. A display device, the display device comprising: The display panel is configured to be driven based on a first strobe clock and a second strobe clock; A clock supply circuit is configured to include a first output terminal for the output of a first gating clock and a second output terminal for the output of a second gating clock, and to supply one of a gating high voltage and a gating low voltage as a first test voltage to the first output terminal and to supply the other of the gating high voltage and the gating low voltage as a second test voltage to the second output terminal during a first time interval immediately following the supply of system power to the clock supply circuit; A power generator configured to generate the gating high voltage and the gating low voltage, and to supply the gating high voltage and the gating low voltage to the clock supply circuit; as well as An overcurrent detector is configured to receive a flag signal to identify an overcurrent from the power generator in order to shut down the power generator when the first output terminal and the second output terminal are short-circuited to each other during the first time interval. The first time interval is longer than one clock cycle of the first strobe clock or the second strobe clock.

2. The display device according to claim 1, further comprising a gating shift register configured to generate a scan signal based on a start signal, a first gating clock, and a second gating clock, and supply the scan signal to the gating lines of the display panel. in, The first time interval is between the first and second pulses of the start signal, which are counted from the timing of applying power to the system.

3. The display device according to claim 2, wherein, The first time interval is defined as a frame of time between the first pulse and the second pulse of the start signal.

4. The display device according to claim 2, wherein, The first time interval is shorter than the time between the first pulse and the second pulse of the starting signal.

5. The display device according to claim 4, wherein, The time between the first pulse and the second pulse of the starting signal is less than the time between adjacent pulses following the second pulse.

6. The display device according to claim 1, further comprising: A first pulse generator is configured to output a first pulse to a first node based on a turn-on clock and a turn-off clock, the first pulse being oscillating between the gating high voltage and the gating low voltage. as well as A second pulse generator is configured to output a second pulse to the second node based on the on-clock and the off-clock, the second pulse having a phase different from that of the first pulse. During the first time interval, the clock supply circuit disconnects the electrical connection between the first node and the first output terminal, as well as the electrical connection between the second node and the second output terminal.

7. The display device according to claim 6, wherein, During the second time interval following the first time interval, the clock supply circuit stops supplying the first test voltage to the first output terminal and stops supplying the second test voltage to the second output terminal, and electrically connects the first node and the second node to the first output terminal and the second output terminal, respectively.

8. The display device according to claim 7, wherein, Within the second time interval The first pulse output through the first output terminal is the first strobe clock, and The second pulse output through the second output terminal is the second strobe clock.

9. The display device according to claim 7, wherein, The clock supply circuit includes: A control voltage output circuit is configured to output a gating control voltage with a conduction level within a first time interval based on a start signal used to define a frame time. A first control transistor is turned on during the first time interval based on a gating control voltage having the on-level, so as to supply the first test voltage to the first output terminal. The second control transistor is turned on during the first time interval based on the gating control voltage having the on-level, so as to supply the second test voltage to the second output terminal; An inverter configured to invert the gating control voltage having the on level to a gating control voltage having the off level within the first time interval; A third control transistor, which is turned off during the first time interval based on the gating control voltage having the cutoff level, thereby disconnecting the electrical connection between the first node and the first output terminal; and A fourth control transistor, which is turned off during the first time interval based on the gating control voltage having the cutoff level, to disconnect the electrical connection between the second node and the second output terminal.

10. The display device according to claim 9, wherein, Within the second time interval The control voltage output circuit outputs the gating control voltage with a cutoff level. The first control transistor and the second control transistor are turned off based on the gating control voltage having the cutoff level. The inverter inverts the gating control voltage having the cutoff level into the gating control voltage having the on level. The third control transistor is turned on based on the gating control voltage having the on-level, so as to electrically connect the first node to the first output terminal, and The fourth control transistor is turned on based on the gating control voltage having the on level, so as to electrically connect the second node to the second output terminal.

11. The display device according to claim 1, wherein, Within the first time interval The overcurrent detector continuously receives the flag signal for the first count and then restarts itself. The overcurrent detector repeats the restart operation a second time and shuts down the power generator.

12. The display device according to claim 11, wherein the first number is greater than the second number.

13. An overcurrent detection method for a display device, the overcurrent detection method comprising the following steps: High-voltage and low-voltage gates are generated by using a power generator; In the first time interval immediately following the application of system power, one of the gating high voltage and the gating low voltage is supplied as a first test voltage to the first output terminal for the output of the first gating clock by using a clock supply circuit. During the first time interval, the clock supply circuit is used to supply the other of the gating high voltage and the gating low voltage as a second test voltage to the second output terminal for the output of the second gating clock. as well as When the first output terminal and the second output terminal are short-circuited to each other within the first time interval, an overcurrent detector is used to receive a flag signal to identify the overcurrent from the power generator, thereby shutting down the power generator. The first time interval is longer than one clock cycle of the first strobe clock or the second strobe clock.

14. The overcurrent detection method according to claim 13, wherein, The first time interval is between the first and second pulses of the start signal, which are counted from the timing of applying power to the system. The start signal defines a frame of time.

15. The overcurrent detection method according to claim 14, wherein, The first time interval is defined as a frame of time between the first pulse and the second pulse of the start signal.

16. The overcurrent detection method according to claim 14, wherein, The first time interval is shorter than the time between the first pulse and the second pulse of the starting signal.

17. The overcurrent detection method according to claim 13, wherein, The step of receiving the flag signal to shut down the power generator includes the following steps: The overcurrent detector is used to continuously receive the first count of the flag signal within the first time interval and then self-restart; then The overcurrent detector is used to repeat the restart operation a second time within the first time interval and then shut down the power generator.

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