Shift register, display driver and display panel

Abstract

The application discloses a shift register, a display driver and a display panel. The shift register comprises a first input module, a second input module, a control module and an output module. The second input module is electrically connected with a shift input end, a first clock input end of the shift register and a second control end of the output module, and the potential of the second control end is adjusted according to an input signal of the shift input end and a first clock signal. The control module is electrically connected with a second clock input end, a second voltage input end, a shift control end and a first control end of the output module, and is configured to input a second voltage signal of the second voltage input end to the first control end of the output module according to a second clock signal and a shift control signal of the shift control end when a first voltage signal is output from a shift output end of the shift register. The application can improve the ripple problem of the existing shift register.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a shift register, a display driver, and a display panel. Background Technology

[0002] With the development of display technology, the application of display panels is becoming more and more widespread, and the requirements for display panels are correspondingly becoming higher and higher.

[0003] The display panel needs to use shift registers to provide various scanning signals required for pixel display. However, existing shift registers will exhibit ripple when outputting pulses with long durations, resulting in inconsistent charging effects across rows of the display panel and consequently causing brightness differences in the display panel. Summary of the Invention

[0004] This invention provides a shift register, a display driver, and a display panel to improve the ripple problem of existing shift registers.

[0005] According to one aspect of the present invention, a shift register is provided, the shift register comprising: a first input module, a second input module, a control module, and an output module;

[0006] The first input module is electrically connected to the first voltage input, the first clock input, the second clock input, and the first control terminal of the output module, and is configured to adjust the potential of the first control terminal according to the first clock signal of the first clock input, the second clock signal of the second clock input, and the first voltage signal of the first voltage input.

[0007] The second input module is electrically connected to the shift input terminal of the shift register, the first clock input terminal, and the second control terminal of the output module, and is configured to adjust the potential of the second control terminal according to the input signal of the shift input terminal and the first clock signal;

[0008] The output module is electrically connected to the first voltage input terminal, the second voltage input terminal, and the shift output terminal of the shift register, and is configured to output the first voltage signal of the first voltage input terminal to the shift output terminal of the shift register according to the potential of the first control terminal; and to output the second voltage signal of the second voltage input terminal to the shift output terminal of the shift register according to the potential of the second control terminal.

[0009] The control module is electrically connected to the second clock input terminal, the second voltage input terminal, the shift control terminal, and the first control terminal. It is configured to input the second voltage signal from the second voltage input terminal to the first control terminal according to the second clock signal and the shift control signal from the shift control terminal when the first voltage signal is output from the shift output terminal of the shift register.

[0010] Optionally, the control module includes: a first control unit and a second control unit;

[0011] The first control unit and the second control unit are connected in series between the second voltage input terminal and the first control terminal. The control terminal of the first control unit is electrically connected to the shift control terminal, and the control terminal of the second control unit is electrically connected to the second clock input terminal.

[0012] Optionally, the on-level of the second control unit is logically opposite to that of the second voltage signal.

[0013] Optionally, the effective level of the first control terminal is logically opposite to the second voltage signal of the second voltage input terminal;

[0014] During the effective level time of the input signal, the pulse end time of the shift control signal is later than the pulse start time of the first effective pulse of the second clock signal, but earlier than the pulse start time of the second effective pulse of the second clock signal.

[0015] Optionally, the pulse start time of the shift control signal is the same as the pulse start time of the input signal;

[0016] Optionally, the duration of the effective pulses at the shift input and shift output of the shift register is greater than the period of the second clock signal;

[0017] Optionally, the duration of the effective pulses at the shift input and shift output of the shift register is longer than the duration of the effective pulses of the shift control signal.

[0018] Optionally, the first input module includes:

[0019] The system includes a power supply unit, a first adjustment unit, a second adjustment unit, and a coupling unit.

[0020] The first terminal of the power supply unit is electrically connected to the first voltage input terminal, the control terminal of the power supply unit is electrically connected to the first clock input terminal, and the second terminal of the power supply unit is electrically connected to the control terminal of the first adjustment unit.

[0021] The first terminal of the first adjustment unit is electrically connected to the second clock input terminal, and the second terminal of the first adjustment unit is electrically connected to the first terminal of the second adjustment unit.

[0022] The control terminal of the second adjustment unit is electrically connected to the second clock input terminal, and the second terminal of the second adjustment unit is electrically connected to the first control terminal.

[0023] The first end of the coupling unit is electrically connected to the control end of the first adjustment unit, and the second end of the coupling unit is electrically connected to the second end of the first adjustment unit.

[0024] Optionally, the shift register further includes: a first feedback module, which is electrically connected to the second control terminal, the first clock input terminal, and the second terminal of the power supply unit. The first feedback module is configured to write the first clock signal into the second terminal of the power supply unit according to the potential of the end of the second input module connected to the second control terminal.

[0025] Optionally, the shift register further includes a second feedback module, which is electrically connected to the second terminal, the second voltage input terminal, the second clock input terminal and the second control terminal of the power supply unit. The second feedback module is configured to adjust the potential of the second control terminal according to the potential of the second terminal of the power supply unit, the second clock signal and the first voltage signal.

[0026] Optionally, the shift register also includes a first normally open module, and the second end of the power supply unit is electrically connected to the control end of the first adjustment unit through the first normally open module.

[0027] Optionally, the second input module includes a shift input unit, a first terminal of which is electrically connected to a shift input terminal, a control terminal of which is electrically connected to a first clock input terminal, and a second terminal of which is electrically connected to a second control terminal.

[0028] Optionally, the shift register further includes a second normally open module, and the second terminal of the shift input unit is electrically connected to the second control terminal through the second normally open module.

[0029] Optionally, the output module includes:

[0030] First output unit, second output unit, and sustaining unit;

[0031] The first terminal of the first output unit is electrically connected to the second voltage input terminal, the second terminal of the first output unit is electrically connected to the shift output terminal, and the control terminal of the first output unit is electrically connected to the first control terminal; the conduction level of the first output unit is the effective level of the first control terminal, and the effective level of the first control terminal is logically opposite to the second voltage signal of the second voltage input terminal;

[0032] The first terminal of the second output unit is electrically connected to the first voltage input terminal, the second terminal of the second output unit is electrically connected to the shift output terminal, and the control terminal of the second output unit is electrically connected to the second control terminal.

[0033] The first end of the sustaining unit is electrically connected to the first end of the first output unit, and the second end of the sustaining unit is electrically connected to the control end of the first output unit.

[0034] According to another aspect of the present invention, a display driver is provided, the display driver comprising a plurality of cascaded shift registers as described above;

[0035] The display driver also includes multiple cascaded shift units, which are electrically connected to the shift control terminals of the corresponding shift registers to provide shift control signals to the corresponding shift registers.

[0036] According to another aspect of the present invention, a display panel is provided, the display panel including the display driver described above.

[0037] The technical solution of this embodiment of the invention employs a shift register comprising a first input module, a second input module, a control module, and an output module. The first input module is electrically connected to a first voltage input terminal, a first clock input terminal, a second clock input terminal, and a first control terminal of the output module, and is configured to adjust the potential of the first control terminal according to a first clock signal from the first clock input terminal, a second clock signal from the second clock input terminal, and a first voltage signal from the first voltage input terminal. The second input module is electrically connected to the shift input terminal of the shift register, the first clock input terminal, and a second control terminal of the output module, and is configured to adjust the potential of the second control terminal according to the input signal from the shift input terminal and the first clock signal. The output module is electrically connected to the first voltage input terminal, the second voltage input terminal, and the shift output terminal of the shift register. It is configured to output the first voltage signal from the first voltage input terminal to the shift output terminal of the shift register based on the potential of the first control terminal; and to output the second voltage signal from the second voltage input terminal to the shift output terminal of the shift register based on the potential of the second control terminal. The control module is electrically connected to the second clock input terminal, the second voltage input terminal, the shift control terminal, and the first control terminal. It is configured to input the second voltage signal from the second voltage input terminal to the first control terminal based on the second clock signal and the shift control signal of the shift control terminal when the first voltage signal is output from the shift output terminal of the shift register. By setting the control module to input the second voltage signal to the first control terminal, when the second clock signal is low, although the second clock signal pulls the potential of the first control terminal low, the control module inputs the second voltage signal to the first control terminal, preventing the potential of the first control terminal from being pulled too low. This prevents excessive changes in the conduction level of the corresponding unit in the output module, thereby improving the ripple phenomenon.

[0038] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the circuit structure of a pixel circuit in a related technology.

[0041] Figure 2 This is a timing diagram of a pixel circuit for a related technology;

[0042] Figure 3 This is a schematic diagram of the circuit structure of a shift register provided in an embodiment of the present invention;

[0043] Figure 4 A schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention;

[0044] Figure 5 A schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention;

[0045] Figure 6 A schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention;

[0046] Figure 7 A timing diagram of a shift register provided in an embodiment of the present invention;

[0047] Figure 8 A schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention;

[0048] Figure 9 A schematic diagram of the circuit structure of a display driver provided in an embodiment of the present invention;

[0049] Figure 10 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0050] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0051] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0052] As mentioned in the background section, existing shift registers exhibit ripple in their output. After careful research, the inventors discovered that the cause of this problem lies in the shift register's output module. This module outputs either a high or low level, generating the shift register's output signal. The control terminal within the output module, used to control the high-level output, is affected by the clock signal, causing varying degrees of conduction and resulting in ripple in the high-level output. The quality of the shift register's output signal determines the charging quality of the pixel circuit, such as... Figure 1 and Figure 2 As shown, Figure 1 This is a schematic diagram of the circuit structure of a pixel circuit in a related technology. Figure 2 This is a timing diagram of a pixel circuit in a related technology. Figure 1 and Figure 2 Correspondingly, the pixel circuit includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T6, a first initialization transistor T5, a second initialization transistor T7, and a storage capacitor Cst. It drives the light-emitting element to emit light through the coordination of scan signals S1 to S4, initialization signals Vref1 and Vref2, light-emitting control signal EM, and power signals ELVDD and ELVSS. Its working principle is well known to those skilled in the art and will not be elaborated here. The threshold compensation transistor T3 is an N-type transistor. The third scan signal S3 at the control electrode of the threshold compensation transistor T3 is active high. Within one frame, the effective time of the third scan signal S3 is relatively long, such as... Figure 2In this process, the effective time of the second scan signal S2 corresponding to the four rows of pixel circuits needs to be included. The high-level waveform of the third scan signal S3 is periodically used to pull the clock signal connected to the scan circuit that generates the second scan signal S3. The effective level of one pulse of the clock signal has the same duration as the effective level of the second scan signal S2, resulting in ripple in the third scan signal S3. When the third scan signal S3 has ripple, the impact on the charging of each row of pixels in the display panel will be different, resulting in differences in the brightness of each row in the display panel.

[0053] To address the aforementioned technical problems, the present invention proposes the following solutions:

[0054] Figure 3 This is a schematic diagram of the circuit structure of a shift register provided in an embodiment of the present invention, with reference to... Figure 3 The shift register includes: a first input module 11, a second input module 12, a control module 13, and an output module 14. The first input module 11 is electrically connected to a first voltage input terminal PVGL, a first clock input terminal SCK1, a second clock input terminal SCK2, and a first control terminal N1. The first input module 11 is configured to adjust the potential of the first control terminal N1 of the output module 14 according to the first clock signal from the first clock input terminal SCK1, the second clock signal from the second clock input terminal SCK2, and the first voltage signal from the first voltage input terminal PVGL. The second input module 12 is electrically connected to the shift input terminal SIN, the first clock input terminal SCK1, and the second control terminal N2 of the shift register. The second input module 12 is configured to adjust the potential of the second control terminal N2 of the output module 14 according to the input signal from the shift input terminal SIN and the first clock signal. The output module 14 is electrically connected to the first control terminal N1. 1. The second control terminal N2, the first voltage input terminal PVGL, the second voltage input terminal PVGH, and the shift output terminal Gout of the shift register are electrically connected. The output module 14 is configured to output the first voltage signal of the first voltage input terminal PVGL to the shift output terminal Gout of the shift register according to the potential of the first control terminal N1; and to output the second voltage signal of the second voltage input terminal PVGH to the shift output terminal Gout according to the potential of the second control terminal N2. The control module 13 is electrically connected to the second clock input terminal SCK2, the second voltage input terminal PVGH, the shift control terminal SIN2, and the first control terminal N1. The control module 13 is configured to input the second voltage signal of the second voltage input terminal PVGH to the first control terminal N1 according to the second clock signal and the shift control signal input by the shift control terminal SIN2 when the first voltage signal is output at the shift output terminal of the shift register.

[0055] Specifically, the shift register can shift the input signal at the shift input terminal SIN and output it at the shift output terminal Gout. The first voltage input terminal PVGL receives a first DC voltage signal, and the second voltage input terminal PVGH receives a second DC voltage signal. The high and low levels of the first and second voltage signals are different; for example, if the first voltage signal is low, the second voltage signal is high. In this embodiment, the pulse of the input signal is high, meaning the effective pulse of the input signal is a high-level pulse. The effective pulses of the first and second clock signals are pulses that turn on the corresponding switching units in the shift register, for example, a low level. The first and second clock signals have the same frequency but opposite phases, i.e., opposite timing. It can be understood that there may be a certain timing margin between the pulses of the first and second clock signals. The first input module 11 is used to adjust the potential of the first control terminal N1, and the second input module 12 is used to adjust the potential of the second control terminal N2. When the first control terminal N1 is at an active level (in this embodiment, the active levels of both the first control terminal N1 and the second control terminal N2 are low), the shift output terminal Gout outputs a second voltage signal; when the second control terminal N2 is at an active level, the shift output terminal Gout outputs a first voltage signal. When the control module 13 is not set, during the period when the first control terminal N1 is at a low level, that is, during the period when the shift output terminal Gout outputs the second voltage signal, the first control terminal N1 will be periodically pulled lower by the second clock signal, causing the conduction degree of the corresponding unit in the output module 14 to be periodically increased, thereby causing ripple in the signal of the shift output terminal Gout. In this embodiment, by setting the control module 13, the second voltage signal is periodically input to the first control terminal N1. It should be noted that the control module 13 may also output the second voltage signal only once to the first control terminal N1. That is, when the second clock signal is low, although the second clock signal pulls the potential of the first control terminal N1 low, the control module 13 inputs the second voltage signal to the first control terminal N1 at this time, so that the potential of the first control terminal N1 is not pulled too low, thereby preventing the conduction degree of the corresponding unit in the output module 14 from changing too much, thus improving the ripple phenomenon.

[0056] The technical solution of this embodiment employs a shift register with a first input module, a second input module, a control module, and an output module. The first input module is electrically connected to a first voltage input terminal, a first clock input terminal, a second clock input terminal, and a first control terminal of the output module, and is configured to adjust the potential of the first control terminal according to the first clock signal of the first clock input terminal, the second clock signal of the second clock input terminal, and the first voltage signal of the first voltage input terminal. The second input module is electrically connected to the shift input terminal, the first clock input terminal, and the second control terminal of the output module of the shift register, and is configured to adjust the potential of the second control terminal according to the input signal of the shift input terminal and the first clock signal. The module is electrically connected to the first voltage input terminal, the second voltage input terminal, and the shift output terminal of the shift register. It is configured to output the first voltage signal from the first voltage input terminal to the shift output terminal of the shift register based on the potential of the first control terminal; and to output the second voltage signal from the second voltage input terminal to the shift output terminal of the shift register based on the potential of the second control terminal. The control module is electrically connected to the second clock input terminal, the second voltage input terminal, the shift control terminal, and the first control terminal. It is configured to input the second voltage signal from the second voltage input terminal to the first control terminal based on the second clock signal and the shift control signal of the shift control terminal when the first voltage signal is output from the shift output terminal of the shift register. By configuring the control module to input the second voltage signal to the first control terminal, even when the second clock signal is low, although it pulls the potential of the first control terminal low, the control module still inputs the second voltage signal to the first control terminal, preventing the potential of the first control terminal from being pulled too low. This prevents excessive changes in the conduction level of the corresponding unit in the output module, thereby improving ripple.

[0057] Optionally, Figure 4 This is a schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention, referred to... Figure 4 The control module includes: a first control unit 131 and a second control unit 132; the first control unit 131 and the second control unit 132 are connected in series between the second voltage input terminal PVGH and the first control terminal N1, the control terminal of the first control unit 131 is electrically connected to the shift control terminal SIN2, and the control terminal of the second control unit 132 is electrically connected to the second clock input terminal SCK2.

[0058] Specifically, the first control unit 131 can be turned off during the pulse time of the shift control signal, that is, the pulse of the shift control signal controls the first control unit 131 to turn off. The second control unit 132 can be turned on during the effective pulse of the second clock signal. When the effective pulse of the second clock signal arrives, the second control unit 132 turns on, causing the second voltage signal to be written to the first control terminal N1, preventing the first control terminal N1 from being pulled too low by the second clock signal, thereby improving the ripple phenomenon. Optionally, such as Figure 4As shown, the first terminal of the first control unit 131 is electrically connected to the first control terminal N1, the second terminal of the first control unit 131 is electrically connected to the first terminal of the second control unit 132, and the second terminal of the second control unit 132 is electrically connected to the second voltage input terminal PVGH. Figure 5 The circuit structure diagram of another shift register provided in the embodiment of the present invention is shown. Optionally, the first terminal of the second control unit 132 is electrically connected to the first control terminal N1, the second terminal of the second control unit 132 is electrically connected to the first terminal of the first control unit 131, and the second terminal of the first control unit 132 is electrically connected to the second voltage input terminal PVGH.

[0059] Preferably, the conduction level of the second control unit 132 is logically opposite to that of the second voltage signal PVGH. For example, when the second voltage signal PVGH is high, the conduction level of the second control unit 132 is low.

[0060] Optionally, Figure 6 This is a schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention, referred to... Figure 6 The first input module includes: a power supply unit 111, a first adjustment unit 112, a second adjustment unit 113, and a coupling unit 114.

[0061] The first terminal of the power supply unit 111 is electrically connected to the first voltage input terminal PVGL, the control terminal of the power supply unit 111 is electrically connected to the first clock input terminal SCK1, and the second terminal of the power supply unit 111 is electrically connected to the control terminal of the first adjustment unit 112. The power supply unit 111 is configured to be turned on in response to a signal from the control terminal of the power supply unit 111, thereby transmitting the signal from the first terminal of the power supply unit 111 to the second terminal of the power supply unit 111.

[0062] The second terminal of the first adjustment unit 112 is electrically connected to the second clock input terminal SCK2, and the second terminal of the first adjustment unit 112 is electrically connected to the first terminal of the second adjustment unit 113. The first adjustment unit 111 is configured to transmit the signal from the first terminal of the first adjustment unit 111 to the second terminal of the first adjustment unit 111 in response to the signal turn-on of the control terminal of the first adjustment unit 111.

[0063] The control terminal of the second adjustment unit 113 is electrically connected to the second clock input terminal SCK2, and the second terminal of the second adjustment unit 113 is electrically connected to the first control terminal N1. The second adjustment unit 113 is configured to transmit the signal from the first terminal of the second adjustment unit 113 to the second terminal in response to the signal turn-on of the control terminal of the second adjustment unit 113.

[0064] The first end of the coupling unit 114 is electrically connected to the control end of the first adjustment unit 112, and the second end of the coupling unit 114 is electrically connected to the second end of the first adjustment unit 112.

[0065] The second input module includes a shift input unit 121. The first terminal of the shift input unit 121 is electrically connected to the shift input terminal SIN; the control terminal of the shift input unit 121 is electrically connected to the first clock input terminal SCK1; and the second terminal of the shift input unit 121 is electrically connected to the second control terminal N2. The shift input unit 121 is configured to transmit the signal from its first terminal to its second terminal in response to a signal being turned on at its control terminal.

[0066] Optionally, the output module includes a first output unit 141, a second output unit 142, and a holding unit 143. A first terminal of the first output unit 141 is electrically connected to a second voltage input terminal PVGH, a second terminal of the first output unit 141 is electrically connected to a shift output terminal Gout, and a control terminal of the first output unit 141 is electrically connected to a first control terminal N1. The first output unit 141 is configured to transmit a signal from its first terminal to its second terminal in response to a signal turn-on at its control terminal. The turn-on level of the first output unit 141 is the effective level of the first control terminal N1, and the effective level of the first control terminal N1 is logically opposite to the second voltage signal at the second voltage input terminal. The first terminal of the second output unit 142 is electrically connected to the first voltage input terminal PVGL, and the second terminal of the second output unit 142 is electrically connected to the shift output terminal Gout. The control terminal of the second output unit 142 is electrically connected to the second control terminal N2. The second output unit 142 is configured to transmit the signal from the first terminal of the second output unit 142 to the second terminal in response to the signal turn-on of the control terminal of the second output unit 142. The first terminal of the holding unit 143 is electrically connected to the first terminal of the first output unit 141, and the second terminal of the holding unit 143 is electrically connected to the control terminal of the first output unit 141.

[0067] Optionally, continue to refer to Figure 6 The shift register may also include a first feedback module 15, which is electrically connected to the second control terminal N2, the first clock input terminal SCK1, and the first terminal of the power supply unit 111. The first feedback module 15 is configured to write the first clock signal into the second terminal of the power supply unit 111 according to the potential of the terminal of the second input module 12 connected to the second control terminal N2.

[0068] The shift register may also include a second feedback module 16, which is electrically connected to the second terminal of the power supply unit 111, the second voltage input terminal PVGH, the second clock input terminal SCK2 and the second control terminal N2. The second feedback module 16 is configured to adjust the potential of the second control terminal N2 according to the potential of the second terminal of the power supply unit 111, the second clock signal and the first voltage signal.

[0069] Specifically, the first feedback module 15 is used to provide feedback on the potential of the second terminal of the power supply unit 111. When the second control terminal is at a low level, the first clock signal SCK1 is written to the second terminal of the power supply unit 111, thereby providing feedback on the state of the first adjustment unit and ensuring the stability of the shift register output signal.

[0070] The second feedback module 16 is used to control the potential of the second control terminal to ensure the stability of the shift register output signal.

[0071] Figure 7 This is a timing diagram of a shift register provided in an embodiment of the present invention. Figure 7 and Figure 6 Corresponding, combined Figure 7 and Figure 6 The operating timing of this invention will be described. It should be noted that in this embodiment, all units are assumed to be off at the second level and on at the first level. One of the first and second levels can be high, and the other can be low. The second level can be high, and the first level can be low. Optionally, the effective level of the first control terminal N1 is logically opposite to the second voltage signal of the second voltage input terminal PVGH. When the first control terminal N1 is active, the output module 14 transmits the second voltage signal from the second voltage input terminal to the shift output terminal of the shift register.

[0072] Optionally, during the effective level time of the input signal, the pulse end time of the shift control signal is later than the pulse start time tx of the first effective pulse of the second clock signal, and earlier than the pulse start time ty of the second effective pulse of the second clock signal. This ensures that the shift register can normally shift the signal at the shift input terminal and output it from its shift output terminal, while minimizing the influence of the second clock signal and improving ripple as early as possible.

[0073] In the first stage T1, the input signal is at a first level, for example, a low level; the shift control signal is at a first level; the first clock signal is at a second level, for example, a high level; and the second clock signal is at a first level. At this time, the power supply unit 111 and the shift input unit 121 are off, and the second control terminal N2 maintains the state of the previous stage. The first control unit 131 and the second control unit 132 are on, causing the first control terminal N1 to write a second voltage signal (i.e., the second level), thereby controlling the first output unit 141 to turn off. At this time, the shift output terminal Gout maintains the state of the previous stage, that is, maintains the first level.

[0074] In the second stage T2, the input signal is at a second level, for example, a high level; the shift control signal is at a second level; the first clock signal is at a first level, for example, a low level; and the second clock signal is at a second level. At this time, the power supply unit 111 and the shift input unit 121 are turned on, and the second control terminal N2 is written with the second level. Therefore, the second output unit 142 remains off, and the power supply unit 111 transmits the first voltage signal (i.e., the first level) to the control terminal of the first adjustment unit 112. The control terminal of the first adjustment unit 112 is written with the first level, and the first adjustment unit 112 is turned on. Since the second clock signal is at a second level at this time, the second adjustment unit 113 is turned off. The first terminal of the coupling unit 114 is written with the first level, and the second terminal is written with the second level. The first control unit 131 is turned off, and the second control unit 132 is turned off. That is, at this time, the first control terminal N1 maintains the potential of the previous stage, i.e., maintains the second level. Therefore, the shift output terminal Gout maintains the state of the previous stage, i.e., maintains the first level.

[0075] In the third stage T3, the input signal is at the second level, for example, a high level. The first valid pulse of the second clock signal arrives within the effective level time of the input signal, and the second clock signal becomes the first level, for example, a low level. At this time, the power supply unit 111 and the shift input unit 121 are turned off. Because the first terminal of the coupling unit 114 maintains the first level, the first adjustment unit 112 is turned on, causing the first level of the second clock signal to be written to the first terminal of the second adjustment unit. The second adjustment unit 113 is turned on under the control of the second clock signal. Therefore, the first control terminal N1 is written with the first level, causing the first output unit 141 to turn on, thereby causing the shift output terminal Gout to output the second level. During this stage, because the pulse end time of the shift control signal is set later than the pulse start time of the first valid pulse of the second clock signal, the second level of the shift control signal and the pulse of the second clock signal have at least a partial overlap period. During this period, only the first level is written to the first control terminal N1. Therefore, it can be ensured that in the third stage T3, the first control terminal N1 is first pulled low to a certain extent, ensuring that the first output unit 141 can be turned on smoothly, thereby ensuring that the shift output terminal Gout can output the second level normally.

[0076] In the fourth stage T4, the input signal is at the second level, for example, a high level. The shift control signal can be at either the second or first level. The first clock signal is at the first level, for example, a low level, and the second clock signal is at the second level. At this time, the power supply unit 111 and the shift input unit 121 are turned on, and the second control terminal N2 is written with the second level, so the second output unit 142 remains off. The control terminal of the first adjustment unit 112 is written with the first level, and the first adjustment unit 112 is turned on. Since the second clock signal is at the second level at this time, the second adjustment unit 113 is turned off. The first terminal of the coupling unit 114 is written with the first level, and the second terminal is written with the second level. The first control unit 131 is turned off, and the second control unit 132 is turned off. That is, at this time, the first control terminal N1 maintains the potential of the previous stage, that is, maintains the first level. Therefore, the shift output terminal Gout maintains the state of the previous stage, that is, maintains the second level.

[0077] In the fifth stage T5, the input signal is at the second level, for example, a high level. The second clock signal arrives during the second valid pulse of the input signal's valid level time, and the second clock signal is at the first level, for example, a low level. At this time, the power supply unit 111 and the shift input unit 121 are turned off. The first terminal of the coupling unit 114 maintains the first level, causing the first adjustment unit 112 to conduct, so that the first level of the second clock signal is written to the first terminal of the second adjustment unit 113. The second adjustment unit 113 conducts under the control of the first level of the second clock signal. Since the second clock signal SCK1 is at the first level, the second clock signal at the first level is written to the first control terminal N1 after passing through the first adjustment unit 112 and the second adjustment unit 113. At this time, if there is no first control unit 131 and the second control unit 132, the first control terminal N1 will be further pulled low. If no processing is performed, it will cause the first output unit 141 to conduct more deeply, generating ripple. This causes the conduction level of the first output unit 141 to change, which in turn causes the shift output terminal Gout to output a second level with ripple. During this stage, because the pulse end time of the shift control signal is set earlier than the pulse start time of the second effective pulse of the second clock signal, the shift control signal can be at the first level during this period. The first control unit 131 is turned on. Since the second control unit 132 is also turned on, the second voltage signal can be written to the first control terminal N1 during this stage, so that the potential of the first control terminal N1 will not be pulled too low by the second clock signal. This will prevent the conduction level of the first output unit 141 from changing too much, thereby improving the ripple phenomenon. It should be noted that the potential of the first control terminal N1 is still low at this time, and the first output unit 141 is still in the turned-on state.

[0078] In stage T6, the input signal is at a first level, for example, low; the shift control signal is at a first level; the first clock signal is at a first level; and the second clock signal is at a second level, for example, high. At this time, the power supply unit 111 and the shift input unit 121 are turned on, and the second control terminal N2 is written with the first level, thus pulling the second output unit 142 low to a certain extent. The control terminal of the first adjustment unit 112 is written with the first level, and the first adjustment unit 112 is turned on. Since the second clock signal is at a second level at this time, the second adjustment unit 113 is turned off. The first terminal of the coupling unit 114 is written with the first level, and the second terminal is written with the second level. The first control unit 131 is turned on, and the second control unit 132 is turned off. That is, the first control terminal N1 maintains the potential of the previous stage, i.e., maintains the first level. Therefore, the shift output terminal Gout is pulled low.

[0079] In stage T7, the input signal is at a first level (e.g., low), the second clock signal is at a first level, the first clock signal is at a second level (e.g., high), and the shift control signal can be at a first level. At this time, the first feedback module 15 is turned on, and the control terminal of the first adjustment unit 112 is written with a second level, thus turning off the first adjustment unit 112. Simultaneously, both the first control unit 131 and the second control unit 132 are turned on, the first control node N1 is written with a second level, and the first output unit 141 is turned off. At this time, the power supply unit 111 and the shift input unit 121 are turned off. The second control terminal N2 is further coupled low because the end of the second feedback module 16 connected to the second clock signal input terminal jumps to a first level, causing the second output unit 142 to fully conduct, thereby further pulling the signal of the shift output terminal Gout low.

[0080] Optionally, the duration of the effective pulses at the shift input and shift output of the shift register is greater than the period of the second clock signal. For example, the duration of the effective pulses at the shift input and shift output of the shift register is n times the period of the second clock signal, where n is an integer greater than or equal to 2, such as 4.

[0081] Optionally, the duration Tx of the effective pulses at the shift input and shift output of the shift register is greater than the duration Ty of the effective pulses of the shift control signal. Optionally, the duration Ty of the effective pulses of the shift control signal is greater than the duration Tz of the effective level of the second clock signal. Figure 7 An example is drawn showing the case where the effective levels of the first and second clock signals are low, and the effective levels of the shift control signal, the shift input terminal, and the shift output terminal of the shift register are high.

[0082] Optionally, continue to refer to Figure 6 The shift register also includes a first normally open module 17. The second end of the power supply unit 111 is electrically connected to the control end of the first adjustment unit 112 through the first normally open module 17. The first end of the first normally open module 17 is electrically connected to the second end of the power supply unit 111, the second end of the first normally open module 17 is electrically connected to the control end of the first adjustment unit 112, and the control end of the first normally open module 17 is electrically connected to the first voltage input terminal PVGL.

[0083] Optionally, the shift register further includes a second normally open module 18. The first terminal of the second normally open module 18 is electrically connected to the second terminal of the shift input unit 121, the second terminal of the second normally open module 18 is electrically connected to the second control terminal N2, and the control terminal of the second normally open module 18 is electrically connected to the first voltage input terminal PVGL. The first normally open module 17 is normally open and is used to improve the leakage current of the control terminal of the first adjustment unit 112; the second normally open module 18 is normally open and is used to improve the leakage current of the second control terminal N2.

[0084] For example, such as Figure 8 As shown, Figure 8 This is a schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention. The power supply unit 111 includes a first transistor m1, the first terminal of the first transistor m1 serves as the first terminal of the power supply unit 111, the second terminal of the first transistor m1 serves as the second terminal of the power supply unit 111, and the control terminal of the first transistor m1 serves as the control terminal of the power supply unit 111.

[0085] The shift input unit 112 includes a second transistor m2. The first terminal of the second transistor m2 serves as the first terminal of the shift input unit 112, the second terminal of the second transistor m2 serves as the second terminal of the shift input unit 112, and the control terminal of the second transistor m2 serves as the control terminal of the shift input unit 112.

[0086] The first feedback module 15 includes a third transistor m3. The first terminal of the third transistor m3 serves as the first terminal of the first feedback module 15, the second terminal of the third transistor m3 serves as the second terminal of the first feedback module 15, and the control terminal of the third transistor m3 serves as the control terminal of the first feedback module 15. The third transistor m3 can be a dual-gate transistor, which is equivalent to two transistors connected in series.

[0087] The second feedback module 16 includes a fourth transistor m4, a fifth transistor m5, and a third capacitor C3. The first terminal of the fourth transistor m4 is electrically connected to the second voltage input terminal PVGH, the second terminal of the fourth transistor m4 is electrically connected to the first terminal of the fifth transistor m5, and the control terminal of the fourth transistor m4 is electrically connected to the second terminal of the first transistor m1. The second terminal of the fifth transistor m5 is electrically connected to the second clock input terminal SCK2. The control terminal of the fifth transistor m5 is electrically connected to the second control terminal N2. The first terminal of the third capacitor C3 is electrically connected to the second terminal of the fourth transistor m4, and the second terminal of the third capacitor C3 is electrically connected to the second control terminal N2. In the sixth stage T6, the fourth transistor m4 is turned on, the fifth transistor m5 is turned off, the terminal of the third capacitor C3 connected to the second control terminal is at a first voltage level, and the terminal of the third capacitor C3 connected to the fifth transistor m5 is at a second voltage level. In the sixth stage T6, the fourth transistor m4 is turned off and the fifth transistor m5 is turned on. The second clock signal jumps from the second level to the first level. Through the coupling effect of the third capacitor C3, the second control terminal N2 is further pulled low, so that the second output unit 142 is fully turned on, and the signal of the shift output terminal Gout is further pulled low.

[0088] The first adjustment unit 112 includes a sixth transistor m6. The first terminal of the sixth transistor m6 serves as the first terminal of the first adjustment unit 112, the second terminal of the sixth transistor m6 serves as the second terminal of the first adjustment unit 112, and the control terminal of the sixth transistor m6 serves as the control terminal of the first adjustment unit 112.

[0089] The second adjustment unit 113 includes a seventh transistor m7. The first terminal of the seventh transistor m7 serves as the first terminal of the second adjustment unit 113, the second terminal of the seventh transistor m7 serves as the second terminal of the second adjustment unit 113, and the control terminal of the seventh transistor m7 serves as the control terminal of the second adjustment unit 113.

[0090] The first control unit 131 includes an eighth transistor m8, the first terminal of the eighth transistor m8 serves as the first terminal of the first control unit 131, the second terminal of the eighth transistor m8 serves as the second terminal of the first control unit 131, and the control terminal of the eighth transistor m8 serves as the control terminal of the first control unit 131.

[0091] The second control unit 132 includes a ninth transistor m9. The first terminal of the ninth transistor m9 serves as the first terminal of the second control unit 132, the second terminal of the ninth transistor m9 serves as the second terminal of the second control unit 132, and the control terminal of the ninth transistor m9 serves as the control terminal of the second control unit 132.

[0092] The first output unit 141 includes a tenth transistor m10. The first terminal of the tenth transistor m10 serves as the first terminal of the first output unit 141, the second terminal of the tenth transistor m10 serves as the second terminal of the first output unit 141, and the control terminal of the tenth transistor m10 serves as the control terminal of the first output unit 141.

[0093] The second output unit 142 includes an eleventh transistor m11. The first terminal of the eleventh transistor m11 serves as the first terminal of the second output unit 142, the second terminal of the eleventh transistor m11 serves as the second terminal of the second output unit 142, and the control terminal of the eleventh transistor m11 serves as the control terminal of the second output unit 142.

[0094] The first normally open module 17 includes a twelfth transistor m12. The first terminal of the twelfth transistor m12 is electrically connected to the second terminal of the first transistor m1. The second terminal of the twelfth transistor m12 is electrically connected to the control terminal of the sixth transistor m6. The control terminal of the twelfth transistor m12 is electrically connected to the first voltage input terminal PVGL.

[0095] The second normally open module 18 includes a thirteenth transistor m14. The first terminal of the thirteenth transistor m14 is electrically connected to the second terminal of the second transistor m2. The second terminal of the thirteenth transistor m13 is electrically connected to the second control terminal N2. The control terminal of the thirteenth transistor m13 is electrically connected to the first voltage input terminal PVGL.

[0096] The coupling unit 114 includes a first capacitor C1, with the first end of the first capacitor C1 serving as the first end of the coupling unit 114 and the second end of the first capacitor C1 serving as the second end of the coupling unit 114.

[0097] The sustaining module 143 includes a second capacitor C2, the first end of the second capacitor C2 serves as the first end of the sustaining module 143, and the second end of the second capacitor C2 serves as the second end of the sustaining module 143.

[0098] Optional, such as Figure 8 As shown, the first transistor m1 to the thirteenth transistor m13 can be P-type transistors. Optionally, the first transistor m1 to the thirteenth transistor m13 can be N-type transistors. Optionally, some of the first transistor m1 to the thirteenth transistor m13 can be P-type transistors, and the rest can be N-type transistors.

[0099] Optionally, continue to refer to Figure 4 The pulse start time of the shift control signal is the same as the pulse start time of the input signal. This setting ensures that the rising edges of both are the same, allowing the shift control signal and input signal required for the first-stage shift register to be generated using a simple circuit. Alternatively, the input signal can be used to generate the shift control signal using a simple circuit, which helps reduce the complexity of the display panel.

[0100] The present invention also provides a display driver, such as Figure 9 As shown, Figure 9 This is a schematic diagram of the circuit structure of a display driver provided in an embodiment of the present invention. The display driver includes a plurality of cascaded shift registers 1 provided in any embodiment of the present invention; the display driver also includes a plurality of cascaded shift units 2, each shift unit 2 being electrically connected to the shift control terminal SIN2 of the corresponding shift register 1, for providing shift control signals to the corresponding shift register.

[0101] Specifically, the display driver can be used in a display panel to provide scanning signals to the display panel. The display driver may also include a first clock line CK1 and a second clock line CK2, used to provide the first clock signal and the second clock signal, respectively. In odd-level shift registers, the first clock signal terminal is electrically connected to the first clock line CK1, and the second clock signal terminal is electrically connected to the second clock line CK2. In even-level shift registers, the first clock signal terminal is electrically connected to the second clock line CK2, and the second clock signal terminal is electrically connected to the first clock line CK1. The cascaded shift unit 2 is used to shift the shift control signal, thereby providing shift control signals to the corresponding shift register.

[0102] The display driver provided in the embodiments of the present invention includes the shift register provided in any embodiment of the present invention, and therefore has the same beneficial effects, which will not be described again here.

[0103] This invention also provides a display panel. Figure 10 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, with reference to... Figure 10 The display panel includes a display driver 201 and a multi-row pixel circuit PX provided in any embodiment of the present invention. The pixel circuit includes a driving module, a light-emitting module, a data writing module, a first initialization module, and a storage module. The driving module generates a driving current, and the light-emitting module responds to the driving current. The storage module maintains the level of the driving module control terminal. The first initialization module initializes the level of the driving module control terminal during the initialization phase. The data writing module writes data signals to the driving module control terminal during the data writing phase. The display panel provided in the embodiments of the present invention includes a shift register provided in the embodiments of the present invention. Because the shift register has weak ripple, the charging effect of each row of pixels in the display panel is relatively similar, and the brightness difference is small. Of course, the shift unit can also be connected to the pixel circuit PX in the display panel to provide a scanning signal to the pixel circuit PX in the display panel.

[0104] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0105] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A shift register, characterized in that, The shift register includes: a first input module, a second input module, a control module, and an output module; The first input module is electrically connected to the first voltage input terminal, the first clock input terminal, the second clock input terminal, and the first control terminal of the output module, and is configured to adjust the potential of the first control terminal according to the first clock signal of the first clock input terminal, the second clock signal of the second clock input terminal, and the first voltage signal of the first voltage input terminal; The second input module is electrically connected to the shift input terminal of the shift register, the first clock input terminal, and the second control terminal of the output module, and is configured to adjust the potential of the second control terminal according to the input signal of the shift input terminal and the first clock signal; The output module is electrically connected to the first voltage input terminal, the second voltage input terminal, and the shift output terminal of the shift register, and is configured to output a first voltage signal from the first voltage input terminal to the shift output terminal of the shift register according to the potential of the first control terminal; and to output a second voltage signal from the second voltage input terminal to the shift output terminal of the shift register according to the potential of the second control terminal. The control module is electrically connected to the second clock input terminal, the second voltage input terminal, the shift control terminal, and the first control terminal, and is configured to input the second voltage signal of the second voltage input terminal to the first control terminal according to the second clock signal and the shift control signal of the shift control terminal when the first voltage signal is output at the shift output terminal of the shift register; The control module includes: a first control unit and a second control unit; The first control unit and the second control unit are connected in series between the second voltage input terminal and the first control terminal. The control terminal of the first control unit is electrically connected to the shift control terminal, and the control terminal of the second control unit is electrically connected to the second clock input terminal. The conduction level of the second control unit is logically opposite to that of the second voltage signal.

2. The shift register according to claim 1, characterized in that, The first control unit includes an eighth transistor, the first terminal of the eighth transistor serves as the first terminal of the first control unit, the second terminal of the eighth transistor serves as the second terminal of the first control unit, and the control terminal of the eighth transistor serves as the control terminal of the first control unit.

3. The shift register according to claim 1, characterized in that, The second control unit includes a ninth transistor, wherein the first terminal of the ninth transistor serves as the first terminal of the second control unit, the second terminal of the ninth transistor serves as the second terminal of the second control unit, and the control terminal of the ninth transistor serves as the control terminal of the second control unit.

4. The shift register according to claim 1, characterized in that, The effective level of the first control terminal is logically opposite to the second voltage signal of the second voltage input terminal; During the effective level time of the input signal, the pulse end time of the shift control signal is later than the pulse start time of the first effective pulse of the second clock signal, and earlier than the pulse start time of the second effective pulse of the second clock signal.

5. The shift register according to claim 4, characterized in that, The pulse start time of the shift control signal is the same as the pulse start time of the input signal.

6. The shift register according to claim 4, characterized in that, The duration of the effective pulses at the shift input and shift output terminals of the shift register is greater than the period of the second clock signal.

7. The shift register according to claim 4, characterized in that, The duration of the effective pulses at the shift input and shift output terminals of the shift register is greater than the duration of the effective pulses of the shift control signal.

8. The shift register according to claim 4, characterized in that, The duration of the effective pulse of the shift control signal is greater than the duration of the effective level of the second clock signal.

9. The shift register according to claim 1, characterized in that, The first input module includes: The system includes a power supply unit, a first adjustment unit, a second adjustment unit, and a coupling unit. The first end of the power supply unit is electrically connected to the first voltage input terminal, the control terminal of the power supply unit is electrically connected to the first clock input terminal, and the second end of the power supply unit is electrically connected to the control terminal of the first adjustment unit. The first end of the first adjustment unit is electrically connected to the second clock input terminal, and the second end of the first adjustment unit is electrically connected to the first end of the second adjustment unit. The control terminal of the second adjustment unit is electrically connected to the second clock input terminal, and the second terminal of the second adjustment unit is electrically connected to the first control terminal. The first end of the coupling unit is electrically connected to the control end of the first adjustment unit, and the second end of the coupling unit is electrically connected to the second end of the first adjustment unit.

10. The shift register according to claim 9, characterized in that, The first adjustment unit is configured to transmit the signal from the first end of the first adjustment unit to the second end of the first adjustment unit in response to the signal being turned on at the control terminal of the first adjustment unit.

11. The shift register according to claim 9, characterized in that, The power supply unit is configured to be turned on in response to a signal from the control terminal of the power supply unit, thereby transmitting a signal from the first terminal of the power supply unit to the second terminal of the power supply unit.

12. The shift register according to claim 9, characterized in that, The second adjustment unit is configured to transmit the signal from the first end of the second adjustment unit to the second end of the second adjustment unit in response to the signal being turned on at the control terminal of the second adjustment unit.

13. The shift register according to claim 9, characterized in that, The coupling unit includes a first capacitor, with a first end of the first capacitor serving as the first end of the coupling unit and a second end of the first capacitor serving as the second end of the coupling unit.

14. The shift register according to claim 9, characterized in that, The first adjustment unit includes a sixth transistor, the first terminal of the sixth transistor serves as the first terminal of the first adjustment unit, the second terminal of the sixth transistor serves as the second terminal of the first adjustment unit, and the control terminal of the sixth transistor serves as the control terminal of the first adjustment unit.

15. The shift register according to claim 9, characterized in that, The second adjustment unit includes a seventh transistor, wherein the first terminal of the seventh transistor serves as the first terminal of the second adjustment unit, the second terminal of the seventh transistor serves as the second terminal of the second adjustment unit, and the control terminal of the seventh transistor serves as the control terminal of the second adjustment unit.

16. The shift register according to claim 9, characterized in that, The shift register further includes a first feedback module, which is electrically connected to the second control terminal, the first clock input terminal, and the second terminal of the power supply unit. The first feedback module is configured to write the first clock signal into the second terminal of the power supply unit according to the potential of the end of the second input module connected to the second control terminal.

17. The shift register according to claim 16, characterized in that, The first feedback module includes a third transistor, the first terminal of the third transistor serves as the first terminal of the first feedback module, the second terminal of the third transistor serves as the second terminal of the first feedback module, and the control terminal of the third transistor serves as the control terminal of the first feedback module.

18. The shift register according to claim 16, characterized in that, The shift register further includes a second feedback module, which is electrically connected to the second terminal of the power supply unit, the second voltage input terminal, the second clock input terminal, and the second control terminal. The second feedback module is configured to adjust the potential of the second control terminal according to the potential of the second terminal of the power supply unit, the second clock signal, and the first voltage signal.

19. The shift register according to claim 18, characterized in that, The power supply unit includes a first transistor, the first terminal of the first transistor serves as the first terminal of the power supply unit, the second terminal of the first transistor serves as the second terminal of the power supply unit, and the control terminal of the first transistor serves as the control terminal of the power supply unit.

20. The shift register according to claim 19, characterized in that, The second feedback module includes a fourth transistor, a fifth transistor, and a third capacitor; the first terminal of the fourth transistor is electrically connected to the second voltage input terminal, the second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor, and the control terminal of the fourth transistor is electrically connected to the second terminal of the first transistor; the second terminal of the fifth transistor is electrically connected to the second clock input terminal; the control terminal of the fifth transistor is electrically connected to the second control terminal; the first terminal of the third capacitor is electrically connected to the second terminal of the fourth transistor, and the second terminal of the third capacitor is electrically connected to the second control terminal.

21. The shift register according to claim 18, characterized in that, The shift register also includes a first normally open module, and the second end of the power supply unit is electrically connected to the control end of the first adjustment unit through the first normally open module.

22. The shift register according to claim 21, characterized in that, The first normally open module includes a twelfth transistor, the first terminal of which is electrically connected to the second terminal of the first transistor, the second terminal of which is electrically connected to the control terminal of the sixth transistor, and the control terminal of which is electrically connected to the first voltage input terminal.

23. The shift register according to claim 21, characterized in that, The first normally open module is in the normally open state.

24. The shift register according to claim 1, characterized in that, The second input module includes a shift input unit, a first end of which is electrically connected to the shift input terminal, a control terminal of which is electrically connected to the first clock input terminal, and a second end of which is electrically connected to the second control terminal.

25. The shift register according to claim 24, characterized in that, The shift register further includes a second normally open module, and the second end of the shift input unit is electrically connected to the second control terminal through the second normally open module.

26. The shift register according to claim 24, characterized in that, The first terminal of the second normally open module is electrically connected to the second terminal of the shift input unit, the second terminal of the second normally open module is electrically connected to the second control terminal, and the control terminal of the second normally open module is electrically connected to the first voltage input terminal; the second normally open module is in a normally open state.

27. The shift register according to claim 26, characterized in that, The shift input unit includes a second transistor, the first terminal of the second transistor serves as the first terminal of the shift input unit, the second terminal of the second transistor serves as the second terminal of the shift input unit, and the control terminal of the second transistor serves as the control terminal of the shift input unit.

28. The shift register according to claim 27, characterized in that, The second normally open module includes a thirteenth transistor, the first terminal of which is electrically connected to the second terminal of the second transistor, the second terminal of which is electrically connected to the second control terminal, and the control terminal of which is electrically connected to the first voltage input terminal.

29. The shift register according to claim 1, characterized in that, The output module includes: First output unit, second output unit, and sustaining unit; The first terminal of the first output unit is electrically connected to the second voltage input terminal, the second terminal of the first output unit is electrically connected to the shift output terminal, and the control terminal of the first output unit is electrically connected to the first control terminal; the conduction level of the first output unit is the effective level of the first control terminal, and the effective level of the first control terminal is logically opposite to the second voltage signal of the second voltage input terminal; The first terminal of the second output unit is electrically connected to the first voltage input terminal, the second terminal of the second output unit is electrically connected to the shift output terminal, and the control terminal of the second output unit is electrically connected to the second control terminal. The first end of the sustaining unit is electrically connected to the first end of the first output unit, and the second end of the sustaining unit is electrically connected to the control end of the first output unit.

30. The shift register according to claim 29, characterized in that, The first output unit is configured to transmit the signal from the first end of the first output unit to the second end of the first output unit in response to the signal being turned on at the control terminal of the first output unit.

31. The shift register according to claim 29, characterized in that, The conduction level of the first output unit is the effective level of the first control terminal, and the effective level of the first control terminal is logically opposite to the second voltage signal of the second voltage input terminal.

32. The shift register according to claim 29, characterized in that, The first output unit includes a tenth transistor, the first terminal of the tenth transistor serves as the first terminal of the first output unit, the second terminal of the tenth transistor serves as the second terminal of the first output unit, and the control terminal of the tenth transistor serves as the control terminal of the first output unit.

33. The shift register according to claim 29, characterized in that, The second output unit includes an eleventh transistor, the first terminal of the eleventh transistor serves as the first terminal of the second output unit, the second terminal of the eleventh transistor serves as the second terminal of the second output unit, and the control terminal of the eleventh transistor serves as the control terminal of the second output unit.

34. A shift register, characterized in that, The shift register includes: a first input module, a second input module, a control module, and an output module; The first input module is electrically connected to the first voltage input terminal, the first clock input terminal, the second clock input terminal, and the first control terminal of the output module, and is configured to adjust the potential of the first control terminal according to the first clock signal of the first clock input terminal, the second clock signal of the second clock input terminal, and the first voltage signal of the first voltage input terminal; The second input module is electrically connected to the shift input terminal of the shift register, the first clock input terminal, and the second control terminal of the output module, and is configured to adjust the potential of the second control terminal according to the input signal of the shift input terminal and the first clock signal; The output module is electrically connected to the first voltage input terminal, the second voltage input terminal, and the shift output terminal of the shift register, and is configured to output a first voltage signal from the first voltage input terminal to the shift output terminal of the shift register according to the potential of the first control terminal; and to output a second voltage signal from the second voltage input terminal to the shift output terminal of the shift register according to the potential of the second control terminal. The control module is electrically connected to the second clock input terminal, the second voltage input terminal, the shift control terminal, and the first control terminal, and is configured to input the second voltage signal of the second voltage input terminal to the first control terminal according to the second clock signal and the shift control signal of the shift control terminal when the first voltage signal is output at the shift output terminal of the shift register; The first input module includes: The system includes a power supply unit, a first adjustment unit, a second adjustment unit, and a coupling unit. The first end of the power supply unit is electrically connected to the first voltage input terminal, the control terminal of the power supply unit is electrically connected to the first clock input terminal, and the second end of the power supply unit is electrically connected to the control terminal of the first adjustment unit. The first end of the first adjustment unit is electrically connected to the second clock input terminal, and the second end of the first adjustment unit is electrically connected to the first end of the second adjustment unit. The control terminal of the second adjustment unit is electrically connected to the second clock input terminal, and the second terminal of the second adjustment unit is electrically connected to the first control terminal. The first end of the coupling unit is electrically connected to the control end of the first adjustment unit, and the second end of the coupling unit is electrically connected to the second end of the first adjustment unit.

35. The shift register according to claim 34, characterized in that, The effective level of the first control terminal is logically opposite to the second voltage signal of the second voltage input terminal; During the effective level time of the input signal, the pulse end time of the shift control signal is later than the pulse start time of the first effective pulse of the second clock signal, and earlier than the pulse start time of the second effective pulse of the second clock signal.

36. The shift register according to claim 35, characterized in that, The pulse start time of the shift control signal is the same as the pulse start time of the input signal.

37. The shift register according to claim 35, characterized in that, The duration of the effective pulses at the shift input and shift output terminals of the shift register is greater than the period of the second clock signal.

38. The shift register according to claim 35, characterized in that, The duration of the effective pulses at the shift input and shift output terminals of the shift register is greater than the duration of the effective pulses of the shift control signal.

39. The shift register according to claim 35, characterized in that, The duration of the effective pulse of the shift control signal is greater than the duration of the effective level of the second clock signal.

40. The shift register according to claim 34, characterized in that, The first adjustment unit is configured to transmit the signal from the first end of the first adjustment unit to the second end of the first adjustment unit in response to the signal being turned on at the control terminal of the first adjustment unit.

41. The shift register according to claim 34, characterized in that, The power supply unit is configured to be turned on in response to a signal from the control terminal of the power supply unit, thereby transmitting a signal from the first terminal of the power supply unit to the second terminal of the power supply unit.

42. The shift register according to claim 34, characterized in that, The second adjustment unit is configured to transmit the signal from the first end of the second adjustment unit to the second end of the second adjustment unit in response to the signal being turned on at the control terminal of the second adjustment unit.

43. The shift register according to claim 34, characterized in that, The coupling unit includes a first capacitor, with a first end of the first capacitor serving as the first end of the coupling unit and a second end of the first capacitor serving as the second end of the coupling unit.

44. The shift register according to claim 34, characterized in that, The first adjustment unit includes a sixth transistor, the first terminal of the sixth transistor serves as the first terminal of the first adjustment unit, the second terminal of the sixth transistor serves as the second terminal of the first adjustment unit, and the control terminal of the sixth transistor serves as the control terminal of the first adjustment unit.

45. The shift register according to claim 34, characterized in that, The second adjustment unit includes a seventh transistor, wherein the first terminal of the seventh transistor serves as the first terminal of the second adjustment unit, the second terminal of the seventh transistor serves as the second terminal of the second adjustment unit, and the control terminal of the seventh transistor serves as the control terminal of the second adjustment unit.

46. ​​The shift register according to claim 34, characterized in that, The shift register further includes a first feedback module, which is electrically connected to the second control terminal, the first clock input terminal, and the second terminal of the power supply unit. The first feedback module is configured to write the first clock signal into the second terminal of the power supply unit according to the potential of the end of the second input module connected to the second control terminal.

47. The shift register according to claim 46, characterized in that, The first feedback module includes a third transistor, the first terminal of the third transistor serves as the first terminal of the first feedback module, the second terminal of the third transistor serves as the second terminal of the first feedback module, and the control terminal of the third transistor serves as the control terminal of the first feedback module.

48. The shift register according to claim 46, characterized in that, The shift register further includes a second feedback module, which is electrically connected to the second terminal of the power supply unit, the second voltage input terminal, the second clock input terminal, and the second control terminal. The second feedback module is configured to adjust the potential of the second control terminal according to the potential of the second terminal of the power supply unit, the second clock signal, and the first voltage signal.

49. The shift register according to claim 48, characterized in that, The power supply unit includes a first transistor, the first terminal of the first transistor serves as the first terminal of the power supply unit, the second terminal of the first transistor serves as the second terminal of the power supply unit, and the control terminal of the first transistor serves as the control terminal of the power supply unit.

50. The shift register according to claim 49, characterized in that, The second feedback module includes a fourth transistor, a fifth transistor, and a third capacitor; the first terminal of the fourth transistor is electrically connected to the second voltage input terminal, the second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor, and the control terminal of the fourth transistor is electrically connected to the second terminal of the first transistor; the second terminal of the fifth transistor is electrically connected to the second clock input terminal; the control terminal of the fifth transistor is electrically connected to the second control terminal; the first terminal of the third capacitor is electrically connected to the second terminal of the fourth transistor, and the second terminal of the third capacitor is electrically connected to the second control terminal.

51. The shift register according to claim 50, characterized in that, The shift register also includes a first normally open module, and the second end of the power supply unit is electrically connected to the control end of the first adjustment unit through the first normally open module.

52. The shift register according to claim 51, characterized in that, The first normally open module includes a twelfth transistor, the first terminal of which is electrically connected to the second terminal of the first transistor, the second terminal of which is electrically connected to the control terminal of the sixth transistor, and the control terminal of which is electrically connected to the first voltage input terminal.

53. The shift register according to claim 51, characterized in that, The first normally open module is in the normally open state.

54. The shift register according to claim 34, characterized in that, The second input module includes a shift input unit, a first end of which is electrically connected to the shift input terminal, a control terminal of which is electrically connected to the first clock input terminal, and a second end of which is electrically connected to the second control terminal.

55. The shift register according to claim 54, characterized in that, The shift register further includes a second normally open module, and the second end of the shift input unit is electrically connected to the second control terminal through the second normally open module.

56. The shift register according to claim 54, characterized in that, The first terminal of the second normally open module is electrically connected to the second terminal of the shift input unit, the second terminal of the second normally open module is electrically connected to the second control terminal, and the control terminal of the second normally open module is electrically connected to the first voltage input terminal; the second normally open module is in a normally open state.

57. The shift register according to claim 56, characterized in that, The shift input unit includes a second transistor, the first terminal of the second transistor serves as the first terminal of the shift input unit, the second terminal of the second transistor serves as the second terminal of the shift input unit, and the control terminal of the second transistor serves as the control terminal of the shift input unit.

58. The shift register according to claim 57, characterized in that, The second normally open module includes a thirteenth transistor, the first terminal of which is electrically connected to the second terminal of the second transistor, the second terminal of which is electrically connected to the second control terminal, and the control terminal of which is electrically connected to the first voltage input terminal.

59. The shift register according to claim 34, characterized in that, The output module includes: First output unit, second output unit, and sustaining unit; The first terminal of the first output unit is electrically connected to the second voltage input terminal, the second terminal of the first output unit is electrically connected to the shift output terminal, and the control terminal of the first output unit is electrically connected to the first control terminal; the conduction level of the first output unit is the effective level of the first control terminal, and the effective level of the first control terminal is logically opposite to the second voltage signal of the second voltage input terminal; The first terminal of the second output unit is electrically connected to the first voltage input terminal, the second terminal of the second output unit is electrically connected to the shift output terminal, and the control terminal of the second output unit is electrically connected to the second control terminal. The first end of the sustaining unit is electrically connected to the first end of the first output unit, and the second end of the sustaining unit is electrically connected to the control end of the first output unit.

60. The shift register according to claim 59, characterized in that, The first output unit is configured to transmit the signal from the first end of the first output unit to the second end of the first output unit in response to the signal being turned on at the control terminal of the first output unit.

61. The shift register according to claim 59, characterized in that, The conduction level of the first output unit is the effective level of the first control terminal, and the effective level of the first control terminal is logically opposite to the second voltage signal of the second voltage input terminal.

62. The shift register according to claim 59, characterized in that, The first output unit includes a tenth transistor, the first terminal of the tenth transistor serves as the first terminal of the first output unit, the second terminal of the tenth transistor serves as the second terminal of the first output unit, and the control terminal of the tenth transistor serves as the control terminal of the first output unit.

63. The shift register according to claim 59, characterized in that, The second output unit includes an eleventh transistor, the first terminal of the eleventh transistor serves as the first terminal of the second output unit, the second terminal of the eleventh transistor serves as the second terminal of the second output unit, and the control terminal of the eleventh transistor serves as the control terminal of the second output unit.

64. A display driver, characterized in that, The display driver includes a plurality of cascaded shift registers as described in any one of claims 1-33 or 34-63; The display driver also includes multiple cascaded shift units, each of which is electrically connected to the shift control terminal of a corresponding shift register and is used to provide the shift control signal to the corresponding shift register.

65. A display panel, characterized in that, The display panel includes the display driver as described in claim 64.

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