Sense amplifier layout design and related devices and methods

Abstract

The present application relates to sense amplifier layout design, and related devices and methods. A device includes a cross-coupled pull-up transistor pair of a sense amplifier, a cross-coupled pull-down transistor pair of the sense amplifier, and a conductive line pair electrically connecting the cross-coupled pull-up transistor pair to the cross-coupled pull-down transistor pair. The device also includes a sense amplifier control transistor that shares a continuous active material with one of the cross-coupled pull-up transistor pair or the cross-coupled pull-down transistor pair. A method includes asserting that a shared control gate terminal of the sense amplifier control transistor shares a continuous active material with the cross-coupled pull-down transistor pair; applying a precharge voltage potential to the conductive line pair; electrically connecting a memory cell to the precharged bit line pair; and amplifying charge delivered to the bit line pair by the memory cell.

Description

[0001] Priority claim

[0002] This application claims the benefit of the filing date of U.S. patent application serial number 17 / 547,574, filed on December 10, 2021, entitled "SENSE AMPLIFIER LAYOUT DESIGNS AND RELATED APPARATUSES AND METHODS," the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to sense amplifier layout design, and more particularly to a sense amplifier layout design including a sense amplifier control transistor that shares a contiguous active material with a cross-coupled transistor pair. Background Art

[0004] The demand for increasingly smaller integrated circuit devices is driving semiconductor device designers to use minimum device pitches and spacings within their devices. Entities governing the design standards for these integrated circuit devices require integrated circuit device designers to meet various requirements. In many cases, these requirements can be the limiting factor on how small a given integrated circuit device can be. Summary of the Invention

[0005] In some embodiments, an apparatus includes a cross-coupled pair of pull-up transistors for a sense amplifier, a cross-coupled pair of pull-down transistors for the sense amplifier, a pair of conductive lines electrically connecting the cross-coupled pair of pull-up transistors to the cross-coupled pair of pull-down transistors, and a sense amplifier control transistor sharing a contiguous active material with one of the cross-coupled pair of pull-up transistors or the cross-coupled pair of pull-down transistors.

[0006] In some embodiments, a method of operating a sense amplifier includes precharging a bit line pair and a conductive line pair by asserting a shared control gate terminal of a sense amplifier control transistor that shares a continuous active material with a cross-coupled pull-down transistor pair and applying a precharge voltage potential to the conductive line pair, the conductive line pair electrically connecting a cross-coupled pull-up transistor pair of the sense amplifier to a cross-coupled pull-down transistor pair of the sense amplifier. The method also includes electrically connecting a memory cell to the precharged bit line pair and amplifying charge delivered by the memory cell to the bit line pair.

[0007] In some embodiments, a device includes a first sense amplifier and a second sense amplifier. The first sense amplifier includes a first cross-coupled pull-up transistor pair, a first cross-coupled pull-down transistor pair, and a first sense amplifier control transistor set that shares a first continuous active material with the first cross-coupled pull-down transistor pair. The second sense amplifier includes a second cross-coupled pull-up transistor pair, a second cross-coupled pull-down transistor pair, and a second sense amplifier control transistor set that shares a second continuous active material with the second cross-coupled pull-down transistor pair. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] While the present disclosure is summarized with claims that particularly point out and distinctly claim specific embodiments, the various features and advantages of embodiments within the scope of this disclosure may be more readily ascertained from the following description when read in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a schematic diagram of an example of a sense amplifier according to some embodiments;

[0010] Figure 2 is a schematic diagram of another example of a sense amplifier according to some embodiments;

[0011] Figure 3A is a top view of a layout design of a portion of an integrated circuit device according to some embodiments;

[0012] Figure 3B 、 Figure 3C and Figure 3D Instructions for electrical connection Figure 3A interconnect material for the cross-coupled pull-up transistor pair, the cross-coupled pull-down transistor pair, and the sense amplifier control transistor set of the integrated circuit device portion;

[0013] Figure 4A yes Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D a top view of a layout design of a sub-portion of an integrated circuit device portion;

[0014] Figure 4B 、 Figure 4C and Figure 4D illustrate Figure 3B 、 Figure 3C and Figure 3D Used for Figure 3A interconnecting materials of sub-portions of an integrated circuit device portion;

[0015] Figure 5 is a top view of a layout design of another integrated circuit device portion according to some embodiments;

[0016] Figure 6 is a perspective view of a fin field effect transistor (FinFET) according to some embodiments;

[0017] Figure 7 is a perspective view of a FinFET sharing continuous active material according to some embodiments;

[0018] Figure 8 is a diagram illustrating the operation of a sense amplifier (eg, Figure 1 、 Figure 2 、 Figure 4A or Figure 5 A flow chart of a method for implementing a sense amplifier;

[0019] Figure 9 is a block diagram of a semiconductor device according to some embodiments; and

[0020] Figure 10 is a block diagram of a computing system according to some embodiments. DETAILED DESCRIPTION

[0021] In the following detailed description, reference is made to the accompanying drawings, which form a part of this disclosure and in which are shown, by way of illustration, specific examples of embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the present disclosure. However, other embodiments embodied herein may be utilized, and structural, material, and process changes may be made without departing from the scope of this disclosure.

[0022] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations for describing embodiments of the present disclosure. In some cases, similar structures or components in various figures may retain the same or similar numbering for the convenience of the reader; however, similarity in numbering does not necessarily mean that the size, composition, configuration, or any other properties of the structure or component are identical.

[0023] The following description may include examples to help enable those skilled in the art to practice the disclosed embodiments. The use of the terms "exemplary," "for example," and "for example" means that the relevant description is illustrative, and while the scope of the present disclosure is intended to encompass examples and legal equivalents, the use of such terms is not intended to limit the embodiments or the scope of the present disclosure to the specified components, steps, features, functions, etc.

[0024] It will be readily understood that the components of the embodiments generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Accordingly, the following description of various embodiments is not intended to limit the scope of the present disclosure, but rather is merely representative of various embodiments. Although various aspects of the embodiments may be presented in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0025] In addition, unless otherwise provided herein, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement the present disclosure. Components, circuits, and functions may be shown in block diagram form to avoid confusing the present disclosure with unnecessary details. On the contrary, unless otherwise provided herein, the specific embodiments shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure. In addition, the block definitions and logical partitioning between the various blocks are exemplary of specific embodiments. It will be apparent to those of ordinary skill in the art that the present disclosure may be practiced through many other partitioning solutions. To a large extent, details on timing considerations, etc. have been omitted, where such details are unnecessary for a complete understanding of the present disclosure and are within the capabilities of those of ordinary skill in the relevant art.

[0026] Those skilled in the art will understand that information and signals may be represented using any of a variety of different technologies and techniques. Some figures may illustrate a signal as a single signal for clarity of presentation and description. Those skilled in the art will understand that a signal may represent a bus of signals, where the bus may have a variety of bit widths, and that the present disclosure may be implemented on any number of data signals, including a single data signal.

[0027] The various illustrative logical blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or executed by a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor (also referred to herein as a host processor or simply a host) may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration. A general-purpose computer that includes a processor is considered a special-purpose computer when the general-purpose computer is configured to execute computing instructions (e.g., software code) related to the embodiments of the present disclosure.

[0028] Embodiments may be described in terms of a process depicted as a flowchart, flow diagram, structure diagram, or block diagram. Although a flowchart may describe operational actions as a sequential process, many of these actions may be performed in another order, in parallel, or substantially simultaneously. Furthermore, the order of the actions may be rearranged. A process may correspond to a method, thread, function, program, subroutine, subprogram, other structure, or a combination thereof. Furthermore, the methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, the functions may be stored or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include both computer storage media and communication media, and communication media include any media that facilitates the transfer of a computer program from one place to another.

[0029] Any reference to an element herein using designations such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitations are explicitly stated. Indeed, these designations may be used herein as a convenient method of distinguishing two or more elements or instances of elements. Thus, reference to a first and a second element does not imply that only two elements may be employed herein or that the first element must precede the second element in some manner. Additionally, unless otherwise indicated, a group of elements may include one or more elements.

[0030] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and encompasses the degree to which a person of ordinary skill in the art would understand that the given parameter, property, or condition is met with small variations (e.g., within acceptable manufacturing tolerances). By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90% met, at least 95% met, or even at least 99% met.

[0031] As used herein, the term "conductive material" refers to a material having a conductivity greater than approximately 10 at room temperature (approximately 20 degrees Celsius). 4 S / cm(10 6Examples of conductive materials include metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), alloys (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe- and N-based alloys), and The present invention also includes an alloy of aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum and nickel, an alloy based on iron, an alloy based on iron, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum, an alloy based on aluminum,

[0032] As used herein, the term "insulating material" refers to a dielectric material having a dielectric strength of less than approximately 10 -8 Examples of "insulating materials" include at least one dielectric oxide material (e.g., silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbO -x- ), titanium oxide (TiO x ), zirconium oxide (ZrO x ), tantalum oxide (TaO x ) and magnesium oxide (MgO x ), at least one dielectric nitride material (e.g., silicon nitride (SiN y )), at least one dielectric oxynitride material (e.g., silicon oxynitride (SiO x N y )), at least one dielectric oxycarbide material (e.g., silicon oxycarbide (SiO x C y )), at least one hydrogenated dielectric oxycarbide material (e.g., hydrogenated silicon oxycarbide (SiC x O y H z )), at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO x Cz N y )), or a combination thereof. The chemical formula herein containing one or more of "x", "y" and "z" (e.g., SiO x 、AlO x , HfO x 、NbO -x 、TiO x 、SiN y 、SiO x N y 、SiO x C y 、SiC x O y H z 、SiO x C z N y ) represents a material containing an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) per atom of the other element (e.g., Si, Al, Hf, Nb, Ti). Since the chemical formula represents relative atomic ratios rather than strict chemical structures, the insulating material may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if present) may be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes a compound having an elemental composition that cannot be represented by a ratio of well-defined natural numbers and that violates the law of definite proportions and the law of multiple proportions. In addition, "insulating structure" means and includes a structure formed of and including an insulating material.

[0033] As used herein, the term "semiconductor material" refers to a material having a conductivity between that of an insulating material and that of a conductive material. For example, a semiconductor material may have a conductivity between about 10 -8 Siemens / cm (S / cm) and about 10 4 S / cm(10 6The conductivity between 100 and 100 nm is determined by the number of electrodes (e.g., 100 nm / s) and the number of electrodes (e.g., 100 nm / s). Examples of semiconductor materials include elements found in column IV of the periodic table, such as silicon (Si), germanium (Ge), and carbon (C). Other examples of semiconductor materials include compound semiconductor materials, such as, but not limited to, binary compound semiconductor materials (e.g., gallium arsenide (GaAs)), ternary compound semiconductor materials (e.g., AlXGa1-XAs), and quaternary compound semiconductor materials (e.g., GaXIn1-XAsYP1-Y). Compound semiconductor materials may include, but are not limited to, combinations of elements from columns III and V (III-V semiconductor materials) or from columns II and VI (II-VI semiconductor materials) of the periodic table. Semiconductor devices typically include crystalline semiconductor materials. By way of non-limiting example, transistors and diodes include crystalline semiconductor materials.

[0034] As used herein, the term "single crystalline semiconductor material" refers to a semiconductor material comprising particles (e.g., atoms, molecules) arranged in a substantially continuous lattice that is substantially free of grain boundaries within the semiconductor material. A substrate of the semiconductor material may comprise a single crystalline semiconductor material, such as single crystalline silicon. A substrate comprising a single crystalline semiconductor material may serve as a substrate material for various devices and structures disclosed herein.

[0035] As used herein, the term "polycrystalline semiconductor material" refers to a semiconductor material that includes multiple crystals (sometimes referred to as crystallites or grains) of semiconductor material. Compared to single-crystalline semiconductor materials, polycrystalline semiconductor materials include grain boundaries within the semiconductor material. Polycrystalline silicon, also known as "polysilicon (poly)", is an example of a polycrystalline semiconductor material.

[0036] As used herein, the term "intrinsic semiconductor material" refers to a semiconductor material having a relatively low impurity density (eg, a low impurity density compared to the electron and hole densities resulting from thermal generation at room temperature).

[0037] As used herein, the term "doped semiconductor material" refers to a semiconductor material that has been introduced with an impurity density that is higher than that of an intrinsic semiconductor material (e.g., an impurity density that is higher than the electron and hole density resulting from thermal generation at room temperature). Doped semiconductor materials may be primarily doped with donor impurities, such as, but not limited to, phosphorus (P), antimony (Sb), bismuth (Bi), and arsenic (As). Each donor impurity in the crystal lattice of the semiconductor material adds a free electron, which increases the conductivity of the semiconductor material relative to the intrinsic form of the semiconductor material. Doped semiconductor materials that have been primarily doped with donor impurities are referred to herein as "n-type semiconductor materials." Doped semiconductors may actually be primarily doped with trivalent or acceptor impurities, such as, but not limited to, boron (B), indium (In), aluminum (Al), and gallium (Ga). Each trivalent or acceptor impurity in the crystal lattice of the semiconductor material adds electron holes (referred to herein as "holes"), which increases the conductivity of the semiconductor material relative to the intrinsic form of the semiconductor material. Doped semiconductor materials that have been primarily doped with trivalent or acceptor impurities are referred to herein as "p-type semiconductor materials."

[0038] As used herein, the term "active material" refers to a semiconductor material that has been doped to serve as a channel material in a metal oxide semiconductor (MOS) field effect transistor (FET) (MOSFET). A MOSFET transistor having a channel material that has been doped primarily with donor impurities is referred to herein as an N-type MOS (NMOS) transistor because the active material that serves as the channel material for the NMOS transistor comprises an N-type semiconductor material. Similarly, a MOSFET transistor having a channel material that has been doped primarily with trivalent or acceptor impurities is referred to herein as a P-type MOS (PMOS) transistor because the active material that serves as the channel material for the PMOS transistor comprises a P-type semiconductor material.

[0039] As used herein, the term "continuous active material" refers to an uninterrupted structure formed of and containing an active material, without intervening structures of other materials that completely isolate or segment portions of the continuous active material. For example, multiple FinFETs sharing a continuous active material can share a common fin that extends through the multiple FinFETs.

[0040] A FinFET is an example of a MOSFET transistor that includes a fin-shaped active material, or "fin," and gate material on at least two sides of the fin. Some FinFETs include gate material on three sides of the fin, such as on the lateral sides and the top side of the fin. Generally speaking, a FinFET can be smaller than a planar transistor (e.g., occupying less chip area). Therefore, FinFETs can be used to help meet the continuing demand for smaller and smaller integrated circuit devices.

[0041] Entities governing the standards for manufacturing various integrated circuit devices may require unique restrictions on the layout and processes of integrated circuit devices that include FinFETs. One particular type of integrated circuit device design that may be subject to such unique restrictions is a dynamic random access memory (DRAM) integrated circuit device that includes complementary metal oxide semiconductor (CMOS) pitch cells. For example, the standards governing the design of such DRAM integrated circuit devices may prohibit the use of polysilicon contact-over-active-gate (COAG) material. Thus, rather than designing a contact for the gate material directly above the transistor's active material, the gate material extends away from the active material into otherwise available chip area, where it contacts the gate material. Given this COAG prohibition, achieving a small chip area can be particularly difficult for cells with many small devices, as contacting the gate material consumes a relatively large amount of chip area. As another example, standards governing the design of DRAM integrated circuit devices may require that the fins of a FinFET all extend parallel to each other across the entire semiconductor die. These standards may also require that gate material lines (e.g., polysilicon lines) all extend in one direction, but perpendicular to the FinFET's fins. Therefore, bidirectional gate material lines may not be used, which can exacerbate layout design difficulties caused by COAG prohibitions. As another non-limiting example, standards governing DRAM integrated circuit device design may require single or double diffusion breaks along the fin direction for active isolation. The conductive material lines of these diffusion breaks can occupy chip area that could otherwise be used to reduce chip size or include additional devices. Therefore, a sense amplifier design layout that adheres to these restrictions and includes FinFETs may occupy more area than a sense amplifier design that includes planar transistors.

[0042] Due to the particular complexity of sense amplifiers, combined with these requirements, designing the layout of sense amplifiers for DRAM memory devices can be particularly difficult. A sense amplifier may not only include two pairs of cross-coupled transistors (e.g., a cross-coupled pair of pull-up transistors and a cross-coupled pair of pull-down transistors), but the sense amplifier may also include additional transistors. By way of non-limiting example, a sense amplifier may include a sense amplifier control transistor used to precharge a bit line before accessing a memory cell electrically connected to the bit line. If each of these transistors includes a gate contact that is offset from the transistor's active material in the otherwise available chip area, a significant area penalty can result. This area can also be complicated by the need for all parallel gate material perpendicular to all parallel active material (e.g., fins).

[0043] In a non-rotated sense amplifier configuration that complies with COAG prohibition, the requirement for parallel fins, and the requirement for parallel gate material perpendicular to the fins (the transistor gate material lines are substantially parallel to the bit lines of the DRAM memory), the fins can be cast obliquely to the array in the sub-word driver (SWD) and the gate material lines can be cast to the array in the sense amplifier. However, such a non-rotated configuration can result in a relatively large number of gate material line contacts. The non-rotated configuration can also be sensitive to COAG prohibition and may require single diffusion barrier active isolation, which is generally considered less desirable than double diffusion barrier active isolation. In addition, the non-rotated configuration may not be scalable by more than 160 times.

[0044] In contrast, in a rotated sense amplifier configuration (where the transistor gate material lines are substantially perpendicular to the bit lines of a DRAM memory), the gate material lines can be routed to the array in the SWD and the fins can be routed to the array in the sense amplifier. However, rotating the sense amplifiers can also result in a relatively large number of multiple contacts and can be sensitive to COAG inhibition (increased sense amplifier pitch and height). While double-diffused barrier isolation can be used, double-diffused barrier isolation can result in approximately 30% greater chip area consumption compared to single-diffused barrier active isolation. Rotating the sense amplifier configuration can be associated with a weaker scaling path. Additionally, rotating the sense amplifier configuration can force the design of a larger SWD than a non-rotated sense amplifier configuration.

[0045] According to various embodiments, a hybrid rotary sense amplifier configuration reduces some of the chip area penalties associated with COAG prohibition, the need for parallel fins, the need for parallel gate material perpendicular to the fins (e.g., multi-line), and the need for active material diffusion breaks. The conductive lines electrically connecting the drain terminals of the cross-coupled pull-up transistor pair to the drain terminals of the cross-coupled pull-down transistor pair can run perpendicular to the bit lines (similar to a rotated sense amplifier), but the gate material lines can run parallel to the bit lines (similar to a non-rotated sense amplifier). This combination of rotated and non-rotated sense amplifier features results in a hybrid rotary sense amplifier according to various embodiments disclosed herein.

[0046] In some embodiments, continuous active material can be shared between transistors of a sense amplifier (sometimes referred to as "shared active material," "shared fins," or "shared diffusions"), gate material lines can be shared between transistors of different sense amplifiers (sometimes referred to as "multiple shares"), and source terminals of cross-coupled transistor pairs can be shared between different cross-coupled sense amplifier pairs (sometimes referred to herein as "shared RNLs" or "shared ACTs"). In some embodiments, sharing these features can result in a reduction in area consumption of the sense amplifier device by approximately 15% compared to non-rotated and rotated sense amplifier configurations. If both COAG inhibition and double diffusion barrier isolation are required, sense amplifiers according to various embodiments disclosed herein can occupy more than 40% less area than non-rotated and rotated sense amplifier configurations.

[0047] Sharing of gate material lines between sense amplifier control transistors enables multiple transistors to share a single gate material line contact, which reduces the chip area penalty otherwise associated with using a gate material contact for each sense amplifier control transistor. Thus, the chip area penalty prohibited by COAG can be reduced.

[0048] Diffusion sharing between transistors of a sense amplifier may reduce some of the area penalties caused by single diffusion breaks and / or double diffusion breaks and may provide design and / or process benefits by allowing shared RNL lines and / or shared ACT lines, matched multi-cut patterns for sense amplifier devices, and performance benefits due to device interconnects being done in active material and / or trench contact material (e.g., trench contact layer).

[0049] Figure 1 FIG1 is a schematic diagram of an example of a sense amplifier 100 according to some embodiments. Sense amplifier 100 is configured to amplify charge delivered by a memory cell to a bit line pair DL, DLF electrically connected to sense amplifier 100. Sense amplifier 100 includes a cross-coupled pull-up transistor pair 102, a cross-coupled pull-down transistor pair 104, a conductive line pair 106, and a sense amplifier control transistor 108. Conductive line pair 106 electrically connects cross-coupled pull-up transistor pair 102 to cross-coupled pull-down transistor pair 104.

[0050] In some embodiments, the sense amplifier control transistor 108 shares a continuous active material with one of the cross-coupled pull-up transistor pair 102 or the cross-coupled pull-down transistor pair 104, as will be discussed in more detail below. In some embodiments, the sense amplifier control transistor 108 shares a continuous active material with the cross-coupled pull-up transistor pair 102. In such embodiments, the sense amplifier control transistor 108 may be implemented using a PMOS transistor rather than an NMOS transistor so that the sense amplifier control transistor 108 will share a common type of active material (P-type active material) with the cross-coupled pull-up transistor pair 102. In some embodiments, the sense amplifier control transistor 108 shares a continuous active material with the cross-coupled pull-down transistor pair 104. In such embodiments, the sense amplifier control transistor 108 is an NMOS transistor, such as Figure 1 In some embodiments, some of the sense amplifier control transistors 108 may be NMOS transistors and may share continuous active material with the cross-coupled pull-down transistor pair 104, and some other of the sense amplifier control transistors 108 may be PMOS transistors and share continuous active material with the cross-coupled pull-up transistor pair 102.

[0051] In some embodiments, the cross-coupled pull-up transistor pair 102 and the cross-coupled pull-down transistor pair 104 are FinFETs (see Figure 6 and Figure 7 In some embodiments, sense amplifier control transistor 108 is a FinFET and shares a common fin with cross-coupled pull-down transistor pair 104. In some embodiments, cross-coupled pull-up transistor pair 102 shares a common fin. In some embodiments, cross-coupled pull-up transistor pair 102, cross-coupled pull-down transistor pair 104, and sense amplifier control transistor 108 can be planar transistors.

[0052] In some embodiments, a gate material line for the control gate terminal of sense amplifier control transistor 108 is shared with other control gate terminals of other sense amplifier control transistors of other sense amplifiers. In some embodiments, the gate material line for the control gate terminal of sense amplifier control transistor 108 extends at least substantially perpendicular to conductive line pair 106. In some embodiments, conductive line pair 106 extends at least substantially parallel to the continuous active material shared by sense amplifier control transistor 108 and one of cross-coupled pull-up transistor pair 102 and cross-coupled pull-down transistor pair 104.

[0053] In some embodiments, cross-coupled pull-down transistor pair 104 includes source terminals electrically connected to other source terminals of other cross-coupled pull-down transistor pairs of other sense amplifiers. In some embodiments, cross-coupled pull-up transistor pair 102 includes source terminals electrically connected to other source terminals of other cross-coupled pull-up transistor pairs of other sense amplifiers.

[0054] The cross-coupled pull-up transistor pair 102 includes a first PMOS transistor P1 and a second PMOS transistor P2. The cross-coupled pull-down transistor pair 104 includes a first NMOS transistor N1 and a second NMOS transistor N2. The conductive line pair 106 electrically connects the drain terminal of the first PMOS transistor P1 to the drain terminal of the first NMOS transistor N1, and electrically connects the drain terminal of the second PMOS transistor P2 to the drain terminal of the second NMOS transistor N2. The source terminals of the first PMOS transistor P1 and the second PMOS transistor P2 are connected at Figure 1 Similarly, the source terminals of the first NMOS transistor N1 and the second NMOS transistor N2 are electrically connected at the node ACT. Figure 1 The gate terminal of the first PMOS transistor P1 is electrically connected to the drain terminal of the second PMOS transistor P2 and the drain terminal of the second NMOS transistor N1. The gate terminal of the second PMOS transistor P2 is electrically connected to the drain terminals of the first PMOS transistor P1 and the first NMOS transistor N1. The gate terminal of the first NMOS transistor N1 is electrically connected to the bit line DLF. The gate terminal of the second NMOS transistor N2 is electrically connected to the bit line DL.

[0055] Sense amplifier control transistor 108 can be used to precharge sense amplifier 100 and the bit lines DL and DLF electrically connected thereto before accessing a memory cell electrically connected to bit lines DL and DLF. Sense amplifier control transistor 108 includes a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6. Third NMOS transistor N3 is electrically connected between bit line DLF and the drain terminals of first NMOS transistor N1 and first PMOS transistor P1. In other words, third NMOS transistor N3 is electrically connected from the gate terminal of first NMOS transistor N1 to the conductive line in conductive line pair 106 that connects the drain terminals of first NMOS transistor N1 and first PMOS transistor P1. Fourth NMOS transistor N4 is electrically connected from bit line DL to the drain terminals of second NMOS transistor N2 and second PMOS transistor P2. In other words, fourth NMOS transistor N4 is electrically connected from the gate terminal of second NMOS transistor N2 to the conductive line in conductive line pair 106 that connects the drain terminals of second NMOS transistor N2 and second PMOS transistor P2.

[0056] The gate terminals of the third NMOS transistor N3 and the fourth NMOS transistor N4 are electrically connected to the precharge control node BLCP. Thus, in response to the assertion of the precharge control voltage potential at the precharge control node BLCP, the third NMOS transistor N3 can electrically connect the gate terminal of the first NMOS transistor N1 and the bit line DLF to the conductive line in the conductive line pair 106 that is electrically connected to the drain terminals of the first PMOS transistor P1 and the first NMOS transistor N1. Furthermore, in response to the assertion of the precharge control voltage potential at the precharge control node BLCP, the fourth NMOS transistor N4 can electrically connect the gate terminal of the second NMOS transistor N2 and the bit line DL to the conductive line in the conductive line pair 106 that is electrically connected to the drain terminals of the second PMOS transistor P2 and the second NMOS transistor N2.

[0057] The fifth NMOS transistor N5 is electrically connected between the bit line DL and the conductive line in the conductive line pair 106 electrically connected to the drain terminals of the first PMOS transistor P1 and the first NMOS transistor N1. The sixth NMOS transistor N6 is electrically connected between the bit line DLF and the conductive line in the conductive line pair 106 electrically connected to the drain terminals of the second PMOS transistor P2 and the second NMOS transistor N2. The gate terminals of the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are electrically connected to the isolation node ISO. Therefore, in response to the assertion of the isolation voltage potential at the isolation node ISO, the fifth NMOS transistor is configured to electrically connect the bit line DL to the conductive line in the conductive line pair 106 electrically connected to the drain terminals of the first PMOS transistor P1 and the first NMOS transistor N1. Furthermore, in response to the assertion of the isolation voltage potential at the isolation node ISO, the sixth NMOS transistor N6 is configured to electrically connect the bit line DLF to the conductive line in the conductive line pair 106 electrically connected to the drain terminals of the second PMOS transistor P2 and the second NMOS transistor N2.

[0058] The sense amplifier 100 further includes a seventh NMOS transistor N7 electrically connected from the bit line precharge voltage potential node VBLP to the conductive line electrically connected to the drain terminals of the second PMOS transistor P2 and the second NMOS transistor N2 in the conductive line pair 106. The gate terminal of the seventh NMOS transistor N7 is electrically connected to the equalization node EQ. Thus, in response to the assertion of the equalization voltage potential at the equalization node EQ, the seventh NMOS transistor N7 is configured to electrically connect the bit line precharge voltage potential node VBLP to the conductive line electrically connected to the drain terminals of the second PMOS transistor P2 and the second NMOS transistor N2 in the conductive line pair 106.

[0059] In operation, the bit lines DL, DLF, and conductive line pair 106 can be precharged to a bit line precharge voltage potential before accessing memory cells electrically connected to the bit lines DL and DLF. The voltage potentials at the precharge control node BLCP, the isolation node ISO, and the equalization node EQ can be asserted to electrically connect the bit lines DL, DLF, and conductive line pair 106 to the precharge voltage potential node VBLP. Thus, the precharge voltage potential can be delivered to the bit lines DL, DLF, and conductive line pair 106.

[0060] Figure 2 FIG. 2 is a schematic diagram of another example of a sense amplifier 200 according to some embodiments. According to some embodiments, the sense amplifier 200 includes Figure 1 The cross-coupled pull-up transistor pair 102, the cross-coupled pull-down transistor pair 104, the conductive line pair 106, the sense amplifier control transistor 108 and the bit lines DL and DLF of the sense amplifier 100. However, compared to Figure 1 In the sense amplifier 100 , the seventh NMOS transistor N7 is electrically connected from the precharge voltage potential node VBLP to the bit line DLF.

[0061] As reference Figure 1 As discussed, in operation, the bit lines DL, DLF, and conductive line pair 106 can be precharged to a bit line precharge voltage potential before accessing memory cells electrically connected to the bit lines DL and DLF. The voltage potentials at the precharge control node BLCP, the isolation node ISO, and the equalization node EQ can be asserted to electrically connect the bit lines DL, DLF, and conductive line pair 106 to the precharge voltage potential node VBLP. Thus, the precharge voltage potential can be delivered to the bit lines DL, DLF, and conductive line pair 106.

[0062] Figure 1 and Figure 2 Sense amplifier control transistors 108 (N3, N4, N5, and N6) and seventh NMOS transistor N7 are NMOS transistors. Therefore, sense amplifier control transistors 108 and / or seventh NMOS transistor N7 can share continuous active material with cross-coupled pull-down transistor pair 104. However, in some embodiments, PMOS transistors can be used in place of NMOS transistors for one or more of NMOS transistors N3, N4, N5, N6, and N7. In such embodiments, any PMOS transistor can share continuous active material with cross-coupled pull-up transistor pair 102.

[0063] Figure 3A FIG. 3 is a top view of a layout design of an integrated circuit device portion 300 according to some embodiments. The integrated circuit device portion 300 includes a plurality of sense amplifiers 306 a - 306 n . Figure 3AThe example of the integrated circuit device portion 300 illustrated in FIG. 1 illustrates fourteen sense amplifiers 306a-306n. The integrated circuit device portion 300 includes a sub-portion 400 including a sense amplifier 306e, which will be referred to as Figure 4A 、 Figure 4B 、 Figure 4C and Figure 4D The integrated circuit device portion 300 includes a cross-coupled pull-up transistor pair 302, a cross-coupled pull-down transistor pair 304, and a sense amplifier control transistor set 308 for sense amplifiers 306a-306n. Each of the cross-coupled pull-up transistor pairs 302 may be similar to Figure 1 and Figure 2 Furthermore, each of the cross-coupled pull-down transistor pairs 304 may be similar to Figure 1 and Figure 2 Furthermore, each of the sense amplifier control transistor sets 308 may be similar to Figure 1 and Figure 2 The sense amplifier controls transistor 108 .

[0064] Each of the sense amplifier control transistor sets 308 shares a continuous active material (e.g., continuous active material 310) with its corresponding pull-down transistor in the cross-coupled pull-down transistor pair 304. In other words, for each of the sense amplifiers 306a-306n, a single continuous active material (e.g., a continuous fin of a FinFET) extends uninterrupted through the corresponding pull-down transistor in the cross-coupled pull-down transistor pair 304 and the corresponding sense amplifier control transistor in the sense amplifier control transistor set 308. By way of non-limiting example, continuous active material 310 extends through the pull-down transistor in the cross-coupled pull-down transistor pair 304 corresponding to sense amplifier 306e and the sense amplifier control transistor in the sense amplifier control transistor set 308 corresponding to sense amplifier 306e.

[0065] The gate terminals of each of the sense amplifier control transistor sets 308 share a common gate material line 312. In other words, the gate material line 312 extends uninterruptedly through each of the sense amplifier control transistor sets 308. The gate material line 312 may comprise a conductive material. By way of non-limiting example, the gate material line 312 may comprise polycrystalline silicon (polysilicon). Also by way of non-limiting example, the gate material line 312 may comprise a metal (e.g., tungsten, copper, a work function metal, titanium, aluminum, or a combination thereof).

[0066] The gate material line 312 may include a gate line contact 314 to electrically connect the gate material line 312 to its respective control node (eg, Figure 1 and Figure 2 Each of the gate material lines 312 includes a single one of the gate line contacts 314 that serves one transistor of each of the sense amplifier control transistor sets 308. Figure 3A In the example of FIG, each of the gate line contacts 314 provides electrical access to fourteen transistors, which takes up less chip area than individual gate line contacts for each of the fourteen transistors. Thus, sharing common gate material line 312, and relatedly sharing gate line contacts 314, reduces the area penalty corresponding to COAG prohibition.

[0067] In some embodiments, cross-coupled pull-up transistor pair 302 and cross-coupled pull-down transistor pair 304 are FinFETs. Sense amplifier control transistor set 308 may also be a FinFET. In such embodiments, sense amplifier control transistor set 308 may share a common fin (continuous active material, such as continuous active material 310) with its corresponding cross-coupled pull-down transistor pair 304. Furthermore, each of cross-coupled pull-up transistor pairs 302 may share a continuous active material, and in the case where cross-coupled pull-up transistor pairs 302 are FinFETs, a common fin (e.g., continuous active material 316 of sense amplifier 306e).

[0068] Integrated circuit device portion 300 may include a diffusion interrupter 318 at the end of a continuous active material (e.g., continuous active material 310 and continuous active material 316). By way of non-limiting example, diffusion interrupter 318 may include a conductive material line (e.g., a polysilicon line) extending across sense amplifiers 306a-306n at the end of the continuous active material. Thus, sense amplifiers 306a-306n may share diffusion interrupter 318. Diffusion interrupter 318 may extend substantially parallel to gate material line 312.

[0069] Figure 3B 、 Figure 3C and Figure 3D Instructions for electrical connection Figure 3A Interconnect materials 320 , 322 , and 324 of a cross-coupled pull-up transistor pair 302 , a cross-coupled pull-down transistor pair 304 , and a sense amplifier control transistor set 308 of an integrated circuit device portion 300 . Figure 3B The interconnect material 320 includes landing pads and is configured to redistribute contacts (e.g., Figure 3A devices are rerouted to the interconnect material 322). Figure 3CThe interconnect material 322 includes vertical device-to-device connections within each individual sense amplifier 306a-306n and electrically connects the interconnect material 322 to the Figure 3B Interconnect material 320 and Figure 3D The contacts of the interconnect material 324 are formed. Figure 3D The interconnect material 324 includes a bit line 332 and electrically connects the interconnect material 324 to the Figure 3C The contacts of the interconnect material 322 are formed.

[0070] Reference together Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D , Figure 3B The interconnect material 320 includes a PMOS source interconnect line 326 that electrically connects the source terminals of the cross-coupled pull-up transistor pair 302. Thus, the source terminals of the cross-coupled pull-up transistor pair 302 for each of the sense amplifiers 306a-306n are electrically connected together. Similarly, the interconnect material 320 includes an NMOS source interconnect line 328 that electrically connects the source terminals of the cross-coupled pull-down transistor pair 304. Thus, the source terminals of the cross-coupled pull-down transistor pair 304 for each of the sense amplifiers 306a-306n are electrically connected together. Figure 4D The interconnect material 324 also includes a PMOS source interconnect line 326 and an NMOS source interconnect line 328. The PMOS source interconnect line 326 and the NMOS source interconnect line 328 may extend substantially parallel to the gate material line 312, the bit line 332, and the material of the diffusion interrupter 318.

[0071] Figure 3C The interconnect material 322 includes conductive line pairs 330a-330n of the sense amplifiers 306a-306n. Each of the conductive line pairs 330a-330n can be similar to the above reference Figure 1 and Figure 2 The conductive line pairs 106 discussed. For example, conductive line pairs 330a-330n can electrically connect the drain terminals of the cross-coupled pull-up transistor pair 302 to the drain terminals of the cross-coupled pull-down transistor pair 304. The conductive line pairs 330a-330n extend at least substantially parallel to the continuous active material (e.g., the continuous active material 310 and the continuous active material 316 of the sense amplifier 306e). The conductive line pairs 330a-330n also extend at least substantially perpendicular to the gate material line 312, the material of the diffusion interrupt 318, the PMOS source interconnect line 326, the NMOS source interconnect line 328, and the bit line 332.

[0072] As discussed previously, Figure 3DThe interconnect material 324 includes a bit line 332. The interconnect material 324 also includes a PMOS source interconnect line 326 and an NMOS source interconnect line 328. The bit line 332, the PMOS source interconnect line 326, and the NMOS source interconnect line 328 extend substantially parallel to the gate material line 312 and the material of the diffusion interrupt 318. The bit line 332, the PMOS source interconnect line 326, and the NMOS source interconnect line 328 also extend substantially perpendicular to the continuous active material (e.g., the continuous active material 310 and the continuous active material 316 of the sense amplifier 306e) and the conductive line pairs 330a-330n.

[0073] In some embodiments, an apparatus includes a first sense amplifier including a first cross-coupled pull-up transistor pair, a first cross-coupled pull-down transistor pair, and a first sense amplifier control transistor set sharing a first continuous active material with the first cross-coupled pull-down transistor pair. The apparatus also includes a second sense amplifier including a second cross-coupled pull-up transistor pair, a second cross-coupled pull-down transistor pair, and a second sense amplifier control transistor set sharing a second continuous active material with the second cross-coupled pull-down transistor pair.

[0074] Figure 4A yes Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D FIG. 1 is a top view of a layout design of a sub-portion 400 of the integrated circuit device portion 300 of FIG. 1 . Sub-portion 400 includes a sense amplifier 306e of the integrated circuit device portion 300. Each of the sense amplifiers 306a-306n can be similar to the sense amplifier 306e. For example, the sense amplifier 306e includes a cross-coupled pull-up transistor pair 402 including a first PMOS transistor P1 and a second PMOS transistor P2. The cross-coupled pull-up transistor pair 402 can be similar to the reference circuit. Figure 1 and Figure 2 The cross-coupled pull-up transistor pair 102 discussed above. The sense amplifier 306e also includes a cross-coupled pull-down transistor pair 404, which includes a first NMOS transistor N1 and a second NMOS transistor N2. The cross-coupled pull-down transistor pair 404 may be similar to the reference Figure 1 and Figure 2 The cross-coupled pull-down transistor pair 104 discussed above. The sense amplifier 306e further includes a sense amplifier control transistor 406, which includes a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6. The sense amplifier control transistor 406 may be similar to the reference Figure 1 and Figure 2The sense amplifier discussed controls transistor 108 .

[0075] As reference Figure 1 and Figure 2 As discussed, the gate terminals of the third NMOS transistor N3 and the fourth NMOS transistor N4 may be electrically connected to the precharge control node BLCP. Furthermore, the gate terminals of the fifth NMOS transistor N5 and the sixth NMOS transistor N6 may be electrically connected to the isolation node ISO. Furthermore, the source terminals of the first PMOS transistor P1 and the second PMOS transistor P2 may be electrically connected together at the node ACT. Furthermore, the source terminals of the first NMOS transistor N1 and the second NMOS transistor N2 may be electrically connected together at the node RNL.

[0076] like Figure 4A , the sense amplifier control transistor 406 shares a continuous active material 310 (e.g., and without limitation, a common fin of the FinFET) with the cross-coupled pull-down transistor pair 404. If the sense amplifier control transistor 406 is instead a PMOS transistor, the sense amplifier control transistor 406 may instead share a continuous active material 316 with the cross-coupled pull-up transistor pair 402. The cross-coupled pull-up transistor pair 402 (the first PMOS transistor P1 and the second PMOS transistor P2) shares the continuous active material 316 (e.g., a common fin of the FinFET).

[0077] The gate material line 312 of the sense amplifier control transistor 406 is shared with the other control gate terminals of the other sense amplifier control transistor sets 308 of the other sense amplifiers 306a-306d and 306f-306n ( Figure 3A ). By comparison Figure 4A and Figure 4C As can be seen, the gate material line 312 of the control gate terminal of the sense amplifier control transistor 406 extends at least approximately perpendicularly to the pair of conductive lines 330e that electrically connect the drain terminals of the cross-coupled pull-up transistor pair 402 to the drain terminals of the cross-coupled pull-down transistor pair 404 ( Figure 4C ). Then, the conductive line pair 330e extends at least substantially perpendicularly to the bit lines DL, DLF to which the sense amplifier 306e is electrically connected ( Figure 4D ).

[0078] exist Figure 4A In FIG, some of the contacts (shown as vertical dashed shaded rectangles) are shown as being off-center from some of the structures to which they are electrically connected. However, it should be noted that contact redistribution material (e.g., a contact redistribution layer, not shown) can be used to electrically connect these off-center contacts to these structures. For simplicity, the contacts may be arranged in a manner similar to the embodiment of FIG. Figure 4AContact redistribution materials are not shown in order to more clearly illustrate the structures according to various embodiments of the present disclosure.

[0079] Figure 4B 、 Figure 4C and Figure 4D Explanation Figure 3A The interconnect material 320, the interconnect material 322, and the interconnect material 324 of the sub-portion 400 of the integrated circuit device portion 300 are shown in FIG. Figure 4A 、 Figure 4B 、 Figure 4C and Figure 4D , the cross-coupled pull-down transistor pair 404 includes a NMOS source interconnect line 328 ( Figure 4B and Figure 4D ) are electrically connected to other cross-coupled pull-down transistor pairs of other sense amplifiers (e.g., Figure 3A Similarly, the cross-coupled pull-up transistor pair 402 includes other cross-coupled pull-up transistor pairs (e.g., Figure 3A The source terminals of the other source terminals of the cross-coupled pull-up transistor pair 302 of the sense amplifiers 306a-306d and the sense amplifiers 306f-306n.

[0080] Figure 4C The diagram illustrates a path at least substantially perpendicular to the sense amplifier 306e ( Figure 4A ) is electrically connected to the bit lines DL, DLF ( Figure 4D ) direction. Moreover, the conductive line pair 330e is at least connected to the continuous active material ( Figure 4A The continuous active material 310 and the continuous active material 316 extend in a substantially parallel manner.

[0081] Figure 3D The bit lines DL and DLF are connected to the interconnect material 324 (eg, the bit lines DL and DLF are electrically connected to the sense amplifier 306e). Figure 3D ), interconnect material 322( Figure 3C ) and interconnect material 320 ( Figure 3B ) is electrically connected to the sense amplifier 306e. The other bit lines 332 are connected to the sense amplifier 306e via the interconnect material 324 ( Figure 3D ), interconnect material 322( Figure 3C ) and interconnect material 320 ( Figure 3B ) are electrically connected to the other sense amplifiers 306a-306d and 306f-306n. Figure 3DAlso illustrated are PMOS source interconnect lines 326 and NMOS source interconnect lines 328. As discussed above, PMOS source interconnect lines 326 and NMOS source interconnect lines 328 also extend through Figure 4B of interconnect material 320 .

[0082] In some embodiments, an apparatus includes a cross-coupled pair of pull-up transistors for a sense amplifier, a cross-coupled pair of pull-down transistors for the sense amplifier, a pair of conductive lines electrically connecting the cross-coupled pair of pull-up transistors to the cross-coupled pair of pull-down transistors, and a sense amplifier control transistor sharing a contiguous active material with one of the cross-coupled pair of pull-up transistors or the cross-coupled pair of pull-down transistors.

[0083] Figure 5 FIG. 5 is a top view of a layout design of another integrated circuit device portion 500 according to some embodiments. The integrated circuit device portion 500 includes fifty-six sense amplifiers. For example, the integrated circuit device portion 500 includes fifty-six cross-coupled pull-up transistor pairs 502, fifty-six cross-coupled pull-down transistor pairs 504, and fifty-six sense amplifier control transistor sets 506. The integrated circuit device portion 500 may include four groups of fourteen sense amplifiers, where each group of fourteen sense amplifiers is similar to Figure 3A The fifty-six sense amplifiers may each be similar to Figure 1 The sense amplifier 100 or Figure 2 The sense amplifiers 200 may each be electrically connected to a bit line pair (eg, Figure 1 and Figure 2 Thus, the integrated circuit device portion 500 may be electrically connected to fifty-six bit line pairs, each of which may be electrically connected to a plurality of memory cells.

[0084] Although Figure 3A and Figure 5 The layout design illustrated in FIG includes a sense amplifier having a cross-coupled pull-down transistor pair that shares continuous active material (e.g., a continuous fin) with four sense amplifier control transistors of each sense amplifier, but in some embodiments, the cross-coupled transistor pair may share continuous active material with more or fewer than four sense amplifier control transistors. By way of non-limiting example, although not shown, the seventh NMOS transistor N7 may share continuous active material with the cross-coupled pull-down transistor pair and the sense amplifier control transistors. In such a non-limiting example, seven transistors may share continuous active material.

[0085] exist Figure 5In FIG. 1 , the gate material lines of the cross-coupled pull-up transistor pairs and the cross-coupled pull-down transistor pairs are shown as extending continuously through the fourteen sense amplifiers to reduce Figure 5 However, it should be noted that a break in the gate terminal lines of the cross-coupled pull-up transistor pair and the cross-coupled pull-down transistor pair may be provided between each sense amplifier, such as Figure 3A and Figure 4A As described in .

[0086] Figure 6 is a perspective view of a FinFET 600 according to some embodiments. As previously discussed, a cross-coupled pull-up transistor pair (e.g., Figure 1 and Figure 2 The cross-coupled pull-up transistor pair 102, Figure 3A The cross-coupled pull-up transistor pair 302, Figure 4A The cross-coupled pull-up transistor pair 402, Figure 5 A cross-coupled pull-up transistor pair 502), a cross-coupled pull-down transistor pair (eg, Figure 1 and Figure 2 The cross-coupled pull-down transistor pair 104, Figure 3A The cross-coupled pull-down transistor pair 304, Figure 4A The cross-coupled pull-down transistor pair 404, Figure 5 A cross-coupled pull-down transistor pair 504), a sense amplifier control transistor (eg, Figure 1 and Figure 2 The sense amplifier controls transistor 108, Figure 3A The sense amplifier control transistor set 308, Figure 4A The sense amplifier control transistor 406, Figure 5 The sense amplifier control transistor set 506) or a combination thereof may include FinFETs. Therefore, in some embodiments, the cross-coupled pull-up transistor pair, the cross-coupled pull-down transistor pair, the sense amplifier control transistor set or a combination thereof may be similar to Figure 6 FinFET 600.

[0087] FinFET 600 is formed on an insulating material 610 (e.g., silicon dioxide). FinFET 600 includes source / drain terminals 602, source / drain terminals 604, a fin 608 including active material extending from source / drain terminals 602 to source / drain terminals 604, and a gate terminal 606 over fin 608.

[0088] Figure 7is a perspective view of a FinFET 700 sharing continuous active material according to some embodiments. As previously discussed, the cross-coupled transistor pairs of the various sense amplifiers disclosed herein can share continuous active material with each other. Furthermore, the cross-coupled transistor pairs of the various sense amplifiers disclosed herein can share continuous active material with the sense amplifier control transistors (e.g., the cross-coupled pull-down transistor pair 404 and the sense amplifier control transistors). Figure 4A The sense amplifier control transistor 406 shares the continuous active material 310). Figure 7 An example of a continuous active material (eg, continuous fin 708 ) extending through a plurality of FinFETs 700 is illustrated.

[0089] For example, FinFET 700 includes gate terminals 712, 714, 716, and 718 and source / drain terminals 702, 704, and 706 formed on insulating material 710. A continuous fin 708 extends through the gate terminals 712, 714, 716, and 718 and source / drain terminals 702, 704, and 706 of the plurality of FinFETs 700.

[0090] FinFET 700 also illustrates metal interconnects 720 that electrically connect source / drain terminals 704 to gate terminal 716 (eg, for a cross-coupled transistor pair of a sense amplifier according to various embodiments disclosed herein).

[0091] Although Figure 7 The FinFET 700 shown in FIG. 7 includes only four transistors sharing a common fin 708, but embodiments disclosed herein may include six transistors sharing a common fin, such as Figure 4A For simplicity, Figure 7 Only four transistors sharing a common fin 708 are illustrated.

[0092] Figure 8 is a diagram illustrating the operation of a sense amplifier (eg, Figure 1 The sense amplifier 100, Figure 2 The sense amplifier 200, Figure 4A The sense amplifier 306e or Figure 5 Flowchart of method 800 of a sense amplifier of a CMOS process. At operation 802, method 800 includes asserting a sense amplifier control transistor (e.g., Figure 1 or Figure 2 The sense amplifier controls transistor 108, or Figure 3AThe shared control gate terminal (eg, gate material line 312) of any one of the sense amplifier control transistor sets 308 of the cross-coupled pull-down transistor pair shares a continuous active material (eg, Figure 3A and Figure 4A and applying a precharge voltage potential to the conductive line pair, thereby switching the bit line pair (e.g., Figure 1 、 Figure 2 or Figure 4D bit lines DL, DLF) and conductive line pairs (eg, Figure 1 or Figure 2 The conductive wire pair 106, or Figure 3C ) precharges any one of the conductive line pairs 330a-330n that will sense the amplifier (e.g., Figure 1 The sense amplifier 100, Figure 2 The sense amplifier 200, Figure 3A A cross-coupled pull-up transistor pair (eg, Figure 1 or Figure 2 The cross-coupled pull-up transistor pair 102 or Figure 3A Any one of the cross-coupled pull-up transistor pairs 302 of the sense amplifier is electrically connected to the cross-coupled pull-down transistor pair (eg, Figure 1 or Figure 2 The cross-coupled pull-down transistor pair 104, Figure 3A Any one of the cross-coupled pull-down transistor pairs 304).

[0093] In some embodiments, applying the pre-charge voltage potential to the conductive line pair includes asserting a node electrically connected to the pre-charge voltage potential node (e.g., Figure 1 The precharge voltage potential node VBLP) is connected to the conductive line pair (eg, Figure 1 The conductive wire pair 106, Figure 3C A precharge transistor (eg, Figure 1 In some embodiments, applying the precharge voltage potential to the conductive line pair includes asserting that the conductive line pair is electrically connected to the precharge voltage potential node (e.g., Figure 2 The precharge voltage potential node VBLP) is connected to at least one bit line in the bit line pair (eg, Figure 2 The bit line DLF, Figure 3D and Figure 4D A precharge transistor (eg, Figure 2The gate terminal of the seventh NMOS transistor N7 is connected to the gate terminal of the seventh NMOS transistor N7, and the precharge voltage potential is conducted from the at least one bit line to the conductive line pair through the sense amplifier control transistor.

[0094] At operation 804, the method 800 includes electrically connecting the memory cell to the precharged bit line pair.At operation 806, the method 800 includes amplifying the charge delivered by the memory cell to the bit line pair using a sense amplifier.

[0095] In some embodiments, a method of operating a sense amplifier includes precharging a bit line pair and a conductive line pair by asserting a shared control gate terminal of a sense amplifier control transistor and a cross-coupled pull-down transistor pair sharing a continuous active material and applying a precharge voltage potential to the conductive line pair, the conductive line pair electrically connecting the cross-coupled pull-up transistor pair of the sense amplifier to the cross-coupled pull-down transistor pair of the sense amplifier. The method also includes electrically connecting a memory cell to the precharged bit line pair and amplifying charge delivered by the memory cell to the bit line pair.

[0096] Figure 9 is a block diagram of a semiconductor device 900 according to some embodiments. By way of non-limiting example, semiconductor device 900 according to an embodiment is a double data rate 4 (DDR4) type DRAM integrated on a single semiconductor chip and is mounted on a substrate 902. Substrate 902 is a memory module substrate or motherboard and is provided with a resistor RE. Resistor RE is connected to a calibration terminal ZQ of semiconductor device 900, and its impedance serves as a reference impedance for calibration circuit 936. In an embodiment, resistor RE is supplied with ground potential VSS.

[0097] like Figure 9 As shown in FIG, a semiconductor device 900 includes a memory cell array 904. The memory cell array 904 is divided into eight banks BANK0 to BANK7. Each of the banks BANK0 to BANK7 is provided with a plurality of word lines WL and a plurality of bit lines BLT and BLB, and a memory cell MC is disposed at the intersection of these lines. By way of non-limiting example, the memory cell MC may be a DRAM cell having a cell transistor T and a memory cell capacitor C connected in series with the cell transistor T.

[0098] The selection of the word line WL is performed by the row decoder 916, and the selection of the bit line BL is performed by the column decoder 918. Figure 9 As shown in FIG, a row decoder 916 and a column decoder 918 are provided for each of BANK0 to BANK7.

[0099] The bit line pair BLT, BLB is connected to a sense amplifier SAMP. The read data read from the bit line BLT or the bit line BLB is amplified by the sense amplifier SAMP and thereafter transmitted to the ECC control circuit 942 via the complementary local data lines LIOT / LIOB, the switch circuit (transfer gate) TG and the complementary main data lines MIOT / MIOB. An ECC control circuit 942 is also provided for each of BANK0 to BANK7. The memory cell array 904 may include a plurality of bit line pairs BLB, BLP electrically connected to a plurality of instances of the sense amplifier SAMP. Each bit line pair BLB, BLP may be similar to the above referenced embodiment. Figure 1 、 Figure 2 and Figure 4D The bit lines DL, DLF, and Figure 3D and Figure 4D Furthermore, each instance of the sense amplifier SAMP may be similar to Figure 1 The sense amplifier 100, Figure 2 The sense amplifier 200, Figure 3A The sense amplifiers 306a-306n and / or Figure 5 Thus, the sense amplifier layout design disclosed herein (e.g., Figures 3A-3D The layout design of the integrated circuit device portion 300, Figure 5 Layout design of integrated circuit device portion 500) layout of sense amplifier SAMP.

[0100] When read data is read from the memory cell array 904, parity is also read synchronously. Conversely, write data output from the ECC control circuit 942 is transmitted to the sense amplifier SAMP via the complementary main data lines MIOT / MIOB, the switch circuit TG, and the complementary local data lines LIOT / LIOB, and is written into the memory cell MC connected to the bit line BLT or the bit line BLB. The write data is written into the memory cell array 904, and the parity is also written synchronously.

[0101] In addition, the semiconductor device 900 is provided with an address terminal 926 , a command terminal 944 , a clock terminal 928 , a data terminal 922 , a data mask terminal 924 , a voltage terminal 930 , a voltage terminal 932 , and a calibration terminal ZQ as external terminals.

[0102] The address terminal 926 is a terminal to which the address signal ADD and the bank address signal BADD are input from the outside. The address signal ADD input to the address terminal 926 is supplied to the address latch circuit 906 via the address input circuit 914 and latched therein. Of the signals latched by the address latch circuit 906, the row address signal XADD and the bank address signal BADD are supplied to the row decoder 916, while the column address signal YADD and the bank address signal BADD are supplied to the column decoder 918.

[0103] The row decoders corresponding to BANK0 to BANK7 in the row decoder 916 are selected based on the bank address signal BADD, and select predetermined word lines WL based on the row address signal XADD. The column decoders corresponding to BANK0 to BANK7 in the column decoder 918 are selected based on the bank address signal BADD, and select predetermined sense amplifiers SAMP based on the column address signal YADD.

[0104] The command terminal 944 is a terminal to which a command signal COM is input from the outside. The command signal COM input to the command terminal 944 is supplied to the command decoder 908 via the command input circuit 934. The command decoder 908 is a circuit that decodes the command signal COM and generates various internal commands ICOM. The internal commands ICOM are supplied to the row decoder 916, the column decoder 918, the timing generator 940, and the like.

[0105] For example, if an active command and a read command are input as command signals COM, and row address XADD and column address YADD are input synchronously therewith, read data and parity are read from the memory cell MC specified by these row address XADD and column address YADD. The read data and parity are input to the ECC control circuit 942, and if an error bit is contained in the read data, the read data is corrected. The corrected read data DQ is burst-outputted from the data terminal 922 to the outside via the data input / output circuit 920. Although not particularly limited, the embodiment is provided with eight terminals (DQ0 to DQ7) of the data terminal 922, and during a read operation, 8 bits of DQ of read data are burst-outputted from each terminal of the data terminal 922. Thus, 64 bits of DQ of read data are output in one read operation.

[0106] On the other hand, if an active command and a write command are input as command signal COM, and row address XADD and column address YADD are input synchronously therewith, and write data DQ is then burst-inputted to data terminal 922, then write data DQ is supplied to ECC control circuit 942 via data input / output circuit 920, and parity is generated based on the write data. The write data and parity are supplied to memory cell array 904 and written into memory cells MC specified by row address XADD and column address YADD. As described above, when eight of data terminals 922 are provided and the burst number is eight bits, 64 bits of DQ write data are input in a single write operation.

[0107] During a write operation, a data mask signal DM may be input into the data mask terminal 924. If the data mask signal DM is input, corresponding burst data of the write data DQ to be burst-input is masked.

[0108] External clock signals CK and / CK are input to clock terminal 928. External clock signal CK and external clock signal / CK are complementary signals, and both are supplied to clock input circuit 910. Upon receiving external clock signals CK and / CK, clock input circuit 910 generates an internal clock signal ICLK. Internal clock signal ICLK is supplied to internal clock generator 912, which in turn generates a phase-controlled internal clock signal LCLK. Although not particularly limited, a DLL circuit may serve as internal clock generator 912. Phase-controlled internal clock signal LCLK is supplied to data input / output circuit 920 and serves as a timing signal that determines the output timing of read data DQ. It should be noted that internal clock generator 912 is activated in response to clock enable signal CKE, which is one of command signals COM.

[0109] The internal clock signal ICLK is also supplied to the timing generator 940, which in turn generates a plurality of timing signals RT1 to RT4, WT1 to WT5. ​​The timing signals RT1 to RT4, WT1 to WT5 generated by the timing generator 940 are supplied to the ECC control circuit 942 and define the operation timing of the ECC control circuit 942 during a read operation and during a write operation, respectively.

[0110] Voltage terminal 930 is a terminal supplied with voltage potentials VDD and VSS. The voltage potentials VDD and VSS supplied to voltage terminal 930 are supplied to internal voltage generator 938. Internal voltage generator 938 generates internal potentials VPP, VOD, VARY, VPERI, and reference potential ZQVREF based on voltage potentials VDD and VSS. Internal potential VPP is primarily used in row decoder 916, internal potentials VOD and VARY are used in sense amplifier SAMP in memory cell array 904, and internal potential VPERI is used in many other circuit blocks. On the other hand, reference potential ZQVREF is used as a reference potential in calibration circuit 936.

[0111] The voltage terminal 932 is a terminal to which the voltage potentials VDDQ and VSSQ are supplied. The voltage potentials VDDQ and VSSQ supplied to the voltage terminal 932 are supplied to the data input / output circuit 920. The voltage potentials VDDQ and VSSQ are the same voltage potentials as the voltage potentials VDD and VSS supplied to the voltage terminal 930, respectively. However, in order to prevent voltage noise caused by the data input / output circuit 920 from propagating to other circuit blocks, the voltage potentials VDDQ and VSSQ dedicated to the data input / output circuit 920 are used.

[0112] The calibration terminal ZQ is connected to the calibration circuit 936. When activated by the calibration signal ZQC, the calibration circuit 936 performs a calibration operation with reference to the impedance of the resistor RE and the reference potential ZQVREF. The impedance code ZQCODE obtained by the calibration operation is supplied to the data input / output circuit 920 and further specifies the impedance of the output buffer (not shown) included in the data input / output circuit 920.

[0113] Figure 10 is a block diagram of a computing system 1000 according to some embodiments. The computing system 1000 includes one or more processors 1004 operatively coupled to one or more memory devices 1002, one or more non-volatile data storage devices 1010, one or more input devices 1006, and one or more output devices 1008. In some embodiments, the computing system 1000 includes a personal computer (PC), such as a desktop computer, a laptop computer, a tablet computer, a mobile computer (for example, and not limitation, a smartphone, a personal digital assistant (PDA)), a network server, or other computer device.

[0114] In some embodiments, the one or more processors 1004 may include a central processing unit (CPU) or other processor configured to control the computing system 1000. In some embodiments, the one or more memory devices 1002 include random access memory (RAM), such as a volatile data storage device (for example, without limitation, dynamic RAM (DRAM), static RAM (SRAM)). In some embodiments, the one or more non-volatile data storage devices 1010 include a hard drive, a solid-state drive, flash memory, an erasable programmable read-only memory (EPROM), other non-volatile data storage devices, or any combination thereof. In some embodiments, the one or more input devices 1006 include a keyboard 1014, a pointing device 1018 (for example, without limitation, a mouse, a trackpad), a microphone 1012, a keypad 1016, a scanner 1020, a camera 1028, other input devices, or any combination thereof. In some embodiments, the output device 1008 includes an electronic display 1022, a speaker 1026, a printer 1024, other output devices, or any combination thereof.

[0115] In some embodiments, one or more memory devices 1002 include sense amplifiers according to various embodiments disclosed herein. By way of non-limiting example, one or more memory devices 1002 may include Figure 1 The sense amplifier 100, Figure 2 The sense amplifier 200, Figures 3A-3D The integrated circuit device portion 300, Figure 5 Also by way of non-limiting example, one or more memory devices 1002 may be configured to perform Figure 8 Method 800.

[0116] As used in this disclosure, the term "module" or "component" may refer to a specific hardware implementation that is configured to perform the actions of a module or component and / or software object or software routine that may be stored on and / or executed by general-purpose hardware of a computing system (e.g., without limitation, a computer-readable medium, a processing device). In some embodiments, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes that execute (e.g., as separate threads) on a computing system. Although some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are possible and contemplated.

[0117] As used in this disclosure, the term "combination" with reference to a plurality of elements may include any of the combination of all elements or any of various subcombinations of some elements. For example, the phrase "A, B, C, D, or a combination thereof" may refer to any of the following: A, B, C, or D; a combination of each of A, B, C, and D; and any subcombination of A, B, C, or D: for example, A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0118] The terms used in this disclosure and especially in the appended claims (e.g., the bodies of the appended claims) are generally intended to be “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “including but not limited to,” etc.).

[0119] In addition, if a specific number of introduced claim recitations is intended, such intention will be explicitly recited in the claim, and in the absence of such recitation, no such intention exists. For example, to aid understanding, the following appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite article "a" limits any particular claim containing such introduced claim recitation to embodiments containing only one such recitation, even when the same claim contains the introductory phrases "one or more" or "at least one" and an indefinite article such as "a" (e.g., "a" and / or "an" should be interpreted to mean "at least one" or "one or more"); the same applies to the use of definite articles to introduce claim recitations.

[0120] Furthermore, even if a specific number or word of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the plain recitation "two recitations" without other modifiers generally means at least two recitations or two or more recitations). Furthermore, in those instances where a convention similar to "at least one of A, B, and C" or "one or more of A, B, and C" is used, generally, such a structure is intended to include only A, only B, only C, A and B, A and C, B and C, or A, B, and C, etc.

[0121] Additionally, it should be understood that any transitional word or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, encompasses the possibility of including one, either, or both of the terms. For example, the phrase "A or B" will be understood to include the possibilities of "A" or "B" or "A and B."

[0122] The following is a non-exhaustive, non-limiting list of example embodiments. Not every example embodiment listed below is explicitly and individually indicated as combinable with all other of the example embodiments listed below and the embodiments discussed above. However, it is contemplated that these example embodiments can be combined with all other example embodiments and embodiments discussed above unless it is clear to one of ordinary skill in the art that the embodiments are not combinable.

[0123] Embodiment 1: A device comprising: a cross-coupled pair of pull-up transistors for a sense amplifier; a cross-coupled pair of pull-down transistors for the sense amplifier; a pair of conductive lines electrically connecting the cross-coupled pair of pull-up transistors to the cross-coupled pair of pull-down transistors; and a sense amplifier control transistor sharing a continuous active material with one of the cross-coupled pair of pull-up transistors or the cross-coupled pair of pull-down transistors.

[0124] Embodiment 2: The apparatus of Embodiment 1, wherein the sense amplifier control transistor shares the contiguous active material with the cross-coupled pair of pull-down transistors.

[0125] Embodiment 3: The apparatus of any one of embodiments 1 and 2, wherein the cross-coupled pair of pull-up transistors and the cross-coupled pair of pull-down transistors are fin field effect transistors (FinFETs).

[0126] Embodiment 4: The apparatus of embodiment 3, wherein: the sense amplifier control transistor is a FinFET; and the sense amplifier control transistor and the cross-coupled pull-down transistor pair share a common fin.

[0127] Embodiment 5: The apparatus of any one of embodiments 1 to 4, wherein the cross-coupled pair of pull-up transistors share a common fin.

[0128] Embodiment 6: The apparatus of any one of embodiments 1 to 5, wherein the gate material line of the control gate terminal of the sense amplifier control transistor is shared with other control gate terminals of other sense amplifier control transistors of other sense amplifiers.

[0129] Embodiment 7: The apparatus of Embodiment 6, wherein the gate material line of the control gate terminal of the sense amplifier control transistor extends at least substantially perpendicular to the pair of conductive lines.

[0130] Embodiment 8: The apparatus of any one of embodiments 1 to 6, wherein the pair of conductive lines extends at least substantially perpendicular to a bit line to which the sense amplifier is electrically connected.

[0131] Embodiment 9: The apparatus of any one of embodiments 1 to 8, wherein the pair of conductive lines extend at least substantially parallel to the continuous active material.

[0132] Embodiment 10: The apparatus of any one of Embodiments 1 to 9, wherein the cross-coupled pull-down transistor pairs include source terminals electrically connected to other source terminals of other cross-coupled pull-down transistor pairs of other sense amplifiers.

[0133] Embodiment 11: The apparatus of any one of Embodiments 1 to 10, wherein the cross-coupled pull-up transistor pair includes source terminals electrically connected to other source terminals of other cross-coupled pull-up transistor pairs of other sense amplifiers.

[0134] Embodiment 12: The apparatus of any one of Embodiments 1 to 11, further comprising a precharge transistor electrically connected from a precharge voltage potential node to a bit line electrically connected to the sense amplifier or electrically connected to one of the conductive line pair.

[0135] Embodiment 13: A method of operating a sense amplifier, the method comprising: precharging a bit line pair and a conductive line pair by asserting that a shared control gate terminal of a sense amplifier control transistor shares continuous active material with a cross-coupled pull-down transistor pair and applying a precharge voltage potential to a conductive line pair, the conductive line pair electrically connecting the cross-coupled pull-up transistor pair of the sense amplifier to the cross-coupled pull-down transistor pair of the sense amplifier; electrically connecting a memory cell to the precharged bit line pair; and amplifying charge delivered to the bit line pair by the memory cell.

[0136] Embodiment 14: The method of Embodiment 13, wherein applying the pre-charge voltage potential to the conductive line pair comprises asserting a gate terminal of a pre-charge transistor electrically connected between a pre-charge voltage potential node and at least one conductive line of the conductive line pair.

[0137] Example 15: A method according to Example 14, wherein applying the precharge voltage potential to the conductive line pair includes: asserting a gate terminal of a precharge transistor electrically connected between a precharge voltage potential node and at least one bit line in the bit line pair; and conducting the precharge voltage potential from the at least one bit line to the conductive line pair through the sense amplifier control transistor.

[0138] Embodiment 16: A device comprising: a first sense amplifier comprising: a first cross-coupled pull-up transistor pair; a first cross-coupled pull-down transistor pair; and a first sense amplifier control transistor set that shares a first contiguous active material with the first cross-coupled pull-down transistor pair; and a second sense amplifier comprising: a second cross-coupled pull-up transistor pair; a second cross-coupled pull-down transistor pair; and a second sense amplifier control transistor set that shares a second contiguous active material with the second cross-coupled pull-down transistor pair.

[0139] Embodiment 17: The apparatus of Embodiment 16, wherein a first source terminal of the first cross-coupled pair of pull-up transistors is electrically connected to a second source terminal of the second cross-coupled pair of pull-up transistors.

[0140] Embodiment 18: The apparatus of any one of Embodiments 16 and 17, wherein the first source terminal of the first cross-coupled pair of pull-down transistors is electrically connected to the second source terminal of the second cross-coupled pair of pull-down transistors.

[0141] Embodiment 19: The apparatus of any one of Embodiments 16 to 18, wherein a first gate terminal of the first set of sense amplifier control transistors and a second gate terminal of the second set of sense amplifier control transistors share a common gate material line.

[0142] Embodiment 20: The apparatus of any one of embodiments 16 to 19, further comprising a third sense amplifier comprising: a third cross-coupled pair of pull-up transistors; a third cross-coupled pair of pull-down transistors; and a third set of sense amplifier control transistors sharing a third contiguous active material with the third cross-coupled pair of pull-down transistors.

[0143] Although the present disclosure has been described herein with respect to certain illustrated embodiments, those skilled in the art will recognize and appreciate that the present invention is not limited thereto. Indeed, many additions, deletions, and modifications may be made to the illustrated and described embodiments without departing from the scope of the present invention as claimed below and its legal equivalents. Additionally, features from one embodiment may be combined with features from another embodiment while still falling within the scope of the invention as contemplated by the inventors.

Claims

1. A sense amplifier device comprising: a cross-coupled pull-up transistor pair of a sense amplifier; a cross-coupled pair of pull-down transistors of the sense amplifier; a pair of conductive lines electrically connecting the cross-coupled pair of pull-up transistors to the cross-coupled pair of pull-down transistors; and A sense amplifier control transistor shares a continuous active material with one of the cross-coupled pair of pull-up transistors or the cross-coupled pair of pull-down transistors, the pair of conductive lines extending at least substantially parallel to the continuous active material. 2 . The sense amplifier device of claim 1 , wherein the sense amplifier control transistor shares the continuous active material with the cross-coupled pair of pull-down transistors. 3 . The sense amplifier device of claim 1 , wherein the cross-coupled pair of pull-up transistors and the cross-coupled pair of pull-down transistors are fin field effect transistors (FinFETs).

4. The sense amplifier device of claim 3 , wherein: The sense amplifier control transistor is a FinFET; and The sense amplifier control transistor and the cross-coupled pull-down transistor pair share a common fin. 5 . The sense amplifier device of claim 1 , wherein the cross-coupled pair of pull-up transistors share a common fin. 6 . The sense amplifier device of claim 1 , wherein the pair of conductive lines extend at least perpendicularly to a bit line to which the sense amplifier is electrically connected. 7 . The sense amplifier apparatus of claim 1 , wherein the cross-coupled pull-down transistor pairs include source terminals electrically connected to other source terminals of other cross-coupled pull-down transistor pairs of other sense amplifiers. 8 . The sense amplifier apparatus of claim 1 , wherein the cross-coupled pull-up transistor pairs include source terminals electrically connected to other source terminals of other cross-coupled pull-up transistor pairs of other sense amplifiers.

9. The sense amplifier device of claim 1 , further comprising a precharge transistor electrically connected from a precharge voltage potential node to a bit line electrically connected to the sense amplifier or electrically connected to one of the conductive line pair.

10. A sense amplifier device comprising: a cross-coupled pull-up transistor pair of a sense amplifier; a cross-coupled pair of pull-down transistors of the sense amplifier; a pair of conductive lines electrically connecting the cross-coupled pair of pull-up transistors to the cross-coupled pair of pull-down transistors; and A sense amplifier control transistor shares a continuous active material with one of the cross-coupled pull-up transistor pair or the cross-coupled pull-down transistor pair, a gate material line sharing a control gate terminal of the sense amplifier control transistor with other control gate terminals of other sense amplifier control transistors of other sense amplifiers. 11 . The sense amplifier device of claim 10 , wherein the gate material line of the control gate terminal of the sense amplifier control transistor extends at least perpendicularly to the pair of conductive lines.

12. A method of operating a sense amplifier, the method comprising: precharging a pair of bit lines and a pair of conductive lines electrically connecting a cross-coupled pair of pull-up transistors of the sense amplifier to the cross-coupled pair of pull-down transistors of the sense amplifier by asserting a shared control gate terminal of the sense amplifier control transistors and a cross-coupled pair of pull-down transistors sharing a continuous active material and applying a precharge voltage potential to the pair of conductive lines, wherein the pair of conductive lines extends at least substantially parallel to the continuous active material; electrically connecting a memory cell to the precharged bit line pair; and Charge delivered to the bit line pair by the memory cell is amplified.

13. The method of claim 12, wherein applying the pre-charge voltage potential to the conductive line pair comprises asserting a gate terminal of a pre-charge transistor electrically connected between a pre-charge voltage potential node and at least one conductive line of the conductive line pair.

14. The method of claim 13 , wherein applying the pre-charge voltage potential to the conductive line pair comprises: asserting a gate terminal of a precharge transistor electrically connected between a precharge voltage potential node and at least one bit line of the bit line pair; and The precharge voltage potential is conducted from the at least one bit line to the conductive line pair through the sense amplifier control transistor.

15. A sense amplifier device comprising: A first sense amplifier comprising: a first cross-coupled pull-up transistor pair; a first cross-coupled pull-down transistor pair; and a first sense amplifier control transistor set sharing a first contiguous active material with the first cross-coupled pull-down transistor pair; and A second sense amplifier comprising: a second cross-coupled pair of pull-up transistors; a second cross-coupled pull-down transistor pair; and A second sense amplifier control transistor set shares a second contiguous active material with the second cross-coupled pull-down transistor pair. 16 . The sense amplifier device of claim 15 , wherein a first source terminal of the first cross-coupled pull-up transistor pair is electrically connected to a second source terminal of the second cross-coupled pull-up transistor pair. 17 . The sense amplifier device of claim 15 , wherein a first source terminal of the first cross-coupled pull-down transistor pair is electrically connected to a second source terminal of the second cross-coupled pull-down transistor pair. 18 . The sense amplifier device of claim 15 , wherein a first gate terminal of the first sense amplifier control transistor set and a second gate terminal of the second sense amplifier control transistor set share a common gate material line.

19. The sense amplifier apparatus of claim 15 , further comprising a third sense amplifier, the third sense amplifier comprising: a third cross-coupled pull-up transistor pair; a third cross-coupled pair of pull-down transistors; and A third sense amplifier control transistor set shares a third contiguous active material with the third cross-coupled pull-down transistor pair.

Images