Reconfigurable ferroelectric single transistor in-memory boolean logic gate and method of fabrication thereof

Abstract

The application provides a reconfigurable ferroelectric single transistor in-memory Boolean logic gate, which comprises a pulse input electrode, a ferroelectric dielectric layer, a direct current input electrode, a dielectric layer, a source electrode, a drain electrode, an ultrathin channel layer, a silicon dioxide layer and a silicon substrate; the high and low resistance states of the ultrathin channel layer represent the Boolean logic output of the single transistor; the pulse input electrode and the direct current input electrode respectively regulate the series resistance in the channel; the polarization state of the ferroelectric dielectric layer stores the information of the pulse input electrode, thereby continuously regulating the series resistance state after the pulse ends. The application utilizes the nonvolatile storage characteristics of the ferroelectric dielectric layer, regulates the series resistance in the ultrathin channel layer by using a pulse signal and a direct current signal respectively, and represents the Boolean logic output of the single transistor by the high and low resistance states of the channel layer, so that the single transistor has the functions of logic calculation and information storage, and the in-memory Boolean logic gate can be switched between OR-NOT and AND, and has the advantages of reconfigurable multifunction.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and relates to a semiconductor memory device, a digital computing device, a data processing device or a data processing method, in particular to a reconfigurable ferroelectric single transistor in-memory Boolean logic gate and a preparation method thereof. BACKGROUND

[0002] Data-intensive applications represented by artificial intelligence and big data have been growing explosively, which is continuously promoting the development of information society. The traditional von Neumann architecture causes great loss of computing power due to the physical separation of storage units and computing units. The improvement of circuit performance cannot keep up with the rapid growth of data operation. For example, the demand for chip computing power has increased significantly in artificial intelligence. Therefore, developing high-function integrated density, low power consumption, high computing power and high energy efficiency "non-von" architecture in-memory computing logic gate and chip technology has become a key bottleneck technology to expand the boundaries of related technologies.

[0003] One of the key technologies to achieve this breakthrough is the ferroelectric field effect transistor with non-volatile storage characteristics. In the transistor structure, the ferroelectric material is used to adjust the conductivity of the semiconductor channel, realizing data storage, which plays a key role in promoting the development of in-memory computing integration. However, a single ferroelectric field effect transistor needs hardware cooperation outside the storage and computing array to complete data input and output, and does not have the function of single transistor data storage and logic calculation, which inevitably faces the problem of data transmission bottleneck and circuit layout and wiring, seriously reducing its energy efficiency. In order to solve this problem, researchers have proposed a single transistor in-memory logic operation gate. Since the transistor integrates storage and logic operation functions, it avoids data transmission loss and improves area efficiency, so it is expected to become a basic unit module of non-von architecture, attracting scientists to invest a lot of effort to accelerate its practical application. However, the research on single transistor in-memory Boolean logic gate is extremely limited, and the existing in-memory logic gate has limited functions, which hinders the application of the device in high-function density integrated circuits and limits the development of high-energy efficiency and high-integration in-memory computing chips. SUMMARY

[0004] In order to overcome the above-mentioned shortcomings of the prior art, in view of the demand for non-von architecture circuit with high energy efficiency and high computing power represented by artificial intelligence and big data, the purpose of the present application is to provide a reconfigurable ferroelectric single transistor in-memory Boolean logic gate and a preparation method thereof, which integrates logic operation and data storage functions, and has high integration characteristics due to the switching ability of the reconfigurable logic gate.

[0005] In order to achieve the above-mentioned purpose, the technical scheme adopted by the present application is:

[0006] The application discloses a reconfigurable ferroelectric single transistor in-memory Boolean logic gate, which is characterized by comprising a silicon substrate, a silicon dioxide layer arranged on the silicon substrate, an ultrathin channel layer arranged on the silicon dioxide layer, a ferroelectric dielectric layer, a dielectric layer, a source electrode and a drain electrode arranged on the ultrathin channel layer, a direct current input electrode arranged between a part of the ferroelectric dielectric layer and the dielectric layer, and a pulse input electrode arranged on the ferroelectric dielectric layer.

[0007] In an embodiment of the application, the ultrathin channel layer is made of an intrinsic semiconductor or a lightly doped semiconductor.

[0008] When the source electrode is grounded and the drain electrode is connected to a power supply voltage, the main carrier in the ultrathin channel layer is an electron, the electron aggregation is represented as a low resistance state of the channel series resistance, the hole aggregation is represented as a high resistance state of the channel series resistance, and the reconfigurable ferroelectric single transistor works in an in-memory logic AND gate mode. In the AND gate mode, a positive pulse is applied to the pulse input electrode, most of the polarization charges in the ferroelectric dielectric layer are reversed, the polarization state is changed, the electron in the ultrathin channel layer and the polarization charge in the ferroelectric dielectric layer respond to each other, and the resistance of the corresponding region of the channel is controlled to be in a low resistance state; meanwhile, a positive voltage is applied to the direct current input electrode, the electron in the ultrathin channel layer is aggregated, the resistance of the corresponding region of the channel is controlled to be in a low resistance state, and when the series resistances in the ultrathin channel layer controlled by the pulse input electrode and the direct current input electrode are both in a low resistance state, the reconfigurable ferroelectric single transistor in-memory logic gate is in a logic state of "1" when the two input electrodes are both positive.

[0009] When the source electrode is connected to a power supply voltage and the drain electrode is grounded, the main carrier in the ultrathin channel layer is a hole, the electron aggregation is represented as a high resistance state of the channel series resistance, and the hole aggregation is represented as a low resistance state of the channel series resistance; the reconfigurable ferroelectric single transistor works in an in-memory logic OR-NOT gate mode. In the OR-NOT gate mode, a negative pulse is applied to the pulse input electrode, most of the polarization charges in the ferroelectric dielectric layer are reversed, the polarization state is changed, the hole in the ultrathin channel layer and the polarization charge in the ferroelectric dielectric layer respond to each other, and the resistance of the corresponding region of the channel is controlled to be in a low resistance state; meanwhile, a negative voltage is applied to the direct current input electrode, the hole in the ultrathin channel layer is aggregated, the resistance of the corresponding region of the channel is controlled to be in a low resistance state, and when the series resistances in the ultrathin channel layer controlled by the pulse input electrode and the direct current input electrode are both in a low resistance state, the reconfigurable ferroelectric single transistor in-memory logic gate is in a logic state of "1" when the two input electrodes are both negative.

[0010] In one embodiment of the present application, the two side portions of the ferroelectric dielectric layer are in direct contact with the ultra-thin channel layer, the middle portion is protruded upward, the dielectric layer is arranged below the protruded portion and in direct contact with the ultra-thin channel layer, the direct current input electrode is arranged above the dielectric layer and in direct contact with the dielectric layer, and the source electrode and the drain electrode are respectively arranged outside the two side portions of the ferroelectric dielectric layer and in direct contact with the ultra-thin channel layer.

[0011] In one embodiment of the present application, the material of the pulse input electrode, the direct current input electrode, the source electrode and the drain electrode can be any one of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide and tantalum silicide.

[0012] In one embodiment of the present application, the ultra-thin channel layer can be any one of Si, Ge, SiGe, GaN, GaAs and SiC, and the thickness is generally less than 200 nm.

[0013] In one embodiment of the present application, the material of the ferroelectric dielectric layer can be any one of HfO2, SiO2, SiON, Si3N4, TiO2, HfO2, ZrO2, Al2O3, ZnSnO3, HYO, HZO, HSO, HAO, BFO, PZT and BST. 0.5 Zr 0.5 O2, Hf 0.3 Zr 0.7 O2, HYO, HZO, HSO, HAO, BFO, PZT, BST, ZrO2, Al2O3, ZnSnO3.

[0014] In one embodiment of the present application, the material of the dielectric layer is HfO2, SiO2, SiON, Si3N4, TiO2, HfO2, ZrO2, Al2O3, ZnSnO3, HYO, HZO, HSO, HAO, BFO, PZT, BST, ZrO2, Al2O3, ZnSnO3. 0.5 Zr 0.5 O2, Hf 0.3 Zr 0.7 O2, HYO, HZO, HSO, HAO, BFO, PZT, BST, ZrO2, Al2O3, ZnSnO3.

[0015] The present application also provides a preparation method of the reconfigurable ferroelectric single transistor in-memory Boolean logic gate, which comprises the following steps:

[0016] Step 1), preparing a silicon dioxide layer on a silicon substrate, preparing an ultra-thin channel layer on the silicon dioxide layer, and etching an active region on the ultra-thin channel layer;

[0017] Step 2), depositing a dielectric material on the ultra-thin channel layer to form a dielectric layer by using a deposition process, growing an electrode material on the dielectric layer by using a sputtering process or a deposition process, and etching to form a direct current input electrode;

[0018] Step 3), growing electrode material at both ends of the active region by using a sputtering process or a deposition process, and stripping or etching to form a source electrode and a drain electrode;

[0019] Step 4), growing a ferroelectric material layer by using a deposition process in a self-aligned manner to form a ferroelectric dielectric layer, growing a layer of electrode material above the ferroelectric dielectric layer by using a sputtering process or a deposition process, and etching to form a pulse input electrode, thereby completing the preparation of the reconfigurable ferroelectric single-crystal transistor in-memory Boolean logic gate.

[0020] In an embodiment of the present application, the pulse input electrode in step 4) is formed in a self-aligned manner at a gap position between the direct current input electrode and the source electrode and the drain electrode formed in steps 2) and 3).

[0021] In an embodiment of the present application, the self-aligned process is used to form the pulse input electrode.

[0022] Compared with the prior art, the present application has the following beneficial effects:

[0023] The present application uses the non-volatile storage characteristics of the ferroelectric dielectric layer to respectively control the series resistance in the ultra-thin channel layer by using a pulse signal and a direct current signal, and the high and low resistance states of the channel layer are used to represent the Boolean logic output of the single-crystal transistor, so that a single transistor has logic computing function and information storage function, and the in-memory Boolean logic gate can be switched between "or non" and "and", which has the significant advantage of reconfiguration. Secondly, the present application has the functions of reconfiguration and in-memory computing, and the structure and materials are compatible with the silicon-based process of integrated circuits, and can be used for the development of high-function density and high-energy efficiency "non-Fon" memory-computing integrated architecture, and is expected to become a basic unit of in-memory computing integrated circuits in the post-moore era. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 FIG. 1 is a structural schematic diagram (perspective view) of a reconfigurable ferroelectric single-crystal transistor in-memory Boolean logic gate according to the present application.

[0025] Figure 2 FIG. 2 is a cross-sectional view of the reconfigurable ferroelectric single-crystal transistor in-memory Boolean logic gate according to the present application. Figure 1 FIG. 3 is a cross-sectional view of the reconfigurable ferroelectric single-crystal transistor in-memory Boolean logic gate according to the present application.

[0026] Figure 3 FIG. 4 is a schematic diagram showing the principle that the high and low resistance states of the channel are controlled by two input terminals when the reconfigurable ferroelectric single-crystal transistor in-memory Boolean logic gate forms an "and" gate state.

[0027] Figure 4 FIG. 5 is a schematic diagram showing the principle that the high and low resistance states of the channel are controlled by two input terminals when the reconfigurable ferroelectric single-crystal transistor in-memory Boolean logic gate forms an "or non" gate state.

[0028] Figure 5The preparation flowchart of the reconfigurable ferroelectric single transistor in-memory Boolean logic gate.

[0029] In the figure: 1, pulse input end electrode, 2, ferroelectric dielectric layer, 3, direct current input end electrode, 4, dielectric layer, 5, source end electrode, 6, drain end electrode, 7, ultrathin channel layer, 8, silicon dioxide layer, 9, silicon substrate. DETAILED DESCRIPTION

[0030] The embodiments of the present application will be described in detail below with reference to the drawings and examples.

[0031] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments in the present application belong to the scope of protection of the present application.

[0032] Those skilled in the art should understand that, in the disclosure of the present application, the orientations or positional relationships indicated by the terms "longitudinal", "transverse", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are based on the orientations or positional relationships shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore the above terms cannot be understood as a limitation on the present application.

[0033] It can be understood that the term "one" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of one element can be one, and in another embodiment, the number of the element can be multiple, and the term "one" cannot be understood as a limitation on the number.

[0034] As shown in Figure 1 and Figure 2 , as shown in Figure 1 and Figure 2 , the structure schematic diagram of the reconfigurable ferroelectric single transistor in-memory Boolean logic gate, the reconfigurable ferroelectric single transistor in-memory Boolean logic gate includes a pulse input end electrode 1, a ferroelectric dielectric layer 2, a direct current input end electrode 3, a dielectric layer 4, a source end electrode 5, a drain end electrode 6, an ultrathin channel layer 7, a silicon dioxide layer 8 and a silicon substrate 9.

[0035] In this invention, the bottommost portion of the silicon substrate 9 consists of a silicon dioxide layer 8 and an ultrathin channel layer 7. A ferroelectric dielectric layer 2, a dielectric layer 4, a source electrode 5, and a drain electrode 6 are all disposed on the ultrathin channel layer 7. A portion of the ferroelectric dielectric layer 2 is not in contact with the ultrathin channel layer 7; the dielectric layer 4 is located below this portion, and the DC input electrode 3 is located below this portion and above the dielectric layer 4, directly contacting the dielectric layer 4. The pulse input electrode 1 is disposed above the ferroelectric dielectric layer 2.

[0036] Among them, the high and low resistance states of the ultrathin channel layer 7 represent the Boolean logic output of a single transistor; the pulse input electrode 1 and the DC input electrode 3 respectively regulate the series resistance in the ultrathin channel layer 7; the polarization state of the ferroelectric dielectric layer 2 stores the information of the pulse input electrode 1, thereby continuously regulating the resistance state of the series resistance after the pulse ends.

[0037] In one specific structure of the present invention, the ferroelectric dielectric layer 2 has a convex cross-section. The lower surfaces of its two outer portions directly contact the upper surface of the ultrathin channel layer 7, while the middle portion protrudes upwards. The dielectric layer 4 is disposed below the protruding portion and directly contacts the upper surface of the ultrathin channel layer 7. The DC input electrode 3 is disposed above the dielectric layer 4 and directly contacts the upper surface of the dielectric layer 4, while also being able to directly contact the lower surface of the protruding portion of the ferroelectric dielectric layer 2. The DC input electrode 3 can be led outwards. The source electrode 5 and drain electrode 6 are respectively disposed on the outer sides of the two outer portions of the ferroelectric dielectric layer 2 and directly contact the upper surface of the ultrathin channel layer 7. For example, the source electrode 5 and drain electrode 6 are symmetrical about the protruding portion of the ferroelectric dielectric layer 2.

[0038] In embodiments of the present invention, the pulse input electrode 1, the DC input electrode 3, the source electrode 5, and the drain electrode 6 are all made of metallic materials. Specifically, the materials used for the pulse input electrode 1, the DC input electrode 3, the source electrode 5, and the drain electrode 6 are any one of the following: tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

[0039] The ultrathin channel layer 7 can be made of intrinsic semiconductor, lightly doped P-type semiconductor, or lightly doped N-type semiconductor. Specifically, the material of the ultrathin channel layer 7 can be any one of Si, Ge, SiGe, GaN, GaAs, and SiC. Its thickness is generally less than 200 nm.

[0040] The material of ferroelectric layer 3 is Hf 0.5 Zr 0.5 O2, Hf 0.3 Zr 0.7Any one of O2, HYO, HZO, HSO, HAO, BFO, PZT, BST, ZrO2, Al2O3, ZnSnO3. Among them, HZO is zirconium-doped hafnium oxide, BFO is bismuth ferrite, PZT is lead zirconate titanate, ZrO2 is zirconium dioxide, Al2O3 is aluminum oxide, ZnSnO3 is zinc stannate, HSO is silicon-doped hafnium oxide, HAO is aluminum-doped hafnium oxide, BST is barium strontium titanate, and HYO is yttrium-doped hafnium oxide.

[0041] The material of the medium layer 4 is HfO2, SiO2, SiON, Si3N4, TiO2, Hf 0.5 Zr 0.5 O2, Hf 0.3 Zr 0.7 Any one of O2, HYO, HZO, HSO, HAO, BFO, PZT, BST, ZrO2, Al2O3, ZnSnO3.

[0042] Figure 3 And Figure 4 The principle diagram of the channel high and low resistance states of the reconfigurable ferroelectric single transistor in-memory Boolean logic gate controlled by two input terminals, taking the intrinsic semiconductor as an example:

[0043] 1) When the source electrode 5 is grounded and the drain electrode 6 is connected to the power supply voltage, the main carriers in the ultra-thin channel layer 7 are electrons, and the electron aggregation is in the low resistance state of the channel series resistance, and the hole aggregation is in the high resistance state of the channel series resistance. At this time, the reconfigurable ferroelectric single transistor works in the in-memory logic AND gate state.

[0044] A positive pulse is applied to the pulse input electrode 1, most of the polarization charges in the ferroelectric medium layer 2 are reversed, the polarization state is changed, the electrons in the ultra-thin channel layer 7 respond to the polarization charges inside the ferroelectric medium layer 2, and the resistance of the corresponding region of the control channel is in the low resistance state. A positive voltage is applied to the direct current input electrode 3 to attract the electrons in the ultra-thin channel layer 7 to gather, and the resistance of the corresponding region of the control channel is in the low resistance state. When the series resistance in the ultra-thin channel layer 7 controlled by the pulse input electrode 1 and the direct current input electrode 3 is in the low resistance state, the logic state of the reconfigurable ferroelectric single transistor in-memory logic gate is "1".

[0045] A positive pulse is applied to the pulse input electrode 1, most of the polarization charges in the ferroelectric medium layer 2 are reversed, the polarization state is changed, the electrons in the ultra-thin channel layer 7 respond to the polarization charges inside the ferroelectric medium layer 2, and the resistance of the corresponding region of the control channel is in the low resistance state. A positive voltage is applied to the direct current input electrode 3 to attract the electrons in the ultra-thin channel layer 7 to gather, and the resistance of the corresponding region of the control channel is in the low resistance state. When the series resistance in the ultra-thin channel layer 7 controlled by the pulse input electrode 1 and the direct current input electrode 3 is in the low resistance state, the logic state of the reconfigurable ferroelectric single transistor in-memory logic gate is "1".

[0046] A negative pulse is applied to the pulse input end electrode 1, most of the polarization charges in the ferroelectric dielectric layer 2 are reversed, the polarization state is changed, the holes in the ultra-thin channel layer 7 respond to the polarization charges inside the ferroelectric dielectric layer 2, and the resistance of the corresponding region of the control channel is in a high resistance state; a positive voltage is applied to the direct current input end electrode 3, the electrons in the ultra-thin channel layer 7 are attracted to gather, the resistance of the corresponding region of the control channel is in a low resistance state, and at this time the logic state of the reconfigurable ferroelectric single transistor in-memory logic gate is "0".

[0047] A negative pulse is applied to the pulse input end electrode 1, most of the polarization charges in the ferroelectric dielectric layer 2 are reversed, the polarization state is changed, the holes in the ultra-thin channel layer 7 respond to the polarization charges inside the ferroelectric dielectric layer 2, and the resistance of the corresponding region of the control channel is in a high resistance state; a negative voltage is applied to the direct current input end electrode 3, the holes in the ultra-thin channel layer 7 are attracted to gather, the resistance of the corresponding region of the control channel is in a high resistance state, and at this time the logic state of the reconfigurable ferroelectric single transistor in-memory logic gate is "0".

[0048] 2) When the source electrode 5 is connected to the power supply voltage and the drain electrode 6 is grounded, the main carrier in the ultra-thin channel layer 7 is a hole, and the electron gathering is in a high resistance state of the channel series resistance, and the hole gathering is in a low resistance state of the channel series resistance, and at this time the reconfigurable ferroelectric single transistor works in an in-memory logic "or non" gate state.

[0049] A negative pulse is applied to the pulse input end electrode 1, most of the polarization charges in the ferroelectric dielectric layer 2 are reversed, the polarization state is changed, the holes in the ultra-thin channel layer 7 respond to the polarization charges inside the ferroelectric dielectric layer 2, and the resistance of the corresponding region of the control channel is in a low resistance state; a negative voltage is applied to the direct current input end electrode 3, the holes in the ultra-thin channel layer 7 are attracted to gather, the resistance of the corresponding region of the control channel is in a low resistance state, and when the series resistance of the ultra-thin channel layer 7 controlled by the pulse input end electrode 1 and the direct current input end electrode 3 is in a low resistance state, the logic state of the reconfigurable ferroelectric single transistor in-memory logic gate is "1".

[0050] A positive pulse is applied to the pulse input end electrode 1, most of the polarization charges in the ferroelectric dielectric layer 2 are reversed, the polarization state is changed, the electrons in the ultra-thin channel layer 7 respond to the polarization charges inside the ferroelectric dielectric layer 2, and the resistance of the corresponding region of the control channel is in a high resistance state; a negative voltage is applied to the direct current input end electrode 3, the holes in the ultra-thin channel layer 7 are attracted to gather, the resistance of the corresponding region of the control channel is in a low resistance state, and at this time the logic state of the reconfigurable ferroelectric single transistor in-memory logic gate is "0".

[0051] When a positive pulse is applied to the pulse input end electrode 1, most of the polarization charges in the ferroelectric dielectric layer 2 are reversed, the polarization state is changed, the holes in the ultra-thin channel layer 7 respond to the polarization charges inside the ferroelectric dielectric layer 2, and the resistance of the corresponding region of the control channel is in a low resistance state; a positive voltage is applied to the direct current input end electrode 3, the electrons in the ultra-thin channel layer 7 are attracted to gather, the resistance of the corresponding region of the control channel is in a high resistance state, and at this time the logic state of the reconfigurable ferroelectric single transistor in-memory logic gate is “0”.

[0052] When a positive pulse is applied to the pulse input end electrode 1, most of the polarization charges in the ferroelectric dielectric layer 2 are reversed, the polarization state is changed, the holes in the ultra-thin channel layer 7 respond to the polarization charges inside the ferroelectric dielectric layer 2, and the resistance of the corresponding region of the control channel is in a low resistance state; a positive voltage is applied to the direct current input end electrode 3, the electrons in the ultra-thin channel layer 7 are attracted to gather, the resistance of the corresponding region of the control channel is in a high resistance state, and at this time the logic state of the reconfigurable ferroelectric single transistor in-memory logic gate is “0”.

[0053] When the ultra-thin channel layer 7 adopts a P-type or N-type lightly doped semiconductor, the principle is the same as above. In summary, by applying a pulse to the pulse input end electrode 11 and applying a voltage to the direct current input end electrode 3, the series resistance in the ultra-thin channel layer 7 is regulated, the high and low resistance states of the channel layer represent the Boolean logic output of the single transistor, so that a single transistor has logic computing function and information storage function, and the in-memory Boolean logic gate can be switched between “NOR” and “AND” according to the voltage of the source electrode 5 and the drain electrode 6.

[0054] The application utilizes the non-volatile storage characteristics of the ferroelectric dielectric layer to regulate the series resistance in the ultra-thin channel layer by pulse signals and direct current signals, the high and low resistance states of the channel layer represent the Boolean logic output of the single transistor, so that a single transistor has logic computing function and information storage function, and the in-memory Boolean logic gate can be switched between “NOR” and “AND”, which has the significant advantage of reconfigurability; secondly, the application has reconfigurability and in-memory computing function, and the structure and materials are compatible with silicon-based process of integrated circuits, which can be used for developing high-function density and high-energy efficiency “non-von” memory-computing integrated architecture, and is expected to become a basic unit of in-memory computing integrated circuits in post-moore era.

[0055] Referring to Figure 5 The application also provides a preparation method of the reconfigurable ferroelectric single transistor in-memory Boolean logic gate, which comprises the following specific steps:

[0056] Step 1), preparing a silicon dioxide layer 8 on a silicon substrate 9, preparing an ultra-thin channel layer 7 on the silicon dioxide layer 8, and etching an active region on the ultra-thin channel layer 7, such as Figure 5 ;

[0057] Step 2), depositing a dielectric material on the ultra-thin channel layer 7 to form a dielectric layer 4, growing an electrode material on the dielectric layer 4 by sputtering or deposition, and etching to form a direct current input electrode 3, as shown in Fig. 2. Figure 5 ;

[0058] Step 3), growing electrode materials at both ends of the active region by sputtering or deposition, and stripping or etching to form a source electrode 5 and a drain electrode 6, as shown in Fig. 3. Figure 5 ;

[0059] Step 4), growing a ferroelectric material on the dielectric layer 4 by self-alignment to form a ferroelectric dielectric layer 2, growing an electrode material on the ferroelectric dielectric layer 2 by sputtering or deposition, and etching to form a pulse input electrode 1, as shown in Fig. 4. Figure 5 .

[0060] In step 4), the pulse input electrode is formed in a self-alignment manner at the gap position between the direct current input electrode 3 and the source electrode 5 and the drain electrode 6 formed in step 2) and step 3). The pulse input electrode 1 can also be formed by a self-alignment process.

[0061] The following gives three specific embodiments of preparation methods of reconfigurable ferroelectric single-crystal transistor in-memory Boolean logic gates based on different materials.

[0062] Embodiment 1:

[0063] HfO2 is used to make the ferroelectric dielectric layer 2, Si is used as the ultra-thin channel layer, and metal tungsten is used as the material of the pulse input electrode 1, the direct current input electrode 3, the source electrode 5, and the drain electrode 6. The specific preparation method is as follows: 0.5 ZrO2 is used to make the ferroelectric dielectric layer 2, Si is used as the ultra-thin channel layer, and metal tungsten is used as the material of the pulse input electrode 1, the direct current input electrode 3, the source electrode 5, and the drain electrode 6. The specific preparation method is as follows: 0.5

[0064] Step 1: etching the active region on the intrinsic Si ultra-thin channel layer 7.

[0065] Step 2), depositing a dielectric material on the ultra-thin channel layer 7 to form a dielectric layer 4, growing an electrode material on the dielectric layer 4 by sputtering or deposition, and etching to form a direct current input electrode 3, as shown in Fig. 2.

[0066] In this step, a reaction sputtering process is used. First, a molecular pump or a cold pump is used to vacuum the reaction chamber until the vacuum pressure in the reaction chamber reaches 0.02 Torr. Then, under the conditions of a sputtering power of 350 W and an argon pressure of 5 mTorr, metal tungsten is used as the target material to uniformly sputter the upper surface of the dielectric layer 4, depositing a layer of metal tungsten on the surface, thereby forming the direct current input electrode 3.

[0067] ​Step three: growing electrode materials at both ends of the active region by sputtering process, and stripping or etching to form source electrode 5 and drain electrode 6;

[0068] In this step, a reaction sputtering process is used. First, a molecular pump or a cold pump is used to vacuum the reaction chamber until the vacuum pressure in the reaction chamber reaches 0.02 Torr. Then, under the conditions of a sputtering power of 350 W and an argon pressure of 5 mTorr, a metal tungsten target is used to uniformly sputter the surface of the ultra-thin channel surface 7, deposit a layer of metal tungsten on the surface, and form the source electrode 5 and the drain electrode 6.

[0069] Step four: self-aligned growth of ferroelectric material to form ferroelectric dielectric layer 2, and growing a layer of electrode material above the ferroelectric dielectric layer 2, and etching to form pulse input electrode 1, to complete the preparation of the reconfigurable ferroelectric single crystal transistor in-memory Boolean logic gate;

[0070] In this step, an atomic layer deposition process is used. First, ion water is used as an oxygen source, tetraethylmethylamino hafnium (TEMAHf) is used as a hafnium precursor source, and tetraethylmethylamino zirconium (TEMAZr) is used as a zirconium precursor source, and the temperature is raised to 573 K. Then, by adjusting the pulse ratio of the hafnium precursor source and the zirconium precursor source, a Hf 0.5 Zr 0.5 O2 ferroelectric material thin film is grown on the upper surface of the ultra-thin channel layer 7 to form the ferroelectric dielectric layer 2.

[0071] In this step, a reaction sputtering process is used. First, a molecular pump or a cold pump is used to vacuum the reaction chamber until the vacuum pressure in the reaction chamber reaches 0.02 Torr. Then, under the conditions of a sputtering power of 350 W and an argon pressure of 5 mTorr, a metal tungsten target is used to uniformly sputter the surface of the ultra-thin channel surface 7, deposit a layer of metal tungsten on the surface, form the pulse input electrode 1, and complete the preparation of the reconfigurable ferroelectric single crystal transistor in-memory Boolean logic gate.

[0072] Example 2:

[0073] The HYO ferroelectric material is used to make the ferroelectric dielectric layer 2, the Ge substrate is used to make the ultra-thin channel surface 7, and the metal titanium is used as the material of the pulse input electrode 1, the direct current input electrode 3, the source electrode 5, and the drain electrode 6. The specific manufacturing method is as follows:

[0074] Step one: etching the active region on the N-type lightly doped semiconductor Ge ultra-thin channel layer 7.

[0075] Step two: depositing a dielectric material on the ultra-thin channel layer 7 to form a dielectric layer 4, and growing a layer of electrode material above the dielectric layer 4, and etching to form a direct current input electrode 3;

[0076] In this step, the reaction sputtering process is used. First, a molecular pump or a cold pump is used to vacuum the reaction chamber until the vacuum pressure in the reaction chamber reaches 0.02 Torr. Then, under the conditions of a sputtering power of 350 W and an argon pressure of 5 mTorr, metal titanium is used as the target material to uniformly sputter the surface of the ultra-thin channel layer 7, depositing a layer of metal titanium on the surface to form the direct current input electrode 3.

[0077] Step three: sputtering electrode material on both ends of the active region, and stripping or etching to form the source electrode 5 and the drain electrode 6.

[0078] In this step, the reaction sputtering process is used. First, a molecular pump or a cold pump is used to vacuum the reaction chamber until the vacuum pressure in the reaction chamber reaches 0.02 Torr. Then, under the conditions of a sputtering power of 350 W and an argon pressure of 5 mTorr, metal titanium is used as the target material to uniformly sputter the surface of the ultra-thin channel layer 7, depositing a layer of metal titanium on the surface to form the source electrode 5 and the drain electrode 6.

[0079] Step four: self-aligned growth of ferroelectric material to form a ferroelectric dielectric layer 2, and growth of a layer of electrode material above the ferroelectric dielectric layer 2, etching to form a pulse input electrode 1, completing the preparation of the reconfigurable ferroelectric single-crystal transistor in-memory Boolean logic gate.

[0080] The pulse laser sputtering deposition process is used to form a thin film of HYO material on the surface of the ultra-thin channel layer 7 by alternating sputtering deposition of double targets (HfO2 ceramic target 99.99%, Y2O3 ceramic target 99.99%), and the HYO material is crystallized by annealing process to form the ferroelectric dielectric layer 2.

[0081] In this step, the reaction sputtering process is used. First, a molecular pump or a cold pump is used to vacuum the reaction chamber until the vacuum pressure in the reaction chamber reaches 0.02 Torr. Then, under the conditions of a sputtering power of 350 W and an argon pressure of 5 mTorr, metal titanium is used as the target material to uniformly sputter the surface of the ferroelectric dielectric layer 2, depositing a layer of metal titanium on the surface to form the pulse input electrode 1, and completing the preparation of the reconfigurable ferroelectric single-crystal transistor in-memory Boolean logic gate.

[0082] Example 3:

[0083] Hf 0.3 Zr 0.7 O2 material to make the ferroelectric dielectric layer 2, Si substrate to make the semiconductor layer 2, and metal copper as the material of the bottom electrode 1 and the top electrode 4. The specific preparation method is as follows:

[0084] Step one: etching the active region on the N-type lightly doped semiconductor Si ultra-thin channel layer 7.

[0085] Step two: depositing dielectric material on the ultra-thin channel layer 7 to form a dielectric layer 4, growing an electrode material on the dielectric layer 4, and etching to form a direct current input electrode 3;

[0086] In this step, a reaction sputtering process is used, a molecular pump or a cold pump is used to vacuum the reaction chamber until the vacuum pressure in the reaction chamber reaches 0.02 Torr, then under the condition that the sputtering power is 350W and the argon pressure is 5mTorr, metal copper is used as the target material to uniformly sputter the surface of the ultra-thin channel layer 7, and a layer of metal copper is deposited on the surface, thereby forming the direct current input electrode 3.

[0087] Step three: growing an electrode material on both ends of the active region by using a sputtering process, and stripping or etching to form a source electrode 5 and a drain electrode 6;

[0088] In this step, a reaction sputtering process is used, a molecular pump or a cold pump is used to vacuum the reaction chamber until the vacuum pressure in the reaction chamber reaches 0.02 Torr, then under the condition that the sputtering power is 350W and the argon pressure is 5mTorr, metal copper is used as the target material to uniformly sputter the surface of the ultra-thin channel layer 7, and a layer of metal copper is deposited on the surface, thereby forming the source electrode 5 and the drain electrode 6.

[0089] Step four: self-aligned growth of ferroelectric material to form a ferroelectric dielectric layer 2, growing an electrode material on the ferroelectric dielectric layer 2, etching to form a pulse input electrode 1, and completing the preparation of the reconfigurable ferroelectric single-crystal transistor in-memory Boolean logic gate.

[0090] In this step, an atomic layer deposition process is used, first ion water is used as an oxygen source, tetraethylmethylamino hafnium (TEMAHf) is used as a hafnium precursor source, and tetraethylmethylamino zirconium (TEMAZr) is used as a zirconium precursor source, and the temperature is raised to 300 degrees Celsius; then by adjusting the pulse ratio of the hafnium precursor source and the zirconium precursor source, a Hf 0.3 Zr 0.7 O2 ferroelectric material thin film is grown on the surface of the ultra-thin channel layer 7 to form the ferroelectric dielectric layer 2.

[0091] In this step, a reaction sputtering process is used, a molecular pump or a cold pump is used to vacuum the reaction chamber until the vacuum pressure in the reaction chamber reaches 0.02 Torr, then under the condition that the sputtering power is 350W and the argon pressure is 5mTorr, metal copper is used as the target material to uniformly sputter the surface of the ferroelectric dielectric layer 2, and a layer of metal copper is deposited on the surface to form the pulse input electrode 1, and the preparation of the reconfigurable ferroelectric single-crystal transistor in-memory Boolean logic gate is completed.

[0092] The reconfigurable ferroelectric single-crystal transistor in-memory Boolean logic gate can be used as a basic unit of post-moore era integrated circuits to realize the functions of operation, storage and in-memory calculation.

[0093] The present application is not limited to the above-described best mode, and anyone can derive other various forms of products under the inspiration of the present application, but regardless of any change in shape or structure, any technical solution having the same or similar to the present application falls within the scope of the present application.

Claims

1. A reconfigurable ferroelectric single-crystal transistor in-memory Boolean logic gate, comprising: The silicon substrate (9) is provided with a silicon dioxide layer (8), and the silicon dioxide layer (8) is provided with an ultra-thin channel layer (7) selected from intrinsic semiconductors or lightly doped semiconductors and having a thickness less than 200 nm; The ultra-thin channel layer (7) is provided with a ferroelectric dielectric layer (2), a dielectric layer (4), a source electrode (5) and a drain electrode (6), a direct current input electrode (3) is arranged between a lower portion of the ferroelectric dielectric layer (2) and an upper portion of the dielectric layer (4), and a pulse input electrode (1) is arranged on an upper portion of the ferroelectric dielectric layer (2); wherein the lower surfaces of the two side portions of the ferroelectric dielectric layer (2) are in direct contact with the ultra-thin channel layer (7), the middle portion is protruded upward, the dielectric layer (4) is arranged below the protruded portion and is in direct contact with the ultra-thin channel layer (7), and the direct current input electrode (3) is arranged above the dielectric layer (4) and is in direct contact with the dielectric layer (4); the source electrode (5) and the drain electrode (6) are arranged outside the two side portions of the ferroelectric dielectric layer (2) and are in direct contact with the ultra-thin channel layer (7); The high and low resistance states of the ultra-thin channel layer (7) represent the Boolean logic output of the single transistor; the pulse input electrode (1) and the direct current input electrode (3) respectively control the series resistance in the ultra-thin channel layer (7); and the polarization state of the ferroelectric dielectric layer (2) stores the information of the pulse input electrode (1), thereby continuously controlling the series resistance state after the pulse ends.

2. The reconfigurable ferroelectric single transistor in-memory Boolean logic gate according to claim 1, wherein, when the source electrode (5) is grounded and the drain electrode (6) is connected to a power supply voltage, the main carriers in the ultra-thin channel layer (7) are electrons, the electron aggregation represents the low resistance state of the channel series resistance, and the hole aggregation represents the high resistance state of the channel series resistance, and the reconfigurable ferroelectric single transistor works in an in-memory logic AND gate mode; in the AND gate mode: a positive pulse is applied to the pulse input electrode (1), most of the polarization charges in the ferroelectric dielectric layer (2) are reversed, the polarization state is changed, the electrons in the ultra-thin channel layer (7) respond to the polarization charges inside the ferroelectric dielectric layer (2), and the resistance of the corresponding region of the control channel is in a low resistance state; at the same time, a positive voltage is applied to the direct current input electrode (3) to attract the electrons in the ultra-thin channel layer (7) to gather, and the resistance of the corresponding region of the control channel is in a low resistance state; when the series resistances in the ultra-thin channel layer (7) controlled by the pulse input electrode (1) and the direct current input electrode (3) are both in a low resistance state, the reconfigurable ferroelectric single transistor in-memory logic gate has a logic state of "1" when the pulse input electrode (1) and the direct current input electrode (3) are both positively input. When the source electrode (5) is connected to the power supply voltage and the drain electrode (6) is grounded, the main carrier in the ultra-thin channel layer (7) is a hole, and the electron aggregation is represented as a high resistance state of the channel series resistance, and the hole aggregation is represented as a low resistance state of the channel series resistance, and the reconfigurable ferroelectric single crystal transistor works in the "or non" mode of in-memory logic; in the "or non" mode: a negative pulse is applied to the pulse input end electrode (1), most of the polarization charges in the ferroelectric dielectric layer (2) are reversed, the polarization state is changed, the holes in the ultra-thin channel layer (7) respond to the polarization charges inside the ferroelectric dielectric layer (2), and the resistance of the corresponding region of the control channel is in a low resistance state; at the same time, a negative voltage is applied to the direct current input end electrode (3), the holes in the ultra-thin channel layer (7) are attracted to gather, the resistance of the corresponding region of the control channel is in a low resistance state, and when the series resistance of the ultra-thin channel layer (7) regulated by the pulse input end electrode (1) and the direct current input end electrode (3) is in a low resistance state, the reconfigurable ferroelectric single crystal transistor in-memory logic gate is in a "1" logic state when the pulse input end electrode (1) and the direct current input end electrode (3) are both negative input.

3. The reconfigurable ferroelectric single transistor in-memory Boolean logic gate of claim 1, wherein, The material of the pulse input electrode (1), the direct current input electrode (3), the source electrode (5) and the drain electrode (6) is any one of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide and tantalum silicide; the material of the dielectric layer (4) is HfO2, SiO2, SiON, Si3N4, TiO2, Hf 0.5 Zr 0.5 O2, Hf 0.3 Zr 0.7 O2, HYO, HZO, HSO, HAO, BFO, PZT, BST, ZrO2, Al2O3, ZnSnO3.

4. The reconfigurable ferroelectric single transistor in-memory Boolean logic gate of claim 1, wherein, The material of the ferroelectric dielectric layer (2) adopts Hf 0.5 Zr 0.5 O2, Hf 0.3 Zr 0.7 O2, HYO, HZO, HSO, HAO, BFO, PZT, BST, ZrO2, Al2O3, ZnSnO3 5. The reconfigurable ferroelectric single transistor in-memory Boolean logic gate of claim 1, wherein, The ultra-thin channel layer (7) is any one of Si, Ge, SiGe, GaN, GaAs and SiC.

6. A method for preparing the reconfigurable ferroelectric single crystal transistor in-memory Boolean logic gate of claim 1, characterized in that it comprises the following steps: Step 1), preparing a silicon dioxide layer (8) on a silicon substrate (9), preparing an ultra-thin channel layer (7) on the silicon dioxide layer (8), and etching an active region on the ultra-thin channel layer (7); Step 2), depositing a dielectric material on the ultra-thin channel layer (7) to form a dielectric layer (4) by using a deposition process, and growing an electrode material on the dielectric layer (4) by using a sputtering process or a deposition process, and etching to form a direct current input end electrode (3); Step 3), growing an electrode material on both ends of the active region by using a sputtering process or a deposition process, and stripping or etching to form a source electrode (5) and a drain electrode (6); Step 4), growing a ferroelectric material to form a ferroelectric dielectric layer (2) by using a deposition process, growing an electrode material on the ferroelectric dielectric layer (2) by using a sputtering process or a deposition process, and etching to form a pulse input end electrode (1), and completing the preparation of the reconfigurable ferroelectric single crystal transistor in-memory Boolean logic gate.

7. The method of claim 6, wherein the reconfigurable ferroelectric single-crystal transistor in-memory Boolean logic gate is prepared by, The pulse input end electrode in step 4) is formed in a self-aligned manner in the gap position between the direct current input end electrode (3) and the source electrode (5) and the drain electrode (6) formed in steps 2) and 3).

8. The method of claim 7, wherein the reconfigurable ferroelectric single-crystal transistor in-memory Boolean logic gate is prepared by, The pulse input end electrode (1) is formed by a self-aligned process.

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