A single-bit in-memory computing device

Abstract

The present invention relates to a single-bit in-memory computing device. In this device, a first array module and a second array module each include: four SRAM memory cell arrays, four ADC modules, and an adder module. The SRAM memory cell arrays are 64 rows by 32 columns. Each SRAM memory cell array is connected to an ADC module. The ADC module quantizes the calculation results of each 64 rows in the corresponding SRAM memory cell array. Each of the four ADC modules is connected to the adder module. The adder module sums the quantized results of the four ADC modules. Word lines WLL_L and WLR_L drive each column of the SRAM memory cell array in the first array module; word lines WLL_R and WLR_R drive each column of the SRAM memory cell array in the second array module. This invention can improve the readout accuracy of single-bit in-memory computing.

Description

Technical Field

[0001] The present invention relates to the field of in-memory computing, and in particular to a single-bit in-memory computing device. Background Art

[0002] Deep convolutional neural networks (DCNNs) continue to demonstrate improvements in inference accuracy, and deep learning is shifting to edge computing. This development is driving work on low-resource machine learning algorithms and their acceleration hardware. The most common operation in DCNNs is multiply and accumulate (MAC), which dominates power and latency. MAC operations are highly regular and parallel, making them well-suited for hardware acceleration. However, the amount of memory access severely limits the energy efficiency of traditional digital accelerators. Therefore, compute-in-memory (CIM) is becoming increasingly attractive for DCNN acceleration.

[0003] Current in-memory computing designs can be divided into SRAM-based designs and designs based on new non-volatile memories, based on the storage medium. While SRAM-based designs are mature, they also present certain challenges. When external inputs drive word lines, if too many columns of memory cells are mounted on the word lines, the pulse width of the signal will decay during long-distance transmission. In in-memory computing arrays, the calculation process requires the word line signal to have a fixed-width pulse. Pulse width decay can lead to inconsistent calculation results across different columns.

[0004] To achieve high-throughput calculations, the size of existing in-memory computing arrays is basically 256 rows by 64 columns. When reading column calculations, it is necessary to multiply and add 256 inputs and 256 weights in each column. The final result is difficult to quantify very finely, and the output result accuracy needs to be reduced to a certain extent.

[0005] Therefore, there is an urgent need to provide a single-bit in-memory calculation device that can improve the single-bit in-memory calculation readout accuracy. Summary of the Invention

[0006] The purpose of the present invention is to provide a new single-bit in-memory calculation device, which can improve the single-bit in-memory calculation readout accuracy.

[0007] To achieve the above object, the present invention provides the following solutions:

[0008] A single-bit in-memory computing device comprises: a first array module, a decoding and input driving module, and a second array module;

[0009] The first array module and the second array module each include: 4 SRAM memory cell arrays, 4 analog-to-digital converter (ADC) modules, and 1 adder module; the SRAM memory cell array is 64 rows by 32 columns;

[0010] Each of the SRAM storage cell arrays is connected to the corresponding analog-to-digital converter (ADC) module; the analog-to-digital converter (ADC) module is used to quantize the calculation results of each column and 64 rows in the corresponding SRAM storage cell array to determine the quantization result;

[0011] The four analog-to-digital converter (ADC) modules are all connected to the adder module; the adder module is used to add the quantization results of the four analog-to-digital converter (ADC) modules;

[0012] The decoding and input driving module includes: word line WLL_L, word line WLR_L, word line WLL_R and word line WLR_R; the word line WLL_L and the word line WLR_L are used to drive each column of the SRAM memory cell array of the first array module; the word line WLL_R and the word line WLR_R are used to drive each column of the SRAM memory cell array of the second array module.

[0013] Optionally, the number of bits of the quantization result is 4 bits.

[0014] Optionally, the number of bits of the addition result of the adder module is 6 bits.

[0015] Optionally, the number of addition results of the adder module is 32.

[0016] Optionally, the word line WLL_L and the word line WLR_L do not operate at the same time; the word line WLL_R and the word line WLR_R do not operate at the same time.

[0017] Optionally, the SRAM memory cell array includes: 64×32 6TSRAM memory cells.

[0018] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0019] The present invention provides a single-bit in-memory computing device, wherein both the first and second array modules include four SRAM memory cell arrays, using four × two 64-row × 32-column small arrays to implement the functionality of a large 256-row × 64-column array for single-bit in-memory computing. Each portion of each array module quantizes a result, and the four results are summed to reduce the difficulty of quantizing the multiplication result of each column's 256 row weights and 256 inputs, thereby improving the accuracy of the output result. Each row of wordline pulses drives 32 columns separately, reducing the difficulty of driving the wordline and reducing pulse width attenuation during the wordline driving process. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 This is a schematic diagram of the structure of a single-bit in-memory computing device provided by the present invention. DETAILED DESCRIPTION

[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0023] The object of the present invention is to provide a single-bit in-memory calculation device capable of improving the single-bit in-memory calculation readout accuracy.

[0024] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] Figure 1 This is a schematic diagram of the structure of a single-bit in-memory computing device provided by the present invention, as shown in FIG. Figure 1 As shown, a single-bit in-memory computing device provided by the present invention includes: a first array module 1 , a decoding and input driving module 2 and a second array module 3 .

[0026] Both the first array module 1 and the second array module 3 include: four SRAM memory cell arrays, four analog-to-digital converter (ADC) modules, and one adder module. The SRAM memory cell arrays have 64 rows by 32 columns. The ADC module includes 32 ADCs, corresponding to the 32 columns of the arrays. The adder module also includes 32 adders.

[0027] Each SRAM memory cell array is connected to a corresponding analog-to-digital converter (ADC) module. The ADC module is configured to quantize the calculation results for each column and 64 rows of the corresponding SRAM memory cell array to determine a quantized result. Specifically, the 256-row by 64-column array is divided into eight blocks, each consisting of 64 rows by 32 columns. Each block is quantized by an ADC. Therefore, only one quantized result is needed for each column and 64 rows, resulting in a fourfold increase in output accuracy.

[0028] The four analog-to-digital converter (ADC) modules are all connected to the adder module; the adder module is used to add the quantization results of the four analog-to-digital converter (ADC) modules.

[0029] The decoding and input driving module 2 includes: word line WLL_L, word line WLR_L, word line WLL_R and word line WLR_R; the word line WLL_L and the word line WLR_L are used to drive each column of the SRAM memory cell array of the first array module 1; the word line WLL_R and the word line WLR_R are used to drive each column of the SRAM memory cell array of the second array module 3.

[0030] The analog-to-digital converter (ADC) module quantizes the calculation results of each column and 64 rows, producing a 4-bit result ADC_i[3:0]. The adder module then adds the results ADC_0[3:0], ADC_1[3:0], ADC_2[3:0], and ADC_3[3:0] from the four analog-to-digital converter (ADC) modules, ultimately outputting a 6-bit result OUT[5:0]. The entire array consists of 64 columns, and the final output is 64 6-bit results OUT[5:0].

[0031] In order to further reduce the driving difficulty and avoid word line pulse attenuation, the word line WLL_L and the word line WLR_L do not work at the same time; the word line WLL_R and the word line WLR_R do not work at the same time, and only one of the word lines is opened at a time during the calculation process.

[0032] As a specific embodiment, the SRAM memory cell array includes: 64×32 6TSRAM memory cells.

[0033] The present invention uses eight small arrays of 64 rows by 32 columns to implement the functionality of a large 256-row by 64-column array for single-bit in-memory computation. This reduces the difficulty of quantizing the multiplication result of each column's 256 row weights by 256 inputs, and improves the accuracy of the output result. Each row of wordline pulses drives 32 columns separately, reducing the difficulty of driving the wordline and minimizing pulse width decay during the wordline driving process.

[0034] As another specific embodiment, the specific workflow of the present invention is as follows:

[0035] 256 1-bit input signals are sent to the decoding and input driver module, which drives the 256-bit input through word lines (WLL_L, WLR_L, WLL_R, WLR_R) to each of the eight subarrays. The high and low levels of the word lines enable and disable the array's memory cells to perform multiplication operations. The result of the multiplication is accumulated as a voltage on the bit line BL. Finally, the multiplication and accumulation results on the bit lines are quantized by the ADC and sent to the adder for addition.

[0036] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0037] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only intended to help understand the method and core concept of the present invention. At the same time, those skilled in the art will find that the specific implementation methods and application scopes may vary based on the concept of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims

1. A single-bit in-memory computing device, characterized in that: include: a first array module, a decoding and input driving module, and a second array module; The first array module and the second array module each include: 4 SRAM memory cell arrays, 4 analog-to-digital converter (ADC) modules, and 1 adder module; the SRAM memory cell array is 64 rows by 32 columns; Each of the SRAM storage cell arrays is connected to the corresponding analog-to-digital converter (ADC) module; the analog-to-digital converter (ADC) module is used to quantize the calculation results of each column and 64 rows in the corresponding SRAM storage cell array to determine the quantization result; The four analog-to-digital converter (ADC) modules are all connected to the adder module; the adder module is used to add the quantization results of the four analog-to-digital converter (ADC) modules; The decoding and input driving module includes: a word line WLL_L, a word line WLR_L, a word line WLL_R and a word line WLR_R; the word line WLL_L and the word line WLR_L are used to drive each column of the SRAM memory cell array of the first array module; the word line WLL_R and the word line WLR_R are used to drive each column of the SRAM memory cell array of the second array module; The number of digits of the quantization result is 4; The number of bits of the summation result of the adder module is 6 bits.

2. A single-bit in-memory computing device according to claim 1, characterized in that: The number of summation results of the adder module is 32.

3. The single-bit in-memory computing device according to claim 1, wherein: The word line WLL_L and the word line WLR_L do not operate at the same time; the word line WLL_R and the word line WLR_R do not operate at the same time.

4. The single-bit in-memory computing device according to claim 1, wherein: The SRAM memory cell array includes: 64×32 6T SRAM memory cells.

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