Erasing method for 3D NAND flash memory

Abstract

Embodiments of an erase method for a three-dimensional (3D) memory device are disclosed. The 3D memory device includes a plurality of levels vertically stacked over a substrate, where each level includes a plurality of memory cells. The erase method includes checking a state of the plurality of memory cells of an erase inhibit level and preparing the erase inhibit level according to the state of the plurality of memory cells. The erase method also includes applying an erase voltage at an array common source, applying a hold-release voltage on unselected word lines of the erase inhibit level, and applying a low voltage on selected word lines of a target level.

Description

[0001] This invention is a divisional application of the patent filed on August 27, 2020, with application number 202080002138.9 and invention title "Erasing Method for 3D NAND Flash Memory". Technical Field

[0002] This disclosure generally relates to the field of semiconductor technology, and more specifically, to methods for erasing three-dimensional (3D) memories. Background Technology

[0003] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase memory density, scaling planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations inherent in planar memory cells.

[0004] In 3D NAND flash memory, multiple layers of memory cells can be stacked vertically to significantly increase the storage density per unit area. To further increase storage density, multiple levels can be stacked vertically, with each level containing numerous vertically stacked memory cells. For efficient reading, writing, and erasing in multi-level 3D NAND flash memory, each level can be processed as a separate memory block; that is, each level can be erased independently of other levels. However, the erase operation of a selected level may be affected by adjacent levels connected in series. For example, when erasing the top level, the charge carriers used for the erase operation may not be able to migrate to the selected level based on data stored in other adjacent levels. Therefore, the selected level may have erase failure bits due to the influence from adjacent levels. Thus, there is a need for a method to erase selected levels in 3D NAND memory such that each memory cell in the selected level can be accurately and efficiently reset to the erase state. Summary of the Invention

[0005] This disclosure describes an implementation of a method for erasure operations in a three-dimensional (3D) storage device having multiple levels.

[0006] One aspect of this disclosure provides an erasure method for a three-dimensional (3D) memory device comprising multiple layers vertically stacked on a substrate, wherein each layer comprises multiple memory cells. The erasure method includes checking the state of the multiple memory cells in an erase suppression layer and preparing an erase suppression layer based on the state of the multiple memory cells. The erasure method also includes applying an erase voltage at an array common source or array cell well body, applying a hold-release voltage on an unselected word line of the erase suppression layer, and applying a low voltage on a selected word line of a target layer.

[0007] In some implementations, preparing the erase suppression level includes applying a first preparation voltage to an unselected word line of the erase suppression level when a plurality of memory cells of the erase suppression level are in a programming state.

[0008] In some implementations, applying the first preparation voltage includes applying a voltage between approximately 0V and approximately 1V.

[0009] In some implementations, applying the first preparation voltage includes applying 0V.

[0010] In some implementations, preparing the erase suppression level includes applying a second preparation voltage to an unselected word line of the erase suppression level when a plurality of memory cells of the erase suppression level are in an erase state. The second preparation voltage is greater than a first preparation voltage.

[0011] In some implementations, applying the second preparation voltage includes applying a voltage between approximately 1V and approximately 7V.

[0012] In some embodiments, preparing the erase suppression level includes: applying a first preparation voltage to the first subset of unselected word lines of the erase suppression level when the first subset of a plurality of memory cells having an unselected word line is in a programming state, and applying a second preparation voltage to the second subset of unselected word lines of the erase suppression level when the second subset of a plurality of memory cells having an unselected word line is in an erasure state. The second preparation voltage is greater than the first preparation voltage.

[0013] In some implementations, a second subset of the plurality of memory cells includes at least two adjacent memory cells.

[0014] In some implementations, preparing the erase suppression level includes applying a first preparation voltage and a second preparation voltage greater than the first preparation voltage to an unselected word line of the erase suppression level when a first subset of the plurality of memory cells in the erase suppression level is in a programming state and a second subset of the plurality of memory cells in the erase suppression level is in an erasure state.

[0015] In some implementations, applying a low voltage includes applying a voltage in the range of approximately 0V and approximately 1V.

[0016] In some implementations, applying a low voltage includes applying a voltage of 0V.

[0017] In some implementations, applying a hold-release voltage includes applying a voltage of 0V and subsequently removing the 0V voltage and any external bias.

[0018] In some implementations, applying the erase voltage includes applying a voltage in the range of approximately 15V to approximately 25V.

[0019] In some implementations, applying the erase voltage includes applying approximately 20V.

[0020] In some implementations, the erasure method further includes applying an erasure voltage at the bit line of the target level.

[0021] In some implementations, the erasure method further includes applying a hold-release voltage to the selected word line of the target level before applying a low voltage to the selected word line of the target level.

[0022] In some implementations, the erasure method further includes applying a hold-release voltage to unselected word lines of the bottom layer and applying a low voltage to selected word lines of the top layer. The top layer is vertically stacked on top of the bottom layer on the substrate.

[0023] In some embodiments, the erasure method further includes applying a hold-release voltage on unselected word lines of the top and bottom layers, and applying a low voltage on selected word lines of the intermediate layers. The top layers are vertically stacked on the intermediate layers, and the intermediate layers are vertically stacked on the bottom layers above the substrate. In some embodiments, the erasure method further includes applying an erasure voltage at the bit lines of the top layers.

[0024] Another aspect of this disclosure provides a three-dimensional (3D) memory device having multiple layers vertically stacked on a substrate. Each layer includes a film stack of alternating conductive and dielectric layers, and multiple memory strings penetrating the film stack, wherein each memory string includes multiple memory cells. The 3D memory device also includes conductive plugs disposed between adjacent layers, electrically connecting the multiple memory strings between adjacent layers. The multiple layers of the 3D memory device include a target layer and an erase suppression layer. The 3D memory device is configured to erase the target layer by: checking the state of multiple memory cells in the erase suppression layer; preparing the erase suppression layer based on the state of the multiple memory cells in the erase suppression layer; applying an erase voltage at an array common source or array cell well body; applying a hold-release voltage on an unselected word line of the erase suppression layer; and applying a low voltage on a selected word line of the target layer.

[0025] Other aspects of this disclosure may be understood by those skilled in the art based on the description, claims, and drawings of this disclosure. Attached Figure Description

[0026] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0027] Figure 1 A schematic top-down view of an exemplary three-dimensional (3D) memory die according to some embodiments of this disclosure is shown.

[0028] Figure 2 A schematic top-down view showing a region of a 3D memory die according to some embodiments of this disclosure.

[0029] Figure 3 A perspective view showing a portion of an exemplary 3D memory array structure according to some embodiments of the present disclosure.

[0030] Figure 4 A cross-sectional view of a 3D storage device having multiple layers is shown according to some embodiments of the present disclosure.

[0031] Figure 5 A schematic circuit diagram of a 3D memory device with multiple layers according to some embodiments of the present disclosure is shown.

[0032] Figure 6-8 Waveforms of erase operations for a 3D memory device with multiple layers according to some embodiments of the present disclosure are shown.

[0033] Figure 9 A flowchart illustrating an erasure method for a 3D storage device having multiple layers, according to some embodiments of the present disclosure.

[0034] Figure 10-11 Waveforms are shown for erasure operations of 3D memory devices having multiple levels, according to some embodiments of the present disclosure.

[0035] The features and advantages of this disclosure will become more apparent from the following detailed description when understood in conjunction with the accompanying drawings, wherein similar reference numerals consistently identify corresponding elements. In the drawings, similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. The first appearance of an element in the drawings is indicated by the leftmost digit in the corresponding reference numerals.

[0036] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0037] While specific configurations and arrangements have been discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will also be apparent to those skilled in the art that this disclosure can be used in a variety of other applications.

[0038] Note that references to "one embodiment," "implementation," "example embodiment," "some embodiments," etc., in this specification indicate that the described embodiment may include specific features, structures, or characteristics, but each embodiment may not necessarily include specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, it will, to the knowledge of those skilled in the art, affect such feature, structure, or characteristic in conjunction with other embodiments (whether explicitly described or not).

[0039] Generally, terms can be understood at least in part from their usage in context. For example, at least in part from context, the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, at least in part from context, terms such as “a,” “an,” and “the” can again be understood to convey either a singular or a plural usage. Furthermore, again at least in part from context, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and alternatively allows for the existence of additional factors that are not necessarily explicitly described.

[0040] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” with an intermediate feature or layer between them, and that “above” or “on top of” means not only “on” or “on top of” but also includes “on” or “on top of” without an intermediate feature or layer between them (i.e., directly on).

[0041] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein for ease of description to describe the relationship of an element or feature to other elements or features as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to also include different orientations of the device during use or processing. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0042] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is generally where semiconductor devices are formed, and therefore the semiconductor devices are formed on the top side of the substrate, unless otherwise specified. The bottom surface is opposite to the top surface, and therefore the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. Material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials (such as silicon, germanium, gallium arsenide, indium phosphide, etc.). Alternatively, the substrate may be made of a non-conductive material (such as glass, plastic, or sapphire wafer).

[0043] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire underlayer or overlay structure, or may have a width smaller than the width of the underlayer or overlay structure. Furthermore, a layer may be a region of a homogeneous or dissimilar continuous structure having a thickness smaller than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes thereon. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0044] In this disclosure, for ease of description, the term "row" is used to refer to elements of substantially the same height along a vertical direction. For example, word lines and the underlying gate dielectric layer may be referred to as a "row," word lines and the underlying insulating layer may be referred to together as a "row," and word lines of substantially the same height may be referred to as a "row of word lines" or similar terms.

[0045] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter of a component or process step set during the design phase of a product or process, together with a range of values ​​higher and / or lower than the expected value. The range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" indicates a given quantity value that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "approximately" may indicate a given quantity value that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0046] In this disclosure, the terms “horizontal / horizontally / laterally” mean a lateral surface that is nominally parallel to the substrate, and the terms “vertical” or “perpendicularly” mean a lateral surface that is nominally perpendicular to the substrate.

[0047] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a direction perpendicular to the substrate.

[0048] Figure 1 This illustration shows a top-down view of an exemplary three-dimensional (3D) memory device 100 according to some embodiments of this disclosure. The 3D memory device 100 may be any portion of a memory chip (package), memory die, or memory die, and may include one or more memory planes 101, each memory plane 101 including a plurality of memory blocks 103. Same and simultaneous operations may occur at each memory plane 101. A memory block 103, which may be megabytes (MB) in size, is the smallest size for performing an erase operation. Figure 1 The exemplary 3D memory device 100 shown includes four memory planes 101, and each memory plane 101 includes six memory blocks 103. Each memory block 103 may include multiple memory cells, wherein each memory cell can be addressed via interconnects (e.g., bit lines and word lines). The bit lines and word lines may be arranged vertically (e.g., in rows and columns, respectively), forming an array of metal lines. The orientation of the bit lines and word lines is... Figure 1 The memory blocks 103 are designated as "BL" and "WL". In this disclosure, memory block 103 is also referred to as a "memory array" or "array". A memory array is a core region within a memory device that performs storage functions.

[0049] The 3D memory device 100 also includes a peripheral region 105 (the region surrounding the memory plane 101). The peripheral region 105 contains a variety of digital, analog, and / or mixed-signal circuitry to support the functionality of the memory array (e.g., page buffers, row and column decoders, and sense amplifiers). The peripheral circuitry uses active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art.

[0050] Note that in Figure 1 The arrangement of memory planes 101 in the 3D storage device 100 and the arrangement of memory blocks 103 in each memory plane 101 shown are for illustrative purposes only and do not limit the scope of this disclosure.

[0051] refer to Figure 2 According to some embodiments of this disclosure, it is shown that in Figure 1 The image shows an enlarged top-down view of region 108. Region 108 of the 3D storage device 100 may include a stepped region 210 and a channel structure region 211. The channel structure region 211 may include an array of memory strings 212, each memory string 212 including a plurality of stacked memory cells. The stepped region 210 may include a stepped structure and an array of contact structures 214 formed on the stepped structure. In some embodiments, a plurality of slit structures 216 extending in the WL direction across the channel structure region 211 and the stepped region 210 may divide the memory block into a plurality of memory fingers 218. At least some of the slit structures 216 may function as common source contacts (e.g., array common source) for the array of memory strings 212 in the channel structure region 211. A top select gate notch 220 may be arranged, for example, in the middle of each memory finger 218 to divide the top select gate (TSG) of the memory finger 218 into two portions, thereby dividing the memory finger into two memory clades 224, wherein memory cells sharing the same word line in the memory clades 224 form programmable (read / write) memory pages. While erase operations on 3D NAND memory can be performed at the memory block level, read and write operations can be performed at the memory page level. Memory pages can be kilobytes (KB) in size. In some embodiments, region 108 also includes a virtual memory string 222 for process variation control during manufacturing and / or for additional mechanical support.

[0052] Figure 3This diagram shows a perspective view of a portion of an exemplary three-dimensional (3D) memory array structure 300 according to some embodiments of the present disclosure. The memory array structure 300 includes a substrate 330, an insulating film 331 over the substrate 330, a row of lower select gates (LSGs) 332 over the insulating film 331, and multiple rows of control gates 333 (also referred to as “word lines (WL)”) stacked on top of the LSGs 332 to form alternating conductive and dielectric layers. For clarity, in Figure 3 The dielectric layer adjacent to the multiple rows of control gates is not shown.

[0053] Each row of control gates is separated by slit structures 216-1 and 216-2 passing through the film stack 335. The memory array structure 300 also includes a row of top select gates (TSGs) 334 above the stack of control gates 333. The stack of TSGs 334, control gates 333, and LSGs 332 are also referred to as “gate electrodes”. The memory array structure 300 also includes doped source line regions 344 in the portions of memory strings 212 and substrate 330 between adjacent LSGs 332. Each memory string 212 includes a channel via 336 extending through the film stack 335 of insulating film 331 and alternating conductive and dielectric layers. The memory string 212 also includes a memory film 337 on the sidewall of the channel via 336, a channel layer 338 above the memory film 337, and a core fill film 339 surrounded by the channel layer 338. Memory cells 340 may be formed at the intersection of the control gates 333 and the memory strings 212. A portion of the channel layer 338 beneath the control gate 333 is also referred to as the channel of the memory cell 340. The memory array structure 300 also includes multiple bit lines (BLs) 341 connected to the memory string 212 over the TSG 334. The memory array structure 300 also includes multiple metal interconnects 343 connected to the gate electrode via multiple contact structures 214. The edges of the film stack 335 are configured in a stepped shape to allow electrical connections to each row of gate electrodes.

[0054] exist Figure 3 For illustrative purposes, three rows of control gates 333-1, 333-2, and 333-3 are shown alongside a row of TSGs 334 and a row of LSGs 332. In this example, each memory string 212 may include three memory cells 340-1, 340-2, and 340-3 corresponding to control gates 333-1, 333-2, and 333-3, respectively. In some embodiments, the number of control gates and the number of memory cells may be more than three to increase storage capacity. The memory array structure 300 may also include other structures, such as TSG cutouts, common source contacts (i.e., array common source), and virtual memory strings. For simplicity, in Figure 3 These structures are not shown in the document.

[0055] Figure 4 A cross-sectional view (along the X direction) of a 3D storage device 400 having multiple layers according to some embodiments of the present disclosure is shown. Figure 4 In the example, the 3D memory device 400 has two layers: a bottom layer 450 and a top layer 452 stacked vertically on top of the bottom layer 450. The bottom layer 450 and the top layer 452 are disposed on a substrate (e.g., substrate 330). The substrate 330 can provide a platform for the 3D memory device 400, which is formed on the front (e.g., top) surface 330f of the substrate 330. Furthermore, subsequent structures are formed in a vertical direction (e.g., orthogonal to the front surface of the substrate 330). Figure 4 In this context, the X and Y directions lie along planes parallel to the front and rear surfaces of the substrate 330, while the Z direction lies orthogonal to the front and rear surfaces of the substrate 330. Here, the X and Y directions are parallel to... Figure 1-3 The corresponding word line (WL) and bit line (BL) directions are shown.

[0056] In some embodiments, substrate 330 may provide a platform for forming subsequent structures. In some embodiments, substrate 330 may be any suitable semiconductor substrate having any suitable semiconductor material, such as single-crystal, polycrystalline, or monocrystalline semiconductor. For example, substrate 330 may include silicon, silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. In some embodiments, substrate 330 may include a layer of semiconductor material formed on an operating wafer, such as glass, plastic, or another semiconductor substrate.

[0057] The front surface 330f of substrate 330 is also referred to herein as the “main surface” or “top surface” of the substrate. Layers of material may be arranged on the front surface 330f of substrate 330. The “uppermost” or “top” layer is the layer furthest from or further from the front surface 330f of the substrate. The “lowermost” or “bottom” layer is the layer closest to or further from the front surface 330f of the substrate.

[0058] In some embodiments, the bottom layer 450 and the top layer 452 respectively include a bottom membrane stack 335-1 and a top membrane stack 335-2. The bottom membrane stack 335-1 and the top membrane stack 335-2 may be similar to... Figure 3The film stack 335 includes a plurality of conductor layers 454 and dielectric layers 456. The conductor layers 454 and dielectric layers 456 in the bottom film stack 335-1 and the top film stack 335-2 alternate in the vertical direction. In other words, each conductor layer 454 may be sandwiched between two dielectric layers 456 on both sides, except for the layers at the bottom of the bottom film stack 335-1 and the top of the top film stack 335-2. The conductor layers 454 may each have the same thickness or different thicknesses. Similarly, the dielectric layers 456 may each have the same thickness or different thicknesses. In some embodiments, the bottom film stack 335-1 and the top film stack 335-2 include different numbers of conductor layers 454 and / or dielectric layers 456, and / or include different materials and / or thicknesses. Conductor layer 454 may include a conductor material, such as W, Co, Cu, Al, Ti, Ta, TiN, TaN, Ni, doped silicon, silicides (e.g., NiSix, WSix, CoSix, TiSix), or any combination thereof. Dielectric layer 456 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0059] In some implementations, bottom layer 450 and top layer 452 may further include memory cells of 3D NAND memory (e.g., Figure 3 The memory cells 340 in the memory (e.g., memory cells 340) can be stacked vertically as a memory string (e.g., memory cells 340). Figure 3 (Memory string 212 in the memory). For example Figure 4 As shown, the memory string 212 extends through the top film stack 335-2 and the bottom film stack 335-1, and includes a bottom vertical structure 212-1 and a top vertical structure 212-2. Each memory string 212 may include a channel layer 338 and a memory film 337 (similar to...). Figure 3 (Those mentioned above). In some embodiments, the channel layer 338 comprises silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some embodiments, the memory film 337 is a composite layer comprising a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. Each memory string 212 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the channel layer 338, tunneling layer, storage layer, and barrier layer are arranged in this order along a direction from the center of the pillar toward the outer surface. The tunneling layer may comprise silicon oxide, silicon nitride, or any combination thereof. The barrier layer may comprise silicon oxide, silicon nitride, a high dielectric constant (high k) dielectric, or any combination thereof. The storage layer may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the memory film 337 comprises an (ONO) dielectric (e.g., a tunneling layer comprising silicon oxide, a storage layer comprising silicon nitride, and a barrier layer comprising silicon oxide).

[0060] In some embodiments, the conductor layer 454 in the bottom film stack 335-1 and the top film stack 335-2 may serve as the control gate of the memory cell 340 (e.g., Figure 3 (Control gate 333 in the middle). For example Figure 4 As shown, memory string 212 may include a lower select gate 332 (e.g., a source select gate) at the lower end (i.e., the source terminal) of memory string 212 in bottom layer 450. Memory string 212 may also include a top select gate 334 (e.g., a drain select gate) at the upper end (i.e., the drain terminal) of memory string 212 in top layer 452. As used herein, the “upper end” of a component (e.g., memory string 212) is the end that is more vertically away from substrate 330, and the “lower end” of a component (e.g., memory string 212) is the end that is more vertically closer to substrate 330. Figure 4 As shown, for each memory string 212, the drain select gate 334 may be above the source select gate 332. In some embodiments, the lower select gate 332 and the top select gate 334 comprise conductive materials such as W, Co, Cu, Al, doped silicon, silicide, or any combination thereof.

[0061] In some embodiments, the 3D memory device 400 includes an epitaxial layer 458 on the lower end of the channel layer 338 of the memory string 212 in the bottom layer 450. The epitaxial layer 458 may comprise a semiconductor material, such as silicon. The epitaxial layer 458 may be epitaxially grown from the substrate 330. For each memory string 212, the epitaxial layer 458 is referred to herein as an “epitaxy plug”. The epitaxial plug 458 may contact the channel layer 338 and the array cell well body 345 in the substrate 330. The epitaxial plug 458 may function as a channel for the lower select gate 332 at the lower end of the memory string 212. In some embodiments, the array cell well body 345 may be p-type doped, while the doped source line region 344 may be n-type doped.

[0062] In some embodiments, the 3D memory device 400 includes an insulating layer 462 in both the top layer 452 and the bottom layer 450. The insulating layer 462 surrounds the memory string 212 and provides isolation between adjacent memory strings 212. The insulating layer 462 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide (e.g., F-, C-, N-, or H-doped silicon oxide), tetraethoxysilane (TEOS), polyimide, spin-coated glass (SOG), low-k dielectric materials such as porous SiCOH, silsesquioxane (SSQ), or any combination thereof.

[0063] In some embodiments, the top vertical structure 212-2 of the memory string 212 in the top layer 452 may be substantially aligned with the bottom vertical structure 212-1 in the bottom layer 450. In some embodiments, each memory string 212 includes a conductive plug 460 between the top vertical structure 212-2 and the bottom vertical structure 212-1. The conductive plug 460 provides an electrical connection between the channel layer 338 located in the bottom vertical structure 212-1 and the channel layer 338 located in the top vertical structure 212-2, such that the top vertical structure 212-2 and the bottom vertical structure 212-1 can form a memory string 212 for a two-layer 3D memory device 400, wherein the memory string 212 provides similar memory functionality as a memory string 212 in a 3D memory device having a single layer. In some embodiments, the conductive plug 460 comprises polysilicon.

[0064] According to some embodiments, the 3D memory device 400 further includes a conductive recess 461 on the top portion of the memory string 212 in the top layer 452. In some embodiments, the conductive recess 461 comprises polysilicon.

[0065] In some embodiments, film stacks 335-1 and 335-2 each include a stepped structure, wherein each of the conductive layers 454 terminates at a different length in the horizontal "X" direction. The stepped structure allows for electrical connections between word lines and conductive layers 454.

[0066] In some embodiments, the 3D memory device 400 includes an array common source (ACS) 464 that penetrates vertically through the top layer 452 and the bottom layer 450 into the substrate 330. The ACS 464 can be electrically connected to the doped source line region 344. Thus, if the lower select gate 332 is turned on, the ACS 464 can be electrically connected to the lower end (i.e., the source terminal) of the memory string 212.

[0067] In some embodiments, the ACS 464 includes a conductive core, which may be a metal or metal alloy, such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof. (Shown for illustrative purposes) Figure 4 The arrangement of the array common source 464. In some embodiments, the ACS 464 may be along the X direction (parallel to...) Figure 1-3 (The word line shown extends). In some embodiments, the ACS464 may be formed on the rear side of the substrate 330 opposite the front surface.

[0068] 3D storage device 400 may further include: bit line contacts formed at the top (i.e., the drain terminal) of memory string 212 in top level 452 (not in Figure 4 (As shown in the diagram) to provide separate access to the channel layer 338 of the memory string 212 in the top layer 452 and the bottom layer 450. Conductive lines and bit line contacts connected to the conductive layer 454 form the word lines and bit lines of the 3D memory device 400, respectively. Generally, the word lines and bit lines are placed perpendicular to each other (e.g., in rows and columns, respectively) to form an “array” of memory.

[0069] Note that this document describes a 3D memory device with only two levels for illustrative purposes. Similar structures and functionalities can be extended to 3D memory devices with more than two levels.

[0070] Figure 5 A schematic circuit diagram of a multi-level 3D memory device 500 according to some embodiments of the present disclosure is shown. As an example, the 3D memory device 500 includes two levels, such as a top level 452 and a bottom level 450. The 3D memory device 500 also includes a memory string 212 having a plurality of stacked memory cells 340, wherein memory cells 340-1 are in the bottom level 450 and memory cells 340-2 are in the top level 452. The 3D memory device 500 also includes a conductive plug 460 between the top level 452 and the bottom level 450. Thus, in the multi-level 3D memory device 500, memory cells 340-2 in the top level 452 can be electrically connected to memory cells 340-1 in the bottom level 450 to form the memory string 212. The memory string 212 also includes at least one field-effect transistor (e.g., MOSFET) at each end, controlled by a lower select gate (LSG) 332 and a top select gate (TSG) 334, respectively. The two corresponding transistors are referred to as lower select transistor 332-T and top select transistor 334-T. The stacked memory cell 340 can be controlled by a control gate 333, which is connected to a word line (not shown) of the 3D memory device 500. The drain terminal of the top select transistor 334-T can be connected to bit line 341, and the source terminal of the lower select transistor 332-T can be connected to a doped source line region 344 (see...). Figure 4 ACS 464 can be formed from the doped source line region 344. ACS 464 can be shared by memory strings 212 throughout the memory block and is also referred to as the common source line.

[0071] In NAND flash memory, read and write operations can be performed in memory pages, which comprise memory cells sharing the same word line. Each memory cell can be in an erased state or a programmed state. Initially, all memory cells in a block can be reset to an erased state as logic "1" by implementing a negative voltage difference between the control gate 333 and the source terminal of the memory cell (e.g., the lower terminal closer to the substrate 330), allowing all electronic charge stored in the memory cell to be removed. In some embodiments, electrons stored in the memory film can be expelled to the channel layer via Flower-Nordheim (FN) tunneling, thereby altering the threshold voltage V of the memory cell 340. th In some embodiments, the ACS 464 can be grounded at zero voltage (0V), and a negative voltage can be applied to the control gate 333. In some embodiments, a positive voltage can be applied to the ACS 464, and the control gate 333 can be grounded at 0V. In the erase state, the threshold voltage V of the memory cell 340... th It can be reset to the lowest value, such as the erase state threshold voltage V. th_erase The corresponding current flowing through the memory cell 340 between the source terminal (e.g., the terminal closer to the substrate 330) and the drain terminal (e.g., the terminal closer to the bit line 341) can be at its highest level.

[0072] Figure 6 The diagram shows waveforms of an erase operation 600 according to some embodiments of this disclosure. This can be applied to memory blocks (e.g.,...) Figure 1 An erase operation 600 is performed on all memory cells in memory block 103. For Figure 4 and 5 The 3D memory device shown has multiple levels and can erase all memory cells in the top level 452 and the bottom level 450 simultaneously. For example, in time period t erase During this period, in ( Figure 5 All memory cells 340 of the memory string 212 in the 3D memory device 500 (including those in the top layer 452 and the bottom layer 450) can be reset to an erase state. The erase operation 600 includes applying an erase voltage V at t0 at ACS 464 and / or bit line 341. erase Simultaneously, maintain the release voltage V. hld-re It can be applied to control gate 333 (including control gate 333-1 in the bottom layer 450 and control gate 333-2 in the top layer 452). In some embodiments, the erase voltage V erase It can be in the range of approximately 15V to approximately 25V. In some implementations, the erase voltage V eraseIt can be approximately 20V. When a hold-release voltage V is applied to the gate electrode... hld-re At that time, a voltage of 0V is applied, followed by a voltage release of 0V. In other words, a hold-release voltage V is applied. hld-re The gate electrode is biased at a voltage of 0V (e.g., at t0), and then the external bias is removed and the gate electrode is released to float (e.g., at t1, where t1>t0), wherein the potential of the gate electrode can be changed by an electromagnetic field or by charge accumulation in the conductor.

[0073] Initially applied hold-release voltage V hld-re Afterwards, the unselected word line (i.e., the control gate of the erase suppressor memory cell) can remain floating after t1, wherein the potential of the unselected word line can rise to voltage V through capacitive coupling at t3 (t3>t2>t1>t0). H In some implementations, the voltage V H It can have a voltage close to the erase voltage V erase The amplitude.

[0074] For the selected word line (i.e., the control gate of the memory cell to be erased), a low voltage V can be applied at t2 (t2>t1>t0). L The potential of the selected word line can reach a low voltage V at t3. L In some implementations, the low voltage V L It can be any voltage less than approximately 1V. In some implementations, the low voltage V L It can be 0V. In this example, the voltage difference between the selected word line and the ACS464 is V. L -V erase It can be high enough to remove the stored charge in the memory cell and reset the memory cell to an erased state.

[0075] In some implementations, bit line 341 and top select gate (TSG) 334 can be floating during the erase operation, i.e., no voltage is applied. In this example, bit line 341 and top select transistor 334-T can be coupled to a high potential due to the parasitic capacitance between bit line 341 and ACS 464. Meanwhile, when the erase voltage V is applied... erase After being applied to the ACS464, the channel potential of memory cell 340 increases accordingly. In the doped source pole region 344 (see...) Figure 4Charge carriers (e.g., holes) in the memory cell 340 can be injected into the channel layer 338. Because the mobility of holes in the channel layer may be low in the channel layer 338 made of polycrystalline or amorphous silicon, the potential of the channel in the memory cell 340 gradually increases from the bottom to the top of the channel. Therefore, the potential of the channel layer 338 in the memory string 212 increases from the bottom (i.e., the potential of the channel layer 338 in the memory string 212 increases from the bottom (i.e., the potential of the channel layer 338 in the memory string 212) ... Figure 4 In the doped source pole region 344 or Figure 5 The ACS (464) gradually rises to the top (near bit line 341).

[0076] In some implementations, after the erase operation, the threshold voltage V of the memory cell 340 can be verified during the erase verification operation by measuring the current flowing through the memory cell 340. th The distribution. For example, a verification voltage V1 (e.g., 0V) can be applied to the control gate 333. For a threshold voltage V that is lower than the verification voltage V1... th The memory cells can be connected and form a conductive path. If the threshold voltage V of the memory cell... th If the voltage exceeds the verification voltage V1, the corresponding memory cell is disconnected. If not all memory cells have a threshold voltage below the verification voltage V1, a step voltage V can then be added. step A higher voltage is applied to re-verify the erase state. The above verification steps can be repeated until the threshold voltage of all memory cells is verified. For cells with a voltage higher than the target erase-verification voltage V after the erase operation... target The memory cell with a threshold voltage is considered to have failed erasure. In some embodiments, the threshold voltage V of memory cell 340 is... th The voltage distribution can be in the range of approximately -4.0V to approximately -2.0V after the erase operation, and the target erase-verification voltage V... target It can operate in the range of approximately -2.0V to approximately -1.0V.

[0077] In NAND flash memory, memory cells can be reset to an erase state across an entire memory block (which can be as large as hundreds of kilobytes (KB) or even megabytes (MB) in size), and the erase operation can take hundreds of microseconds to complete, much longer than the random access time for reading or writing. Therefore, reducing the memory block size for faster erase operations is desirable. Without sacrificing storage capacity, erase operations can be performed, for example, on a sub-block basis for selected levels in a 3D memory device with multiple levels.

[0078] Figure 7 The waveform of an erase operation 700 according to some embodiments of this disclosure is shown. In this example, for Figure 5The 3D storage device 500 in the middle can target the memory cell 340-1 in the bottom layer 450 for a time period t. erase During this period, an erase operation 700 is performed, while the erasure of memory cells 340-2 in the top level 452 can be suppressed, meaning that the data stored in memory cells 340-2 in the top level 452 continues to exist after the erase operation. In this example, a hold-release voltage V can be applied to a selected word line (e.g., the control gate 333-1 of the bottom level 450) at t0 / t1. hld-re A low voltage V is applied at t2 (t2>t1>t0). L Similar to erase operation 600, an erase voltage V can be applied to ACS 464 and / or bit line 341. erase As a result, a negative voltage difference can be established between the control gate 333-1 in the bottom layer 450 and the source terminal of the memory cell 340-1 in the bottom layer 450. During time period t... erase At the end, memory cell 340-1 in the bottom level 450 can be reset to the erase state. In this example, an unselected word line (e.g., control gate 333-2 in the top level 452) can be applied with a hold-release voltage V at t0 / t1. hld-re And it remains floating after t1 (i.e., no external voltage is applied). The potential of the control gate 333-2 in the top layer 452 can be raised to voltage V via capacitive coupling. H .

[0079] Figure 8 The diagram illustrates waveforms of an erase operation 800 according to some embodiments of the present disclosure. In this example, the erase operation 800 can be performed on memory cell 340-2 in top level 452, wherein a selected word line (e.g., control gate 333-2 in top level 452) can be subjected to a hold-release voltage V at t0 / t1. hld-re And a low voltage V is applied at t2. L Similar to erase operation 600, an erase voltage V can be applied to ACS 464 and / or bit line 341. erase As a result, a negative voltage difference can be established between the control gate 333-2 in the top layer 452 and the source terminal of the memory cell 340-2 in the top layer 452. During time period t... erase At the end, memory cell 340-2 in top level 452 can be reset to the erase state. In this example, an unselected word line (e.g., control gate 333-1 in bottom level 450) can be applied with a hold-release voltage V at t0 / t1. hld-reAnd it remains floating after t1, meaning no external voltage is applied. The potential of the control gate 333-1 in the bottom layer 450 can be raised to voltage V via capacitive coupling. H In some implementations, the voltage V H It can have a voltage close to the erase voltage V erase The amplitude of the voltage difference between the control gate 333-1 and the source terminal of the memory cell 340-1 can be very small. Therefore, the erasure of the memory cell 340-1 in the bottom layer 450 can be suppressed, that is, the data stored in the memory cell 340-1 in the bottom layer 450 continues to exist after the erasure operation.

[0080] However, in Figure 8 In the example shown, the state and data mode of memory cell 340-1 in the bottom layer 450 during erase operation 800 can affect the erase state threshold voltage V of memory cell 340-2 in the top layer 452. th_erase As discussed earlier, at the erase voltage V erase After being applied to the ACS 464, charge carriers (e.g., holes) are injected into the channel of memory cell 340 from bottom to top, and the channel potential gradually rises from bottom to top. However, the state or data mode of memory cell 340-1 in the bottom layer affects the potential of the corresponding memory cell 340-1, and thus affects the charge carriers from the ACS 464 (or Figure 4 The migration of the doped source pole region 344 to the position line 341. As a result, in Figure 5 The potential at the conductive plug 460 in the middle can be lower than the erase voltage V applied to the ACS 464. erase When the potential of memory cell 340-2 in the top level 452 changes from the erase voltage V... erase When the voltage is significantly reduced, the voltage difference between the control gate 333-2 and the channel of the memory cell 340-2 may not be high enough to reset the corresponding memory cell 340-2 to a value with an ideal threshold voltage (i.e., below the target erase-verification voltage V). target Erase state threshold voltage V th_erase The erase state of memory cell 340-2 in the top level 452. The erase state threshold voltage V. th_erase When moved to a higher value, it has a voltage higher than the target erase-verification voltage V. target Erase state threshold voltage V th_erase More memory cells and therefore more memory cells have erase failures.

[0081] Therefore, in some embodiments of this disclosure, a preparation step is added before performing the erase operation. During the preparation step, the state and / or data pattern of adjacent levels can be checked, and memory cells of adjacent levels can be addressed accordingly to allow charge carriers to be retrieved from the ACS 464 (or... Figure 4 The doped source pole region 344) migrates to the position line 341, thereby reducing the number of erase failures.

[0082] Figure 9 Some embodiments according to this disclosure are shown. Figure 5 The flowchart illustrates the erasure method 900 for the 3D storage device 500. It should be understood that the erasure method 900 is not exclusive, and other operational steps may be performed before, after, or between any of the illustrated operational steps. In some embodiments, some operational steps of the exemplary erasure method 900 may be omitted, or other operational steps may be included; for simplicity, these steps are not described herein. In some embodiments, the operational steps of the erasure method 900 may be performed in a different order and / or changed.

[0083] According to some implementations of this disclosure, it is possible to target Figure 5 The 3D memory device 500 shown, with a top layer 452 and a bottom layer 450, implements an erase method 900. However, the method provided herein is scalable to any 3D memory device with multiple vertically stacked layers, where an erase method can be performed on selected layers. The bias conditions are similar to those described above. Figure 6-8 The bias conditions are discussed below, with differences among them.

[0084] In the example of erasure method 900, an erasure voltage V is applied at ACS 464. erase In some implementations, an erase voltage V can be applied at bit line 341. erase Furthermore, the following discussion regarding the top and bottom levels can then be applied to the bottom and top levels, respectively. In some implementations, an erase voltage V can be applied at ACS 464 and bit line 341. erase The following discussion of top and bottom levels can be extended to any selected and unselected levels.

[0085] The erasure method 900 for the 3D storage device 500 begins at operation step S910.

[0086] At operation step S915, it is evaluated whether the target memory level to be erased is the bottom level 452.

[0087] If memory cell 340-1 at the bottom level 450 is to be erased, then at operation step S920, the erase voltage V... eraseA common source (ACS) 464 can be applied at t0, along with a hold-release voltage V. hld-re A voltage of 0V can be applied to control gate 333 at t0 / t1 (t1>t0), where 0V can be applied at t0 and then removed at t1. The control gate 333-2 of the top gate 333-2 (i.e., the unselected word line in this example) can remain floating after t1 (i.e., no external voltage is applied). The control gate 333-1 of the bottom gate 333-1 (i.e., the selected word line in this example) can be supplied with a low voltage V at t2 (t2>t1>t0). L In the preceding text, along with Figure 7 The details were discussed together. Because the target memory level is the bottom level 450, close to ACS 464, the charge carrier can be obtained from ACS 464 (or... Figure 4 The doped source pole region 344 is injected into the channel of memory cell 340-1 without being affected by the state or data mode from the top layer 452. Therefore, the channel potential of memory cell 340-1 can rise to the erase voltage V at ACS464. erase It is then unaffected by the state or data mode from the top level 452. As a result, the erase state of memory cell 340-1 in the bottom level 450 can achieve the target erase failure rate.

[0088] If it is determined at operation step S915 that the target memory level to be erased is not the bottom level 450 but the top level 452, then at operation step S925 the status and / or data mode of the memory cell 340-1 in the bottom level 450 are further checked.

[0089] In some embodiments, operation step S930 is performed if the bottom level 450 is fully programmed, i.e., all memory cells 340-1 in the bottom level 450 are in a programmed state. In some embodiments, the programming state includes a voltage V that is higher than the erase state threshold voltage V. th_erase High threshold voltage (e.g., programmable threshold voltage V) th_program The logic state is "0". In some implementations, multi-level cell or three-level cell technology is used, and each memory cell 340-1 can have multiple programming states, i.e., threshold voltage V. th Multiple values. In other words, each memory cell 340-1 can store multiple bits, resulting in a significant increase in storage capacity.

[0090] At operation step S930, a first preparation voltage V can be applied to the control gate 333-1 of the memory cell 340-1 in the bottom layer 450. prep1 ACS 464 can be grounded. Figure 10The waveform of operation step S930 is shown. In some embodiments, a first preparation voltage V can be selected. prep1 This allows memory cell 340-1 to switch to an accumulation mode, where charge carriers (e.g., holes) can accumulate in the channel. To avoid interfering with the data stored in memory cell 340-1, a first preparation voltage V... prep1 It can be kept low. In some implementations, the first preparation voltage V prep1 It can be in the range of approximately 0V to approximately 1.0V. In some implementations, the first preparation voltage V prep1 It can be 0V.

[0091] Next, at operation step S950, a first preparation voltage V is applied to the control gate 333-1 of the memory cell 340-1 in the bottom layer 450. prep1 It can be removed, and the control gate 333-1 can first be applied with a hold-release voltage V. hld-re And then it remains floating, meaning no external voltage is applied. Therefore, erasure of memory cell 340-1 can be prevented, similar to the situation regarding... Figure 8 The previous discussion. Meanwhile, low voltage V L Hold-release voltage V hld-re It is then applied to the control gate 333-2 of the top layer 452. Because charge carriers (e.g., holes) accumulate in the channels of memory cells 340-1 in the bottom layer 450, from ACS 464 (or...) Figure 4 Charge carriers (e.g., holes) injected into memory cell 340-1 via the doped source pole region 344 can easily migrate upwards. Therefore, the channel potential of memory cell 340-1 can rise to the erase voltage V applied to the ACS 464. erase Therefore, the potential at the conductive plug 460 can be set to be close to the erase voltage V. erase This allows the erase operation to be performed on memory cells 340-2 in the top level 452, virtually independent of the state or data mode of the bottom level 450. As a result, the erase state of memory cells 340-2 in the top level 452 can achieve the target erase failure rate.

[0092] If it is determined at operation step S925 that the bottom level has not been fully programmed (not all memory cells 340-1 are in the programmed state), then at operation step S935, it can be further checked whether the bottom level has been completely erased, that is, whether all memory cells 340-1 are in the erased state.

[0093] If it is determined at operation step S935 that all memory cells 340-1 in the bottom layer 450 are in an erased state, then operation step S940 can be executed, wherein a second preparation voltage V can be applied to the control gate 333-1 of the memory cells 340-1 in the bottom layer 450. prep2 .exist Figure 11 The waveform of operation step S940 is shown. In some embodiments, the second preparation voltage V prep2 It can be higher than the first preparation voltage V prep1 In some implementations, the second preparation voltage V prep2 It can be in the range of approximately 1.0V to approximately 7.0V. In some implementations, the second preparation voltage V prep2 It can be approximately 1.0V. The erasure method 900 can then continue after the previously described operation step S950. In some embodiments, the second preparation voltage V... prep2 The voltage can be high enough to write the virtual data pattern into memory cell 340-1, that is, to set memory cell 340-1 to a programming state. In some embodiments, the virtual data pattern can be programmed into all memory cells 340-1 at the bottom level. In some embodiments, this can be achieved by applying a second preparation voltage V. prep2 A virtual data pattern is applied to the corresponding control gate 333-1 to program each of the other memory cells 340-1 in the bottom layer. In some embodiments, the virtual data pattern may be programmed to a subset of the memory cells 340-1 in the bottom layer.

[0094] If it is determined at operation step S935 that the bottom layer 450 has not been completely erased, then the bottom layer 450 is partially programmed and partially erased. In this example, some memory cells 340-1 are in the erase state while some memory cells 340-1 are in the programming state. At operation step S955, the first preparation voltage V... prep1 The second preparation voltage V can be applied to those memory cells 340-1 that are in the programming state, and at operation step S960. prep2 The erasure method 900 can then be applied to those memory cells 340-1 that are in the erasure state. The erasure method 900 can then continue after the operation step S950 described above.

[0095] In some implementations, operation steps S955 and S960 are executed when both adjacent memory cells 340-1 in the bottom level are in an erased state.

[0096] In cases where data pattern recognition in the bottom layer 450 causes significant delays, in some implementations, the first preparation voltage V prep1 Second preparation voltage V prep2It can be randomly applied to the control gate 333-1 in the bottom layer 450.

[0097] By preparing the memory cell 340-1 in the bottom layer 450 according to the state and data pattern, the potential at the conductive plug 460 can rise to near the erase voltage V applied at ACS 464. erase Therefore, memory cells 340-2 in the top level 452 can be erased similarly to memory cells in the bottom level 450 or in a 3D memory device with a single level, and the erase failure rate in the top level 452 can be reduced.

[0098] The method described herein can also be implemented in 3D memory devices with multiple levels (more than two levels), wherein the intermediate and top levels may have erase failures similar to those described above. By adding a preparation operation, the potential at the source terminal of the intermediate or top level (e.g., conductive plug 460) can be controlled to the erase voltage V applied at the array common source in the substrate. erase For example, when the top layer is vertically stacked on the middle layer and the middle layer is vertically stacked on the bottom layer above the substrate, the top, middle, and bottom layers can be selectively erased. To improve the erase yield of the middle layer, operation steps S940, S955, and / or S960 can be implemented on the top and bottom layers before erasing the middle layer. In this example, at operation step S950, a hold-release voltage can be applied to the unselected word lines of the top and bottom layers, and a low voltage V can be applied to the selected word lines of the middle layer. L .

[0099] Similarly, the method described herein can also be implemented in 3D memory devices with multiple levels, wherein an erase voltage V can be applied at ACS 464 and / or bit line 341. erase In this example, depending on the distance between the corresponding level and ACS 464 and / or bit line 341, the bottom level, middle level, or top level may experience erase failure. By adding a similar preparation operation discussed above, the potential at the source and / or drain terminals of the corresponding level can be controlled to the erase voltage V. erase Therefore, a sufficient voltage difference can be maintained between the selected word line (i.e., the control gate of the target memory cell) and the channel of the target memory cell. Thus, the corresponding level (i.e., the selected sub-block) can be successfully erased.

[0100] In summary, this disclosure provides an erasure method for a three-dimensional (3D) memory device. The 3D memory device includes multiple layers vertically stacked on a substrate, wherein each layer includes multiple memory cells. The erasure method includes: checking the state of multiple memory cells in an erase suppression layer, and preparing an erase suppression layer based on the state of the multiple memory cells. The erasure method further includes: applying an erase voltage at an array common source, applying a hold-release voltage on an unselected word line of the erase suppression layer, and applying a low voltage on a selected word line of a target layer.

[0101] This disclosure also provides a three-dimensional (3D) memory device having multiple layers vertically stacked on a substrate. Each layer includes a film stack of alternating conductive and dielectric layers, and multiple memory strings penetrating the film stack, wherein each memory string includes multiple memory cells. The 3D memory device further includes conductive plugs disposed between adjacent layers, electrically connecting the multiple memory strings between adjacent layers. The multiple layers of the 3D memory device include a target layer and an erase suppression layer. The 3D memory device is configured to erase the target layer by: checking the state of multiple memory cells in the erase suppression layer, preparing the erase suppression layer based on the state of the multiple memory cells in the erase suppression layer, applying an erase voltage at an array common source, applying a hold-release voltage on an unselected word line of the erase suppression layer, and applying a low voltage on a selected word line of the target layer.

[0102] The foregoing description of specific embodiments will thus reveal the general nature of this disclosure, which allows others to easily modify and / or adapt such specific embodiments for various applications using knowledge of the art, without departing from the general conception of this disclosure. Therefore, based on the teachings and guidance set forth herein, such modifications and adaptations are defined as being within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the terminology or language used herein is for descriptive rather than limiting purposes, and that the terminology or language used in this specification should be interpreted by those skilled in the art in accordance with the teachings and guidance.

[0103] The above description of implementation methods of this disclosure uses functional building blocks to illustrate how the specified functions and their relationships are implemented. For ease of description, the boundaries of these functional building blocks are arbitrarily defined herein. Optional boundaries may be defined, provided that the specified functions and their relationships are properly performed.

[0104] The overview and summary sections may set forth one or more, but not all, exemplary embodiments of this disclosure as conceived by the inventors, and are therefore not intended to limit this disclosure and the appended claims in any way.

[0105] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined only by the appended claims and their equivalents.

Claims

1. An erasing method of a three-dimensional (3D) memory device, the three- dimensional (3D) memory device comprising: A plurality of levels stacked on a substrate, wherein each level includes a plurality of memory cells, the erase method comprising: applying a preparation voltage on unselected word lines of an erase inhibit level when the erase inhibit level is positioned between a target level to be erased and an erase voltage application terminal; applying an erase voltage on an array common source or bit line; applying a hold-release voltage on the unselected word lines of the erase inhibit level; and applying a low voltage on selected word lines of the target level to be erased, wherein the low voltage is less than the erase voltage.

2. The erasing method according to claim 1, wherein, The erase method further comprises: not applying the preparation voltage on the unselected word lines of the erase inhibit level when the erase inhibit level is not positioned between the target level to be erased and the erase voltage application terminal.

3. The erasing method of claim 1, wherein, applying a preparation voltage on unselected word lines of an erase inhibit level when the erase inhibit level is positioned between a target level to be erased and an erase voltage application terminal comprises: applying a first preparation voltage on the unselected word lines of the erase inhibit level when the plurality of memory cells of the erase inhibit level are in a program state.

4. The erasing method according to claim 3, wherein, applying the first preparation voltage comprises applying a voltage greater than or equal to 0V and less than 1V.

5. The erasing method according to claim 3, wherein, applying a preparation voltage on unselected word lines of an erase inhibit level when the erase inhibit level is positioned between a target level to be erased and an erase voltage application terminal comprises: applying a second preparation voltage on the unselected word lines of the erase inhibit level when the plurality of memory cells of the erase inhibit level are in an erase state, wherein the second preparation voltage is greater than the first preparation voltage.

6. The erasing method according to claim 5, wherein, applying the second preparation voltage comprises applying a voltage greater than or equal to 1V and less than 7V.

7. The erasing method of claim 1, wherein, applying a preparation voltage on unselected word lines of an erase inhibit level when the erase inhibit level is positioned between a target level to be erased and an erase voltage application terminal comprises: applying a first preparation voltage on the unselected word lines of the memory cells in a program state when a portion of the plurality of memory cells in the erase inhibit level are in a program state; and applying a second preparation voltage on the unselected word lines of the memory cells in an erase state when a portion of the plurality of memory cells in the erase inhibit level are in an erase state, wherein the second preparation voltage is greater than the first preparation voltage.

8. The erasing method according to claim 7, wherein, The memory cells in an erase state comprise at least two adjacent memory cells.

9. The erasing method of claim 1, wherein, applying a preparation voltage on unselected word lines of an erase inhibit level when the erase inhibit level is positioned between a target level to be erased and an erase voltage application terminal comprises: applying a first preparation voltage on a portion of the unselected word lines of the erase inhibit level and a second preparation voltage greater than the first preparation voltage on another portion of the unselected word lines of the erase inhibit level when the plurality of memory cells in the erase inhibit level are partially in a program state and partially in an erase state.

10. The erasing method of claim 1, wherein, applying the low voltage comprises applying a voltage greater than or equal to 0V and less than 1V.

11. The erasing method of claim 1, wherein, after applying the hold-release voltage, comprises: applying a bias to selected word lines of a target level to be erased; and subsequently removing the bias.

12. The erase method of claim 1, further comprising: applying the hold-release voltage to the selected word lines of the target level to be erased prior to applying the low voltage to the selected word lines of the target level to be erased.

13. The erase method of claim 1, further comprising: applying the hold-release voltage to unselected word lines of a top level and a bottom level in an erase inhibit level; and applying the low voltage to selected word lines of an intermediate level to be erased, wherein the top level is stacked on the intermediate level and the intermediate level is stacked on the bottom level above the substrate.

14. A three-dimensional (3D) memory device, comprising: a plurality of levels stacked on a substrate, each level comprising a plurality of memory cells; wherein the plurality of levels comprises a target level to be erased and an erase inhibit level, and the 3D memory device is configured to perform the erase method of any one of claims 1-13.

Images