High-voltage adjustable multilayer capacitor

Abstract

An adjustable multilayer capacitor is provided. The capacitor includes a first active electrode in electrical contact with a first active terminal and a second active electrode in electrical contact with a second active terminal. The capacitor includes a first DC bias electrode in electrical contact with a first DC bias terminal and a second DC bias electrode in electrical contact with a second DC bias terminal. A plurality of dielectric layers are disposed between the first and second active electrodes and between the first and second bias electrodes. At least a portion of the dielectric layers comprise an adjustable dielectric material that exhibits a variable dielectric constant when an applied DC voltage is applied across the first and second DC bias electrodes. At least one of the plurality of dielectric layers has a thickness greater than about 15 microns.

Description

[0001] This application is a divisional application of PCT application PCT / US2018 / 049900 filed on September 7, 2018, which entered the Chinese national phase (application number: 201880058397.6, invention title: high voltage adjustable multilayer capacitor, applicant: Kyocera AVX Components Co., Ltd.). Technical Field

[0002] This application relates to a capacitor, and more particularly to an adjustable multilayer capacitor for high-voltage applications. Background Technology

[0003] Adjustable capacitors have been proposed in a variety of applications that rely on the variable dielectric properties of the dielectric. For such capacitors, the capacitance at zero bias is typically close to its maximum value, and the capacitance decreases with the applied voltage. This variation in capacitance allows these units to be used to create adjustable circuits in filters, matching networks, resonant circuits, and other applications ranging from audio to RF and microwave frequencies. Despite their advantages, the use of such capacitors has been relatively limited, partly due to the relatively low capacitance values ​​achievable at high power and voltage levels. Therefore, there is a current need for a voltage-adjustable capacitor with improved performance that can be used in a wider range of possible applications. Summary of the Invention

[0004] According to one embodiment of this disclosure, an adjustable multilayer capacitor is disclosed, comprising a first active electrode electrically contacting a first active terminal and a second active electrode electrically contacting a second active terminal. The capacitor also includes a first DC bias electrode electrically contacting a first DC bias terminal and a second DC bias electrode electrically contacting a second DC bias terminal. The capacitor further includes a plurality of dielectric layers disposed between the first and second active electrodes and between the first and second bias electrodes. At least a portion of the dielectric layers comprises an adjustable dielectric material that exhibits a variable dielectric constant when an applied DC voltage is applied across the first and second DC bias electrodes. At least one of the plurality of dielectric layers has a thickness greater than about 15 micrometers.

[0005] According to another embodiment of this disclosure, an adjustable multilayer capacitor is disclosed, comprising a first active electrode electrically contacting a first active terminal and a second active electrode electrically contacting a second active terminal. The capacitor also includes a first DC bias electrode electrically contacting a first DC bias terminal and a second DC bias electrode electrically contacting a second DC bias terminal. The capacitor further includes a plurality of dielectric layers disposed between the first and second active electrodes and between the first and second bias electrodes. At least a portion of the dielectric layers comprises an adjustable dielectric material that exhibits a variable dielectric constant when an applied DC voltage is applied across the first and second DC bias electrodes. The applied DC voltage is greater than about 100V but does not exceed about 50% of the breakdown voltage of the adjustable dielectric material.

[0006] Other features and aspects of the invention are set forth below in more detail. Attached Figure Description

[0007] The remainder of this specification sets forth in more detail the full and practical disclosure of the invention, including the best mode thereof, for those skilled in the art, with reference to the following figures:

[0008] Figure 1 The illustration shows the capacitance variation that can be obtained using the currently disclosed subject matter within the range of normalized bias voltage variation;

[0009] Figure 2A , 2B Figures 2C and 2C respectively show a cross-sectional view, an exploded plan view, and an exploded perspective view of an exemplary embodiment of a four-terminal biased multilayer capacitor according to the currently disclosed subject matter;

[0010] Figure 2D It shows the current Figures 2A to 2C An overall side view, top view, and end perspective view of the assembly apparatus of an exemplary embodiment;

[0011] Figure 2E and 2F The current ones are shown respectively. Figures 2A to 2D The parallel and series configurations of the exemplary embodiments are represented in the diagram;

[0012] Figure 3A , 3B Figures 3C and 3C respectively show a cross-sectional view, an exploded plan view and an exploded perspective view of an exemplary embodiment of a four-terminal adjustable cascaded multilayer capacitor according to the currently disclosed subject matter;

[0013] Figure 3D and 3E The current ones are shown respectively. Figures 3A to 3C The parallel and series configurations of the exemplary embodiments are represented in the diagram;

[0014] Figure 4A and 4B Cross-sectional and exploded plan views of exemplary embodiments of a multilayer capacitor constructed with a four-terminal adjustable portion bias according to the currently disclosed subject matter are shown respectively.

[0015] Figure 4C The current Figure 4A and 4B Representative diagrams of exemplary embodiments;

[0016] Figure 5 This describes an exemplary embodiment of a chip manufacturing automation process (CMAP) according to the subject matter of this disclosure, which can be used to manufacture exemplary embodiments of apparatuses as disclosed herein;

[0017] Figure 6 A cross-sectional view of an exemplary embodiment of a bias-asymmetric multilayer capacitor according to the currently disclosed subject matter is shown;

[0018] Figure 7A and 7B Cross-sectional views and partial enlarged perspective views of exemplary embodiments of a 1:1 ratio overlapping symmetrical design of a biased multilayer capacitor according to the currently disclosed subject matter are shown respectively.

[0019] Figure 7C and 7D Exploded view and assembled perspective view of a 1:1 ratio overlapping symmetrical design of a biased multilayer capacitor based on the currently disclosed subject matter are shown respectively.

[0020] Figure 8 A cross-sectional view is shown of an exemplary embodiment of an 11:1 ratio unshielded asymmetric design of a biased multilayer capacitor according to the subject matter currently disclosed.

[0021] Figure 9 A cross-sectional view is shown of an exemplary embodiment of an 11:1 ratio shielded asymmetric design for a biased multilayer capacitor according to the subject matter currently disclosed.

[0022] Figure 10 A cross-sectional view is shown of an exemplary embodiment of a biased multilayer capacitor with a mixture of components according to the currently disclosed subject matter;

[0023] Figure 11 (a)-11(c) respectively illustrate various symmetrical orientations that can be used for active and bias terminals in certain embodiments of the present invention;

[0024] Figure 12 Embodiments of stacked capacitor arrays having a single lead and lead frame attachments according to various aspects of the subject matter of this disclosure are shown; and

[0025] Figure 13The measured capacitance of an example stacked capacitor array according to various aspects of this disclosure is shown, wherein the applied DC bias voltage level is in the range of 0V to 200V.

[0026] Reference characters are used repeatedly in this specification and drawings to indicate the same or similar features, elements or steps thereof. Detailed Implementation

[0027] Those skilled in the art will understand that this discussion is merely a description of exemplary embodiments and is not intended to limit the broader aspects of this disclosure, which are embodied in the exemplary constructions.

[0028] Generally, the present invention relates to a multilayer capacitor comprising a plurality of dielectric layers interposed between alternating active electrode layers. At least a portion of the dielectric layers comprises a tunable material that exhibits a variable dielectric constant when an applied voltage is applied. More particularly, the “voltage tunability factor” of such material is typically in the range of about 10% to about 90%, in some embodiments about 20% to about 80%, and in some embodiments about 30% to about 70%, wherein the “voltage tunability factor” is determined according to the following general formula:

[0029] T = 100x(ε0 - ε V ) / ε0

[0030] in,

[0031] T is the voltage adjustability coefficient;

[0032] ε0 is the static dielectric constant of the material when no voltage is applied; and

[0033] ε V It is the variable dielectric constant of the material after the applied voltage (DC) is applied.

[0034] The static dielectric constant of the material is typically in the range of about 100 to about 25,000, in some embodiments about 200 to about 10,000, and in some embodiments about 500 to about 9,000, determined according to ASTM D2149-13, for example, at an operating temperature of about -55°C to about 150°C (e.g., 25°C) and a frequency of about 100 Hz to about 1 GHz (e.g., 1 kHz). It should be understood, of course, that the specific value of the static dielectric constant is typically chosen based on the specific application using the capacitor. The dielectric constant typically decreases within the aforementioned range when an increased DC bias is applied. The tuning voltage applied to induce the desired change in dielectric constant can typically be varied relative to the voltage at which the dielectric composition begins to conduct after an electric field is applied (“breakdown voltage”), which can be determined according to ASTM D149-13 at a temperature of 25°C. In most embodiments, the applied DC bias voltage is about 50% or less of the breakdown voltage of the dielectric composition, in some embodiments about 30% or less, and in some embodiments about 0.5% to about 10%.

[0035] As is known in the art, any variety of tunable dielectric materials can generally be used. Particularly suitable materials are dielectrics whose base components include one or more ferroelectric phases, such as perovskites, tungsten bronze materials (e.g., barium sodium niobate), and layered materials (e.g., bismuth titanate). Suitable perovskites may include, for example, barium titanate and related solid solutions (e.g., barium strontium titanate, calcium barium titanate, barium zirconate titanate, barium strontium zirconium titanate, barium zirconate barium titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), sodium bismuth titanate, etc. In a particular embodiment, for example, Ba can be used. x Sr 1- x Barium strontium titanate (“BSTO”) of TiO3, wherein x is 0 to 1, about 0.15 to about 0.65 in some embodiments, and about 0.25 to about 0.6 in others. Other electronically tunable dielectric materials can be used in partial or complete substitution for barium strontium titanate. For example, one example is Ba... x Ca 1-x TiO3, wherein x is from about 0.2 to about 0.8, and in some embodiments from about 0.4 to about 0.6. Other suitable perovskites may include Pb. x Zr 1-xTiO3 (“PZT”), where x ranges from about 0.05 to about 0.4, lanthanum zirconium lead titanate (“PLZT”), lead titanate (PbTiO3), barium calcium zirconium titanate (BaCaZrTiO3), sodium nitrate (NaNO3), KNbO3, LiNbO3, LiTaO3, PbNb2O6, PbTa2O6, KSr(NbO3) and NaBa2(NbO3)5KHb2PO4. Other complex perovskites may include A[B1 1 / 3 B2 2 / 3 O3 material, where A is Ba x Sr 1-x (x can be a value from 0 to 1); B1 is Mg y Zn 1-y (y can be a value from 0 to 1); B2 is Ta z Nb 1-z (z can be a value from 0 to 1). Potential dielectric materials of interest can be formed by combining two end-member components in alternating layers, such as... Figure 10 An exemplary embodiment is shown. These end-member components can be chemically similar, but the ratio of A-site dopant differs, as described above. For example, component 1 ( Figure 10 132 in the formula can be a general formula (A1) x A2 (1-x) ) BO3 perovskite compounds, component 2 (134) can be of the general formula (A1 y A2 (1-y) )BO3 perovskite, where A1 and A2 are derived from Ba, Sr, Mg, and Ca; potential B-site members are Zr, Ti, and Sn, and "x" and "y" represent the mole fraction of each component. A specific example of compound 1 could be (Ba 0.8 Sr 0.2 TiO3, compound 2 can be (Ba 0.6 Sr 0.4 TiO3. These two compounds can be combined in alternating layers in sintered multilayer capacitors with tunable electrode structures, such as... Figure 10 As shown, the dielectric properties of each material overlap. If desired, the perovskite material may also be doped with rare earth oxides (“REO”), for example, at a concentration of less than or equal to 5.0 mol%, more preferably 0.1 to 1 mol%. Suitable rare earth oxide dopants for this purpose may include, for example, scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, praseodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.

[0036] Regardless of the specific materials used, the use of tunable dielectric materials allows the capacitance of the resulting capacitor to be tuned by applying a DC bias voltage through bias terminals. More specifically, the capacitor comprises a set of first active electrodes in electrical contact with a first active terminal (e.g., an input terminal) and a set of second active electrodes in electrical contact with a second active terminal (e.g., an output terminal). The capacitor also comprises a set of first DC bias electrodes in electrical contact with a first DC bias terminal and a set of second DC bias electrodes in electrical contact with a second DC bias terminal. When arranged in a circuit, a DC power source (e.g., a battery, a constant voltage power supply, a multi-output power supply, a DC-DC converter, etc.) can provide DC bias to the capacitor through the first and second bias terminals, which are typically bipolar as they have opposite polarities. The electrodes and terminals can be formed from any of the various metals known in the art, such as noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, etc.), and various combinations thereof. A dielectric layer is interposed between the respective active electrodes and bias electrodes.

[0037] Regardless of the specific configuration used, the inventors have discovered that by selectively controlling the properties of the tunable dielectric material, the number of dielectric layers, and the thickness of the dielectric layers, a capacitor with excellent tunability over a wide range of voltage and capacitance values ​​can be obtained. For example, such a capacitor can allow for higher applied DC bias voltage values ​​and higher capacitance (compared to multiple capacitors connected in parallel) in a single capacitor, with a total size smaller than conventionally considered possible. For example, in some embodiments, the applied DC bias voltage can be greater than about 10V, in some embodiments greater than about 50V, in some embodiments greater than about 100V, in some embodiments greater than about 350V, in some embodiments greater than about 500V, in some embodiments greater than about 750V, in some embodiments greater than about 1000V, in some embodiments greater than about 1200V, and in some embodiments greater than about 1500V. For example, in some embodiments, the applied DC bias voltage can be in the range of about 10V to about 1500V, in some embodiments about 20V to about 1000V, in some embodiments about 30V to about 750V, in some embodiments about 40V to about 500V, and in some embodiments about 50V to about 350V. Similarly, the applied bias field ranges from about 0.2V / μm to about 50V / μm, in some embodiments about 0.5V / μm to about 40V / μm, in some embodiments about 0.5V / μm to about 25V / μm, and in some embodiments about 1V / μm to about 7V / μm.

[0038] The capacitance value can also be controlled within a wider range than conventionally thought possible. For example, a capacitor can be constructed to have a tuning capability of an initial capacitance value ranging from 0.5 to 50,000,000 pF, as discussed below. Therefore, the capacitor can be used in applications requiring high capacitance, such as at values ​​of 100 pF or higher, about 10,000 pF or higher in some embodiments, about 100,000 to about 10,000,000 pF in some embodiments, about 200,000 to 5,000,000 pF in some embodiments, and about 400,000 to about 3,500,000 pF in some embodiments. Similarly, in other embodiments, the capacitor can be used in applications requiring low capacitance, such as at values ​​less than 100 pF, about 50 pF or higher in some embodiments, about 0.5 to about 30 pF in some embodiments, and about 1 to about 10 pF in some embodiments. The degree to which the capacitance can be tuned can be varied as needed. For example, the capacitance value can be adjusted to approximately 10% to approximately 100% of its initial value, in some embodiments approximately 20% to approximately 95%, and in some embodiments approximately 30% to approximately 80%. The capacitance can be determined using an Agilent 4294A impedance analyzer at a frequency of 1 kHz or 1 MHz, a temperature of approximately 25°C, and a fixed oscillation of 500 mV.

[0039] In some embodiments, the thickness of the dielectric layer can range from about 5 micrometers (μm) to about 150 μm, in some embodiments from about 15 μm to about 100 μm, in some embodiments from about 30 μm to about 70 μm, for example about 50 μm. The thickness of the electrode layer can range from about 0.5 μm to about 3.0 μm, in some embodiments from about 1 μm to about 2.5 μm, in some embodiments from about 1 μm to about 2 μm, for example about 1.5 μm.

[0040] The total number of active and bias electrode layers can vary. For example, in some embodiments, the total number of active electrode layers can range from 2 to about 10,000, in some embodiments from 2 to about 1,000, in some embodiments from about 10 to about 500, in some embodiments from about 30 to about 120, such as about 50. Similarly, in some embodiments, the total number of bias electrodes can range from 2 to about 10,000, in some embodiments from 2 to about 1,000, in some embodiments from about 10 to about 500, in some embodiments from about 30 to about 120, such as about 50. It should be understood that the number of electrode layers and bias layers depicted in the drawings and described herein are merely illustrative.

[0041] The length of the capacitor can range, for example, from about 1 millimeter (mm) to about 50 mm, in some embodiments from about 2 mm to about 35 mm, in some embodiments from about 5 mm to about 15 mm, and in some embodiments from about 7 mm to about 14 mm. The width of the capacitor can range, for example, from about 1 mm to about 50 mm, in some embodiments from about 2 mm to about 35 mm, in some embodiments from about 5 mm to about 15 mm, and in some embodiments from about 7 mm to about 14 mm.

[0042] The height of the capacitor can range, for example, from about 0.5 mm to about 14 mm, in some embodiments from about 0.75 mm to about 7 mm, in some embodiments from about 1 mm to about 5 mm, in some embodiments from about 2 mm to about 5 mm, for example from about 3 mm. The ratio of the length of the capacitor to the height of the capacitor can range, for example, from about 1 to about 15, in some embodiments from about 2 to about 7, in some embodiments from about 3 to about 5, for example from about 4. The ratio of the width of the capacitor to the height of the capacitor can range, for example, from about 1 to about 15, in some embodiments from about 2 to about 7, in some embodiments from about 3 to about 5, for example from about 4.

[0043] Figure 1 The capacitance variation achievable over a normalized bias voltage range is illustrated graphically. Specifically, the horizontal axis plots the normalized bias voltage as a percentage of the device's rated voltage, such as 0% to 150%. As shown, the corresponding variation in the device's effective capacitance is plotted on the vertical axis as a percentage change relative to the capacitance value, without any bias. Figure 1 As shown in the graph, a 150% increase in the normalized bias voltage along a relatively straight curve approaches an 80% decrease in the unbiased capacitance value, as illustrated. In this way, the voltage-adjustable capacitor device according to the currently disclosed subject matter helps to maximize efficiency within the operating conditions.

[0044] Now refer to Figures 2A-2DA particular embodiment of a capacitor 10 that can be formed according to the present invention will now be described in more detail. As shown, the capacitor 10 comprises a plurality of dielectric layers 12 stacked alternately with respect to two sets of separate active electrodes 14 and 20 and two sets of separate bias electrodes 22 and 26. The capacitor may be hexahedral, such as a rectangular body. In the illustrated embodiment, a first active terminal 16 is electrically connected to the first active electrode 14, and a second active terminal 18 is electrically connected to the second active electrode 20. The first bias electrode 22 is electrically connected to a first DC bias (+) terminal 30 via an extension member 24 (e.g., a tab) extending to the side of the capacitor 10. Similarly, the second bias electrode 26 is electrically connected to a second DC bias (-) terminal 32 via an extension member 28. Thus, the resulting capacitor 10 comprises four (4) separate terminals. In some embodiments, the active terminals 16, 18 may be wound around the respective ends of the capacitor 10 to provide larger terminals 16, 18 for electrically connecting the capacitor 10 in a circuit. DC bias terminals 30, 32 may be configured as strips that do not extend across the entire side of capacitor 10. However, in other embodiments, DC bias terminals 30, 32 may instead be wound around the side of capacitor 10, and active terminals 16, 18 may be configured as strips that do not extend along the entire end of capacitor.

[0045] Figure 2E and 2F The current ones are shown respectively. Figures 2A to 2D The exemplary embodiments are shown in the parallel and series configuration diagrams. As shown, a ground 34 is also provided relative to the bias input, shown for the parallel configuration.

[0046] In the embodiments discussed above, the active electrodes are stacked such that each alternating electrode is connected to an opposite terminal. In some embodiments, alternating layers can be connected to the same terminal using a "cascaded" configuration, wherein each set of active electrodes is spaced laterally rather than in a stacked manner. One embodiment of such a cascaded capacitor 49 is... Figures 3A-3C As shown, capacitor 49 includes a plurality of dielectric layers 44 arranged relative to two sets of separate active electrodes 36 and 40 and two sets of separate bias electrodes 46 and 50. In the illustrated embodiment, a first active terminal 38 is electrically connected to a first active electrode 36, and a second active terminal 42 is electrically connected to a second active electrode 40. The first bias electrode 46 is electrically connected to a first DC bias (-) terminal 54 via an extension member 48 extending to the side of capacitor 49. Similarly, the second bias electrode 50 is electrically connected to a second DC bias (+) terminal 56 via an extension member 52. Figure 3D and 3E The current ones are shown respectively. Figures 3A to 3CThe exemplary embodiments are shown in the parallel and series configuration diagrams. As shown, a ground 58 is also provided relative to the bias input, shown for the parallel configuration.

[0047] Figures 4A-4C Another embodiment of the capacitor 59 according to the invention is shown, which can be formed in a partially cascaded configuration. The capacitor 59 is considered "partially cascaded" because only a portion 60 of the entire active capacitance region is biased (see [link to documentation]). Figure 4A As shown in the figures, the addition of the bias floating electrode allows an external voltage to be applied to change the dielectric properties of the total capacitance, which will be determined by other factors and characteristics. As these figures show, dielectric layer 62 can be alternately stacked relative to first and second sets of active electrodes 64 and 66, first and second sets of bias electrodes 68 and 72, and a plurality of floating electrodes 76. The first active electrode 64 is electrically connected to the first active terminal 78, while the second active electrode 66 is electrically connected to the second active terminal 80. The first bias electrode 68 is electrically connected to the first DC bias (+) terminal 82 via an extension member 70 extending to the side of the capacitor 59. Similarly, the second bias electrode 72 is electrically connected to the second DC bias (-) terminal 84 via an extension member 74. It should be understood that... Figure 4A The number of electrode layers shown is illustrative only. As mentioned above, in some embodiments, the number of active electrodes can range from 2 to approximately 10,000. As mentioned above, in some embodiments, the number of bias electrodes can range from 2 to approximately 10,000.

[0048] According to yet another embodiment of various aspects of this disclosure, in Figure 7A and 7B As shown in the diagram. In this embodiment, the first and second sets of active electrodes 114, 120 are respectively stacked with the first and second sets of bias electrodes 122, 126 in an alternating 1:1 ratio pattern. (Refer to...) Figure 7B In some embodiments, the leads 124, 128 of the bias electrodes 122, 126 may be configured as protruding tabs. The leads 124, 128 may be in finished form contact with the DC bias terminals 30, 32, such as... Figure 2D As shown. It should be understood that, Figure 7A and 7B The number of electrode layers shown is for illustrative purposes only.

[0049] According to another embodiment of various aspects of this disclosure, in Figure 7C and 7D As shown in the diagram. In this embodiment, the active electrodes 114 and 120 may include respective leads 125 and 127, which may be configured as protruding tabs. Leads 125 and 127 may be connected to... Figure 7DThe corresponding active terminals 16 and 18 are electrically connected as shown. This can provide improved stacking between the edges of the capacitor layers, especially at the corners of the layers, which can result in a more robust capacitor. Furthermore, this configuration can reduce the occurrence of delamination problems during manufacturing.

[0050] Additionally, the widths of the terminals 124, 125, 126, and 127 can be selected to advantageously provide greater electrical contact (e.g., with lower resistance) with the corresponding electrodes 114, 120, 122, and 126. Furthermore, the widths of the terminals 124 and 128 associated with the DC bias electrodes 122 and 126, as well as the widths of the terminals 30 and 32, can be selected to avoid contact between the bias electrode terminals 30 and 32 and the signal electrode terminals 16 and 18. For example, in some embodiments, the terminals 124, 125, 126, and 127 may extend 10% or more along the edge of the capacitor, in some embodiments 30% or more, and in some embodiments 60% or more. It should be understood that... Figures 7A-7D The number of electrode layers shown is illustrative only. As mentioned above, in some embodiments, the number of active electrodes can range from 2 to approximately 10,000. As mentioned above, in some embodiments, the number of bias electrodes can range from 2 to approximately 10,000.

[0051] In the above embodiments, the electrodes are typically used in a “symmetrical” configuration because the distance (or dielectric thickness) between the first and second active electrodes is typically the same as the distance between the first and second bias electrodes. However, in some embodiments, it may be desirable to vary this thickness to achieve an “asymmetrical” configuration. For example, the distance between the first and second active electrodes may be smaller than the distance between the first and second bias electrodes. In other embodiments, the distance between the first and second active electrodes may be greater than the distance between the first and second bias electrodes. This may increase the applied DC field for a given level of applied DC bias, which increases the level of adjustability of a given DC bias voltage. For relatively moderate DC voltages, this arrangement also allows for relatively large adjustability and the use of materials with moderate adjustability (with potentially lower losses and temperature / frequency variability). While this asymmetrical configuration can be implemented in various ways, it is generally desirable to use an additional “floating” bias electrode between each pair of active electrodes. Reference Figure 6 For example, an embodiment of such an asymmetric capacitor is shown, which includes first and second active electrodes 114 and 120 respectively coupled to first and second bias electrodes 122 and 126.

[0052] Figure 8Another embodiment of the asymmetric capacitor is shown, where every 11th electrode is an active electrode rather than a bias electrode (11:1 ratio design). In this case, each such corresponding active electrode (e.g., an AC electrode) can be defined by a pair of DC bias electrodes with opposite polarities. Therefore, a bias field can be generated on each AC electrode. Such a configuration can provide capacitive coupling between the two polarities of the AC signal and the DC bias voltage, and vice versa. Each AC electrode 214, 220 can be positioned between a pair of bias electrodes with opposite polarities 222, 226. The first set of bias electrodes 222 can all have the same polarity, and the second set of bias electrodes 226 (shown in dashed lines) can all have their respective polarities opposite to those of the first set of bias electrodes 222. This configuration can provide capacitive coupling between each AC electrode 214, 220 and the two DC bias polarities.

[0053] Figure 9 A cross-sectional view is shown of an exemplary embodiment of an 11:1 ratio “shielded” asymmetric design for a biased multilayer capacitor according to the currently disclosed subject matter. This is similar to Figure 8 In the example shown, each AC electrode 314, 320 is defined by a pair of DC electrodes (322 or 326) of the same polarity. One set of bias electrodes 322 may all have the same polarity, while another set of bias electrodes 326 (shown in dashed lines) may all have opposite polarities. While the material between two DC electrodes (322 or 326) of the same polarity may not provide tuning, it may provide shielding for the AC signal, thus reducing associated noise. Such a configuration also provides coupling between each of the first set of AC electrodes 314 having only a single DC bias polarity. Similarly, such a configuration can provide capacitive coupling only between the second set of AC electrodes 320 and the opposite DC bias polarity.

[0054] It should be understood that, Figure 8 and 9 The number of electrode layers shown is illustrative only. As mentioned above, in some embodiments, the number of active electrodes can range from 2 to approximately 10,000. As mentioned above, in some embodiments, the number of bias electrodes can range from 2 to approximately 10,000.

[0055] While not strictly required, it is generally desirable that the active and DC bias terminals be arranged symmetrically about the capacitor's axis. For example, in one embodiment, the capacitor may comprise opposing first and second end regions spaced apart in the longitudinal direction and opposing first and side regions spaced apart in the transverse direction. In some embodiments, active terminals may be located in the respective end regions of the capacitor, while DC bias terminals may be located in the respective side regions. When arranged symmetrically, the active terminals and / or DC bias terminals may be equidistant from the longitudinal and / or transverse axes extending through the geometric center of the capacitor. Reference Figure 11 (a) For example, an embodiment of capacitor 1000 is shown, which includes a longitudinal axis "x" and a transverse axis "y" that are perpendicular to each other and extend through a geometric center "C". In this particular embodiment, capacitor 1000 includes first and second active terminals 1100 and 1120, respectively, located in the end region of capacitor 1000 and centered on axes "x" and "y". Similarly, capacitor 1000 includes first and second bias terminals 1140 and 1160, located in the side region of capacitor 1000 and also centered on axes "x" and "y".

[0056] In some embodiments, it may be desirable to place two or more terminals on the same side of the capacitor. For example, in Figure 11 (b) illustrates an embodiment of a capacitor 2000, which includes a first active terminal 2100 and a second active terminal 2140 located on the same side region. The capacitor 2000 also includes a first bias terminal 2160 and a second bias terminal 2120, both located on a side region opposite the active terminals. Although the active terminals 2100 and 2140 are located only on the side regions, they are still arranged symmetrically because they are both equidistant from axes “x” and “y”. Similarly, the bias terminals 2160 and 2120 are also equidistant from axes “x” and “y”. In the above embodiment, the first active terminal and the first bias terminal are positioned opposite the corresponding second active terminal and the second bias terminal. Of course, this is by no means necessary. For example, in… Figure 11 In (c), a capacitor 3000 is shown, which includes first and second active electrode terminals 3100 and 3160, respectively, which are located in opposing side regions in a bias configuration. However, the first active terminal 3100 and the second active terminal 3160 are still arranged symmetrically because they are both equidistant from the axes "x" and "y". Similarly, the capacitor 3000 also includes a first bias terminal 3120 and a second bias terminal 3140, which are located in opposing side regions in a bias configuration equidistant from the axes "x" and "y".

[0057] The currently disclosed subject matter also covers related and / or corresponding methods for improving voltage-adjustable devices, including, for example, the production of such devices and their combined use with related circuitry. As a further example, Figure 5 The diagram illustrates a Chip Manufacturing Automation Process (CMAP) 86, which can be used in conjunction with exemplary apparatus embodiments disclosed herein. As shown, process 86 may include multiple successive stages, and in some cases, three ovens, with inserted ceramic tables or other steps / facets, such as those representatively shown using sieves or elevator and conveyor features. Those skilled in the art will understand that the exact provision of successive steps will depend on which of the exemplary apparatus embodiments (or modifications thereof) disclosed herein is being produced. Similarly, the individual steps indicated are intended only to indicate the type of step indicated and not to indicate any requirement for use in any aspect other than the general nature of the indicated steps. For example, a sieve step may include using a stainless steel sieve with electrode paste for the electrode layer, or other techniques may be practiced for this step. For example, a more conventional step of alternating stacking and lamination (with tape) may be practiced. In any process (or other process), those skilled in the art will recognize that selected steps may be practiced to produce a specific design chosen for a given application of the subject matter currently disclosed.

[0058] refer to Figure 12 A stacked capacitor array 4000 can be formed by stacking the individual capacitors 10, for example... Figures 2A-2D As shown. Compared to a single capacitor 10, the stacked capacitor array 4000 can provide increased capacitance and allows for easier manufacturing and assembly. The capacitors 10 can be connected in parallel. For example, a first lead frame 4002 can connect to each first active terminal 16, and a second lead frame 4004 can connect to each second active terminal 19. A first single lead 4006 can connect to each first DC bias terminal 30, and a second single lead 4008 can connect to each second DC bias terminal 32. (As mentioned above regarding...) Figures 2A-2D As shown, in some embodiments, the configuration of the active terminals 16, 18 and the DC bias terminals 30, 32 can be reversed. For example, the DC bias terminals 30, 32 can be wound around the capacitor 10 instead of the active terminals 16, 18 being wound around the capacitor 10, as... Figure 12 As shown. In some embodiments, the stacked capacitor array 4000 may include 2 to 24 capacitors, 3 to 12 capacitors in some embodiments, and 4 to 6 capacitors in some embodiments. In other embodiments, the stacked capacitor array 4000 may include more than 24 capacitors.

[0059] The capacitor of the present invention can be used in a variety of applications, including circuits used, for example, in aircraft. For example, one application may include an AC circuit operating at frequencies ranging from about 200 Hz to about 1200 Hz, in some embodiments from about 300 Hz to about 1100 Hz, and in some embodiments from about 400 Hz to about 1000 Hz. In such applications, the capacitance of the capacitor can range from about 5 microfarads (μF) to about 15 μF, in some embodiments from about 8 μF to about 12 μF, for example, about 10 μF. The applied bias voltage can range from about 100 V to about 300 V, in some embodiments from about 150 V to about 250 V, for example, about 200 V.

[0060] Additional applications may include circuitry enabled for tuning the oscillation frequency of a switch-mode power supply. By using the capacitors of this invention, better tunability can be selectively obtained at high DC voltages (i.e., bias voltages), while allowing the use of materials with relatively moderate tunability but potentially lower losses and lower temperature / frequency variability. Other suitable applications may include, for example, waveguides, RF applications (e.g., delay lines), antenna structures, filters (e.g., point-of-load filters and circuits), matching networks, resonant circuits, smoothing capacitors in variable-load circuits, and others.

[0061] Example

[0062] An array of stacked capacitors comprising multiple adjustable multilayer capacitors is demonstrated according to various aspects of this disclosure. For example... Figure 12 The diagram shows an assembled stacked capacitor array, which includes three adjustable multilayer capacitors. The total length of the capacitor array is approximately 12.7 mm (0.5 inches), the total width is approximately 12.7 mm (0.5 inches), and the total height is approximately 3.1 mm (0.12 inches).

[0063] Each of the three capacitors in the array comprises a dielectric material including barium titanate. Each dielectric layer has a thickness of approximately 50 μm. There are 54 active electrodes and 55 bias electrodes alternating between them. The capacitance of each capacitor is approximately 1.8 μF.

[0064] An AC sinusoidal signal with an amplitude of 1V and a frequency of 1kHz is applied to the active terminals 16 and 19 (via the first and second lead frames 4002 and 4004). Various DC bias voltage levels are applied to the DC bias terminals 30 and 32 (via the first and second single leads 4006 and 4008).

[0065] Figure 13 The measured capacitance of the stacked capacitor array on the first and second lead frames 4002, 4004 is shown under a DC bias voltage level ranging from 0V to 200V. Figure 13As shown, the measurement capacitance between active terminals 16 and 19 decreases from 5.47 μF at a DC bias voltage of 0 V to approximately 3.66 μF at a DC bias voltage of 200 V. Besides the "adjustability" parameter, in Figure 13 The measured capacitance values ​​and applied DC bias voltages plotted in the table below are shown in the figure. The "adjustability" parameter is calculated by dividing the measured capacitance at each DC bias voltage level by the initial capacitance (5.47 μF) at a DC bias voltage of 0 V.

[0066]

[0067]

[0068] Table 1: Relationship between capacitance and DC bias voltage

[0069] These and other modifications and variations of the invention can be practiced by those skilled in the art without departing from the spirit and scope of the invention. Furthermore, it should be understood that aspects of the various embodiments can be interchanged in whole or in part. Moreover, those skilled in the art will understand that the foregoing description is merely exemplary and is not intended to limit the invention further described in the appended claims.

Claims

1. An adjustable multilayer capacitor, comprising: The first active electrode is in electrical contact with the first active terminal; The second active electrode is in electrical contact with the second active terminal; The first DC bias electrode is in electrical contact with the first DC bias terminal; The second DC bias electrode is in electrical contact with the second DC bias terminal; as well as Multiple dielectric layers are disposed between first and second active electrodes and between first and second bias electrodes, wherein at least a portion of the dielectric layers comprises an tunable dielectric material that exhibits a variable dielectric constant when an applied DC voltage is applied across the first and second DC bias electrodes, and each of the plurality of dielectric layers has a thickness of 15 micrometers or greater. The voltage adjustability coefficient of the adjustable dielectric material is 10% to 95%, and the voltage adjustability coefficient is determined according to the following general formula: T = 100 x (ε0-ε V ) / ε0 in, T is the voltage adjustability coefficient; ε0 is the static dielectric constant of the material when no voltage is applied; and ε V It is the variable dielectric constant of the material after an applied voltage (DC) is applied. The total number of the first and second active electrodes is in the range of 10 to 100, and The capacitor has an adjustability of 66.9% or greater over an applied DC voltage range of at least 200V, wherein the adjustability is the measured capacitance of the capacitor under the applied DC voltage within the range divided by the initial capacitance of the capacitor at the lowest value in the range.

2. The adjustable multilayer capacitor according to claim 1, wherein, The thickness of each of the plurality of dielectric layers is in the range of 15 micrometers to 150 micrometers.

3. The adjustable multilayer capacitor according to claim 1, wherein, The applied DC bias voltage ranges from 100V to 1000V.

4. The adjustable multilayer capacitor according to claim 1, wherein, The adjustable multilayer capacitor has a length ranging from 7 mm to 14 mm.

5. The adjustable multilayer capacitor according to claim 1, wherein, The adjustable multilayer capacitor has a width ranging from 7 mm to 14 mm.

6. The adjustable multilayer capacitor according to claim 1, wherein, The adjustable multilayer capacitor has a height ranging from 2 mm to 5 mm.

7. The adjustable multilayer capacitor according to claim 1, wherein, The ratio of the length of the adjustable multilayer capacitor to its height is from 3 to 5.

8. The adjustable multilayer capacitor according to claim 1, wherein, The static dielectric constant of the dielectric material is 100 to 10000, as determined by ASTM D2149-13 at an operating temperature of 25°C and a frequency of 1 kHz.

9. The adjustable multilayer capacitor according to claim 1, wherein, The dielectric material includes one or more ferroelectric phases.

10. The adjustable multilayer capacitor according to claim 9, wherein, The dielectric material is perovskite, tungsten bronze, layered structure material, or a combination thereof.

11. The adjustable multilayer capacitor according to claim 1, wherein, The first and second active terminals and the first and second bias terminals are arranged symmetrically with respect to the adjustable multilayer capacitor.

12. The adjustable multilayer capacitor according to claim 1, wherein, The distance between the first active electrode and the second active electrode is approximately the same as the distance between the first bias electrode and the second bias electrode.

13. The adjustable multilayer capacitor according to claim 1, wherein, The distance between the first active electrode and the second active electrode is greater than the distance between the first bias electrode and the second bias electrode.

14. The adjustable multilayer capacitor according to claim 1, wherein, The adjustable multilayer capacitor can be tuned to a capacitance value ranging from 200,000 pF to 5,000,000 pF.

15. The adjustable multilayer capacitor according to claim 1, wherein, The capacitor can be tuned to a capacitance value of 200,000 pF or less.

16. The adjustable multilayer capacitor according to claim 1, wherein, The first bias electrode includes a terminal block extending to the first DC bias terminal, and the second bias electrode includes a terminal block extending to the second DC bias terminal.

17. The adjustable multilayer capacitor according to claim 1, wherein, The first active electrode includes a terminal block extending to the first active terminal, and the second active electrode includes a terminal block extending to the second active terminal.

18. The adjustable multilayer capacitor according to claim 1, further comprising: A plurality of first active electrodes, wherein the plurality of first active electrodes are in electrical contact with a first active terminal; A plurality of second active electrodes, wherein the plurality of second active electrodes are in electrical contact with a second active terminal; The first group includes a plurality of first active electrodes stacked in the thickness direction of the adjustable multilayer capacitor, and the second group includes a plurality of second active electrodes stacked in the thickness direction. The first group and the second group are arranged spaced apart from each other in a transverse direction orthogonal to the thickness direction, and the first group and the second group form an electrode stack in the thickness direction.

19. A circuit comprising an adjustable multilayer capacitor according to claim 1 and a power source providing the applied DC bias voltage to the adjustable multilayer capacitor via the first and second DC bias terminals.

20. The circuit according to claim 19, wherein, The applied DC bias ranges from 100V to 1000V.

21. A stacked capacitor array, comprising an adjustable multilayer capacitor according to claim 1, a first lead frame connected to each first active terminal, and a second lead frame connected to each second active terminal.

22. The stacked capacitor array of claim 21, further comprising a first single lead connected to each first DC bias terminal and a second single lead connected to a second DC bias terminal.

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