Method of fabricating a semiconductor structure

Abstract

The embodiment of the present disclosure relates to a semiconductor structure manufacturing method, comprising: providing a substrate; etching a third protective layer from the top surface of the third protective layer; etching a sacrificial layer, a second mask layer located in a mark area and a third protective layer located in an array area; removing a second protective layer; patterning a first protective layer and a pattern transfer layer; etching the substrate. By removing part of the sacrificial layer in the mark area, the present disclosure synchronously obtains a smaller exposed area of the remaining sacrificial layer in the array area, so that the sacrificial layer in the vertical part of the array area and the mark area can be removed at the same time, and the purpose that the first protective layer in the array area and the mark area can be exposed is achieved, which is beneficial to the alignment of the bit line coupling and the normally closed contact covering process.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and specifically to a method for fabricating a semiconductor structure. Background Technology

[0002] Currently, embedded word line manufacturing presents a problem of differences in the morphology of the array area and the marker area, which prevents the semiconductor device from forming a path and affects the alignment of the semiconductor device. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] To overcome the problems existing in related technologies, this disclosure provides a method for fabricating a semiconductor structure.

[0005] This disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0006] A substrate is provided, the substrate including an array region and a marking region. The substrate has a pattern transfer layer, a first protective layer, a first mask layer, a second protective layer, a sacrificial layer, a second mask layer, and a third protective layer stacked sequentially. The first mask layer has a first preset pattern, which includes a plurality of first stripe patterns spaced apart along a first direction. The second protective layer covers the top surface of the first mask layer. The sacrificial layer covers the first protective layer, the first mask layer, and the second protective layer. The second mask layer has a second preset pattern, which includes a plurality of second stripe patterns spaced apart along the first direction, each second stripe pattern being located between two adjacent first stripe patterns. The third protective layer covers the sacrificial layer and the second mask layer. The top surface of the second mask layer in the marking region is higher than the second mask layer in the array region. The top surface of the first protective layer is etched; the third protective layer is etched from its top surface until the top surface of the sacrificial layer and the top surface of the second mask layer located in the marking region are exposed, retaining a portion of the third protective layer on the second mask layer located in the array region; the sacrificial layer, the second mask layer located in the marking region, and the third protective layer located in the array region are etched until the top surface of the second protective layer and the top surface of the second mask layer located in the array region are exposed; the second protective layer is removed, and the sacrificial layer is etched from its top surface until the top surface of the first protective layer is exposed; the first protective layer and the pattern transfer layer are patterned using the first mask layer and the second mask layer as masks to transfer the first preset pattern and the second preset pattern to the pattern transfer layer; based on the patterned pattern transfer layer, the substrate is etched to obtain word line trenches.

[0007] According to some embodiments of this disclosure, etching the third protective layer from its top surface until the top surface of the sacrificial layer and the top surface of the second mask layer located in the marking region are exposed, while retaining a portion of the third protective layer on the second mask layer located in the array region, includes: the thickness of the remaining third protective layer in the array region is the same as the thickness of the sacrificial layer.

[0008] According to some embodiments of this disclosure, etching the sacrificial layer, the second mask layer located in the marked region, and the third protective layer located in the array region until the top surface of the second protective layer and the top surface of the second mask layer located in the array region are exposed, including: the top surface of the second mask layer located in the array region is flush with the top surface of the first mask layer.

[0009] According to some embodiments of this disclosure, removing the second protective layer and etching the sacrificial layer from its top surface until the top surface of the first protective layer is exposed includes: etching the second protective layer, the sacrificial layer, the second mask layer, and the first mask layer located in the marker region until the top surface of the first mask layer located in the array region is exposed; and etching the sacrificial layer from its top surface until the top surface of the first protective layer is exposed.

[0010] According to some embodiments of this disclosure, etching the second protective layer, the sacrificial layer, the second mask layer, and the first mask layer located in the marked region until the top surface of the first mask layer is exposed includes: the top surface of the remaining second mask layer exposed in the array region is lower than the top surface of the sacrificial layer.

[0011] According to some embodiments of this disclosure, etching the second protective layer, the sacrificial layer, the second mask layer, and the first mask layer located in the marked area until the top surface of the first mask layer is exposed includes: the top surface of the remaining second mask layer exposed in the marked area is flush with the top surface of the first mask layer.

[0012] According to some embodiments of this disclosure, the step of patterning the first protective layer and the pattern transfer layer using the first mask layer and the second mask layer as masks to transfer the first preset pattern and the second preset pattern to the pattern transfer layer includes: removing a portion of the first protective layer and the pattern transfer layer, exposing a portion of the top surface of the substrate between two adjacent remaining pattern transfer layers; removing the first mask layer, the second mask layer, and the sacrificial layer to expose the top surface of the first protective layer.

[0013] According to some embodiments of this disclosure, etching the third protective layer from the top surface of the third protective layer includes: dry etching the third protective layer using carbon tetrafluoride gas and trifluoromethane gas.

[0014] According to some embodiments of this disclosure, etching the sacrificial layer, the second mask layer located in the marked region, and the third protective layer located in the array region includes: dry etching the sacrificial layer using oxygen, carbon tetrafluoride gas, and trifluoromethane gas.

[0015] According to some embodiments of this disclosure, the etching of the second protective layer, the sacrificial layer, the second mask layer, and the first mask layer located in the marked region includes: dry etching of the second protective layer using carbon difluoride gas and sulfur hexafluoride gas.

[0016] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects: by removing part of the sacrificial layer of the marker area, a smaller exposure area of ​​the remaining sacrificial layer of the array area is obtained simultaneously, so that the sacrificial layers of the vertical portions of the array area and the marker area can be removed at the same time, achieving the purpose that the first protective layers of the array area and the marker area can be exposed, which is beneficial to the alignment of the bit line coupling and normally closed contact coverage process.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0019] Figure 1-6 This is a background technical diagram.

[0020] Figure 7 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0021] Figure 8 This is a schematic diagram of a substrate top surface stacked structure in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0022] Figure 9 This is a schematic diagram illustrating the removal of a third protective layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0023] Figure 10 This is a schematic diagram illustrating the removal of a portion of the sacrificial layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0024] Figure 11 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0025] Figure 12 This is a schematic diagram illustrating the removal of a second protective layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0026] Figure 13 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a portion of the sacrificial layer is removed and the top surface of the first protective layer is exposed.

[0027] Figure 14 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0028] Figure 15 This is a schematic diagram illustrating the removal of a portion of the first protective layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0029] Figure 16 This is a schematic diagram of a patterned pattern transfer layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0030] Figure 17 This is a schematic diagram of a patterned substrate in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0031] Figure Labels

[0032] 1. Substrate; 11. Substrate; 12. Oxide layer; 13. Pattern transfer layer; 2. First protective layer; 3. First mask layer; 4. Sacrificial layer; 5. Second protective layer; 6. Third protective layer; 7. Second mask layer. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0034] As stated in the background section, currently, referring to Figure 1 The embedded lettering process specifically includes:

[0035] S100, Provide a substrate, refer to Figure 1 , attached Figure 1The uppermost part of the illustration represents the array area, while the lowermost part represents the marker area; this also applies unless otherwise specified in other accompanying figures. (See reference...) Figure 2 The substrate includes an array region and a marker region. The substrate has a stacked pattern transfer layer, a first protective layer, a first mask layer, a second protective layer, a sacrificial layer, a second mask layer, and a third protective layer.

[0036] S200, remove part of the third protective layer and part of the sacrificial layer, refer to... Figure 3 The top surface of the remaining sacrificial layer is exposed, as is the top surface of the second protective layer. Simultaneously, a portion of the second mask layer is removed in the marked area, and the top surface of the second mask layer exposed in the marked area is flush with the top surface of the second protective layer.

[0037] S300, Remove some of the remaining sacrificial layers, refer to... Figure 4 The top surface of the first protective layer is exposed in the array region.

[0038] S400, Remove part of the first protective layer, refer to... Figure 5 The top surface of a portion of the diamond carbon layer is exposed in the array region.

[0039] S500, Remove some graphic transfer layers, refer to... Figure 6 The top surface of the exposed base is partially exposed.

[0040] The aforementioned process has the problem of damage to overlay and alignment marks, which prevents the formation of pathways and affects the alignment of semiconductor devices.

[0041] Based on this, the present disclosure provides a method for fabricating a semiconductor structure. By removing part of the third protective layer and part of the sacrificial layer in stages, a smaller exposure area of ​​the remaining sacrificial layer in the array region can be obtained. This makes the exposure area of ​​the remaining sacrificial layer in the array region even smaller after removing the second protective layer. At the same time, part of the sacrificial layer in the marker region is removed. This allows the sacrificial layers of the vertical portions of the array region and the marker region to be removed simultaneously when removing part of the remaining sacrificial layer under the same conditions. This exposes the first protective layers of both the array region and the marker region, which is beneficial for the alignment of bit line coupling and normally closed contact coverage processes.

[0042] This disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments, such as... Figure 7 As shown, Figure 7 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment; Figure 8 This is a schematic diagram of a substrate top surface stacked structure in a method for fabricating a semiconductor structure according to an exemplary embodiment; Figure 9 This is a schematic diagram illustrating the removal of a third protective layer in a method for fabricating a semiconductor structure according to an exemplary embodiment; Figure 10This is a schematic diagram illustrating the removal of a portion of the sacrificial layer in a method for fabricating a semiconductor structure according to an exemplary embodiment; Figure 11 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment; Figure 12 This is a schematic diagram illustrating the removal of a second protective layer in a method for fabricating a semiconductor structure according to an exemplary embodiment; Figure 13 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a portion of the sacrificial layer is removed and the top surface of the first protective layer is exposed; Figure 14 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment; Figure 15 This is a schematic diagram illustrating the removal of a portion of the first protective layer in a method for fabricating a semiconductor structure according to an exemplary embodiment; Figure 16 This is a schematic diagram of a patterned pattern transfer layer in a method for fabricating a semiconductor structure according to an exemplary embodiment; Figure 17 This is a schematic diagram of a patterned substrate in a method for fabricating a semiconductor structure according to an exemplary embodiment. The following is in conjunction with... Figures 7 to 17 To explain.

[0043] The specific embodiments described below are intended to help those skilled in the art understand this embodiment, but this embodiment is not limited to the specific embodiments described below.

[0044] Reference Figure 7 This disclosure provides an exemplary embodiment of a method for fabricating a semiconductor structure, referring to... Figure 7 Methods for fabricating semiconductor structures include:

[0045] S100. A substrate is provided, the substrate including an array region and a marker region. The substrate has a pattern transfer layer, a first protective layer, a first mask layer, a second protective layer, a sacrificial layer, a second mask layer, and a third protective layer stacked sequentially. The first mask layer has a first preset pattern, the first preset pattern including a plurality of first strip patterns spaced apart along a first direction. The second protective layer covers the top surface of the first mask layer. The sacrificial layer covers the first protective layer, the first mask layer, and the second protective layer. The second mask layer has a second preset pattern, the second preset pattern including a plurality of second strip patterns spaced apart along the first direction. Each second strip pattern is located between two adjacent first strip patterns. The third protective layer covers the sacrificial layer and the second mask layer. The top surface of the second mask layer in the marker region is higher than the top surface of the second mask layer in the array region.

[0046] For example, refer to Figure 8The substrate 1 serves as the support base. The substrate 1 includes a substrate 11 and an oxide layer 12 covering the top surface of the substrate 11. A pattern transfer layer 13 covers the top surface of the oxide layer 12. A first protective layer 2 covers the pattern transfer layer 13. A first mask layer 3 covers a portion of the first protective layer 2. A sacrificial layer 4 covers the first mask layer 3 and the remaining portion of the first protective layer 2. A second mask layer 7 covers a portion of the sacrificial layer 4. A third protective layer 6 covers the second mask layer 7 and the remaining portion of the sacrificial layer 4.

[0047] S200: Etch the third protective layer from the top surface of the third protective layer until the top surface of the sacrificial layer and the top surface of the second mask layer in the marker area are exposed, while retaining part of the third protective layer on the second mask layer in the array area.

[0048] For example, refer to Figure 8 and Figure 9 Since the top surfaces of the first mask layer 3 and the second mask layer 7 in the array region are flush, and the second protective layer 5 and part of the sacrificial layer 4 both cover the first mask layer 3, the sacrificial layer 4 extends in a Z-shape. The sacrificial layer 4 includes a top horizontal segment positioned above the second protective layer 5, a vertical segment between the first mask layer 3 and the second mask layer 7, and a bottom horizontal segment below the second mask layer 7. Part of the third protective layer 6 extends towards the substrate 1 to the region between two adjacent vertical segments of the sacrificial layer 4 above the second mask layer 7. In the marking region, the top surface of the second mask layer 7 is flush with the top surface of the sacrificial layer 4 in the top horizontal segment, and the third protective layer 6 simultaneously covers the top surfaces of the sacrificial layer 4 in the top horizontal segment and the second mask layer 7.

[0049] In this embodiment, the third protective layer 6 above the sacrificial layer 4 in the top horizontal segment of the array region is removed, while the sacrificial layer 4 is retained. Simultaneously, a portion of the third protective layer 6 filling the area between two adjacent vertical sacrificial layers 4 above the second mask layer 7 is removed. All the third protective layers 6 in the marking region are removed, while both the sacrificial layer 4 and the second mask layer 7 are retained. The portion of the third protective layer 6 retained in the area between two adjacent vertical sacrificial layers 4 above the second mask layer 7 in the array region can protect the second mask layer 7 in subsequent steps, allowing more of the second mask layer 7 to be retained. This results in a smaller exposed vertical segment of the sacrificial layer 4 in the array region, enabling the rate at which the vertical sacrificial layer 4 in the array region is removed in subsequent steps to more closely approximate the disappearance rate of the vertical sacrificial layer 4 in the marking region. This achieves the goal of simultaneously exposing a portion of the top surface of the first protective layer 2 in both the array region and the marking region.

[0050] S300, etching the sacrificial layer, the second mask layer located in the marked area, and the third protective layer located in the array area, until the top surface of the second protective layer and the top surface of the second mask layer located in the array area are exposed.

[0051] For example, refer to Figure 9 and Figure 10 In the array region, the sacrificial layer 4 of the top horizontal segment is removed, exposing the top surface of the vertical segment sacrificial layer 4 and the top surface of the second protective layer 5. During this process, the portion of the third protective layer 6 retained above the second mask layer 7 in the previous step is also removed, exposing the top surface of the second mask layer 7. In the marking region, the sacrificial layer 4 of the top horizontal segment is removed, exposing the top surface of the vertical segment sacrificial layer 4 and the top surface of the second protective layer 5. Since the top surface of the sacrificial layer 4 retained in the previous step is flush with the top surface of the second mask layer 7, a portion of the second mask layer 7 is removed simultaneously with the removal of the sacrificial layer 4 of the top horizontal segment.

[0052] In this embodiment, the sacrificial layer 4 of the top horizontal segment is removed by etching process with the top surface of the second protective layer 5 as the stop surface. Since the selectivity of the etching medium for the sacrificial layer 4 of the top horizontal segment is the same as the selectivity of the third protective layer 6 retained above the second mask layer 7 in the previous step, the sacrificial layer 4 of the vertical segment with a smaller exposed height can be obtained in the array area. This makes the rate at which the sacrificial layer 4 of the vertical segment of the array area is removed in the subsequent steps closer to the disappearance rate of the sacrificial layer 4 of the vertical segment of the marker area, thereby achieving the purpose of simultaneously exposing the top surface of part of the first protective layer 2 on the array area and the marker area.

[0053] S400: Remove the second protective layer and etch the sacrificial layer from the top surface of the sacrificial layer until the top surface of the first protective layer is exposed.

[0054] For example, refer to Figure 11 and Figure 12 During the process of removing the second protective layer 5 in the array region, the portion of the vertical segment sacrificial layer 4 covering both sides of the second protective layer 5 is also removed. Since the top surface of the second mask layer 7 in the array region is exposed in the previous step, the second mask layer 7 will be removed along with the second protective layer 5 and the vertical segment sacrificial layer 4 during this process.

[0055] During the process of removing the second protective layer 5 in the marked area, the portion of the vertical segment sacrificial layer 4 covering both sides of the second protective layer 5 is also removed. Since the top surface of the second mask layer 7 in the array area is exposed in the previous step, the second mask layer 7 will be removed along with the second protective layer 5 and the vertical segment sacrificial layer 4 during this process.

[0056] With the complete removal of the sacrificial layer 4 in the vertical section, the sidewalls of the first mask layer 3, the sidewalls of the second mask layer 7, and part of the outer wall of the sacrificial layer 4 in the bottom horizontal section are exposed, and the top surface of the first protective layer 2 is exposed between the adjacent first mask layer 3 and second mask layer 7.

[0057] In this embodiment, the second protective layer 5 and the sacrificial layer 4 of the vertical segment are removed by an etching process. Since the selectivity of the etching medium for the second protective layer 5 and the sacrificial layer 4 of the vertical segment is different from that for the second mask, the height of the second mask removed in the array region is less than the height of the second protective layer 5. Combined with the protection of the second mask layer 7 by the third protective layer 6 when etching the sacrificial layer 4 in the aforementioned step S300, a sacrificial layer 4 of the vertical segment with a smaller exposed height in the array region is obtained. This makes the rate at which the sacrificial layer 4 of the vertical segment in the array region is removed closer to the disappearance rate of the sacrificial layer 4 of the vertical segment in the marker region, thereby achieving the purpose of simultaneously exposing part of the top surface of the first protective layer 2 on the array region and the marker region.

[0058] S500: Using the first mask layer and the second mask layer as masks, pattern the first protective layer and the pattern transfer layer to transfer the first preset pattern and the second preset pattern to the pattern transfer layer.

[0059] For example, refer to Figure 13 , Figure 15 and Figure 16 Remove the portion of the first protective layer 2 exposed between the adjacent first mask layer 3 and second mask layer 7, and simultaneously remove the portion of the pattern transfer layer 13 below this location.

[0060] In this embodiment, after the patterned transfer layer 13 is patterned, the first mask layer 3, the second mask layer 7 and the remaining sacrificial layer 4 are removed by an etching process with the top surface of the first protective layer 2 as the stop surface, so that the remaining first protective layer 2 covering the top surface of the pattern transfer layer 13 is exposed.

[0061] S600: Based on the patterned pattern transfer layer, the substrate is etched to obtain word line trenches.

[0062] For example, refer to Figure 17 Using the patterned pattern transfer layer 13 as a mask, the substrate 11 is patterned, and the oxide layer 12 on the top surface of the substrate 11 is etched into the interior of the substrate 11 to obtain word line trenches.

[0063] In this embodiment, after patterning the substrate 11, the pattern transfer layer 13 is removed by etching, with the top surface of the oxide layer 12 as the stop surface.

[0064] In this embodiment, by removing part of the third protective layer 6 and part of the sacrificial layer 4 in stages, a smaller exposed area of ​​the remaining sacrificial layer 4 in the array region can be obtained. This makes the exposed area of ​​the remaining sacrificial layer 4 in the array region even smaller after removing the second protective layer 5. At the same time, part of the sacrificial layer 4 in the marker region is removed. This ensures that when removing part of the remaining sacrificial layer 4 under the same conditions, the sacrificial layer 4 in the vertical portion of the array region and the marker region can be removed simultaneously. This allows the first protective layer 2 of both the array region and the marker region to be exposed, which is beneficial for the alignment of bit line coupling and normally closed contact coverage processes.

[0065] In an exemplary embodiment of this disclosure, reference is made to Figure 9 Step S200: Etch the third protective layer from its top surface until the top surface of the sacrificial layer and the top surface of the second mask layer located in the marker region are exposed, retaining a portion of the third protective layer on the second mask layer in the array region, including:

[0066] The thickness of the remaining third protective layer in the array region is the same as the thickness of the sacrificial layer.

[0067] For example, refer to Figure 9 The third protective layer 6 above the sacrificial layer 4 in the top horizontal segment of the array region is removed, while the sacrificial layer 4 is retained. At the same time, part of the third protective layer 6 filling the area between two adjacent vertical sacrificial layers 4 above the second mask layer 7 is removed, and the thickness of the retained part of the third protective layer 6 is the same as the thickness of the sacrificial layer 4 in the top horizontal segment.

[0068] In this embodiment, the portion of the third protective layer 6 in the area between two adjacent vertical sacrificial layers 4 above the second mask layer 7 in the array region can protect the second mask layer 7 in subsequent steps. During the subsequent removal of the top horizontal sacrificial layer 4, the third protective layer 6 retained on the second mask layer 7 is completely removed, while retaining as much of the second mask layer 7 as possible. This allows for the acquisition of a smaller vertical sacrificial layer 4 exposed in the array region, enabling the rate at which the vertical sacrificial layer 4 in the array region is removed in subsequent steps to be closer to the disappearance rate of the vertical sacrificial layer 4 in the marking region. This achieves the goal of simultaneously exposing the top surface of the first protective layer 2 on both the array region and the marking region.

[0069] In an exemplary embodiment of this disclosure, reference is made to Figure 9 and Figure 10 Step S300, etching the sacrificial layer, the second mask layer located in the marked area, and the third protective layer located in the array area, until the top surface of the second protective layer and the top surface of the second mask layer located in the array area are exposed, includes:

[0070] The top surface of the second mask layer located in the array region is flush with the top surface of the first mask layer.

[0071] For example, the top of the sacrificial layer 4 is etched towards the substrate 1. At the same time that the top horizontal section of the sacrificial layer 4 is etched, the third protective layer 6 covering the second mask layer 7 is also etched. When the top horizontal section of the sacrificial layer 4 is etched away, the third protective layer 6 covering the second mask layer 7 is also etched away, and the top surface of the second mask layer 7 is exposed.

[0072] In this embodiment, the third protective layer 6 covering the second mask layer 7 can protect the second mask layer 7, reducing the possibility that the second mask layer 7 will be simultaneously etched during the etching of the top horizontal section sacrificial layer 4. That is, it reduces the exposed area of ​​the sacrificial layer 4 in the vertical section of the array area. As a result, the sacrificial layer 4 in the vertical section with a smaller exposed height can be obtained in the array area. This allows the rate at which the sacrificial layer 4 in the vertical section of the array area is removed in subsequent steps to be closer to the disappearance rate of the sacrificial layer 4 in the vertical section of the marker area. This achieves the purpose of simultaneously exposing part of the top surface of the first protective layer 2 on the array area and the marker area.

[0073] In an exemplary embodiment of this disclosure, reference is made to Figure 11 Step S400, removing the second protective layer and etching the sacrificial layer from its top surface until the top surface of the first protective layer is exposed, specifically includes:

[0074] S410, etch the second protective layer, sacrificial layer, second mask layer and the first mask layer located in the marker area until the top surface of the first mask layer located in the array area is exposed.

[0075] For example, refer to Figure 10 and Figure 12 The second protective layer 5 is etched from the top surface of the second protective layer 5, and the sacrificial layer 4 and the second mask layer 7 are etched simultaneously. The first mask layer 3 is used as the etching stop surface, so that the top surface of the first mask layer 3, the top surface of the sacrificial layer 4 in the remaining vertical section and the top surface of the remaining second mask layer 7 are exposed.

[0076] S420: Etch the sacrificial layer from the top surface of the sacrificial layer until the top surface of the first protective layer is exposed.

[0077] For example, refer to Figure 12 and Figure 13 Remove the remaining vertical section of the sacrificial layer 4, exposing the sidewalls of the first mask layer 3, the sidewalls of the second mask layer 7, and part of the outer wall of the bottom horizontal section of the sacrificial layer 4. The top surface of the first protective layer 2 is exposed between the adjacent first mask layer 3 and second mask layer 7.

[0078] In this embodiment, an etching process is used to remove the remaining sacrificial layer 4 of the vertical segment with the top surface of the first protective layer 2 as the stop surface. Since the top surface of the second mask layer 7 retained in the array region in the previous step is lower than the top surface of the first mask layer 3, the exposed area of ​​the sacrificial layer 4 of the vertical segment in the array region is greater than the exposed area of ​​the sacrificial layer 4 of the vertical segment in the marking region. Since the top surface of the sacrificial layer 4 of the vertical segment retained in the marking region is lower than the top surface of the first mask layer 3, the disappearance rate of the sacrificial layer 4 of the vertical segment in the array region is equal to the disappearance rate of the sacrificial layer 4 of the vertical segment in the marking region during the removal of the remaining sacrificial layer 4 of the vertical segment. That is, the top surfaces of the portion of the first protective layer 2 in the array region and the portion of the first protective layer 2 in the marking region can be exposed by one etching process, which is beneficial to the alignment of the bit line coupling and normally closed contact coverage process of the semiconductor structure.

[0079] In an exemplary embodiment of this disclosure, reference is made to Figure 10 and Figure 12 Step S400, etching the second protective layer, the sacrificial layer, the second mask layer, and the first mask layer located in the marked area until the top surface of the first mask layer is exposed, specifically includes:

[0080] The top surface of the remaining second mask layer exposed in the array region is lower than the top surface of the sacrificial layer.

[0081] Exemplary, exemplary, reference Figure 10 and Figure 12 During the process of removing the second protective layer 5 in the array region, the portion of the vertical segment sacrificial layer 4 covering both sides of the second protective layer 5 is also removed. Since the top surface of the second mask layer 7 in the array region is exposed in the previous step, the second mask layer 7 will be removed along with the second protective layer 5 and the vertical segment sacrificial layer 4 during this process.

[0082] In this embodiment, the second protective layer 5 and the sacrificial layer 4 of the vertical segment are removed by an etching process. Since the selectivity of the etching medium for the second protective layer 5 and the sacrificial layer 4 of the vertical segment is different from that for the second mask, the height of the second mask removed in the array region is less than the height of the second protective layer 5. This results in a sacrificial layer 4 of the vertical segment with a smaller exposed height in the array region. This allows the rate at which the sacrificial layer 4 of the vertical segment of the array region is removed in subsequent steps to be closer to the disappearance rate of the sacrificial layer 4 of the vertical segment of the marker region. This achieves the goal of simultaneously exposing part of the top surface of the first protective layer 2 on the array region and the marker region.

[0083] In an exemplary embodiment of this disclosure, reference is made to Figure 10 and Figure 12 Step S400, etching the second protective layer, the sacrificial layer, the second mask layer, and the first mask layer located in the marked area until the top surface of the first mask layer is exposed, specifically includes:

[0084] The top surface of the remaining second mask layer exposed in the marked area is flush with the top surface of the first mask layer.

[0085] For example, refer to Figure 10 and Figure 12 During the process of removing the second protective layer 5 in the marked area, the portion of the vertical segment sacrificial layer 4 covering both sides of the second protective layer 5 is also removed. Since the top surface of the second mask layer 7 in the array area is exposed in the previous step, the second mask layer 7 will be removed along with the second protective layer 5 and the vertical segment sacrificial layer 4 during this process.

[0086] In this embodiment, the second protective layer 5 and the sacrificial layer 4 of the vertical section are removed by etching. Since the selectivity of the etching medium for the second protective layer 5 and the sacrificial layer 4 of the vertical section is different from that for the second mask, the rate at which the second mask is removed in the marked area is less than the rate at which the second protective layer 5 is removed. When the top surface of the remaining sacrificial layer 4 exposed in the marked area is lower than the top surface of the first mask layer 3, the top surface of the second mask layer 7 is closer to being flush with the top surface of the first mask layer 3, which facilitates the continued processing in subsequent steps.

[0087] Those skilled in the art should understand after reading the above content that, in this embodiment, the etching stop surfaces of the second protective layer 5 and the vertical segment sacrificial layer 4 are located on the first mask layer 3, and can be changed according to different working conditions, so as to obtain a vertical segment sacrificial layer 4 with a smaller exposed area in the array area, and to obtain a vertical segment sacrificial layer 4 with a top surface lower than the top surface of the first mask layer 3 in the marking area.

[0088] In an exemplary embodiment of this disclosure, reference is made to Figure 14 Step S600, using the first mask layer and the second mask layer as masks, patterning the first protective layer and the pattern transfer layer to transfer the first preset pattern and the second preset pattern to the pattern transfer layer includes:

[0089] S610, Remove part of the first protective layer and the pattern transfer layer, and expose part of the top surface of the substrate between the two adjacent remaining pattern transfer layers.

[0090] For example, refer to Figure 15 and Figure 16 The first protective layer 2 is etched from the top surface of the first protective layer 2, with the pattern transfer layer 13 as the stop surface. The top surface of the pattern transfer layer 13 is exposed between the adjacent first mask layer 3 and second mask layer 7. The pattern transfer layer 13 is etched from the exposed top surface of the pattern transfer layer 13, with the oxide layer 12 on the top surface of the substrate 11 as the stop surface, and the oxide layer 12 covering the top surface of the substrate 11 is exposed.

[0091] S620: Remove the first mask layer, the second mask layer, and the sacrificial layer to expose the top surface of the first protective layer.

[0092] For example, refer to Figure 17 The first mask layer 3 is etched from the top surface of the first mask layer 3, and the second mask layer 7 and the sacrificial layer 4 are etched simultaneously, with the top surface of the first protective layer 2 as the stop surface, so that the top surface of the first protective layer 2 is exposed.

[0093] In this embodiment, the final retained structure is a substrate 11, a pattern transfer layer 13 covering the top surface of the substrate 11, and a first protective layer 2 covering the top surface of the pattern transfer layer 13. By using the pattern transfer as a mask, the substrate 11 can be patterned, ultimately forming word line trenches.

[0094] In an exemplary embodiment of this disclosure, reference is made to Figure 8 and Figure 9 Step S200, etching the third protective layer from the top surface of the third protective layer, specifically includes:

[0095] The third protective layer is dry etched using carbon tetrafluoride gas and trifluoromethane gas.

[0096] In an exemplary embodiment of this disclosure, the flow rates of both carbon tetrafluoride gas and trifluoromethane gas are 45-55 sccm, the temperatures of both gas are 35-45°C, the pressures of both are 18-22 mt, and the average power of dry etching is 860-880 W.

[0097] For example, the flow rates of both carbon tetrafluoride gas and trifluoromethane gas are 50 sccm, the temperatures of both gas are 40°C, the pressures of both are 20 mt, and the average power of dry etching is 880 W.

[0098] In an exemplary embodiment of this disclosure, reference is made to Figure 9 and Figure 10 Step S300, etching the sacrificial layer, the second mask layer located in the marked area, and the third protective layer located in the array area specifically include:

[0099] Dry etching of the sacrificial layer is performed using oxygen, carbon tetrafluoride gas, and trifluoromethane gas.

[0100] In an exemplary embodiment of this disclosure, the oxygen flow rate is 7-13 scm, the flow rates of both carbon tetrafluoride gas and trifluoromethane gas are 45-55 sccm, the temperatures of both carbon tetrafluoride gas and trifluoromethane gas are 35-45°C, the pressures of all three gases are 18-22 mt, and the average power of the dry etching process is 780-820 W.

[0101] For example, the oxygen flow rate is 10 scm, the flow rates of carbon tetrafluoride gas and trifluoromethane gas are both 50 sccm, the temperature of carbon tetrafluoride gas and trifluoromethane gas is 40°C, the pressure of oxygen gas, carbon tetrafluoride gas and trifluoromethane gas is 20 mt, and the average power of dry etching is 800 W.

[0102] In this embodiment, a lower flow rate, such as 10 scm of oxygen, can reduce the consumption of the second mask layer 7 in the array region during the etching process, that is, to obtain a sacrificial layer 4 with a smaller vertical segment exposed in the array region. This allows the rate at which the sacrificial layer 4 in the vertical segment of the array region is removed in subsequent steps to be closer to the disappearance rate of the sacrificial layer 4 in the vertical segment of the marker region, thereby achieving the purpose of simultaneously exposing part of the top surface of the first protective layer 2 on the array region and the marker region.

[0103] In an exemplary embodiment of this disclosure, reference is made to Figure 10 and Figure 12 Step S400, etching the second protective layer, the sacrificial layer, the second mask layer, and the first mask layer located in the marked area specifically includes:

[0104] The second protective layer is dry etched using carbon difluoride gas and sulfur hexafluoride gas.

[0105] For example, carbon difluoride gas and sulfur hexafluoride gas are used to etch the second protective layer, the sacrificial layer, the second mask layer, and the first mask layer located in the marker region until the top surface of the first mask layer located in the array region is exposed.

[0106] In this embodiment, the selectivity of carbon difluoride gas and sulfur hexafluoride gas for the first mask layer 3 and the second mask layer 7 is greater than that for the second protective layer 5 and the sacrificial layer 4. Therefore, it can reduce the loss of the first mask layer 3 and the second mask layer 7 during the etching process. This reduces the possibility that the second mask layer 7 in the array area will be etched through due to excessive loss of the second mask layer 7 in the previous step during the etching of the first protective layer 2, which would affect the subsequent patterned transfer layer 13.

[0107] In an exemplary embodiment of this disclosure, the flow rate of carbon difluoride gas is 62-72 sccm, the flow rate of sulfur hexafluoride gas is 15-21 sccm, the temperature of both carbon difluoride gas and sulfur hexafluoride gas is 30-40°C, the pressure of both carbon tetrafluoride gas and trifluoromethane gas is 4-6 mt, and the average power of dry etching is 480-520 W.

[0108] For example, the flow rate of carbon difluoride gas is 67 sccm, the flow rate of sulfur hexafluoride gas is 18 sccm, the temperature of both carbon difluoride gas and sulfur hexafluoride gas is 35°C, the pressure of both carbon tetrafluoride gas and trifluoromethane gas is 5 mt, and the average power of dry etching is 500 W.

[0109] In an exemplary embodiment of this disclosure, reference is made to Figure 12 and Figure 13 Step S500, etching the top surface of the self-sacrificing layer, specifically includes:

[0110] Dry etching of the sacrificial layer was performed using oxygen and perfluorobutadiene gas. The flow rate of oxygen was 5-11 sccm, the flow rate of perfluorobutadiene gas was 14-20 sccm, the temperature of both oxygen and perfluorobutadiene gas was 30-40℃, the pressure of both oxygen and perfluorobutadiene gas was 5-9 mt, and the average power of dry etching was 480-520 W.

[0111] For example, the oxygen flow rate is 8 sccm, the perfluorobutadiene gas flow rate is 17 sccm, the temperature of both oxygen and perfluorobutadiene gas is 35°C, the pressure of both oxygen and perfluorobutadiene gas is 7 mt, and the average power of dry etching is 500 W.

[0112] In this embodiment, perfluorobutadiene gas tends to form polymers during the etching process. Selecting a lower flow rate, such as 17 sccm of perfluorobutadiene gas, can increase the selectivity of the first mask layer 3 and the second mask layer 7, reduce the generation of polymers during the etching process, and thus reduce the possibility of polymer clogging the channels and causing the etching to stop.

[0113] In an exemplary embodiment of this disclosure, reference is made to Figure 13 The thickness of the first protective layer 2 is 20-30nm.

[0114] In this embodiment, refer to Figure 15 and Figure 16 The first protective layer 2 covers the top surface of the pattern transfer layer 13. The thinner first protective layer 2 can be etched faster and more stably, so that part of the top surface of the pattern transfer layer 13 is exposed between the first mask layer 3 and the second mask layer 7, which facilitates the patterning of the pattern transfer layer 13 using the first mask layer 3 and the second mask layer 7 as masks, so that the pattern transfer layer 13 can stably form a mask for patterning the substrate 11.

[0115] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0116] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A method of fabricating a semiconductor structure, the method comprising: The application relates to a substrate manufacturing method. The substrate comprises an array area and a mark area, and has a pattern transfer layer, a first protective layer, a first mask layer, a second protective layer, a sacrificial layer, a second mask layer and a third protective layer stacked in sequence. The first mask layer has a first preset pattern, and the first preset pattern comprises a plurality of first strip patterns arranged at intervals along a first direction. The second protective layer covers the top surface of the first mask layer, the sacrificial layer covers the first protective layer, the first mask layer and the second protective layer, the second mask layer has a second preset pattern, the second preset pattern comprises a plurality of second strip patterns arranged at intervals along the first direction, and each second strip pattern is located between two adjacent first strip patterns. The third protective layer covers the sacrificial layer and the second mask layer, wherein the top surface of the second mask layer in the mark area is higher than the top surface of the second mask layer in the array area. The third protective layer is etched from the top surface of the third protective layer until the top surface of the sacrificial layer and the top surface of the second mask layer in the mark area are exposed, and part of the third protective layer on the second mask layer in the array area is reserved. The sacrificial layer, the second mask layer in the mark area and the third protective layer in the array area are etched until the top surface of the second protective layer and the top surface of the second mask layer in the array area are exposed. The second protective layer is removed, and the sacrificial layer is etched from the top surface of the sacrificial layer until the top surface of the first protective layer is exposed. The first protective layer and the pattern transfer layer are patterned with the first mask layer and the second mask layer as masks, so as to transfer the first preset pattern and the second preset pattern to the pattern transfer layer. Based on the patterned pattern transfer layer, the substrate is etched to obtain a word line trench.

2. The method of fabricating a semiconductor structure of claim 1, wherein, The thickness of the remaining third protective layer in the array area is consistent with the thickness of the sacrificial layer. The top surface of the second mask layer in the array area is flush with the top surface of the first mask layer.

3. The method of fabricating a semiconductor structure of claim 1, wherein, The second protective layer, the sacrificial layer, the second mask layer and the first mask layer in the mark area are etched until the top surface of the first mask layer in the array area is exposed. The second protective layer is removed, and the sacrificial layer is etched from the top surface of the sacrificial layer until the top surface of the first protective layer is exposed.

4. The method of fabricating a semiconductor structure of claim 1, wherein, ​ ​ etching the sacrificial layer from a top surface of the sacrificial layer until a top surface of the first protective layer is exposed.

5. The method of fabricating a semiconductor structure of claim 4, wherein, The etching the second protective layer, the sacrificial layer, the second mask layer and the first mask layer in the mark region until a top surface of the first mask layer is exposed comprises: a top surface of the remaining second mask layer exposed in the array region is lower than a top surface of the sacrificial layer.

6. The method of fabricating a semiconductor structure of claim 4, wherein, The etching the second protective layer, the sacrificial layer, the second mask layer and the first mask layer in the mark region until a top surface of the first mask layer is exposed comprises: a top surface of the remaining second mask layer exposed in the mark region is flush with a top surface of the first mask layer.

7. The method of fabricating a semiconductor structure of claim 4, wherein, The etching the second protective layer, the sacrificial layer, the second mask layer and the first mask layer in the mark region comprises: dry etching the second protective layer using carbon difluoride gas and sulfur hexafluoride gas.

8. The method of fabricating a semiconductor structure of claim 1, wherein, The patterning the first protective layer and the pattern transfer layer using the first mask layer and the second mask layer as masks to transfer the first pre-set pattern and the second pre-set pattern to the pattern transfer layer comprises: removing part of the first protective layer and the pattern transfer layer, and part of a top surface of the substrate is exposed between two remaining pattern transfer layers adjacent to each other; removing the first mask layer, the second mask layer and the sacrificial layer to expose a top surface of the first protective layer.

9. The method of fabricating a semiconductor structure of claim 1, wherein, The etching the third protective layer from a top surface of the third protective layer comprises: dry etching the third protective layer using carbon tetrafluoride gas and trifluoromethane gas.

10. The method of fabricating a semiconductor structure of claim 1, wherein, The etching the sacrificial layer, the second mask layer in the mark region and the third protective layer in the array region comprises: dry etching the sacrificial layer using oxygen gas, carbon tetrafluoride gas and trifluoromethane gas.

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