Semiconductor processing tool and method of operating the same

Abstract

A semiconductor processing tool and method of operation thereof, some embodiments described herein provide techniques and apparatuses for a semiconductor processing tool including an electrostatic chuck having a voltage adjustment system for adjusting an electrical potential in an entire area of a semiconductor substrate positioned above the electrostatic chuck. The voltage adjustment system can determine that an electrical potential within an area of the semiconductor substrate does not satisfy a threshold value. The voltage adjustment system can position one or more electrically conductive pins within the area based on determining that the electrical potential in the entire area does not satisfy the threshold value. The one or more electrically conductive pins, when positioned within the area, can change the electrical potential of the area.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor processing tool and a method of operating the same. BACKGROUND

[0002] A semiconductor processing tool can include an electrostatic chuck (ESC) that supports a semiconductor substrate for processing. For example, a scanning electron microscope (SEM) can include an ESC that temporarily captures and positions a semiconductor substrate over the ESC for inspection. While the semiconductor substrate is temporarily supported over the ESC, one or more electron beams of the SEM can scan the semiconductor substrate for defects such as contaminants, material bridging, or incorrect feature sizes, among other examples. SUMMARY

[0003] According to some embodiments of the present disclosure, a method of operating a semiconductor processing tool includes receiving, by a controller from a sensor associated with a region of a semiconductor substrate supported by an electrostatic chuck, a first signal including voltage measurement data; determining, by the controller based on the voltage measurement data, that a potential of the region does not satisfy a threshold value; transmitting, by the controller based on determining that the potential does not satisfy the threshold value, a second signal to cause a pin positioning subsystem to position a tip of a set of electrically conductive pins within the region and a third signal to activate a power source such that the set of electrically conductive pins transfers a charge to the region to cause the potential of the region to satisfy the threshold value.

[0004] According to some embodiments of the present disclosure, a method of operating a semiconductor processing tool includes receiving, by a controller from a sensor, a first signal including voltage measurement data; identifying, by the controller based on the voltage measurement data, a positively charged region of a semiconductor substrate supported by an electrostatic chuck; and transmitting, by the controller based on identifying the positively charged region, a second signal including positioning data to a pin positioning subsystem to cause the pin positioning subsystem to position a tip of an electrically conductive pin within the positively charged region and a third signal to adjust a setting of a power source such that the electrically conductive pin transfers a negative charge to the positively charged region to neutralize a positive charge.

[0005] According to some embodiments of the present disclosure, a semiconductor processing tool includes an electrostatic chuck comprising an electrode; an array of pin guides through the electrode; and a voltage adjustment system comprising: a pin positioning subsystem; a set of electrically conductive pins; a power supply electrically coupled with the set of electrically conductive pins; and a controller to: determine that a condition associated with an electrical arc discharge between a top side surface of a semiconductor substrate positioned above the electrode and a component of the semiconductor processing tool has occurred; and based on determining that the condition has occurred, transmit: a first signal to cause the pin positioning subsystem to position one or more tips of a corresponding one or more electrically conductive pins of the set of electrically conductive pins near or positioned through one or more pin guide outlets of the array of pin guides; and a second signal to cause the power supply to adjust a setting such that the one or more electrically conductive pins transfer an electrical charge to or from the semiconductor substrate to change an electrical potential of a region of the semiconductor substrate comprising the top side surface. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present disclosure can best be understood by reading the following detailed description in conjunction with the accompanying drawings, in which:

[0007] Figures 1A-1C is a diagram of an exemplary environment in which the voltage adjustment system and related methods described herein can be implemented;

[0008] Figure 2 is a diagram of an exemplary implementation of the array of electrically conductive pins and pin guides described herein;

[0009] Figures 3A-3C and Figures 4A-4C is a diagram of an exemplary implementation of the voltage adjustment system described herein;

[0010] Figure 5A , Figure 5B and Figure 6 is a diagram of an exemplary implementation of the electrically conductive pins described herein;

[0011] Figure 7 is a diagram of exemplary components of one or more devices described herein;

[0012] Figure 8 and Figure 9 is a flowchart of exemplary processes related to a semiconductor processing tool comprising the voltage adjustment system described herein.

[0013] SYMBOL KEY

[0014] 100: environment

[0015] 102: deposition tool

[0016] 104: exposure tool

[0017] 106: developer tool

[0018] 108: etch tool

[0019] 110: planarization tool

[0020] 112: plating tool

[0021] 114: inspection tool

[0022] 116: wafer / die transport tool

[0023] 118: electrostatic chuck / ESC

[0024] 120: semiconductor substrate

[0025] 122: assembly

[0026] 124: electrical ground

[0027] 126: top side surface

[0028] 128, 128a, 128b, 128c, 128d: electrical potential

[0029] 130: semiconductor element

[0030] 132, 132a, 132b: conductive pin

[0031] 134: back side surface

[0032] 136: distance

[0033] 138: electrode

[0034] 140: substrate

[0035] 142, 142a, 142b: pin guide

[0036] 144: region

[0037] 146: voltage adjustment system

[0038] 148: sensor

[0039] 150: power supply

[0040] 152: pin positioning subsystem

[0041] 154, 154a, 154b, 154c, 154d: vertical movement

[0042] 156: lateral movement

[0043] 158: controller

[0044] 160: communication link

[0045] 200: embodiment

[0046] 202: array

[0047] 204, 204a, 204b, 204c: set

[0048] 206: linear spacing

[0049] 300: embodiment

[0050] 302, 304, 306: process

[0051] 400: embodiment

[0052] 402, 404, 406: process

[0053] 500A, 500B: embodiment

[0054] 502: length

[0055] 504: diameter

[0056] 506: pointed tip

[0057] 600: embodiment

[0058] 602: warpage

[0059] 700: apparatus

[0060] 710: bus

[0061] 720: processor

[0062] 730: memory

[0063] 740: input component

[0064] 750: output component

[0065] 760: communication component

[0066] 800: process

[0067] 810, 820, 830: block

[0068] 900: process

[0069] 910, 920, 930: block DETAILED DESCRIPTION

[0070] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. In the following description, for the purposes of explanation, specific details are set forth to provide a thorough understanding of embodiments. However, it will be apparent to one skilled in the art that these specific details are not required in every case and that claims can be practiced without these specific details. For example, in the following description, forming a first feature on or over a second feature can include embodiments in which the first feature is formed in direct contact with the second feature, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features can not be in direct contact. Additionally, the disclosure can refer to various examples using corresponding reference numerals and / or letters. This repetition is for the purpose of simplicity and clarity and does not necessarily dictate a corresponding relationship between the various embodiments and / or configurations discussed.

[0071] Moreover, spatial or directional terms, such as "below," "lower," "bottom," "above," "upper," and the like, can be used in this disclosure to describe one element's or feature's relationship to another element or feature as illustrated in the figures. Spatial and directional terms are used with respect to the orientation of the figure(s) as shown. The spatial and directional terms are used for purposes of illustration and the description, and are not intended to limit the scope of the disclosure. The apparatus(es) can be oriented in other ways (rotated 90 degrees or otherwise) and the spatial and directional terms are interpreted accordingly.

[0072] An electrostatic chuck (ESC) of a semiconductor process tool can support a semiconductor substrate. While the semiconductor substrate is supported by the ESC, an electrical potential (e.g., a charge amount) can be formed in a region of the semiconductor substrate. The electrical potential can cause an electrical arc discharge between the semiconductor substrate and a component of the semiconductor process tool. Additionally or alternatively, the electrical potential can cause an electrical arc discharge between the semiconductor substrate and an electrical ground of the semiconductor process tool.

[0073] The electrical arc discharge can cause damage to the semiconductor substrate and can reduce a yield of semiconductor devices manufactured from the semiconductor substrate. The electrical arc discharge can also damage the semiconductor process tool, which can result in an increased downtime of the semiconductor process tool and / or a reduced throughput of semiconductor devices manufactured using the semiconductor process tool.

[0074] Some embodiments described herein provide a semiconductor manufacturing tool including an ESC (Electronic Stability Control) and a voltage adjustment system. The voltage adjustment system is used to adjust the potential across an entire region of a semiconductor substrate supported by the ESC. The voltage adjustment system can determine that the potential (e.g., charge) in a region of the semiconductor substrate does not meet a threshold value. Based on the determination that the potential in that region does not meet the threshold value, the voltage adjustment system can position one or more conductive pins within that region. The one or more conductive pins can change the potential of the region when positioned within it. In some embodiments, the voltage adjustment system uses varying ranges of vertical movement to position one or more conductive pins to accommodate a degree of warpage in the semiconductor substrate.

[0075] In this way, the voltage regulation system ensures that the potential of the region meets the threshold value. By ensuring that the potential meets the threshold value, the voltage regulation system reduces the possibility of arcing between the semiconductor substrate and the components of the semiconductor process tool. Therefore, the voltage regulation system prevents damage to the semiconductor substrate and / or reduces the possibility of damage, which increases the yield of semiconductor devices manufactured from the semiconductor substrate. Furthermore, the voltage regulation system prevents damage to the semiconductor process tool and / or reduces the possibility of damage, which increases the uptime of the semiconductor process tool and increases the output of semiconductor devices manufactured using the semiconductor process tool.

[0076] Figures 1A-1C This is a diagram of an exemplary environment 100 in which the voltage regulation system and related methods described herein can be implemented. (See diagram 100 for details.) Figure 1A As shown, environment 100 may include multiple semiconductor process tools 102-114 and wafer / die transport tools 116. The multiple semiconductor process tools 102-114 may include deposition tools 102, exposure tools 104, developer tools 106, etching tools 108, planarization tools 110, electroplating tools 112, inspection tools 114, and / or another type of semiconductor process tool. The multiple semiconductor process tools 102-114 included in exemplary environment 100 may be found in semiconductor cleanrooms, semiconductor foundries, semiconductor process facilities and / or manufacturing facilities, and other instances.

[0077] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more elements capable of depositing various types of materials onto a semiconductor substrate. In some embodiments, the deposition tool 102 includes a spin-on tool capable of depositing a photoresist layer onto a semiconductor substrate. In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, a low-pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, the deposition tool 102 includes an epitaxy tool to form layers and / or regions of a device through epitaxial growth. In some embodiments, the exemplary environment 100 includes multiple types of deposition tools 102.

[0078] The exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a source of radiation, such as an ultraviolet (UV) light source (e.g., a deep UV light source, an extreme UV (EUV) light source, and / or the like), an x-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the source of radiation to transfer a pattern from a mask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns for forming one or more semiconductor devices, can include a pattern for forming one or more structures of a semiconductor device, can include a pattern for etching various portions of a semiconductor device, and / or the like. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0079] The developer tool 106 is a semiconductor process tool capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool 104. In some implementations, the developer tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some implementations, the developer tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some implementations, the developer tool 106 develops the pattern by dissolving unexposed or exposed portions of the photoresist layer using a chemical developer.

[0080] The etch tool 108 is a semiconductor process tool capable of etching various types of materials of a semiconductor substrate or a semiconductor element. For example, the etch tool 108 can include a wet etch tool, a dry etch tool, and / or the like. In some implementations, the etch tool 108 includes a chamber filled with an etchant, and a semiconductor substrate is placed in the chamber for a certain period of time to remove a certain amount of one or more portions of the semiconductor substrate. In some implementations, the etch tool 108 can use plasma etching or plasma-assisted etching to etch one or more portions of the semiconductor substrate, which can involve using an ionized gas to isotropically or directionally etch the one or more portions.

[0081] The planarization tool 110 is a semiconductor process tool capable of polishing or planarizing various layers of a semiconductor substrate or a semiconductor element. For example, the planarization tool 110 can include a chemical mechanical planarization (CMP) tool that polishes or planarizes a layer or surface of deposited or plated material, and / or another type of planarization tool. The planarization tool 110 can polish or planarize a surface of a semiconductor element with a combination of chemical and mechanical forces, such as chemical etching and free abrasive polishing. The planarization tool 110 can utilize abrasive and corrosive chemical slurries in conjunction with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor element). The polishing pad and the semiconductor element can be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head can be rotated on different axes of rotation to remove material and level any irregular topography of the semiconductor element, thereby flattening or planarizing the semiconductor element.

[0082] The plating tool 112 is a semiconductor process tool capable of electroplating a semiconductor substrate (e.g., a semiconductor wafer, a semiconductor element, and / or the like) or a portion thereof with one or more metals. For example, the plating tool 112 can include a copper plating device, an aluminum plating device, a nickel plating device, a tin plating device, a composite or alloy (e.g., tin silver, tin lead, and / or the like) plating device, and / or a plating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0083] Inspection tool 114 is a semiconductor process tool capable of inspecting a semiconductor substrate for defects. Defects that can be detected by inspection tool 114 include contaminants, material bridges, incorrect feature sizes (e.g., incorrect critical dimensions) of integrated circuits formed on the semiconductor substrate, pattern misalignment, overlay misalignment, and / or voids and other types of discontinuities, among other examples. By inspecting a semiconductor substrate for defects, inspection tool 114 can provide data and / or feedback to maintain process control over one or more semiconductor process tools 102-112. Examples of inspection tools include a scanning electron microscope (SEM), a transmissive electronic microscope (TEM), and / or another type of electron beam inspection tool, among other examples.

[0084] Wafer / die transport tool 116 includes a mobile robot, a robotic arm, a trolley or track car, an overhead hoist transport (OHT) system, an automated material-handling system (AMHS), and / or another type of device to transport semiconductor substrates and / or semiconductor elements between semiconductor process tools 102-114, between process chambers of the same semiconductor process tool, and / or to and from other locations such as wafer racks, storage rooms, and / or the like. In some embodiments, wafer / die transport tool 116 can be a programmed device to travel along a particular path, and / or can be semi-autonomously or autonomously operated. In some embodiments, environment 100 includes multiple wafer / die transport tools 116.

[0085] For example, wafer / die transport tool 116 may be included in a cluster tool or another type of tool that includes multiple process chambers and may be used to transport semiconductor substrates and / or semiconductor devices between multiple process chambers, to transport semiconductor substrates and / or semiconductor devices between a process chamber and a buffer, to transport semiconductor substrates and / or semiconductor devices between a process chamber and an interface tool such as an equipment front end module (EFEM), and / or to transport semiconductor substrates and / or semiconductor devices between a process chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), and other examples. In some embodiments, the wafer / die transport tool 116 may include a multi-chamber (or clustered) deposition tool 102, which may include a pre-cleaning process chamber (e.g., for cleaning or removing oxides, oxide layers, and / or other types of contaminants or byproducts from the semiconductor substrate and / or semiconductor device) and various types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations). In these embodiments, the wafer / die transport tool 116 is used to transport the semiconductor substrate and / or semiconductor device between the process chambers of the deposition tool 102 without disrupting or removing the vacuum (or at least a partial vacuum) between the process chambers and / or between process operations in the deposition tool 102, as described herein.

[0086] In some embodiments, one or more of the semiconductor process tools 102-114 include a holding assembly that supports (e.g., temporarily holds, temporarily aligns, or temporarily positions, and other instances) the semiconductor substrate during individual manufacturing processes. For example, inspection tool 114 may include an electrostatic chuck (ESC) 118, such as... Figure 1A As shown.

[0087] Figure 1B An exemplary implementation of ESC 118 is shown. Figure 1B In this configuration, ESC 118 supports a semiconductor substrate 120 (e.g., a semiconductor wafer) within an inspection tool 114. ESC 118 is used to generate an attractive force between ESC 118 and the semiconductor substrate 120 based on a voltage applied to ESC 118. The voltage can be provided by a power supply that provides a high bias voltage to ESC 118. The attractive force (e.g., a Coulomb force) causes the semiconductor substrate 120 to be held on and supported by ESC 118.

[0088] The size and shape of ESC 118 can be determined based on the size and shape of semiconductor substrate 120. For example, ESC 118 can be circular and can support all or part of semiconductor substrate 120, which is also circular. ESC 118 can be made of metal such as aluminum, stainless steel, or another suitable material.

[0089] As shown, ESC 118 positions the semiconductor substrate 120 relative to component 122 of inspection tool 114. In embodiments where inspection tool 114 includes a scanning electron microscope (SEM), component 122 may correspond to a lens cap structure (e.g., a structure that accommodates one or more lenses through which one or more electron beams pass). Inspection tool 114 may further include electrical ground 124.

[0090] like Figure 1B As shown, the top surface 126 of the semiconductor substrate 120 includes a potential 128 (e.g., charge). Although in Figure 1B The value is shown as positive, but the polarity of the potential can be negative. In some embodiments, the inspection tool 114 generates an electron beam that scans the top-side surface 126. During the scanning of the top-side surface 126, the electron beam can generate conditions related to changes in the potential 128. For example, the electron beam can cause electron accumulation on the top-side surface 126 of the semiconductor substrate 120, resulting in the formation of a negative charge on the top-side surface 126. Alternatively, the electron beam can bombard electrons on the top-side surface 126 of the semiconductor substrate 120, causing electron displacement and resulting in hole formation. In this example, hole accumulation occurs, resulting in a positive charge on the top-side surface 126.

[0091] Potential 128 can generate conditions associated with arcing (or an increased likelihood of arcing) between component 122 and top surface 126, semiconductor substrate 120, and / or ESC 118. Alternatively, potential 128 can also generate conditions associated with arcing (or an increased likelihood of arcing) between electrical ground 124 and top surface 126, semiconductor substrate 120, and / or ESC 118. Arcing can damage semiconductor elements 130 (e.g., chips, integrated circuits) included on semiconductor substrate 120. Alternatively, arcing can damage testing tools 114.

[0092] As used herein, the term "arc discharge" can refer to any discharge that occurs through a generally non-conductive medium, such as an insulating material or air. As used herein, "arc discharge" can refer to intermittent or discrete discharges (also referred to as electrical sparks) and / or continuous discharges (also referred to as electrical arcs). For example, a discharge can occur if the potential 128 increases to the order of magnitude sufficient to create a conductive path through the non-conductive medium between the semiconductor substrate 120 and the component 122 or between the semiconductor substrate 120 and the electrical ground 124.

[0093] One or more conditions associated with the arc discharge can be related to one or more materials included in the semiconductor substrate 120. For example, if the semiconductor substrate 120 includes a silicon material, a potential 128 greater than or equal to a band gap of the silicon material can increase the likelihood of an arc discharge. For a silicon material, and for example, the band gap can include in a range from approximately 1.0 electron volt (eV) to approximately 1.5 eV.

[0094] To reduce the likelihood of an arc discharge, a tip of the conductive pin 132 (or a tip of a collection including one or more conductive pins 132) can be positioned near the backside surface 134 of the semiconductor substrate 120 and near or within a region including the potential 128. In this way, an electrical charge can be transferred from the conductive pin 132 to the semiconductor substrate 120 to reduce the order of magnitude of the potential 128 and / or to neutralize the potential 128. Reducing the order of magnitude and / or neutralizing the potential 128 reduces the likelihood of and / or prevents a conductive path from being formed between the semiconductor substrate 120 and the component 122 and / or between the semiconductor substrate 120 and the electrical ground 124, which reduces the likelihood of an arc discharge.

[0095] In some implementations, the tip of the conductive pin 132 is positioned at a distance 136 from the backside surface 134 of the semiconductor substrate 120, the distance 136 being in a range from greater than 0 microns (pm) to less than or equal to approximately 1 pm. Positioning the tip within this range can allow the power source to provide a neutralizing potential 128 (or reduce the order of magnitude of the potential 128) through the conductive pin 132 without damaging the electrical charge of the semiconductor substrate 120. However, other values and / or ranges of the distance 136, including ranges that result in the conductive pin 132 contacting the backside surface 134 or other surfaces of the semiconductor substrate 120, are also within the scope of the present disclosure.

[0096] Other semiconductor processing tools (e.g., the semiconductor processing tools 102-112 and other examples) can include a variant of the chuck assembly (e.g., a vacuum chuck assembly, or the ESC 118 and other examples) and a variant of the conductive pin 132. Additionally or alternatively, a tip of the conductive pin 132 can be positioned near the top side surface 126 of the semiconductor substrate 120 or near a chuck assembly of other semiconductor processing tools to neutralize the potential 128.

[0097] Figure 1C An exemplary embodiment of an ESC 118 is shown. In this exemplary embodiment, the ESC 118 includes an electrode 138 and a substrate 140. A voltage can be applied to the electrode 138 to generate a Coulomb force that attracts the semiconductor substrate 120 to the electrode 138 for the ESC 118 to support (e.g., temporarily secure, temporarily align, or temporarily position, among other examples) the semiconductor substrate 120.

[0098] The electrode 138 includes a pin guide 142 through which the conductive pin 132 can be positioned. The pin guide 142 can include a cylindrical hole or include a bushing, among other examples. In some embodiments, the conductive pin 132 is positioned such that a tip of the conductive pin 132 protrudes from an exit of the pin guide 142. In some embodiments, the conductive pin 132 is positioned such that the tip of the conductive pin 132 remains within the pin guide 142. As shown, the tip of the conductive pin 132 is located within a region 144 that includes an electrical potential 128. Figure 1C

[0099] As shown, the conductive pin 132 can be included as part of a voltage adjustment system 146 that can change the electrical potential 128 of the region 144. In addition to the conductive pin 132, the voltage adjustment system 146 includes a sensor 148 (e.g., a voltage level sensor, among other examples). The voltage adjustment system 146 further includes a power source 150 (e.g., a power source that can generate a positive or negative electrical potential, among other examples) that is electrically coupled to the conductive pin 132. Figure 1C The voltage adjustment system 146 further includes a pin positioning subsystem 152 that is mechanically coupled to the conductive pin 132. The pin positioning subsystem 152 can include one or more components, such as a linear induction motor component, a servo motor component, a stepper motor component, a pneumatic cylinder component, or a ball screw component, among other examples. The pin positioning subsystem 152 can cause a combination of one or more of a vertical motion 154 and / or a lateral motion 156 to position the tip of the conductive pin 132 within the region 144 that includes the electrical potential 128. In embodiments that include a collection of multiple conductive pins 132, one or more components of the pin positioning subsystem 152 can provide independent positioning control of each conductive pin 132 in the collection.

[0100] The voltage adjustment system 146 further includes a controller 158. The controller 158 can include a processor, a combination of a processor and a memory, and / or a transceiver that transmits and receives signals, among other examples. As shown, the controller 158 is electrically coupled to the power source 150, the sensor 148, and the pin positioning subsystem 152.

[0101] Figure 1C ​​As shown, the controller 158 is communicatively connected to the sensor 148, the power source 150, and the pin positioning subsystem 152 using one or more communication links 160 (e.g., one or more wireless communication links, one or more wired communication links, or a combination of one or more wireless communication links and one or more wired communication links, among other examples).

[0102] The controller 158 can perform one or more processes. For example, the controller 158 can receive voltage measurement data from the sensor 148 and determine, based on the voltage measurement data, that the potential 128 of the region 144 does not satisfy a threshold value. The controller 158 can further be configured to transmit a signal to the pin positioning subsystem 152 to cause the pin positioning subsystem 152 to position a tip of the conductive pin 132 within the region 144. The controller 158 can transmit another signal to the power source 150 to cause the conductive pin 132 to transfer an electrical charge to the region 144 such that the potential 128 of the region 144 satisfies the threshold value.

[0103] The controller 158 can use a machine learning model to determine one or more conditions that can be associated with an electrical arc discharge. The machine learning model can include one or more of a neural network model, a random forest model, a clustering model, or a regression model, among other examples, and / or can be associated with the electrical arc discharge. In some implementations, the controller 158 uses the machine learning model to determine the one or more conditions by providing, as input to the machine learning model, candidate voltage measurements of the region 144, positioning measurements of the semiconductor substrate 120 over the ESC 118, warpage measurements of the semiconductor substrate 120, and / or operating parameters of the inspection tool 114. Using the machine learning model, the controller 158 can determine a likelihood, probability, or confidence that a particular outcome (e.g., an electrical arc discharge) of a subsequent inspection operation will be achieved using the candidate measurements and / or parameters. In some implementations, the controller 158 provides, as input to the machine learning model, conditions under which an electrical arc discharge does not occur, and the controller 158 uses the machine learning model to determine or identify a particular combination of operating and / or positioning parameters that are likely to achieve conditions that prevent an electrical arc discharge.

[0104] The controller 158 (or another system) can train, update, and / or fine-tune the machine learning model to increase an accuracy of results and / or parameters determined using the machine learning model. The controller 158 can train, update, and / or fine-tune the machine learning model based on feedback and / or results from subsequent inspection operations performed by the inspection tool 114, as well as historical or related inspection operations (e.g., hundreds, thousands, or more historical or related inspection operations).

[0105] The controller 158 can perform one or more processes to change the potential 128 of the region 144. For example, and with reference to FIG. 1, the controller 158 can receive voltage measurement data from the sensor 148 and determine, based on the voltage measurement data, that the potential 128 of the region 144 does not satisfy a threshold value. The controller 158 can further be configured to transmit a signal to the pin positioning subsystem 152 to cause the pin positioning subsystem 152 to position a tip of the conductive pin 132 within the region 144. The controller 158 can transmit another signal to the power source 150 to cause the conductive pin 132 to transfer an electrical charge to the region 144 such that the potential 128 of the region 144 satisfies the threshold value. Figure 1CThe one or more processes can include receiving, by the controller 158 from the sensor 148, a first signal including voltage measurement data, identifying, by the controller 158 based on the voltage measurement data, a positive charge region (e.g., region 144) of the semiconductor substrate 120 supported by the ESC 118. The one or more processes can then include transmitting, by the controller 158 based on identifying the positive charge region 144, a second signal including positioning data to the pin positioning subsystem 152 to cause the pin positioning subsystem 152 to position a tip of the conductive pin 132 within the positive charge region 144. The one or more processes can also include transmitting a third signal to adjust a setting of the power source 150 such that the conductive pin 132 transmits a negative charge to the region 144 to neutralize the positive charge.

[0106] In some embodiments, including those described herein, positioning and / or supporting the semiconductor substrate 120 over the ESC 118 while the voltage adjustment system 146 changes the potential 128 includes using a lift pin and / or a vacuum bar (not illustrated) to separate the semiconductor substrate 120 from a surface of the electrode 138. Figure 1C In some embodiments, including those described herein, positioning and / or supporting the semiconductor substrate 120 over the ESC 118 while the voltage adjustment system 146 changes the potential 128 includes contacting the semiconductor substrate 120 to a surface of the electrode 138. Figure 1C In some embodiments, including those described herein, positioning and / or supporting the semiconductor substrate 120 over the ESC 118 while the voltage adjustment system 146 changes the potential 128 includes contacting the semiconductor substrate 120 to a surface of the electrode 138.

[0107] Figures 1A-1C The number and configuration of devices shown are provided as one or more examples. In practice, there can be additional devices, fewer devices, different devices, or devices configured differently than those shown. Moreover, Figures 1A-1C The number and configuration of devices shown are provided as one or more examples. In practice, there can be additional devices, fewer devices, different devices, or devices configured differently than those shown. Moreover, Figures 1A-1C The two or more devices shown can be implemented within a single device, or Figures 1A-1C The single device shown can be implemented as a plurality of distributed devices. For example, and with respect to Figure 2 As described herein and elsewhere, an array including one or more of the pin guides 142 can be included in the electrode 138, and a set including one or more of the conductive pins 132 can be included as part of the voltage adjustment system 146. Additionally or alternatively, a set of devices (e.g., one or more devices) of the environment 100 can perform one or more functions described as being performed by another set of devices of the environment 100.

[0108] Figure 2 is a diagram of an exemplary embodiment 200 of an array 202 of conductive pins 132 and pin guides 142 described herein. The array 202 can be formed such that the conductive pins 132 and pin guides 142 pass through the electrode 138.

[0109] Array 202 includes one or more of the conductive pins 132 and one or more of the pin guides 142. In some embodiments, voltage regulation system 146 (e.g., controller 158 combined with pin positioning subsystem 152) can select set 204 from array 202. For example, voltage regulation system 146 can select set 204a, which includes one of the conductive pins 132 and one of the pin guides 142 to change the potential 128 in a region of semiconductor substrate 120. Alternatively, voltage regulation system 146 can select set 204b, which includes two of the conductive pins 132 and two of the pin guides 142 to change the potential 128 in another region of semiconductor substrate 120. Alternatively, voltage regulation system 146 can select set 204c, which includes four of the conductive pins 132 and four of the pin guides 142 to change the potential 128 in another region of semiconductor substrate 120. Sets 204a, 204b, and 204c are provided by way of example. In other instances, an additional or different number of conductive pins 132 and pin guides 142 may be selected.

[0110] like Figure 2 As shown, and for example, array 202 includes an “X by X” pattern with a linear spacing 206 of approximately 5.0 centimeters (cm). However, other patterns (e.g., linear patterns, radial patterns, and other instances) and spacings (including variable spacing) are also within the scope of this disclosure.

[0111] according to Figure 2 The array 202 of conductive pins 132 and pin guides 142 may be included in a semiconductor process tool (e.g., semiconductor process tool 114) that includes a controller 158. Furthermore, the array 202 of conductive pins 132 and pin guides 142 may be used in one or more processes performed by the semiconductor process tool.

[0112] For example, and according to Figure 2 In the array 202, the controller 158 can execute one or more processes to cause the potential 128 of region 144 to meet a threshold value. One or more processes may include the controller 158 receiving a first signal, including voltage measurement data, from a sensor 148 associated with region 144 of the semiconductor substrate 120 supported by ESC 118, and the controller 158 determining, based on the voltage measurement data, that the potential 128 of region 144 does not meet the threshold value. One or more processes may further include the controller 158, based on the determination that the potential 128 does not meet the threshold value, transmitting: a second signal to cause the pin positioning subsystem 152 to position the top of the assembly 204c of conductive pins 132 within region 144; and a third signal to activate the power supply 150, causing the assembly 204c of conductive pins 132 to transfer charge to region 144 so that the potential 128 of region 144 meets the threshold value.

[0113] Additionally or alternatively, the semiconductor process tool can include the ESC 118 having the electrode 138, the array 202 of pin guides 142 passing through the electrode 138, and the voltage adjustment system 146. The voltage adjustment system 146 can include the pin positioning subsystem 152, the set 204 of conductive pins 132, and the power source 150 electrically coupled with the set 204 of conductive pins 132. The voltage adjustment system 146 can further include the controller 158 to determine that a condition associated with an electrical arc discharge between the top side surface 126 of the semiconductor substrate 120 positioned above the electrode 138 and a component 122 of the semiconductor process tool has occurred. Then, the controller 158 can be to transmit a first signal to cause the pin positioning subsystem 152 to position one or more tips of a corresponding one or more conductive pins 132 of the set 204c of conductive pins 132 near or positioned through an exit of one or more pin guides 142 of the array 202 of pin guides 142 based on determining that the condition has occurred. The controller 158 can be further to transmit a second signal to cause the power source 150 to adjust a setting such that the one or more conductive pins 132 transmit an electrical charge to or from the semiconductor substrate 120 to change the potential 128 of the region 144 of the semiconductor substrate 120 including the top side surface 126.

[0114] As indicated above, Figure 2 are provided as examples. Other examples can differ from what is described Figure 2 above without departing from the spirit of the disclosure as recited in the claims section.

[0115] Figures 3A-3C is a diagram of an exemplary implementation 300 of the voltage adjustment system 146 described herein. For simplicity, this implementation describes a process performed by the voltage adjustment system 146 including a single conductive pin 132. However, different permutations, combinations, and / or variations of this implementation can use a set of one or more conductive pins 132 in the array 202 as set forth above and elsewhere herein. Figure 2

[0116] From Figure 3A beginning, the process 302 includes the controller 158 receiving a first signal from the sensor 148 using one or more communication links 160. The controller 158 can determine that the potential 128a (e.g., a positive bias) of the region 144 does not satisfy a threshold value based on voltage measurement data included in the first signal.

[0117] ​For example, the threshold value can correspond to an upper threshold value in a range from approximately 1.0 eV to approximately 1.5 eV, in which case satisfying the threshold value corresponds to a potential 128a less than approximately 1.0 eV to approximately 1.5 eV. By selecting a threshold value in this range, the likelihood of arcing between the region 144 and a component 122 of the inspection tool 114 is reduced due to the bandgap of silicon being exceeded. However, other values and / or ranges of threshold values are also within the scope of the present disclosure.

[0118] Additionally or alternatively, the threshold value can correspond to a uniformity threshold value across the plurality of regions of the semiconductor substrate 120. The controller 158 can determine that a measure of uniformity (e.g., a distribution, a standard deviation, or a range, among other examples) across the semiconductor substrate 120 does not satisfy the threshold value based on the voltage measurement data associated with the region 144 and other voltage measurement data associated with other regions of the semiconductor substrate 120.

[0119] Further, the controller 158 can determine that the conductive pin 132 is in the retracted state and that the top end of the conductive pin 132 is below the region 144.

[0120] In Figure 3B , as part of the process 304 and based on determining that the potential 128a of the region 144 does not satisfy the threshold value, the controller 158 transmits a second signal to the pin positioning subsystem 152 using the one or more communication links 160. The second signal can cause the pin positioning subsystem 152 to position the conductive pin 132 using the vertical motion 154 such that the top end of the conductive pin 132 is within a particular distance range of the backside surface 134 of the semiconductor substrate 120.

[0121] As part of the process 306, in Figure 3C , the controller 158 transmits a third signal to the power source 150 using the one or more communication links 160. In some implementations, the third signal causes the power source 150 to neutralize the potential 128a. As Figure 3C shown, the power source 150 can neutralize the potential 128a by providing another potential 128b (e.g., a negative bias or charge).

[0122] In some implementations, the conductive pin 132 can discharge the potential 128a (e.g., the power source 150 is in a neutral state and does not bias the conductive pin 132 using other potentials 128b).

[0123] As indicated above, Figures 3A-3C are provided as examples. Other examples can differ from what is described with regard to Figures 3A-3C . Additionally or alternatively, Figures 3A-3C implementations of the process 300 use a plurality of conductive pins 132, including one or more of the set 204 as described with regard to Figure 2 . For example,Figures 3A-3C One implementation may use a first set including a first number of conductive pins 132, and simultaneously or continuously use a second set including a second number of conductive pins 132.

[0124] Figures 4A-4C This is a figure of an exemplary embodiment 400 of the voltage regulation system 146 described herein. For simplicity, this embodiment describes the process performed by the voltage regulation system 146 including a single conductive pin 132. However, different substitutions, combinations, and / or variations of this embodiment can be used as follows: Figure 2 The array 202 and the collection of one or more conductive pins 132 described elsewhere in this document.

[0125] since Figure 4A Initially, process 402 includes a controller 158 receiving a first signal using one or more communication links 160 and sensor 148. The controller 158 may determine that the potential 128c of region 144 (e.g., negative bias or charge) does not meet a threshold value (e.g., potential 128c is greater than the bandgap of silicon, and other instances). Furthermore, the controller 158 may determine that the conductive pin 132 is within the pin guide 142a and that the tip of the conductive pin 132 is not within region 144.

[0126] exist Figure 4B In process 404, and based on the fact that the potential 128c of the determination region 144 does not meet the threshold value, the controller 158 uses one or more communication links 160 to send a second signal to the pin positioning subsystem 152. The second signal can cause the pin positioning subsystem 152 to reposition the conductive pin 132 from the pin guide 142a to another pin guide 142b.

[0127] For example, the pin positioning subsystem 152 may use a pneumatic cylinder assembly to retract the pin from the pin guide 142a using a vertical movement 154a. Continuing this example, the pin positioning subsystem 152 may use a linear induction motor assembly to laterally reposition the conductive pin 132 from the pin guide 142a to the pin guide 142b (e.g., among two or more pin guides) and to reposition it within region 144 using a lateral movement 156. Continuing this example, the pin positioning subsystem 152 may use a pneumatic cylinder assembly to extend the conductive pin 132 using a vertical movement 154b such that the tip of the conductive pin 132 is within a specific distance range of the back surface 134 of the semiconductor substrate 120.

[0128] As part of process 406, in Figure 4C In this embodiment, controller 158 uses one or more communication links 160 to transmit a third signal to power supply 150. In some implementations, the third signal causes power supply 150 to neutralize potential 128c. For example... Figure 4CAs shown, power supply 150 can neutralize potential 128c by providing another potential 128d (e.g., a positive bias or charge).

[0129] As indicated above, Figures 4A-4C are provided as examples. Other examples can differ from what is described with respect to Figures 4A-4C for example, additionally or instead, Figures 4A-4C Embodiments of the conductive pins 132 use a plurality of conductive pins 132, including one or more sets 204 as described with respect to Figure 2 and elsewhere herein.

[0130] Figure 5A and Figure 5B are graphs of exemplary embodiments 500A and 500B of the conductive pins 132 described herein. Figure 5A and Figure 5B The conductive pins 132 can include one or more materials. In some embodiments, the conductive pins 132 include a carbon nanotube material. In some embodiments, the conductive pins 132 include another material, such as aluminum, copper, gold, or tungsten, among other examples.

[0131] As indicated above, Figure 5A The conductive pins 132 can have a length 502 in a range of approximately 20.0 centimeters (cm) to approximately 30.0 cm. By having a length 502 in this range, the conductive pins 132 can pass through the ESC 118 and mechanically connect to the pin positioning subsystem 152. However, other values and / or ranges of the length 502 are within the scope of the present disclosure.

[0132] As also indicated above, Figure 5A The conductive pins 132 can have a diameter 504 in a range of approximately 1.0 nanometer (nm) to approximately 2.0 nm. By having a diameter 504 in this range, the conductive pins 132 can be compatible with the carbon nanotube material included in the conductive pins 132. However, other values and / or ranges of the diameter 504 are within the scope of the present disclosure.

[0133] In some embodiments, and as indicated above, Figure 5B The conductive pins 132 include a pointed tip 506. The pointed tip 506 can increase the accuracy of positioning the conductive pins 132 by the pin positioning subsystem 152. In embodiments where the conductive pins 132 are in physical contact with the backside surface 134 of the semiconductor substrate 120, the pointed tip 506 can penetrate oxide growth to improve the quality of electrical contact with the backside surface 134. In some embodiments, the voltage adjustment system 146 includes conductive pins 132 that include a combination of non-pointed tips and pointed tips.

[0134] As indicated above, Figure 5A andFigure 5B are provided as examples. Other examples can differ from what is described with respect to Figure 5A and Figure 5B described with respect to

[0135] Figure 6 is an exemplary embodiment 600 of the conductive pin 132 described herein. As Figure 6 illustrated, the semiconductor substrate 120 has a warpage 602. In some embodiments, the controller 158 identifies the warpage 602 based on received information of a batch (e.g., a group or a lot) of semiconductor substrates 120 provided to the inspection tool 114. In some embodiments, the controller 158 identifies the warpage 602 based on metrology performed by the inspection tool 114.

[0136] The controller 158 can transmit a signal to cause the pin positioning subsystem 152 to individually adjust a “stroke” of one or more conductive pins 132 to compensate for the warpage 602 based on the warpage 602. For example, and as Figure 6 illustrated, a stroke (e.g., a vertical motion 154c) of the conductive pin 132a is different from another stroke (e.g., a vertical motion 154d) of the conductive pin 132b. The stroke difference can compensate for the warpage 602 and position the top ends of the conductive pins 132a and 132b within the same range (e.g., distance) from the backside surface 134 of the semiconductor substrate.

[0137] As indicated above, Figure 6 are provided as examples. Other examples can differ from what is described with respect to Figure 6 and

[0138] Figure 7 is a diagram of exemplary components of a device 700, which can correspond to one or more of the semiconductor processing tools 102-112, the inspection tool 114, the sensor 148, the power source 150, the pin positioning subsystem 152, and / or the controller 158. In some embodiments, one or more of the semiconductor processing tools 102-112, the inspection tool 114, the sensor 148, the power source 150, the pin positioning subsystem 152, and / or the controller 158 comprise one or more devices 700 and / or one or more components of the device 700. As Figure 7 illustrated, the device 700 can include a bus 710, a processor 720, a memory 730, an input component 740, an output component 750, and a communication component 760.

[0139] The bus 710 includes one or more components that enable wired and / or wireless communication between components of the device 700. The bus 710 can couple the components of the device 700 together, such as via operative coupling, communicative coupling, electronic coupling, and / or electrical coupling. Figure 7The processor 720 includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, a special-purpose application integrated circuit, and / or another type of processing component. The processor 720 is implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, the processor 720 includes one or more processors capable of being programmed to perform one or more operations or processes described elsewhere herein.

[0140] The memory 730 includes volatile and / or nonvolatile memory. For example, the memory 730 can include random access memory (RAM), read only memory (ROM), hard disk drives, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 730 can include internal memory (e.g., RAM, ROM, or a hard disk drive) and / or removable memory (e.g., that can be removed via a universal serial bus connection). The memory 730 can be a non-transitory computer-readable medium. The memory 730 stores information, instructions, and / or software (e.g., one or more software applications) related to the operation of the device 700. In some embodiments, the memory 730 includes one or more memories coupled to one or more processors (e.g., the processor 720) such as via the bus 710.

[0141] The input component 740 enables the device 700 to receive input, such as user input and / or readout input. For example, the input component 740 can include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, an accelerometer, a gyroscope, and / or an actuator. The output component 750 enables the device 700 to provide output, such as via a display, a speaker, and / or a light emitting diode. The communication component 760 enables the device 700 to communicate with other devices, such as via a wired connection and / or a wireless connection. For example, the communication component 760 can include a receiver, a transmitter, a transceiver, a data modem, a network interface card, and / or an antenna.

[0142] Device 700 can perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 730) can store a set of instructions (e.g., one or more instructions or code) for execution by processor 720. Processor 720 can execute the set of instructions to perform one or more operations or processes described herein. In some implementations, execution of the set of instructions by one or more processors 720 causes one or more processors 720 and / or device 700 to perform one or more operations or processes described herein. In some implementations, hard-wired circuitry is used in place of or in combination with software instructions to perform one or more operations or processes described herein. Additionally, or alternatively, processor 720 can be used to perform one or more operations or processes described herein. Thus, embodiments described herein are not limited to any specific combination of hardware circuitry and software.

[0143] Figure 7 The number and arrangement of components shown in FIG. 7 are provided as an example. Device 700 can include additional components, fewer components, different components, or differently arranged components than those shown in FIG. 7. Additionally or alternatively, a set of components (e.g., one or more components) of device 700 can perform one or more functions described as being performed by another set of components of device 700. Figure 7 The number and arrangement of components shown in FIG. 7 are provided as an example. Device 700 can include additional components, fewer components, different components, or differently arranged components than those shown in FIG. 7. Additionally or alternatively, a set of components (e.g., one or more components) of device 700 can perform one or more functions described as being performed by another set of components of device 700.

[0144] Figure 8 is a flow diagram of an exemplary process related to a semiconductor process tool including the voltage adjustment system described herein. In some implementations, Figure 8 One or more process blocks of Figure 8 One or more process blocks of Figure 8 Additionally or alternatively, one or more process blocks of

[0145] As shown, process 800 can include receiving, from a sensor associated with a region of a semiconductor substrate supported by an ESC, a first signal including voltage measurement data (block 810). For example, controller 158 can receive, from sensor 148 associated with region 144 of semiconductor substrate 120 supported by ESC 118, a first signal including voltage measurement data, as described above. Figure 8

[0146] As shown, process 800 can include receiving, from a sensor associated with a region of a semiconductor substrate supported by an ESC, a first signal including voltage measurement data (block 810). For example, controller 158 can receive, from sensor 148 associated with region 144 of semiconductor substrate 120 supported by ESC 118, a first signal including voltage measurement data, as described above. Figure 8 ​Further, process 800 can include determining that the potential of the region does not satisfy a threshold value based on the voltage measurement data (block 820). For example, controller 158 can determine that the potential 128 of the region 144 does not satisfy a threshold value based on the voltage measurement data, as described above.

[0147] As Figure 8 Further, process 800 can include transmitting: a second signal to cause a pin positioning subsystem to position tips of a set of conductive pins within the region; and a third signal to activate a power source such that the set of conductive pins transmit a charge to the region to cause the potential of the region to satisfy the threshold value based on determining that the potential does not satisfy the threshold value (block 830). For example, controller 158 can transmit: a second signal to cause pin positioning subsystem 152 to position tips of a set of conductive pins 132 within region 144; and a third signal to activate power source 150 such that the set of conductive pins 132 transmit a charge to region 144 to cause the potential 128 of the region to satisfy the threshold value based on determining that the potential 128 does not satisfy the threshold value, as described above.

[0148] Process 800 can include additional implementations, such as any individual implementation or any combination of the implementations described below and / or in connection with one or more other processes described elsewhere herein.

[0149] In a first implementation, determining that the potential 128 does not satisfy the threshold value includes determining that the potential 128 is greater than or equal to a band gap of a material of semiconductor substrate 120.

[0150] In a second implementation, alone or in combination with the first implementation, the material of semiconductor substrate 120 includes silicon, and the band gap includes a range of approximately 1.0 electron volt (eV) to approximately 1.5 eV.

[0151] In a third implementation, alone or in combination with one or more of the first and second implementations, determining that the potential 128 does not satisfy the threshold value includes determining that the potential 128 does not satisfy a uniformity threshold value based on one or more other potentials of one or more other regions of semiconductor substrate 120.

[0152] In a fourth implementation, alone or in combination with one or more of the first through third implementations, transmitting the second signal includes transmitting the second signal to cause pin positioning subsystem 152 to position tips of a set of conductive pins 132 at a distance 136 from a backside surface 134 of semiconductor substrate 120 within region 144, the distance 136 being in a range of greater than 0 microns (pm) to less than or equal to approximately 1 pm.

[0153] In the fifth embodiment, transmitting the second signal, either alone or in combination with one or more of the first to fourth embodiments, includes transmitting data from an array 202 of conductive pins 132, which includes a set 204 of conductive pins 132, identifying the set 204 of conductive pins 132.

[0154] In the sixth embodiment, transmitting the third signal, either alone or in combination with one or more of the first to fifth embodiments, includes transmitting the third signal to activate the power supply 150, such that the power supply 150 provides continuous power to the assembly 204 of the conductive pins 132 while the ESC 118 supports the semiconductor substrate 120.

[0155] although Figure 8 The diagram shows an exemplary block of process 800, but in some embodiments, process 800 includes... Figure 8 The blocks depicted are compared to additional blocks, fewer blocks, different blocks, or blocks configured differently. Alternatively, two or more of the blocks in process 800 can be executed in parallel.

[0156] Figure 9 This is a flowchart of an exemplary process associated with semiconductor process tools, including the voltage regulation system described herein. In some implementations, Figure 9 One or more process blocks are executed by a controller (e.g., controller 158). In some implementations, Figure 9 One or more process blocks are executed by another device or group of devices, separate from or including the controller 158, such as inspection tool 114, sensor 148, power supply 150, and / or pin positioning subsystem 152. Alternatively or additionally, Figure 8 One or more process blocks may be executed by one or more components of device 700 such as processor 720, memory 730, input component 740, output component 750 and / or communication component 760.

[0157] like Figure 9 As shown, process 900 may include a self-sensor receiving a first signal including voltage measurement data (block 910). For example, controller 158 may receive the first signal including voltage measurement data from self-sensor 148, as described above.

[0158] like Figure 9 As further shown, process 900 may include identifying positively charged regions (block 920) of the ESC-supported semiconductor substrate based on voltage measurement data. For example, controller 158 may identify positively charged regions 144 of the ESC-supported semiconductor substrate 120 based on voltage measurement data, as described above.

[0159] like Figure 9Further, process 900 can include transmitting, to the pin positioning subsystem based on identifying the positive charge region: a second signal including positioning data to cause the pin positioning subsystem to position a tip of the electrically conductive pin within the positive charge region; and a third signal to adjust a setting of the power source such that the electrically conductive pin transmits a negative charge to the region to neutralize the positive charge (block 930). For example, controller 158 can transmit, to pin positioning subsystem 152 based on identifying positive charge region 144: a second signal including positioning data to cause pin positioning subsystem 152 to position a tip of electrically conductive pin 132 within positive charge region 144; and a third signal to adjust a setting of power source 150 such that electrically conductive pin 132 transmits a negative charge to the region 144 to neutralize the positive charge, as described above.

[0160] Process 900 can include additional implementations, such as any single implementation or any combination of the implementations described below and / or in connection with one or more other processes described elsewhere herein.

[0161] In a first implementation, identifying region 144 includes determining an operating parameter of semiconductor process tool 114 including ESC 118, and identifying region 144 based on a machine learning model that relates the operating parameter of semiconductor process tool 114 to positive charge region 144.

[0162] In a second implementation, alone or in combination with the first implementation, process 900 includes providing data including the operating parameter and a magnitude of the positive charge to the machine learning model, and using the data to update an algorithm of the machine learning model that relates the operating parameter of semiconductor process tool 114 to a likelihood of an electrical arc discharge occurring between semiconductor process tool 114 and semiconductor substrate 120.

[0163] In a third implementation, alone or in combination with one or more of the first and second implementations, transmitting the second signal includes transmitting positioning data that identifies a warpage 602 of semiconductor substrate 120 within region 144 to cause pin positioning subsystem 152 to position a tip of electrically conductive pin 132 within positive charge region 144 using one or more positioning adjustments that compensate for warpage 602.

[0164] In a fourth implementation, alone or in combination with one or more of the first through third implementations, transmitting the second signal includes transmitting positioning data to cause pin positioning subsystem 152 to reposition a tip of electrically conductive pin 132 from a first position corresponding to a first pin guide 142a through ESC 118 to a second position corresponding to a second pin guide 152b through ESC 118.

[0165] In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, process 900 includes transmitting the positioning data to cause the pin positioning subsystem 152 to reposition the tip of the conductive pin 132 to the second position is to cause the pin positioning subsystem 152 to reposition the tip of the conductive pin within a positively charged region 144. In some implementations, the positively charged region is different from another region corresponding to the first position.

[0166] Although Figure 9 An exemplary block of process 900 is shown, but in some implementations, process 900 includes additional blocks, fewer blocks, different blocks, or differently configured blocks than those depicted in Figure 9 Additionally or alternatively, two or more of the blocks of process 900 can be performed in parallel.

[0167] Some implementations described herein provide techniques and apparatuses for a semiconductor process tool including an ESC having a voltage adjustment system for adjusting an electrical potential in an entire region of a semiconductor substrate positioned above the ESC. The voltage adjustment system can determine that an electrical potential within a region of the semiconductor substrate does not satisfy a threshold value. The voltage adjustment system can position one or more conductive pins within the region based on determining that the electrical potential in the entire region does not satisfy the threshold value. The one or more conductive pins, when positioned within the region, can change the electrical potential of the region.

[0168] The voltage adjustment system ensures that the electrical potential of each region satisfies the threshold value. By ensuring that the electrical potential satisfies the threshold value, the voltage adjustment system can reduce the likelihood of arcing between the semiconductor substrate and components of the semiconductor process tool. In this way, damage to the semiconductor substrate can be prevented, increasing the yield of semiconductor elements manufactured from the semiconductor substrate. Furthermore, damage to the semiconductor process tool can be prevented, increasing the up-time of the semiconductor process tool and increasing the throughput of semiconductor elements manufactured using the semiconductor process tool.

[0169] As described in more detail above, some embodiments described herein provide a method of semiconductor process tool operation. The method includes receiving, by a controller from a sensor associated with a region of a semiconductor substrate supported by an electrostatic chuck, a first signal comprising voltage measurement data. The method includes determining, by the controller based on the voltage measurement data, that a potential of the region does not satisfy a threshold value. The method includes transmitting, by the controller based on determining that the potential does not satisfy the threshold value, a second signal to cause a pin positioning subsystem to position tips of a set of electrically conductive pins within the region, a third signal to activate a power source such that the set of electrically conductive pins transmit a charge to the region such that the potential of the region satisfies the threshold value. In some embodiments, determining that the potential does not satisfy the threshold value includes determining that the potential is greater than or equal to a band gap of a material of the semiconductor substrate. In some embodiments, the material of the semiconductor substrate includes silicon; and the band gap is included in a range from approximately 1.0 electron volts (eV) to approximately 1.5 electron volts (eV). In some embodiments, determining that the potential does not satisfy the threshold value includes determining that the potential does not satisfy a uniformity threshold value based on one or more other potentials of one or more other regions of the semiconductor substrate. In some embodiments, transmitting the second signal includes transmitting the second signal to cause the pin positioning subsystem to position the tips of the set of a plurality of electrically conductive pins at a distance from a backside surface of the semiconductor substrate within a range from greater than 0 microns to less than or equal to approximately 1 micron within the region. In some embodiments, transmitting the second signal includes transmitting data identifying the set of a plurality of electrically conductive pins, the data from an array of a plurality of electrically conductive pins, wherein the set of a plurality of electrically conductive pins is included. In some embodiments, transmitting the third signal includes transmitting the third signal to activate the power source such that the power source provides continuous power to the set of a plurality of electrically conductive pins while the electrostatic chuck supports the semiconductor substrate.

[0170] As described in greater detail above, some embodiments described herein provide a method of semiconductor process tool operation. The method includes receiving, by a controller from a sensor, a first signal including voltage measurement data. The method includes identifying, by the controller based on the voltage measurement data, a positively charged region of a semiconductor substrate supported by an electrostatic chuck. The method includes transmitting, by the controller based on identifying the positively charged region, to a pin positioning subsystem: a second signal including positioning data to a pin positioning subsystem to cause the pin positioning subsystem to position a tip of a conductive pin within the positively charged region; and a third signal to adjust a setting of a power source such that the conductive pin transmits a negative charge to the region to neutralize the positive charge. In some embodiments, identifying the positively charged region includes determining an operating parameter of a semiconductor process tool including the electrostatic chuck and identifying the positively charged region based on a machine learning model that relates the operating parameter of the semiconductor process tool to the positively charged region. In some embodiments, the method further includes providing data including the operating parameter and a magnitude of the positive charge to the machine learning model and updating an algorithm of the machine learning model that relates the operating parameter of the semiconductor process tool to a likelihood of an electrical arc discharge between the semiconductor process tool and the semiconductor substrate using the data. In some embodiments, transmitting the second signal includes transmitting positioning data that identifies a warpage of the semiconductor substrate within the positively charged region to cause the pin positioning subsystem to position the tip of the conductive pin within the positively charged region using one or more positioning adjustments that compensate for the warpage. In some embodiments, transmitting the second signal includes transmitting positioning data to cause the pin positioning subsystem to reposition the tip of the conductive pin from a first position corresponding to a first pin guide through the electrostatic chuck to a second position corresponding to a second pin guide through the electrostatic chuck. In some embodiments, transmitting the positioning data to cause the pin positioning subsystem to reposition the tip of the conductive pin to the second position is to cause the pin positioning subsystem to reposition the tip of the conductive pin within the positively charged region, where the positively charged region is different from another region corresponding to the first position.

[0171] As described in greater detail above, some embodiments described herein provide a semiconductor processing tool. The semiconductor processing tool includes an electrostatic chuck including an electrode. The semiconductor processing tool includes an array of pin guides through the electrode. The semiconductor processing tool includes a voltage adjustment system including: a pin positioning subsystem; a set of electrically conductive pins; a power supply electrically coupled with the set of electrically conductive pins; and a controller. The controller is to determine that a condition associated with an electrical arc discharge between a top side surface of a semiconductor substrate positioned above the electrode and a component of the semiconductor processing tool has occurred, and to emit a first signal to cause the pin positioning subsystem to position one or more tip ends of a corresponding one or more electrically conductive pins of the set of electrically conductive pins proximate to or through an outlet of one or more pin guides of the array of pin guides based on determining that the condition has occurred. The controller is to emit a second signal to cause the power supply to adjust a setting such that the one or more electrically conductive pins transfer electrical charge to or from the semiconductor substrate to change a potential of a region of the semiconductor substrate including the top side surface. In some embodiments, the set of electrically conductive pins includes at least one electrically conductive pin including a carbon nanotube. In some embodiments, the set of electrically conductive pins includes at least one electrically conductive pin having a sharp tip end. In some embodiments, the semiconductor processing tool further includes a source that generates an electron beam to generate the condition by changing the potential of the region of the top side surface of the semiconductor substrate. In some embodiments, the pin positioning subsystem includes a linear induction motor assembly to laterally reposition at least one electrically conductive pin of the set of electrically conductive pins among two or more pin guides of the array of pin guides. In some embodiments, the pin positioning subsystem includes one or more components to provide independent positioning control of each electrically conductive pin of the set of electrically conductive pins. In some embodiments, the controller is to determine that the condition associated with the electrical arc discharge has occurred based on a machine learning model that relates a bow of the semiconductor substrate to the condition.

[0172] As used herein, depending on the context, "satisfies a threshold value" can refer to a value that is greater than the threshold value, greater than or equal to the threshold value, less than the threshold value, less than or equal to the threshold value, equal to the threshold value, not equal to the threshold value, or the like.

[0173] The foregoing outlines features of several embodiments so that a person of ordinary skill in the art can better understand the present disclosure. Those of ordinary skill in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein without departing from the spirit and scope of the present disclosure. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of operating a semiconductor process tool, the method comprising: Includes the following steps: A controller receives a first signal, including voltage measurement data, from a sensor associated with a region of a semiconductor substrate supported by an electrostatic chuck, the electrostatic chuck including an electrode and an array of multiple pin conductors passing through the electrode. The controller determines, based on the voltage measurement data, that a potential in the region does not meet a threshold value, and determines that a condition associated with an arc discharge between the region of the semiconductor substrate located above the electrode and a component of the semiconductor process tool has occurred. The controller determines that the voltage does not meet the threshold value before transmitting: A second signal causes a pin positioning subsystem to position multiple tips of a set of multiple conductive pins in the region and near or through multiple outlets of one or more pins in the array of multiple pins. and A third signal is used to activate a power source, causing the set of multiple conductive pins to transfer a charge to the region so that the potential of the region meets the threshold value.

2. The method of claim 1, wherein, Determining that the potential does not meet the threshold value includes: Determine if the potential is greater than or equal to the band gap of the material of the semiconductor substrate.

3. The method as described in claim 2, characterized in that: The semiconductor substrate is made of silicon; and The band gap is in the range of 1.0 electron volts to 1.5 electron volts.

4. The method of claim 1, wherein, Determining that the potential does not meet the threshold value includes: The potential is determined not to meet a uniformity threshold based on one or more other potentials in one or more other regions of the semiconductor substrate.

5. The method as described in claim 1, characterized in that, The transmission of the second signal includes: The second signal is emitted such that the pin positioning subsystem positions the tips of the set of multiple conductive pins in the region at a distance from a back surface of the semiconductor substrate, the distance being greater than 0 micrometers and less than or equal to 1 micrometer.

6. The method as described in claim 1, characterized in that, The transmission of the second signal includes: Data is emitted that identifies the set of multiple conductive pins, the data coming from an array of multiple conductive pins, including the set of multiple conductive pins.

7. The method as described in claim 1, characterized in that, The transmission of this third signal includes: The third signal is emitted to activate the power supply, which then provides continuous power to the assembly of multiple conductive pins as the electrostatic chuck supports the semiconductor substrate.

8. A method for operating a semiconductor manufacturing tool, characterized in that, Includes the following steps: A controller receives a first signal, including voltage measurement data, from a sensor. The controller identifies a positively charged region on a semiconductor substrate supported by an electrostatic chuck, based on voltage measurement data. The electrostatic chuck includes an electrode and an array of multiple pin conductors passing through the electrode. The controller determines, based on the identification of the positively charged region, that a condition associated with an arc discharge between the positively charged region on the semiconductor substrate positioned above the electrode and a component of the semiconductor process tool has occurred. The controller emits based on identifying the positively charged region: A second signal includes positioning data to a pin positioning subsystem, such that the pin positioning subsystem positions a tip of a conductive pin near the positive charge region and near or through the outlet of one of the pins in the array of a plurality of pins. and A third signal is used to adjust a setting of a power supply, such that the conductive pin transfers a negative charge to the positive charge region to neutralize a positive charge.

9. The method as described in claim 8, characterized in that, The steps for identifying the positively charged region include: Determine an operating parameter of a semiconductor process tool, including the electrostatic chuck; and The positively charged region is identified using a machine learning model, which correlates the operating parameters of the semiconductor manufacturing tool with the positively charged region.

10. The method as described in claim 9, characterized in that, Further steps include: The machine learning model is provided with the following data: The operating parameters and the order of magnitude of the positive charge; and An algorithm that uses this data to update the machine learning model correlates the operating parameters of the semiconductor process tool with the probability of an arc discharge occurring between the semiconductor process tool and the semiconductor substrate.

11. The method as described in claim 8, characterized in that, The steps for transmitting the second signal include the following: The system transmits positioning data that identifies a warpage of the semiconductor substrate within the positively charged region, such that the pin positioning subsystem uses one or more positioning adjustments to compensate for the warpage to position the tip of the conductive pin within the positively charged region.

12. The method as described in claim 8, characterized in that, The steps for transmitting the second signal include the following: The system transmits positioning data such that the pin positioning subsystem repositions the tip of the conductive pin from a first position corresponding to a first pin guide passing through the electrostatic chuck to a second position corresponding to a second pin guide passing through the electrostatic chuck.

13. The method as described in claim 12, characterized in that, Transmitting the positioning data so that the pin positioning subsystem repositions the tip of the conductive pin to the second position is to cause the pin positioning subsystem to reposition the tip of the conductive pin within the positive charge region, wherein the positive charge region is different from another region corresponding to the first position.

14. A semiconductor manufacturing tool, characterized in that, Include: An electrostatic chuck includes an electrode; An array of multiple pin guides passes through the electrode; and A voltage regulation system, comprising: One-pin positioning subsystem; A collection of multiple conductive pins; A power source, electrically coupled to the assembly of multiple conductive pins; and A controller, used to: A condition associated with an arc discharge between a top surface of a semiconductor substrate positioned above the electrode and an assembly of the semiconductor process tool has occurred; and Launch based on the determination that this condition has occurred: A first signal causes the pin positioning subsystem to position one or more tips of corresponding one or more conductive pins in the set of multiple conductive pins near or through multiple outlets of one or more pin guides in the array of multiple pin guides; and A second signal causes the power supply to adjust a setting such that one or more conductive pins transmit a charge to or from the semiconductor substrate to change a potential in a region of the semiconductor substrate including the top side surface.

15. The semiconductor manufacturing tool as described in claim 14, characterized in that, This set of multiple conductive pins includes: At least one conductive pin contains a carbon nanotube.

16. The semiconductor manufacturing tool as claimed in claim 14, characterized in that, This set of multiple conductive pins includes: At least one conductive pin has a pointed tip.

17. The semiconductor manufacturing tool as claimed in claim 14, characterized in that, Further includes: A source generates an electron beam to produce the condition by changing the potential of the region on the top side surface of the semiconductor substrate.

18. The semiconductor manufacturing tool as claimed in claim 14, characterized in that, The pin positioning subsystem includes: A linear induction motor assembly for laterally repositioning at least one conductive pin from the set of a plurality of conductive pins into two or more pin guides in the array of a plurality of pin guides.

19. The semiconductor manufacturing tool as claimed in claim 14, characterized in that, The pin positioning subsystem includes: One or more components are used to provide independent positioning control for each conductive pin in the set of multiple conductive pins.

20. The semiconductor manufacturing tool as claimed in claim 14, characterized in that, The controller is used to determine, based on a machine learning model, that conditions associated with arc discharge have occurred, and that the machine learning model correlates a warpage of the semiconductor substrate with these conditions.

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