Guard Ring and Method for Forming the Same, Semiconductor Structure

Abstract

Embodiments of the present disclosure provide a guard ring, a method for forming the same, and a semiconductor structure. The guard ring at least includes an embedded protection structure. The embedded protection structure is located in a semiconductor substrate and is used to protect a first functional structure formed inside the semiconductor substrate. The guard ring provided by the embodiments of the present disclosure can protect the first functional structure formed inside the semiconductor substrate, thereby effectively resisting the damage to the chip caused by the stress during the wafer dicing process and improving the dicing yield of the chip.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a guard ring and a forming method thereof, and a semiconductor structure. Background Art

[0002] In the semiconductor manufacturing process, wafers formed with integrated circuits are usually cut into individual chips (Chips), and then these chips are made into semiconductor package structures with different functions. During the chip cutting process, the stress generated by the cutting tool will damage the edges of the chips, and even cause the chips to collapse.

[0003] In the related art, in order to prevent chips from being damaged during cutting, a guard ring is provided around the active device area of the chip. The guard ring has the following three functions: one is to block the stress generated by the cutting tool to prevent cracks from occurring in the active device area; the second is to block the penetration of water vapor, fog, moisture, etc. to chemically damage the circuits on the chip; the third is to be able to absorb minority carriers to prevent the chip from being affected by electromagnetic interference or other noise interference from external electrons.

[0004] However, the guard ring in the related art only protects the functional structures formed on the surface of the substrate, and lacks protection for the functional structures formed inside the substrate. When the guard ring in the related art is used to protect the chip, stress damage and other problems still occur in the chip during the cutting process. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a guard ring and a forming method thereof, and a semiconductor structure.

[0006] In a first aspect, embodiments of the present disclosure provide a guard ring, which at least includes: an embedded protection structure;

[0007] The embedded protection structure is located in a semiconductor substrate;

[0008] The embedded protection structure is used to protect a first functional structure formed inside the semiconductor substrate.

[0009] In some embodiments, the embedded protection structure includes an embedded word line protection structure; the first functional structure includes a word line structure;

[0010] The embedded word line protection structure is used to protect the word line structure.

[0011] In some embodiments, the embedding depth of the embedded word line protection structure is the same as the embedding depth of the word line structure; or, the embedding depth of the embedded word line protection structure is greater than the embedding depth of the word line structure; or, the embedding depth of the embedded word line protection structure is less than the embedding depth of the word line structure.

[0012] In some embodiments, the word line structure has the same constituent structure as the embedded word line protection structure; the constituent structure of the embedded word line protection structure at least includes a gate dielectric layer, a word line metal layer, and a gate protection pattern;

[0013] Wherein, the gate dielectric layer is located between the word line metal layer and the semiconductor substrate;

[0014] The gate protection pattern is located on the top surfaces of the gate dielectric layer and the word line metal layer;

[0015] The top surface of the semiconductor substrate is flush with the top surface of the gate protection pattern, or the top surface of the semiconductor substrate protrudes beyond the top surface of the gate protection pattern.

[0016] In some embodiments, the embedded protection structure includes an embedded bit line protection structure; the first functional structure includes a bit line structure;

[0017] The embedded bit line protection structure is used to protect the bit line structure.

[0018] In some embodiments, the embedded depth of the embedded bit line protection structure is the same as the embedded depth of the bit line structure; or, the embedded depth of the embedded bit line protection structure is greater than the embedded depth of the bit line structure; or, the embedded depth of the embedded bit line protection structure is less than the embedded depth of the bit line structure.

[0019] In some embodiments, the bit line structure has the same constituent structure as the embedded bit line protection structure;

[0020] The constituent structure of the embedded bit line protection structure at least includes a bit line metal layer; wherein, the top surface of the semiconductor substrate protrudes beyond the top surface of the bit line metal layer.

[0021] In some embodiments, the embedded bit line protection structure is electrically connected through internal or external potential components of one or more metal layers.

[0022] In some embodiments, the protection ring further includes a non-embedded protection structure;

[0023] The non-embedded protection structure is located on the surface of the semiconductor substrate, and the non-embedded protection structure is electrically connected to the semiconductor substrate;

[0024] The non-embedded protection structure is used to protect a second functional structure formed on the surface of the semiconductor substrate.

[0025] In some embodiments, the non-embedded protection structure includes: at least two metal layers, at least one first through-hole, and metal plugs;

[0026] The first through-hole is used to achieve electrical connection between two adjacent metal layers;

[0027] The metal plugs are used to achieve electrical connection between the bottommost metal layer in the non-embedded protection structure and the semiconductor substrate.

[0028] In some embodiments, the second functional structure includes a capacitor structure;

[0029] The at least two metal layers, the at least one first through-hole, and the metal plugs are used to protect the capacitor structure.

[0030] In some embodiments, the height of the non-embedded protection structure is greater than the height of the capacitor structure.

[0031] In some embodiments, the protection ring structure further includes a second through-hole;

[0032] The second through-hole is used to achieve electrical connection between the bottommost metal layer in the non-embedded protection structure and the word line metal layer.

[0033] In some embodiments, the protection ring is formed around the semiconductor chip;

[0034] The semiconductor chip includes a dynamic random access memory chip, a static random access memory chip, a phase change memory chip, a ferroelectric memory chip, a resistive random access memory chip, or a flash memory chip.

[0035] In a second aspect, an embodiment of the present disclosure provides a method for forming a protection ring, the method including:

[0036] Providing a semiconductor substrate;

[0037] While forming a first functional structure inside the semiconductor substrate, forming an embedded protection structure in the semiconductor substrate; wherein, the embedded protection structure is used to protect the first functional structure.

[0038] In some embodiments, the first functional structure and the embedded protection structure are formed simultaneously using the same process steps;

[0039] The embedded protection structure and the first functional structure have the same or different embedded depths, and the embedded protection structure and the first functional structure have the same compositional structure.

[0040] In some embodiments, the first functional structure includes a word line structure or a bit line structure.

[0041] In some embodiments, the method further includes:

[0042] forming a non-embedded protection structure on the surface of the semiconductor substrate;

[0043] wherein the non-embedded protection structure is configured to protect a second functional structure formed on the surface of the semiconductor substrate.

[0044] In some embodiments, the second functional structure includes a capacitor structure.

[0045] In a third aspect, embodiments of the present disclosure provide a semiconductor structure, including: a chip and a protection ring located around the chip;

[0046] wherein the protection ring is configured to protect the internal circuit structure of the chip;

[0047] the protection ring at least includes an embedded protection structure located inside the semiconductor substrate; the internal circuit structure at least includes a first functional structure located inside the semiconductor substrate of the chip;

[0048] the embedded protection structure is configured to protect the first functional structure.

[0049] In some embodiments, the first functional structure includes a word line structure or a bit line structure.

[0050] In some embodiments, the protection ring further includes a non-embedded protection structure located on the surface of the semiconductor substrate; the internal circuit structure further includes a second functional structure located on the surface of the semiconductor substrate of the chip;

[0051] the non-embedded protection structure is configured to protect the second functional structure.

[0052] In some embodiments, the second functional structure includes a capacitor structure.

[0053] The protection ring, its forming method, and the semiconductor structure provided by the embodiments of the present disclosure, wherein the protection ring at least includes an embedded protection structure located in the semiconductor substrate and configured to protect a first functional structure formed inside the semiconductor substrate. Since the protection ring provided by the embodiments of the present disclosure at least includes an embedded protection structure, thus, it can protect the first functional structure formed inside the semiconductor substrate, and further can effectively resist the damage to the chip caused by the stress during the wafer dicing process, improving the dicing yield of the chip. In addition, the non-embedded protection structure on the upper part of the semiconductor substrate can protect the core area capacitor structure. Description of the Drawings

[0054] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe like components in different views. Like reference numerals with different alphabetical suffixes may represent different examples of like components. The drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0055] Figure 1 is a cross-sectional view of the guard ring structure in the related art;

[0056] Figure 2a is a top view of the guard ring provided by an embodiment of the present disclosure;

[0057] Figure 2b is a cross-sectional view of the guard ring provided by an embodiment of the present disclosure;

[0058] Figure 3a and 3b is a cross-sectional view of the DRAM chip guard ring provided by an embodiment of the present disclosure;

[0059] Figure 4 is a schematic flowchart of a method for forming a guard ring provided by an embodiment of the present disclosure;

[0060] Figure 5a is a top view of the semiconductor structure provided by an embodiment of the present disclosure;

[0061] Figure 5b is a cross-sectional view of the semiconductor structure provided by an embodiment of the present disclosure. Detailed Description of the Embodiments

[0062] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully communicated to those skilled in the art.

[0063] In the following description, numerous specific details are given to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure can be practiced without one or more of these details. In other instances, some well-known technical features are not described in order to avoid obscuring the present disclosure; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0064] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. Like reference numerals throughout denote like elements.

[0065] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be denoted as the second element, component, region, layer, or part. And when discussing the second element, component, region, layer, or part, it does not imply that there must be a first element, component, region, layer, or part in the present disclosure.

[0066] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0067] Figure 1 FIG. is a cross-sectional view of a guard ring in the related art. Before detailing the guard ring provided by the embodiments of the present disclosure, first, in combination with Figure 1 the structure of the guard ring in the related art will be described.

[0068] As Figure 1 shown, the guard ring 10 in the related art includes a metal plug 101, a first metal layer 102, a second metal layer 103, a third metal layer 104, a fourth metal layer 105, and a via 106 connecting adjacent two metal layers, which are sequentially located on the surface of the active region 100a of the substrate 100. It can be seen that the guard ring in the related art is only formed on the surface of the semiconductor substrate. Therefore, the guard ring in the related art only has a protective effect on the functional structures formed on the surface of the substrate. When there are functional structures formed inside the substrate, a good protective effect cannot be achieved.

[0069] Based on the above problems existing in the related art, embodiments of the present disclosure provide a guard ring, a method for forming the same, and a semiconductor structure. The guard ring at least includes an embedded protection structure located in a semiconductor substrate and used to protect a first functional structure formed inside the semiconductor substrate. Since the guard ring provided by the embodiments of the present disclosure at least includes an embedded protection structure, the first functional structure formed inside the semiconductor substrate can be protected, and thus the damage to the chip caused by the stress during the wafer dicing process can be effectively resisted, and the dicing yield of the chip can be improved.

[0070] Embodiments of the present disclosure provide a guard ring. Figure 2a is a top view of the guard ring provided by the embodiments of the present disclosure. Figure 2b is a cross-sectional view of the guard ring provided by the embodiments of the present disclosure. As Figure 2a and 2b shown, the guard ring 20 is located in the scribe line 23 around the chip composed of the array region 21 and the peripheral circuit region 22. The guard ring 20 is at least used to block the stress damage during the chip dicing process. The guard ring 20 includes an embedded protection structure 201. Among them, the embedded protection structure 201 is located in the semiconductor substrate 200; the embedded protection structure 201 is used to protect a first functional structure (not shown in the figure) formed inside the semiconductor substrate 200.

[0071] In the embodiments of the present disclosure, the semiconductor substrate 200 may be a silicon substrate, or the semiconductor substrate 200 may also include other semiconductor elements, such as: germanium (Ge), or include semiconductor compounds, such as: silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys, such as: silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or a combination thereof.

[0072] In some embodiments, the embedded protection structure 201 may be an embedded word line protection structure; the first functional structure may be a word line structure; the embedded word line protection structure is used to protect the word line structure.

[0073] In the embodiments of the present disclosure, the embedding depth of the embedded word line protection structure is the same as that of the word line structure; or, the embedding depth of the embedded word line protection structure is greater than that of the word line structure; or, the embedding depth of the embedded word line protection structure is less than that of the word line structure. When the embedding depths of the embedded word line protection structure and the word line structure are the same, the protection effect of the embedded word line protection structure on the word line structure is the strongest.

[0074] In some embodiments, when the buried depth of the buried word line protection structure is less than that of the word line structure, the value of the buried depth of the buried word line protection structure is within a buried depth range, and the minimum value of this buried depth range is greater than 0. That is to say, the buried depth of the buried word line protection structure is at least greater than 0. In terms of process implementation, the buried depth of the buried word line protection structure should be as close as possible to the buried depth of the word line structure. Therefore, the buried word line protection structure and the word line structure can be formed simultaneously, or, after the word line structure is formed, the buried depth of the buried word line protection structure can be determined based on the buried depth of the formed word line structure, and then the buried word line protection structure can be further formed.

[0075] In some embodiments, when the buried depth of the buried word line protection structure is greater than that of the word line structure, or when the buried depth of the buried word line protection structure is less than that of the word line structure, the difference between the buried depth of the buried word line protection structure and the buried depth of the word line structure is less than or equal to a first preset depth value. When the difference between the buried depth of the buried word line protection structure and the buried depth of the word line structure is greater than the first preset depth value, the buried word line protection structure cannot provide protection for the word line structure.

[0076] In the embodiments of the present disclosure, the component structures of the word line structure and the buried word line protection structure are the same; please continue to refer to Figure 2b , the component structure of the buried word line protection structure at least includes a gate dielectric layer 2011, a word line metal layer 2012, and a gate protection pattern 2013; wherein, the gate dielectric layer 2011 is located between the word line metal layer 2012 and the semiconductor substrate 200; the gate protection pattern 2013 is located on the top surfaces of the gate dielectric layer 2011 and the word line metal layer 2012. The top surface of the semiconductor substrate 200 is flush with the top surface of the gate protection pattern 2013, or the top surface of the semiconductor substrate 200 protrudes beyond the top surface of the gate protection pattern 2013.

[0077] In some embodiments, the gate dielectric layer 2011 can be a silicon oxide layer, a thermal oxide layer, or a high-k dielectric layer, etc., for example, a silicon oxide layer. The word line metal layer 2012 can be formed of a conductive material, for example, a doped polysilicon material, a metal material (such as tungsten metal), or a metal silicide material. The gate protection pattern 2013 can be any insulating layer, for example, a silicon oxide layer.

[0078] In some embodiments, please continue to refer to Figure 2b , the buried word line protection structure further includes a word line barrier layer 2014, and the word line barrier layer 2014 is located between the gate dielectric layer 2011 and the word line metal layer 2012. The word line barrier layer 2014 is used to block the diffusion of the metal material in the word line metal layer 2012 into the semiconductor substrate 200.

[0079] In some embodiments, the word line blocking layer 2014 may be a titanium nitride layer, a tungsten nitride layer, a tantalum nitride layer, or the like. +

[0080] In some embodiments, the embedded protection structure 201 may also be an embedded bit line protection structure; the first functional structure may also be a bit line structure, and the embedded bit line protection structure is used to protect the bit line structure.

[0081] In the embodiments of the present disclosure, the embedding depth of the embedded bit line protection structure is the same as the embedding depth of the bit line structure; or, the embedding depth of the embedded bit line protection structure is greater than the embedding depth of the bit line structure; or, the embedding depth of the embedded bit line protection structure is less than the embedding depth of the bit line structure. When the embedding depths of the embedded bit line protection structure and the bit line structure are the same, the protection effect of the embedded bit line protection structure on the bit line structure is the strongest.

[0082] In some embodiments, when the embedding depth of the embedded bit line protection structure is less than the embedding depth of the bit line structure, the value of the embedding depth of the embedded bit line protection structure is within an embedding depth range, and the minimum value of the embedding depth range is greater than 0, that is to say, the embedding depth of the embedded bit line protection structure is at least greater than 0. In terms of process implementation, the embedding depth of the embedded bit line protection structure should be as close as possible to the embedding depth of the bit line structure. Therefore, the embedded bit line protection structure and the bit line structure can be formed simultaneously, or, after the bit line structure is formed, the embedding depth of the embedded bit line protection structure can be determined based on the embedding depth of the formed bit line structure, and the embedded bit line protection structure is further formed.

[0083] In some embodiments, when the embedding depth of the embedded bit line protection structure is greater than the embedding depth of the bit line structure, or, when the embedding depth of the embedded bit line protection structure is less than the embedding depth of the bit line structure, the difference between the embedding depth of the embedded bit line protection structure and the embedding depth of the bit line structure is less than or equal to a second preset depth value. When the difference between the embedding depth of the embedded bit line protection structure and the embedding depth of the bit line structure is greater than the second preset depth value, the embedded bit line protection structure cannot provide protection for the bit line structure.

[0084] In some embodiments, the bit line structure and the embedded bit line protection structure have the same composition structure, and the composition structure of the embedded bit line protection structure at least includes a bit line metal layer; wherein, the top surface of the semiconductor substrate protrudes beyond the top surface of the bit line metal layer.

[0085] In some embodiments, the embedded bit line protection structure can be electrically connected through internal or external potential components of one or more metal layers.

[0086] In some embodiments, the buried bitline protection structure further includes a bitline barrier layer located between the bitline metal layer and the semiconductor substrate. The bitline barrier layer is configured to prevent the metal material in the bitline metal layer from diffusing into the semiconductor substrate.

[0087] In some embodiments, please continue to refer to Figure 2b , the protection ring 20 further includes a non-buried protection structure 202; the non-buried protection structure 202 is located on the surface of the semiconductor substrate 200, and the non-buried protection structure 202 is electrically connected to the semiconductor substrate 200; the non-buried protection structure 202 is configured to protect a second functional structure formed on the surface of the semiconductor substrate 200 ( Figure 2b not shown in

[0088] In some embodiments, the second functional structure may be a capacitor structure.

[0089] In the embodiments of the present disclosure, the non-buried protection structure includes: at least two metal layers, at least one first through hole, and a metal plug; wherein, the first through hole is configured to electrically connect adjacent two metal layers; the metal plug is configured to electrically connect the bottommost metal layer in the non-buried protection structure to the semiconductor substrate. The at least two metal layers, the at least one first through hole, and the metal plug are configured to protect the capacitor structure.

[0090] In some embodiments, the height of the non-buried protection structure may be greater than the height of the said structure.

[0091] Please continue to refer to Figure 2b , the non-buried protection structure 202 includes a first metal layer 2021, a second metal layer 2022, a third metal layer 2023, a fourth metal layer 2024, a metal plug 2025 connecting the active region 200a in the semiconductor substrate 200 to the first metal layer 2021, and a first through hole 2026 connecting adjacent two metal layers.

[0092] In some embodiments, the active region 200a may be formed in the semiconductor substrate 200 and be located below the surface of the semiconductor substrate 200. The thickness of the active region 200a in the direction perpendicular to the substrate surface is equal to the gate protection pattern 2013, or, the thickness of the active region 200a in the direction perpendicular to the substrate surface is greater than the gate protection pattern 2013, or, the thickness of the active region 200a in the direction perpendicular to the substrate surface is less than the gate protection pattern 2013. The upper surface of the active region 200a, the upper surface of the gate protection pattern 2013, and the upper surface of the semiconductor substrate 200 are coplanar, that is to say, the upper surface of the active region 200a, the upper surface of the gate protection pattern 2013, and the upper surface of the semiconductor substrate 200 are located in the same plane.

[0093] In some embodiments, the guard ring may further include a second through hole; the second through hole is used to realize the electrical connection between the bottommost metal layer in the non-embedded protection structure and the word line metal layer 2012.

[0094] In the embodiments of the present disclosure, the guard ring is formed around the semiconductor chip; the semiconductor chip includes but is not limited to any one of the following: a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a phase change memory (PCM) chip, a ferroelectric random access memory (FeRAM) chip, a resistive random access memory (ReRAM) chip, or a flash memory chip.

[0095] In the embodiments of the present disclosure, the guard ring can be grounded or connected to a negative voltage through a metal layer. In other embodiments, the guard ring may not be connected to any metal layer or potential.

[0096] Next, taking the DRAM chip as an example, the structure of the guard ring around the chip in the dynamic random access memory will be described. Figure 3a and 3b is a cross-sectional view of the guard ring of the DRAM chip provided by the embodiments of the present disclosure. As Figure 3a and 3b shown, the guard ring 30 of the DRAM chip includes an embedded protection structure 301 and a non-embedded protection structure 302. Among them, the embedded protection structure 301 is used to protect the first functional structure 401 formed inside the semiconductor substrate 300; the non-embedded protection structure 302 is used to protect the second functional structure 402 formed on the surface of the semiconductor substrate 300.

[0097] Please continue to refer to Figure 3a and 3b, the embedded protection structure 301 includes an embedded word line protection structure, and the first functional structure 401 includes a word line structure located in the array region A. In the embodiments of the present disclosure, the embedded word line protection structure and the word line structure have the same structural composition, and the embedded depths of the embedded word line protection structure and the word line structure are the same. The embedded word line protection structure and the word line structure both include a gate dielectric layer 3011, a word line barrier layer 3012, a word line metal layer 3013, and a gate protection pattern 3014. Among them, the gate dielectric layer 3011 is located between the word line metal layer 3013 and the semiconductor substrate 300; the word line barrier layer 3012 is located between the gate dielectric layer 3011 and the word line metal layer 3013, and the gate protection pattern 3014 is located on the top surfaces of the gate dielectric layer 3011, the word line barrier layer 3012, and the word line metal layer 3013; the top surface of the gate protection pattern 3014 is flush with the top surface of the semiconductor substrate 300.

[0098] In the embodiments of the present disclosure, the gate dielectric layer may be a silicon oxide layer, a thermal oxide layer, or a high-k dielectric layer, for example, a silicon oxide layer. The word line barrier layer may be a titanium nitride layer, a tungsten nitride layer, or a tantalum nitride layer. The word line metal layer may be formed of a conductive material, for example, a doped polysilicon material, a metal material (such as tungsten), or a metal silicide material. The gate protection pattern may be any insulating layer, for example, a silicon oxide layer.

[0099] Please continue to refer to Figure 3a and 3b , the non-embedded protection structure 302 includes a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4, a metal plug CT connecting the active region 300a in the semiconductor substrate 300 and the first metal layer M1, a first via V1 connecting M1 and M2, a first via V2 connecting M2 and M3, and a first via V3 connecting M3 and M4. In the embodiments of the present disclosure, the second functional structure 402 includes a capacitor structure located on the surface of the array region A. And in the embodiments of the present disclosure, the height of the non-embedded protection structure 302 is greater than the height of the capacitor structure, the first via V1 connecting the first metal layer M1 and the second metal layer M2 is formed simultaneously with the capacitor structure, and the height of the first via V1 connecting the first metal layer M1 and the second metal layer M2 is equal to the height of the capacitor structure.

[0100] In some embodiments, please continue to refer to Figure 3b , the DRAM chip protection ring structure 30 further includes a second via 303; the second via 303 is used to realize the electrical connection between the bottommost metal layer (i.e., the first metal layer M1) in the non-embedded protection structure 302 and the word line metal layer 3013.

[0101] In an embodiment of the present disclosure, the gate of the buried metal-oxide-semiconductor field-effect (MOS) structure (i.e., the word-line metal layer in the buried word-line protection structure) in the buried protection structure in the DRAM chip protection ring can be floating or electrically connected to the first metal layer M1 in the non-buried protection structure; when the DRAM chip protection ring is grounded, the shielding effect against noise or electromagnetic interference will be better.

[0102] Next, combined with Figure 3a and 3d, analyze the stress conduction during the chip cutting process. During the cutting process, M4-V3-M3-V2-M2-V1-M1-CT located on the substrate surface can protect the capacitive structure on the surface of the array region A. When cutting into the semiconductor substrate, the buried word-line protection structure 301 buried in the semiconductor substrate is used to resist the stress conducted through the semiconductor substrate 300, thereby protecting the MOS structure (i.e., the word-line structure 401 in the present disclosure) inside the semiconductor substrate 300.

[0103] In an embodiment of the present disclosure, since the array region is next to the protection ring, the gate of the buried MOS in the protection ring region is tungsten and titanium nitride (TiN) with a relatively high hardness, and the buried depth of the buried MOS structure in the protection ring region is the same as that of the MOS structure in the array region. Therefore, it can effectively resist the stress or cracks conducted from the semiconductor substrate to the array region.

[0104] In an embodiment of the present disclosure, since the protection ring at least includes a buried protection structure, the first functional structure formed inside the semiconductor substrate can be protected, and thus the damage to the chip caused by the stress during the wafer cutting process can be effectively resisted, improving the cutting yield of the chip.

[0105] An embodiment of the present disclosure provides a method for forming a protection ring. Figure 4 is a schematic flow chart of the method for forming the protection ring provided by the embodiment of the present disclosure. As Figure 4 shown, the method for forming the protection ring includes the following steps:

[0106] Step S401, provide a semiconductor substrate.

[0107] In the embodiments of the present disclosure, the semiconductor substrate may be a silicon substrate, or the semiconductor substrate may also include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys, such as silicon-germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP), or a combination thereof.

[0108] Step S402: While forming the first functional structure inside the semiconductor substrate, form a buried protection structure in the semiconductor substrate.

[0109] Wherein, the buried protection structure is used to protect the first functional structure.

[0110] In the embodiments of the present disclosure, the buried protection structure and the first functional structure have the same or different buried depths. For example, the buried depth of the buried protection structure is greater than the buried depth of the first functional structure, or the buried depth of the buried protection structure is less than the buried depth of the first functional structure.

[0111] In some embodiments, the first functional structure and the buried protection structure may be formed simultaneously using the same process steps.

[0112] In the embodiments of the present disclosure, the first functional structure may be a word line structure or a bit line structure. The buried protection structure and the first functional structure have the same compositional structure. For example, the buried protection structure may be a buried word line structure or a buried bit line structure.

[0113] In some embodiments, when the first functional structure includes a word line structure and the buried protection structure includes a buried word line, the buried protection structure may be formed through the following steps:

[0114] Step S1: Form an etching groove inside the semiconductor substrate.

[0115] Step S2: Sequentially form an initial gate dielectric layer, an initial word line blocking layer, and an initial word line metal layer on the inner wall of the etching groove, wherein the initial word line metal layer fills the etching groove.

[0116] In the embodiments of the present disclosure, an initial gate dielectric layer, an initial word line blocking layer, and an initial word line metal layer can be formed by any suitable deposition process, such as Chemical Vapor Deposition (CVD) process, Physical Vapor Deposition (PVD) process, Atomic Layer Deposition (ALD) process, spin coating process, or coating process.

[0117] Step S3: Etch back the initial gate dielectric layer, the initial word line blocking layer, and the initial word line metal layer to form a gate dielectric layer, a word line blocking layer, and a word line metal layer.

[0118] Step S4: Form a gate insulating layer on the top surfaces of the gate dielectric layer, the word line blocking layer, and the word line metal layer.

[0119] In the embodiments of the present disclosure, the gate insulating layer can be formed by any suitable deposition process.

[0120] In some embodiments, the method for forming a protection ring further includes the following steps: forming a non-embedded protection structure and a second functional structure on the surface of a semiconductor substrate.

[0121] Wherein, the non-embedded protection structure is used to protect the second functional structure formed on the surface of the semiconductor substrate.

[0122] In some embodiments, the second functional structure includes a capacitor structure. The non-embedded protection structure includes at least two metal layers, at least one first through hole, and a metal plug; wherein, the first through hole is used to realize the electrical connection between two adjacent metal layers; the metal plug is used to realize the electrical connection between the bottommost metal layer in the non-embedded protection structure and the semiconductor substrate; at least two metal layers, at least one first through hole, and the metal plug are used to protect the capacitor structure.

[0123] It should be noted that in the embodiments of the present disclosure, the height of the non-embedded protection structure is greater than the height of the capacitor structure, the first through hole between the first metal layer and the second metal layer among the at least two metal layers is formed simultaneously with the capacitor structure, and the height of the first through hole between the first metal layer and the second metal layer is equal to the height of the capacitor structure.

[0124] In the method for forming a protection ring provided by the embodiments of the present disclosure, since the embedded protection structure can be formed while the first functional structure is formed in the semiconductor substrate, thus, the formation process of the protection ring will not additionally increase the process steps.

[0125] The method for forming the guard ring provided by the embodiments of the present disclosure is similar to the guard ring in the above embodiments. For the technical features not disclosed in detail in the embodiments of the present disclosure, please refer to the above embodiments for understanding and will not be elaborated here.

[0126] In addition, the embodiments of the present disclosure also provide a semiconductor structure. Figure 5a is a top view of the semiconductor structure provided by the embodiments of the present disclosure. Figure 5b is a cross-sectional view of the semiconductor structure provided by the embodiments of the present disclosure. As Figure 5a and 5b shown, the semiconductor structure 50 includes a chip 501 and a guard ring 502 located around the chip 501. The guard ring 502 is used to protect the internal circuit structure of the chip; the guard ring 502 at least includes an embedded protection structure 5021 located inside the semiconductor substrate 500; the internal circuit structure at least includes a first functional structure 5011 located inside the semiconductor substrate 500 of the chip 501; the embedded protection structure 5021 is used to protect the first functional structure 5011.

[0127] In some embodiments, the first functional structure 5011 may be a word line structure or a bit line structure. The embedded protection structure 5021 may be an embedded word line protection structure or an embedded bit line protection structure.

[0128] In the embodiments of the present disclosure, the embedded word line protection structure has the same composition structure as the word line structure, and the embedding depth of the embedded word line protection structure is the same as or different from the embedding depth of the word line structure; the embedded bit line protection structure has the same composition structure as the bit line structure, and the embedding depth of the embedded bit line protection structure is the same as or different from the embedding depth of the bit line structure.

[0129] Among them, the embedded word line protection structure adopts a tungsten metal structure (see Figure 3b) The buried word line protection structure is made of the same material as the word line structure, and the word line metal layer in the buried word line protection structure can be externally connected to a potential. Through metal layers such as the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4, the word line metal layer in the buried word line protection structure is externally connected to a potential to apply a voltage to the word line metal layer, thereby forming a negative potential in the word line metal layer. Through the adsorption effect of the negative potential, holes in the semiconductor substrate are adsorbed, thereby reducing the electromagnetic interference or other noise effects on the semiconductor chip and helping to stabilize the performance of the semiconductor device. Among them, the externally connected potential can be adjusted by a temperature sensor. In the case of a higher temperature, since the higher the temperature, the greater the electron energy, the potential of the word line metal layer can be reduced to improve the ability to absorb minority carriers in the semiconductor substrate, thereby reducing the electromagnetic interference or other noise effects on the finally formed semiconductor chip. In the case of a lower temperature, the potential of the word line metal layer can be increased to increase the number of electrons, thereby improving the ability to absorb minority carriers in the semiconductor substrate, and further reducing the electromagnetic interference or other noise effects on the finally formed semiconductor chip.

[0130] In some embodiments, the guard ring 502 around the chip 501 can also be grounded, so that minority carriers can be further absorbed and the electromagnetic interference or other noise on the semiconductor chip can be reduced.

[0131] Please continue to refer to Figure 5b , the guard ring 502 further includes a non-buried protection structure 5022 on the surface of the semiconductor substrate 500; the internal circuit structure further includes a second functional structure 5012 on the surface of the semiconductor substrate 500 of the chip; the non-buried protection structure 5022 is used to protect the second functional structure 5012.

[0132] In some embodiments, the second functional structure 5011 can be a capacitor structure. The non-buried protection structure 5022 includes at least two metal layers, at least one first through hole, and metal plugs, wherein the at least two metal layers, the at least one first through hole, and the metal plugs are used to protect the capacitor structure.

[0133] In the embodiments of the present disclosure, the height of the non-buried protection structure is greater than the height of the capacitor structure.

[0134] In some embodiments, the guard ring structure further includes a second through hole; the second through hole is used to realize the electrical connection between the bottommost metal layer in the non-buried protection structure and the buried word line protection structure.

[0135] In the embodiments of the present disclosure, the chip of the semiconductor structure can be a dynamic random access memory chip, a static random access memory chip, a phase change memory chip, a ferroelectric memory chip, a resistive random access memory chip, or a flash memory chip.

[0136] In the embodiments of the present disclosure, the guard ring in the semiconductor structure is similar to the guard ring in the above embodiments. For the technical features not exhaustively disclosed in the embodiments of the present disclosure, please refer to the above embodiments for understanding and will not be elaborated here.

[0137] In the semiconductor structure provided by the embodiments of the present disclosure, since the semiconductor structure includes a guard ring, and the guard ring includes an embedded protection structure, thus, the guard ring can protect the first functional structure formed inside the semiconductor substrate, and further has a good protection effect on the chip in the semiconductor structure.

[0138] In several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. Additionally, the couplings between the various components shown or discussed are either direct couplings.

[0139] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0140] The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0141] As described above, only some embodiments of the embodiments of the present disclosure are provided, but the protection scope of the embodiments of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the embodiments of the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A protection ring, characterized in that, At least include an embedded protection structure; The embedded protection structure is located in the semiconductor substrate; The embedded protection structure is used to protect a first functional structure formed inside the semiconductor substrate; wherein, The embedded protection structure includes an embedded word line protection structure; the first functional structure includes a word line structure; The embedded word line protection structure is used to protect the word line structure; The word line structure has the same compositional structure as the embedded word line protection structure; the compositional structure of the embedded word line protection structure at least includes a gate dielectric layer, a word line metal layer, and a gate protection pattern.

2. The guard ring according to claim 1, wherein The embedding depth of the embedded word line protection structure is the same as the embedding depth of the word line structure; or, the embedding depth of the embedded word line protection structure is greater than the embedding depth of the word line structure; or, the embedding depth of the embedded word line protection structure is less than the embedding depth of the word line structure.

3. The guard ring according to claim 2, characterized in that, In the embedded word line protection structure, the gate dielectric layer is located between the word line metal layer and the semiconductor substrate; The gate protection pattern is located on the top surfaces of the gate dielectric layer and the word line metal layer; The top surface of the semiconductor substrate is flush with the top surface of the gate protection pattern, or, the top surface of the semiconductor substrate protrudes beyond the top surface of the gate protection pattern.

4. The guard ring according to claim 1 or 2, characterized in that, The embedded protection structure includes an embedded bit line protection structure; the first functional structure includes a bit line structure; The embedded bit line protection structure is used to protect the bit line structure.

5. The guard ring according to claim 4, characterized in that, The embedding depth of the embedded bit line protection structure is the same as the embedding depth of the bit line structure; or, the embedding depth of the embedded bit line protection structure is greater than the embedding depth of the bit line structure; or, the embedding depth of the embedded bit line protection structure is less than the embedding depth of the bit line structure.

6. The guard ring according to claim 5, characterized in that, The bit line structure has the same compositional structure as the embedded bit line protection structure; The compositional structure of the embedded bit line protection structure at least includes a bit line metal layer; wherein, the top surface of the semiconductor substrate protrudes beyond the top surface of the bit line metal layer.

7. The guard ring according to claim 4, wherein The embedded bit line protection structure is electrically connected through internal or external potential components of one or more metal layers.

8. The guard ring according to claim 1, characterized in that, The protection ring further includes a non-embedded protection structure; The non-embedded protection structure is located on the surface of the semiconductor substrate, and the non-embedded protection structure is electrically connected to the semiconductor substrate; The non-embedded protection structure is used to protect a second functional structure formed on the surface of the semiconductor substrate.

9. The guard ring according to claim 8, wherein, The non-embedded protection structure includes: at least two metal layers, at least one first through hole, and a metal plug; The first through hole is used to achieve electrical connection between adjacent two metal layers; The metal plug is used to achieve electrical connection between the bottommost metal layer in the non-embedded protection structure and the semiconductor substrate.

10. The guard ring according to claim 9, characterized in that, The second functional structure includes a capacitor structure; The at least two metal layers, the at least one first through hole, and the metal plug are used to protect the capacitor structure.

11. The guard ring according to claim 10, wherein The height of the non-embedded protection structure is greater than the height of the capacitor structure.

12. The guard ring according to any one of claims 8 to 11, characterized in that, The protection ring further includes a second through hole; The second through hole is used to realize the electrical connection between the bottommost metal layer in the non-embedded protection structure and the word line metal layer.

13. The guard ring according to claim 1, characterized in that, The protection ring is formed around the semiconductor chip; The semiconductor chip includes a dynamic random access memory chip, a static random access memory chip, a phase change memory chip, a ferroelectric memory chip, a resistive random access memory chip, or a flash memory chip.

14. A protection ring, characterized in that, At least includes an embedded protection structure; The embedded protection structure is located in the semiconductor substrate; The embedded protection structure is used to protect the first functional structure formed inside the semiconductor substrate; wherein, The embedded protection structure includes an embedded bit line protection structure; the first functional structure includes a bit line structure; The embedded bit line protection structure is used to protect the bit line structure; The composition structure of the bit line structure is the same as that of the embedded bit line protection structure; The composition structure of the embedded bit line protection structure at least includes a bit line metal layer; wherein, the top surface of the semiconductor substrate protrudes beyond the top surface of the bit line metal layer.

15. The guard ring according to claim 14, characterized in that, The embedding depth of the embedded bit line protection structure is the same as that of the bit line structure; or, the embedding depth of the embedded bit line protection structure is greater than that of the bit line structure; or, the embedding depth of the embedded bit line protection structure is less than that of the bit line structure.

16. The guard ring according to claim 14, wherein The embedded bit line protection structure is electrically connected through internal or external potential components of one or more metal layers.

17. The guard ring according to claim 14, wherein The protection ring further includes a non-embedded protection structure; The non-embedded protection structure is located on the surface of the semiconductor substrate, and the non-embedded protection structure is electrically connected to the semiconductor substrate; The non-embedded protection structure is used to protect the second functional structure formed on the surface of the semiconductor substrate.

18. The guard ring according to claim 17, wherein The non-embedded protection structure includes: at least two metal layers, at least one first through hole, and a metal plug; The first through hole is used to realize the electrical connection between adjacent two metal layers; The metal plug is used to realize the electrical connection between the bottommost metal layer in the non-embedded protection structure and the semiconductor substrate.

19. The guard ring according to claim 18, characterized in that, The second functional structure includes a capacitor structure; The at least two metal layers, the at least one first through hole, and the metal plug are used to protect the capacitor structure.

20. The guard ring according to claim 19, wherein, The height of the non-embedded protection structure is greater than the height of the capacitor structure.

21. The guard ring according to any one of claims 17 to 20, characterized in that, The protection ring further includes a second through hole; The second through hole is used to realize the electrical connection between the bottommost metal layer in the non-embedded protection structure and the word line metal layer.

22. The guard ring according to claim 14, characterized in that, The protection ring is formed around the semiconductor chip; The semiconductor chip includes a dynamic random access memory chip, a static random access memory chip, a phase change memory chip, a ferroelectric memory chip, a resistive random access memory chip, or a flash memory chip.

23. A method for forming a protection ring, characterized in that, The method includes: Providing a semiconductor substrate; While forming the first functional structure located inside the semiconductor substrate, forming an embedded protection structure in the semiconductor substrate; wherein, the embedded protection structure is used to protect the first functional structure; The first functional structure and the embedded protection structure are formed simultaneously using the same process steps; The embedded protection structure has the same or different embedded depths as the first functional structure, and the embedded protection structure has the same compositional structure as the first functional structure.

24. The method according to claim 23, wherein The first functional structure includes a word line structure or a bit line structure.

25. The method according to any one of claims 23 to 24, characterized in that, The method further includes: Forming a non-embedded protection structure on the surface of the semiconductor substrate; Wherein, the non-embedded protection structure is used to protect a second functional structure formed on the surface of the semiconductor substrate.

26. The method according to claim 25, wherein The second functional structure includes a capacitor structure.

27. A semiconductor structure, characterized in that, Comprising: A chip and a protection ring located around the chip; Wherein, the protection ring is used to protect the internal circuit structure of the chip; The protection ring at least includes an embedded protection structure located inside the semiconductor substrate; the internal circuit structure at least includes a first functional structure located inside the semiconductor substrate of the chip; The embedded protection structure is used to protect the first functional structure; wherein, The embedded protection structure includes an embedded word line protection structure; the first functional structure includes a word line structure; The embedded word line protection structure is used to protect the word line structure; The compositional structure of the word line structure is the same as that of the embedded word line protection structure; the compositional structure of the embedded word line protection structure at least includes a gate dielectric layer, a word line metal layer, and a gate protection pattern; And / or The embedded protection structure includes an embedded bit line protection structure; the first functional structure includes a bit line structure; The embedded bit line protection structure is used to protect the bit line structure; The compositional structure of the bit line structure is the same as that of the embedded bit line protection structure; The compositional structure of the embedded bit line protection structure at least includes a bit line metal layer; wherein, the top surface of the semiconductor substrate protrudes beyond the top surface of the bit line metal layer.

28. The semiconductor structure according to claim 27, wherein The protection ring further includes a non-embedded protection structure located on the surface of the semiconductor substrate; the internal circuit structure further includes a second functional structure located on the surface of the semiconductor substrate of the chip; The non-embedded protection structure is used to protect the second functional structure.

29. The semiconductor structure according to claim 28, wherein The second functional structure includes a capacitor structure.

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