Capacitor and its manufacturing method and working method

Abstract

The present invention provides a capacitor and a manufacturing method and working method thereof, wherein the capacitor comprises: a substrate; a lower plate, a first dielectric layer and an upper plate formed on the substrate from bottom to top, wherein the lower plate comprises a metal layer and the upper plate comprises an N-type doped polysilicon layer; or, the lower plate comprises an N-type doped polysilicon layer and the upper plate comprises a metal layer; or, the lower plate and the upper plate both comprise an N-type doped polysilicon layer. The technical solution of the present invention enables the capacitor to have a plurality of variable capacitance values ​​while avoiding increasing the complexity of the process, increasing the cost and causing waste of chip area.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a capacitor and a manufacturing method and a working method thereof. Background Art

[0002] Existing MIM (Metal Insulator Metal) capacitors are manufactured by stacking a metal layer-a dielectric layer-a metal layer. Since the structure of MIM capacitors is fixed, this type of capacitor has only one capacitance value. If MIM capacitors with multiple capacitance values ​​are required, capacitors with different dielectric layer thicknesses need to be prepared. However, preparing dielectric layers with different thicknesses in the same film layer will increase the complexity of the process, increase costs, and cause a waste of chip area.

[0003] Therefore, how to prepare MIM capacitors with various capacitance values ​​while avoiding increasing process complexity, increasing costs, and wasting chip area is an urgent problem to be solved. Summary of the invention

[0004] The object of the present invention is to provide a capacitor and a manufacturing method and a working method thereof, so that the capacitor has a plurality of variable capacitance values ​​while avoiding increasing the complexity of the process, raising the cost and causing waste of chip area.

[0005] To achieve the above object, the present invention provides a capacitor, comprising:

[0006] substrate;

[0007] A lower plate, a first dielectric layer and an upper plate are formed on the substrate from bottom to top, wherein the lower plate includes a metal layer, and the upper plate includes an N-type doped polysilicon layer; or, the lower plate includes an N-type doped polysilicon layer, and the upper plate includes a metal layer; or, both the lower plate and the upper plate include an N-type doped polysilicon layer.

[0008] Optionally, the capacitor further includes:

[0009] A second dielectric layer is formed on the upper electrode plate.

[0010] Optionally, the lower plate and the first dielectric layer extend to the periphery of the upper plate; and the capacitor further comprises:

[0011] A third dielectric layer is formed on the substrate, and the third dielectric layer covers the second dielectric layer, the upper plate, the first dielectric layer and the lower plate;

[0012] a first conductive plug and a second conductive plug, wherein the first conductive plug is electrically connected to the upper plate after passing through the third dielectric layer and the second dielectric layer, and the second conductive plug is electrically connected to the lower plate after passing through the third dielectric layer and the first dielectric layer at the periphery of the upper plate;

[0013] A first pad and a second pad are formed on the third dielectric layer, the first pad is electrically connected to the first conductive plug, and the second pad is electrically connected to the second conductive plug.

[0014] Optionally, the material of the metal layer includes metal and / or metal nitride.

[0015] Optionally, the base includes a substrate and a fourth dielectric layer located on the substrate.

[0016] The present invention also provides a method for manufacturing a capacitor, comprising:

[0017] providing a substrate;

[0018] A lower plate, a first dielectric layer and an upper plate are formed from bottom to top on the substrate, wherein the lower plate includes a metal layer, and the upper plate includes an N-type doped polysilicon layer; or, the lower plate includes an N-type doped polysilicon layer, and the upper plate includes a metal layer; or, both the lower plate and the upper plate include an N-type doped polysilicon layer.

[0019] Optionally, the energy range of doping N-type ions is 50KeV to 200KeV, and the dose range is 5*10 11 cm -2 ~5*10 14 cm -2 .

[0020] The present invention also provides a working method of a capacitor, wherein the capacitor comprises a lower plate, a first dielectric layer and an upper plate formed on a substrate from bottom to top;

[0021] Wherein, the lower plate includes a metal layer, the upper plate includes an N-type doped polysilicon layer, and the working method of the capacitor includes:

[0022] Connecting the lower plate to a positive voltage so that the first dielectric layer serves as the dielectric layer of the capacitor; connecting the upper plate to a positive voltage so that a portion of the upper plate close to the first dielectric layer forms an equivalent dielectric layer, and the first dielectric layer and the equivalent dielectric layer serve together as the dielectric layer of the capacitor;

[0023] Alternatively, the lower plate includes an N-type doped polysilicon layer, the upper plate includes a metal layer, and the working method of the capacitor includes:

[0024] Connecting the upper plate to a positive voltage so that the first dielectric layer serves as the dielectric layer of the capacitor; connecting the lower plate to a positive voltage so that a portion of the thickness of the lower plate close to the first dielectric layer forms an equivalent dielectric layer, and the first dielectric layer and the equivalent dielectric layer serve together as the dielectric layer of the capacitor;

[0025] Alternatively, the lower plate and the upper plate both include an N-type doped polysilicon layer, and the working method of the capacitor includes:

[0026] The lower plate is connected to a positive voltage so that a portion of the thickness of the lower plate close to the first dielectric layer forms an equivalent dielectric layer, and the first dielectric layer and the equivalent dielectric layer together serve as the dielectric layer of the capacitor; the upper plate is connected to a positive voltage so that a portion of the thickness of the upper plate close to the first dielectric layer forms an equivalent dielectric layer, and the first dielectric layer and the equivalent dielectric layer together serve as the dielectric layer of the capacitor.

[0027] Optionally, the capacitor further includes:

[0028] A second dielectric layer is formed on the upper electrode plate.

[0029] Optionally, the lower plate and the first dielectric layer extend to the periphery of the upper plate; and the capacitor further comprises:

[0030] A third dielectric layer is formed on the substrate, and the third dielectric layer covers the second dielectric layer, the upper plate, the first dielectric layer and the lower plate;

[0031] a first conductive plug and a second conductive plug, wherein the first conductive plug is electrically connected to the upper plate after passing through the third dielectric layer and the second dielectric layer, and the second conductive plug is electrically connected to the lower plate after passing through the third dielectric layer and the first dielectric layer at the periphery of the upper plate;

[0032] A first pad and a second pad are formed on the third dielectric layer, the first pad is electrically connected to the first conductive plug, and the second pad is electrically connected to the second conductive plug.

[0033] Optionally, the material of the metal layer includes metal and / or metal nitride.

[0034] Optionally, the base includes a substrate and a fourth dielectric layer located on the substrate.

[0035] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0036] 1. The capacitor of the present invention comprises a lower plate, a first dielectric layer and an upper plate formed from bottom to top on a substrate, wherein the metal layer serves as the lower plate of the capacitor, the lower plate comprises a metal layer, and the upper plate comprises an N-type doped polysilicon layer; or, the lower plate comprises an N-type doped polysilicon layer, and the upper plate comprises a metal layer; or, the lower plate and the upper plate both comprise an N-type doped polysilicon layer, so that the capacitor has a plurality of variable capacitance values ​​while avoiding increasing the complexity of the process, increasing the cost and causing a waste of chip area.

[0037] 2. The manufacturing method of the capacitor of the present invention forms a lower plate, a first dielectric layer and an upper plate from bottom to top on a substrate, wherein the lower plate includes a metal layer, and the upper plate includes an N-type doped polysilicon layer; or, the lower plate includes an N-type doped polysilicon layer, and the upper plate includes a metal layer; or, the lower plate and the upper plate both include an N-type doped polysilicon layer, so that the capacitor has a plurality of variable capacitance values ​​while avoiding increasing the complexity of the process, increasing the cost and causing a waste of chip area.

[0038] 3. The working method of the capacitor of the present invention, when the lower plate includes a metal layer and the upper plate includes an N-type doped polysilicon layer, the lower plate is connected to a positive voltage so that the first dielectric layer serves as the dielectric layer of the capacitor; the upper plate is connected to a positive voltage so that a portion of the thickness of the upper plate close to the first dielectric layer is formed into an equivalent dielectric layer, and the first dielectric layer and the equivalent dielectric layer serve together as the dielectric layer of the capacitor; or, when the lower plate includes an N-type doped polysilicon layer and the upper plate includes a metal layer, the upper plate is connected to a positive voltage so that the first dielectric layer serves as the dielectric layer of the capacitor; the lower plate is connected to a positive voltage so that a portion of the thickness of the lower plate close to the first dielectric layer is formed into an equivalent dielectric layer. The first dielectric layer and the equivalent dielectric layer are used together as the dielectric layer of the capacitor; or, when the lower plate and the upper plate both include an N-type doped polysilicon layer, by connecting the lower plate to a positive voltage so that a portion of the thickness of the lower plate close to the first dielectric layer is formed as an equivalent dielectric layer, the first dielectric layer and the equivalent dielectric layer are used together as the dielectric layer of the capacitor; connecting the upper plate to a positive voltage so that a portion of the thickness of the upper plate close to the first dielectric layer is formed as an equivalent dielectric layer, the first dielectric layer and the equivalent dielectric layer are used together as the dielectric layer of the capacitor, so that the capacitor has a plurality of variable capacitance values ​​while avoiding increasing the complexity of the process, increasing the cost and causing a waste of chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a schematic structural diagram of a capacitor according to an embodiment of the present invention;

[0040] Figure 2a to Figure 2b is a schematic diagram showing the principle of a capacitor having a variable capacitance value according to an embodiment of the present invention;

[0041] Figure 3 is a flow chart of a method for manufacturing a capacitor according to an embodiment of the present invention;

[0042] Figure 4a to Figure 4c yes Figure 3 A device schematic diagram of a capacitor manufacturing method is shown.

[0043] Among them, Figure 1 to Figure 4c The reference numerals are described as follows:

[0044] 11-metal interconnection line; 12-fourth dielectric layer; 13-lower electrode; 131-lower electrode material layer; 14-first dielectric layer; 141-first dielectric material layer; 15-upper electrode; 151-upper electrode material layer; 16-second dielectric layer; 161-second dielectric material layer; 17-third dielectric layer; 181-first conductive plug; 182-second conductive plug; 191-first pad; 192-second pad; 20-equivalent dielectric layer. DETAILED DESCRIPTION

[0045] In order to make the purpose, advantages and features of the present invention more clear, the capacitor and its manufacturing method and working method proposed in the present invention are further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0046] An embodiment of the present invention provides a capacitor, comprising: a substrate; a lower plate, a first dielectric layer and an upper plate formed on the substrate from bottom to top, the lower plate comprising a metal layer, and the upper plate comprising an N-type doped polysilicon layer; or, the lower plate comprising an N-type doped polysilicon layer, and the upper plate comprising a metal layer; or, both the lower plate and the upper plate comprise an N-type doped polysilicon layer.

[0047] See below Figure 1 to Figure 2b The capacitor provided by this embodiment is described in detail.

[0048] In one embodiment, the base includes a substrate and a fourth dielectric layer located on the substrate.

[0049] In another embodiment, the base includes a substrate (not shown) from bottom to top, a fourth dielectric layer 12 , and a metal interconnection line 11 formed in the fourth dielectric layer 12 .

[0050] It should be noted that the fourth dielectric layer 12 is a multi-layer stacked structure. Figure 1Only a portion of the fourth dielectric layer 12 covering the metal interconnection line 11 is shown schematically; in addition, a conductive plug or the like electrically connected to the metal interconnection line 11 may also be formed in the fourth dielectric layer 12 .

[0051] The material of the substrate can be any suitable base material known to those skilled in the art, for example, it can be at least one of the following materials: silicon, germanium, silicon germanium, carbon silicon, carbon germanium silicon, indium arsenide, gallium arsenide, indium phosphide or semiconductor on insulator (SOI, such as silicon on insulator), etc.

[0052] A lower plate 13, a first dielectric layer 14 and an upper plate 15 are formed on the fourth dielectric layer 12 from bottom to top, wherein the lower plate 13 includes a metal layer, and the upper plate 15 includes an N-type doped polysilicon layer; or, the lower plate 13 includes an N-type doped polysilicon layer, and the upper plate 15 includes a metal layer; or, both the lower plate 13 and the upper plate 15 include an N-type doped polysilicon layer.

[0053] The material of the metal layer may include metal or metal nitride, or may include both metal and metal nitride. The material of the metal layer is a metal or metal compound with metallic properties such as aluminum, copper, tantalum, tantalum nitride, titanium, titanium nitride or tungsten.

[0054] The material of the first dielectric layer 14 is preferably a high-K (relative dielectric constant) dielectric, such as at least one of zinc oxide, hafnium oxide, titanium oxide, and zirconium oxide. It should be noted that the material of the first dielectric layer 14 can also be at least one of silicon oxide, silicon oxynitride, silicon nitride, and ONO (silicon oxide-silicon nitride-silicon oxide).

[0055] The material of the N-type doped polysilicon layer is polysilicon doped with N-type ions, so that majority carriers in the N-type doped polysilicon layer are electrons. The N-type ions include phosphorus, arsenic or antimony.

[0056] The capacitor further includes a second dielectric layer 16 formed on the upper plate 15 .

[0057] The lower plate 13 and the first dielectric layer 14 are formed on a portion of the fourth dielectric layer 12 , and the upper plate 15 and the second dielectric layer 16 are formed on a portion of the first dielectric layer 14 , that is, the lower plate 13 and the first dielectric layer 14 extend to the periphery of the upper plate 15 .

[0058] The capacitor may further include:

[0059] A third dielectric layer 17 is formed on the substrate, and the third dielectric layer 17 covers the second dielectric layer 16, the upper electrode plate 15, the first dielectric layer 14 and the lower electrode plate 13;

[0060] A first conductive plug 181 and a second conductive plug 182, wherein the first conductive plug 181 penetrates the third dielectric layer 17 and the second dielectric layer 16 and is electrically connected to the upper electrode plate 15, and the second conductive plug 182 penetrates the third dielectric layer 17 and the first dielectric layer 14 at the periphery of the upper electrode plate 15 and is electrically connected to the lower electrode plate 13;

[0061] A first pad 191 and a second pad 192 are formed on the third dielectric layer 17 , wherein the first pad 191 is electrically connected to the first conductive plug 181 , and the second pad 192 is electrically connected to the second conductive plug 182 , so that voltage can be applied to the upper electrode plate 15 and the lower electrode plate 13 through the first pad 191 and the second pad 192 .

[0062] The second dielectric layer 16 and the third dielectric layer 17 may be made of silicon oxide, silicon oxynitride, silicon nitride, ONO (silicon oxide-silicon nitride-silicon oxide), or the like.

[0063] Taking the case where the lower plate 13 includes a metal layer and the upper plate 15 includes an N-type doped polysilicon layer as an example, the principle of realizing that the capacitor has a plurality of variable capacitance values ​​is described as follows:

[0064] like Figure 2a As shown, when the lower plate 13 (i.e., the metal layer) is connected to a positive voltage and the upper plate 15 (i.e., the N-type doped polysilicon layer) is grounded or connected to a negative voltage, the electrons in the N-type doped polysilicon layer move toward the first dielectric layer 14, and the electrons gather on the side of the N-type doped polysilicon layer close to the first dielectric layer 14. At this time, the first dielectric layer 14 serves as the dielectric layer of the capacitor (i.e., the dielectric layer located between the upper plate 15 and the lower plate 13). The thickness of the dielectric layer of the capacitor is always maintained at the thickness h1 of the first dielectric layer 14, and will not change with the change of the voltage difference between the lower plate 13 and the upper plate 15, so that the capacitance value of the capacitor remains fixed.

[0065] And as Figure 2bAs shown, when the upper plate 15 (i.e., the N-type doped polysilicon layer) is connected to a positive voltage and the lower plate 13 (i.e., the metal layer) is grounded or connected to a negative voltage, the electrons in the N-type doped polysilicon layer move in a direction away from the first dielectric layer 14 and flow away along the wire in the external circuit, so that the potential of the N-type doped polysilicon layer is the same as that of the power supply, and the electrons in the metal layer sense the potential difference and gather on the side of the metal layer close to the first dielectric layer 14, so that there is no carrier on the side of the N-type doped polysilicon layer close to the first dielectric layer 14 and a depletion layer is formed. This depletion layer can serve as an equivalent dielectric layer 20, that is, the thickness of the portion of the upper plate 15 close to the first dielectric layer 14 is formed as the equivalent dielectric layer 20. At this time, the first dielectric layer 14 and the equivalent dielectric layer 20 together serve as the dielectric layer of the capacitor, so that the thickness of the dielectric layer of the capacitor is increased from Figure 2a The thickness h1 of the first dielectric layer 14 in the embodiment increases to the sum of the thickness h1 of the first dielectric layer 14 and the thickness h2 of the equivalent dielectric layer 20, thereby making Figure 2a Compared with the capacitor, the capacitance value of the capacitor is reduced; and the thickness h2 of the equivalent dielectric layer 20 also changes with the change of the voltage difference between the upper plate 15 and the lower plate 13, so that the capacitance value of the capacitor can change with the change of the voltage difference between the upper plate 15 and the lower plate 13. Among them, the thickness h2 of the equivalent dielectric layer 20 increases with the increase of the voltage difference between the upper plate 15 and the lower plate 13, so that the capacitance value of the capacitor decreases with the increase of the voltage difference between the upper plate 15 and the lower plate 13.

[0066] Therefore, the capacitance value of the capacitor changes with the different ways in which the upper plate 15 and the lower plate 13 are connected to the positive voltage, and the capacitance value of the capacitor changes with the change of the voltage difference between the upper plate 15 and the lower plate 13, so that the capacitor has multiple variable capacitance values.

[0067] Similarly, when the lower plate 13 includes an N-type doped polysilicon layer and the upper plate 15 includes a metal layer, if the upper plate 15 is connected to a positive voltage and the lower plate 13 is grounded or connected to a negative voltage, the first dielectric layer 14 serves as the dielectric layer of the capacitor; if the lower plate 13 is connected to a positive voltage and the upper plate 15 is grounded or connected to a negative voltage, the partial thickness of the lower plate 13 close to the first dielectric layer 14 is formed as an equivalent dielectric layer, and the first dielectric layer 14 and the equivalent dielectric layer together serve as the dielectric layer of the capacitor.

[0068] Alternatively, when the lower plate 13 and the upper plate 15 both include an N-type doped polysilicon layer, if the lower plate 13 is connected to a positive voltage and the upper plate 15 is grounded or connected to a negative voltage, the thickness of the lower plate 13 close to the first dielectric layer 14 is formed as an equivalent dielectric layer, and the first dielectric layer 14 and the equivalent dielectric layer together serve as the dielectric layer of the capacitor; if the upper plate 15 is connected to a positive voltage and the lower plate 13 is grounded or connected to a negative voltage, the thickness of the upper plate 15 close to the first dielectric layer 14 is formed as an equivalent dielectric layer, and the first dielectric layer 14 and the equivalent dielectric layer together serve as the dielectric layer of the capacitor.

[0069] Furthermore, due to the existence of the equivalent dielectric layer 20, the dielectric layer thickness of the capacitor increases, thereby making the capacitor more difficult to break down, thereby improving the stability of the capacitor in use.

[0070] Furthermore, compared with the existing method of preparing capacitors with different dielectric layer thicknesses to make the capacitors have multiple capacitance values, the capacitor of the present invention adopts the N-type doped polysilicon layer to replace the existing metal layer as the upper plate 15 and / or the lower plate 13 of the capacitor, so that only the way of connecting the upper plate 15 and the lower plate 13 to the positive voltage and the size of the voltage difference between the upper plate 15 and the lower plate 13 need to be changed to achieve the capacitor having multiple variable capacitance values, thereby avoiding increasing the complexity of the process, increasing the cost and causing waste of chip area.

[0071] Moreover, when the lower plate 13 includes a metal layer and the upper plate 15 includes an N-type doped polysilicon layer, since the plurality of first conductive plugs 181 electrically connected to the upper plate 15 can be evenly distributed on the upper plate 15, the depletion layer generated when the upper plate 15 is connected to a positive voltage and the lower plate 13 is grounded or connected to a negative voltage can be more evenly distributed on the side of the upper plate 15 close to the first dielectric layer 14, that is, the thickness of the formed equivalent dielectric layer 20 is more uniform, thereby avoiding leakage problems and increasing the service life of the capacitor.

[0072] In summary, the present invention provides a capacitor, comprising: a substrate; a lower plate, a first dielectric layer and an upper plate formed on the substrate from bottom to top, the lower plate comprising a metal layer, the upper plate comprising an N-type doped polysilicon layer; or, the lower plate comprising an N-type doped polysilicon layer, the upper plate comprising a metal layer; or, the lower plate and the upper plate both comprising an N-type doped polysilicon layer. The capacitor provided by the present invention enables the capacitor to have a variety of variable capacitance values ​​while avoiding increasing the complexity of the process, increasing costs and causing waste of chip area.

[0073] Based on the same inventive concept, an embodiment of the present invention provides a method for manufacturing a capacitor, referring to Figure 3 ,from Figure 3 It can be seen that the manufacturing method of the capacitor includes:

[0074] Step S1, providing a substrate;

[0075] Step S2, forming a lower plate, a first dielectric layer and an upper plate from bottom to top on the substrate, wherein the lower plate includes a metal layer, and the upper plate includes an N-type doped polysilicon layer; or, the lower plate includes an N-type doped polysilicon layer, and the upper plate includes a metal layer; or, both the lower plate and the upper plate include an N-type doped polysilicon layer.

[0076] See below Figure 2a to Figure 2b , Figure 4a to Figure 4c The method for manufacturing the capacitor provided in this embodiment is described in detail.

[0077] According to step S1, a substrate is provided.

[0078] In one embodiment, the base includes a substrate and a fourth dielectric layer located on the substrate.

[0079] In another embodiment, the base includes a substrate (not shown) from bottom to top, a fourth dielectric layer 12 , and a metal interconnection line 11 formed in the fourth dielectric layer 12 .

[0080] It should be noted that the fourth dielectric layer 12 is a multi-layer stacked structure. Figure 4a to Figure 4c Only a portion of the fourth dielectric layer 12 covering the metal interconnection line 11 is shown schematically; in addition, a conductive plug or the like electrically connected to the metal interconnection line 11 may also be formed in the fourth dielectric layer 12 .

[0081] The material of the substrate can be any suitable base material known to those skilled in the art, for example, it can be at least one of the following materials: silicon, germanium, silicon germanium, carbon silicon, carbon germanium silicon, indium arsenide, gallium arsenide, indium phosphide or semiconductor on insulator (SOI, such as silicon on insulator), etc.

[0082] According to step S2, a lower plate 13, a first dielectric layer 14 and an upper plate 15 are formed from bottom to top on the substrate, wherein the lower plate 13 includes a metal layer, and the upper plate 15 includes an N-type doped polysilicon layer; or, the lower plate 13 includes an N-type doped polysilicon layer, and the upper plate 15 includes a metal layer; or, both the lower plate 13 and the upper plate 15 include an N-type doped polysilicon layer.

[0083] The material of the metal layer may include metal or metal nitride, or may include both metal and metal nitride. The material of the metal layer is a metal or metal compound with metallic properties such as aluminum, copper, tantalum, tantalum nitride, titanium, titanium nitride or tungsten.

[0084] The material of the first dielectric layer 14 is preferably a high-K (relative dielectric constant) dielectric, such as at least one of zinc oxide, hafnium oxide, titanium oxide, and zirconium oxide. It should be noted that the material of the first dielectric layer 14 can also be at least one of silicon oxide, silicon oxynitride, silicon nitride, and ONO (silicon oxide-silicon nitride-silicon oxide).

[0085] The method for manufacturing the capacitor may further include: forming a second dielectric layer 16 on the upper electrode plate 15 .

[0086] The steps of forming the lower plate 13, the first dielectric layer 14, the upper plate 15 and the second dielectric layer 16 may include: first, Figure 4a As shown, a lower plate material layer 131, a first dielectric material layer 141, an upper plate material layer 151 and a second dielectric material layer 161 are sequentially formed to cover the fourth dielectric layer 12 in the substrate; then, as shown in FIG. Figure 4b As shown, a portion of the second dielectric material layer 161 and a portion of the upper plate material layer 151 are sequentially etched away to expose the first dielectric material layer 141, and the remaining second dielectric material layer 161 is used as the second dielectric layer 16, and the remaining upper plate material layer 151 is used as the upper plate 15; then, as shown Figure 4b As shown, the partially exposed first dielectric material layer 141 and the lower electrode material layer 131 are etched away in sequence to expose the fourth dielectric layer 12 in the substrate, and the remaining first dielectric material layer 141 serves as the first dielectric layer 14, and the remaining lower electrode material layer 131 serves as the lower electrode 13, and the lower electrode 13 and the first dielectric layer 14 extend to the periphery of the upper electrode 15.

[0087] Among them, when the lower electrode plate 13 and / or the upper electrode plate 15 both include an N-type doped polysilicon layer, the step of forming the N-type doped polysilicon layer may include: simultaneously depositing polysilicon and doping N-type ions into the polysilicon, wherein a low-temperature chemical vapor deposition process can be used at 380°C to 420°C; or, polysilicon can be deposited first, and then an ion implantation process is used to dope N-type ions into the polysilicon.

[0088] When doping N-type ions into the polysilicon, a suitable amount of the N-type ions may be selected to avoid excessive doping that results in a reduction in the polysilicon depletion effect, and to avoid less doping that results in a higher resistance of the N-type doped polysilicon layer.

[0089] The energy range of doping the N-type ions is preferably 50KeV to 200KeV, and the dosage range is preferably 5*10 11 cm -2 ~5*10 14 cm -2 Moreover, when the N-type ion is phosphorus, the energy range is preferably 50KeV to 150KeV; when the N-type ion is arsenic, the energy range is preferably 50KeV to 170KeV; when the N-type ion is antimony, the energy range is preferably 70KeV to 200KeV.

[0090] After forming polysilicon doped with N-type ions, a laser annealing process may be performed to activate the N-type ions. The temperature range of the laser annealing process is preferably 350° C. to 450° C., and the time range of the laser annealing process is preferably 30s to 60s.

[0091] like Figure 4c As shown, the method for manufacturing the capacitor may further include:

[0092] First, a third dielectric layer 17 is formed on the substrate, and the third dielectric layer 17 covers the second dielectric layer 16, the upper electrode plate 15, the first dielectric layer 14 and the lower electrode plate 13;

[0093] Then, a first conductive plug 181 and a second conductive plug 182 are formed. The first conductive plug 181 penetrates the third dielectric layer 17 and the second dielectric layer 16 and is electrically connected to the upper electrode plate 15. The second conductive plug 182 penetrates the third dielectric layer 17 and the first dielectric layer 14 at the periphery of the N-type doped polysilicon layer 15 and is electrically connected to the lower electrode plate 13.

[0094] Then, a first pad 191 and a second pad 192 are formed on the third dielectric layer 17 , wherein the first pad 191 is electrically connected to the first conductive plug 181 , and the second pad 192 is electrically connected to the second conductive plug 182 , so that voltage can be connected to the upper electrode 15 and the lower electrode 13 through the first pad 191 and the second pad 192 .

[0095] The second dielectric layer 16 and the third dielectric layer 17 may be made of silicon oxide, silicon oxynitride, silicon nitride, ONO (silicon oxide-silicon nitride-silicon oxide), or the like.

[0096] Taking the case where the lower plate 13 includes a metal layer and the upper plate 15 includes an N-type doped polysilicon layer as an example, the principle of realizing that the capacitor has a plurality of variable capacitance values ​​is described as follows:

[0097] like Figure 2aAs shown, when the lower plate 13 (i.e., the metal layer) is connected to a positive voltage and the upper plate 15 (i.e., the N-type doped polysilicon layer) is grounded or connected to a negative voltage, the electrons in the N-type doped polysilicon layer move toward the first dielectric layer 14, and the electrons gather on the side of the N-type doped polysilicon layer close to the first dielectric layer 14. At this time, the first dielectric layer 14 serves as the dielectric layer of the capacitor (i.e., the dielectric layer located between the upper plate 15 and the lower plate 13). The thickness of the dielectric layer of the capacitor is always maintained at the thickness h1 of the first dielectric layer 14, and will not change with the change of the voltage difference between the lower plate 13 and the upper plate 15, so that the capacitance value of the capacitor remains fixed.

[0098] And as Figure 2b As shown, when the upper plate 15 (i.e., the N-type doped polysilicon layer) is connected to a positive voltage and the lower plate 13 (i.e., the metal layer) is grounded or connected to a negative voltage, the electrons in the N-type doped polysilicon layer move in a direction away from the first dielectric layer 14 and flow away along the wire in the external circuit, so that the potential of the N-type doped polysilicon layer is the same as that of the power supply, and the electrons in the metal layer sense the potential difference and gather on the side of the metal layer close to the first dielectric layer 14, so that there is no carrier on the side of the N-type doped polysilicon layer close to the first dielectric layer 14 and a depletion layer is formed. This depletion layer can serve as an equivalent dielectric layer 20, that is, the thickness of the portion of the upper plate 15 close to the first dielectric layer 14 is formed as the equivalent dielectric layer 20. At this time, the first dielectric layer 14 and the equivalent dielectric layer 20 together serve as the dielectric layer of the capacitor, so that the thickness of the dielectric layer of the capacitor is increased from Figure 2a The thickness h1 of the first dielectric layer 14 in the embodiment increases to the sum of the thickness h1 of the first dielectric layer 14 and the thickness h2 of the equivalent dielectric layer 20, thereby making Figure 2a Compared with the capacitor, the capacitance value of the capacitor is reduced; and the thickness h2 of the equivalent dielectric layer 20 also changes with the change of the voltage difference between the upper plate 15 and the lower plate 13, so that the capacitance value of the capacitor can change with the change of the voltage difference between the upper plate 15 and the lower plate 13. Among them, the thickness h2 of the equivalent dielectric layer 20 increases with the increase of the voltage difference between the upper plate 15 and the lower plate 13, so that the capacitance value of the capacitor decreases with the increase of the voltage difference between the upper plate 15 and the lower plate 13.

[0099] Therefore, the capacitance value of the capacitor changes with the different ways in which the upper plate 15 and the lower plate 13 are connected to the positive voltage, and the capacitance value of the capacitor changes with the change of the voltage difference between the upper plate 15 and the lower plate 13, so that the capacitor has multiple variable capacitance values.

[0100] Similarly, when the lower plate 13 includes an N-type doped polysilicon layer and the upper plate 15 includes a metal layer, if the upper plate 15 is connected to a positive voltage and the lower plate 13 is grounded or connected to a negative voltage, the first dielectric layer 14 serves as the dielectric layer of the capacitor; if the lower plate 13 is connected to a positive voltage and the upper plate 15 is grounded or connected to a negative voltage, the partial thickness of the lower plate 13 close to the first dielectric layer 14 is formed as an equivalent dielectric layer, and the first dielectric layer 14 and the equivalent dielectric layer together serve as the dielectric layer of the capacitor.

[0101] Alternatively, when the lower plate 13 and the upper plate 15 both include an N-type doped polysilicon layer, if the lower plate 13 is connected to a positive voltage and the upper plate 15 is grounded or connected to a negative voltage, the thickness of the lower plate 13 close to the first dielectric layer 14 is formed as an equivalent dielectric layer, and the first dielectric layer 14 and the equivalent dielectric layer together serve as the dielectric layer of the capacitor; if the upper plate 15 is connected to a positive voltage and the lower plate 13 is grounded or connected to a negative voltage, the thickness of the upper plate 15 close to the first dielectric layer 14 is formed as an equivalent dielectric layer, and the first dielectric layer 14 and the equivalent dielectric layer together serve as the dielectric layer of the capacitor.

[0102] Furthermore, due to the existence of the equivalent dielectric layer 20, the dielectric layer thickness of the capacitor increases, thereby making the capacitor more difficult to break down, thereby improving the stability of the capacitor in use.

[0103] Furthermore, compared with the existing method of preparing capacitors with different dielectric layer thicknesses to make the capacitors have multiple capacitance values, the capacitor manufacturing method of the present invention adopts the N-type doped polysilicon layer to replace the existing metal layer as the upper plate 15 and / or the lower plate 13 of the capacitor, so that only the way of connecting the upper plate 15 and the lower plate 13 to the positive voltage and the size of the voltage difference between the upper plate 15 and the lower plate 13 need to be changed to achieve the capacitor having multiple variable capacitance values, thereby avoiding increasing the complexity of the process, increasing the cost and causing waste of chip area.

[0104] Moreover, when the lower plate 13 includes a metal layer and the upper plate 15 includes an N-type doped polysilicon layer, since the plurality of first conductive plugs 181 electrically connected to the upper plate 15 can be evenly distributed on the upper plate 15, the depletion layer generated when the upper plate 15 is connected to a positive voltage and the lower plate 13 is grounded or connected to a negative voltage can be more evenly distributed on the side of the upper plate 15 close to the first dielectric layer 14, that is, the thickness of the formed equivalent dielectric layer 20 is more uniform, thereby avoiding leakage problems and increasing the service life of the capacitor.

[0105] In summary, the present invention provides a method for manufacturing a capacitor, comprising: providing a substrate; forming a lower plate, a first dielectric layer and an upper plate from bottom to top on the substrate, wherein the lower plate includes a metal layer, and the upper plate includes an N-type doped polysilicon layer; or, the lower plate includes an N-type doped polysilicon layer, and the upper plate includes a metal layer; or, the lower plate and the upper plate both include an N-type doped polysilicon layer. The method for manufacturing a capacitor provided by the present invention allows the capacitor to have a plurality of variable capacitance values ​​while avoiding increasing the complexity of the process, increasing costs and causing waste of chip area.

[0106] Based on the same inventive concept, an embodiment of the present invention provides a method for operating a capacitor, wherein the capacitor includes a lower plate 13, a first dielectric layer 14 and an upper plate 15 formed on a substrate from bottom to top.

[0107] The specific structure of the capacitor is shown in the above description and will not be repeated here.

[0108] When the lower plate 13 includes a metal layer and the upper plate 15 includes an N-type doped polysilicon layer, the working method of the capacitor includes:

[0109] like Figure 2a As shown, the lower plate 13 (i.e., the metal layer) is connected to a positive voltage and the upper plate 15 (i.e., the N-type doped polysilicon layer) is grounded or connected to a negative voltage, so that the electrons in the N-type doped polysilicon layer move toward the first dielectric layer 14, and the electrons gather on the side of the N-type doped polysilicon layer close to the first dielectric layer 14, thereby making the first dielectric layer 14 serve as the dielectric layer of the capacitor (i.e., the dielectric layer located between the upper plate 15 and the lower plate 13), and the thickness of the dielectric layer of the capacitor is always maintained at the thickness h1 of the first dielectric layer 14, and will not change with the change of the voltage difference between the lower plate 13 and the upper plate 15, so that the capacitance value of the capacitor is fixed.

[0110] like Figure 2bAs shown, the upper plate 15 (i.e., the N-type doped polysilicon layer) is connected to a positive voltage and the lower plate 13 (i.e., the metal layer) is grounded or connected to a negative voltage, so that the electrons in the N-type doped polysilicon layer move in a direction away from the first dielectric layer 14 and flow away along the wire in the external circuit, so that the N-type doped polysilicon layer has the same potential as the power supply, and the electrons in the metal layer are induced by the potential difference and gather on the side of the metal layer close to the first dielectric layer 14, so that there is no carrier on the side of the N-type doped polysilicon layer close to the first dielectric layer 14 and a depletion layer is formed, and this depletion layer can be used as an equivalent dielectric layer 20, that is, the thickness of the upper plate 15 close to the first dielectric layer 14 is formed as the equivalent dielectric layer 20, so that the first dielectric layer 14 and the equivalent dielectric layer 20 are used together as the dielectric layer of the capacitor, so that the thickness of the dielectric layer of the capacitor is increased from Figure 2a The thickness h1 of the first dielectric layer 14 in the embodiment increases to the sum of the thickness h1 of the first dielectric layer 14 and the thickness h2 of the equivalent dielectric layer 20, thereby making Figure 2a Compared with the capacitor, the capacitance value of the capacitor is reduced; and the thickness h2 of the equivalent dielectric layer 20 also changes with the change of the voltage difference between the upper plate 15 and the lower plate 13, so that the capacitance value of the capacitor can change with the change of the voltage difference between the upper plate 15 and the lower plate 13. Among them, the thickness h2 of the equivalent dielectric layer 20 increases with the increase of the voltage difference between the upper plate 15 and the lower plate 13, so that the capacitance value of the capacitor decreases with the increase of the voltage difference between the upper plate 15 and the lower plate 13.

[0111] Alternatively, when the lower plate 13 includes an N-type doped polysilicon layer and the upper plate 15 includes a metal layer, the working method of the capacitor includes:

[0112] The upper plate 15 is connected to a positive voltage and the lower plate 13 is grounded or connected to a negative voltage, so that the first dielectric layer 14 serves as the dielectric layer of the capacitor; the lower plate 13 is connected to a positive voltage and the upper plate 15 is grounded or connected to a negative voltage, so that the thickness of the lower plate 13 close to the first dielectric layer 14 forms an equivalent dielectric layer, and the first dielectric layer 14 and the equivalent dielectric layer together serve as the dielectric layer of the capacitor.

[0113] Alternatively, when both the lower plate 13 and the upper plate 15 include an N-type doped polysilicon layer, the working method of the capacitor includes:

[0114] The lower electrode plate 13 is connected to a positive voltage and the upper electrode plate 15 is grounded or connected to a negative voltage, so that the thickness of the lower electrode plate 13 close to the first dielectric layer 14 forms an equivalent dielectric layer, and the first dielectric layer 14 and the equivalent dielectric layer together serve as the dielectric layer of the capacitor; the upper electrode plate 15 is connected to a positive voltage and the lower electrode plate 13 is grounded or connected to a negative voltage, so that the thickness of the upper electrode plate 15 close to the first dielectric layer 14 forms an equivalent dielectric layer, and the first dielectric layer 14 and the equivalent dielectric layer together serve as the dielectric layer of the capacitor.

[0115] Furthermore, due to the existence of the equivalent dielectric layer, the thickness of the dielectric layer of the capacitor increases, thereby making the capacitor more difficult to break down, thereby improving the stability of the capacitor in use.

[0116] Furthermore, compared with the existing method of preparing capacitors with different dielectric layer thicknesses to make the capacitors have multiple capacitance values, the capacitor of the present invention adopts the N-type doped polysilicon layer to replace the existing metal layer as the upper plate 15 and / or the lower plate 13 of the capacitor, so that only the way of connecting the upper plate 15 and the lower plate 13 to the positive voltage and the size of the voltage difference between the upper plate 15 and the lower plate 13 need to be changed to achieve the capacitor having multiple variable capacitance values, thereby avoiding increasing the complexity of the process, increasing the cost and causing waste of chip area.

[0117] Moreover, when the lower plate 13 includes a metal layer and the upper plate 15 includes an N-type doped polysilicon layer, since the plurality of first conductive plugs 181 electrically connected to the upper plate 15 can be evenly distributed on the upper plate 15, the depletion layer generated when the upper plate 15 is connected to a positive voltage and the lower plate 13 is grounded or connected to a negative voltage can be more evenly distributed on the side of the upper plate 15 close to the first dielectric layer 14, that is, the thickness of the formed equivalent dielectric layer 20 is more uniform, thereby avoiding leakage problems and increasing the service life of the capacitor.

[0118] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A capacitor, characterized in that: include: substrate; A lower plate, a first dielectric layer and an upper plate are formed on the substrate from bottom to top, the lower plate includes a metal layer, and the upper plate includes an N-type doped polysilicon layer, so that when the upper plate is connected to a positive voltage, a portion of the thickness of the upper plate close to the first dielectric layer forms a depletion layer as an equivalent dielectric layer, and the first dielectric layer and the equivalent dielectric layer together serve as the dielectric layer of the capacitor; Alternatively, the lower plate includes an N-type doped polysilicon layer, and the upper plate includes a metal layer, so that when the lower plate is connected to a positive voltage, a portion of the thickness of the lower plate close to the first dielectric layer forms a depletion layer as an equivalent dielectric layer, and the first dielectric layer and the equivalent dielectric layer together serve as the dielectric layer of the capacitor; Alternatively, both the lower plate and the upper plate include an N-type doped polysilicon layer, so that when the lower plate is connected to a positive voltage, a portion of the thickness of the lower plate close to the first dielectric layer forms a depletion layer as an equivalent dielectric layer, and the first dielectric layer and the equivalent dielectric layer together serve as the dielectric layer of the capacitor, and when the upper plate is connected to a positive voltage, a portion of the thickness of the upper plate close to the first dielectric layer forms a depletion layer as an equivalent dielectric layer, and the first dielectric layer and the equivalent dielectric layer together serve as the dielectric layer of the capacitor; the material of the N-type doped polysilicon layer is polysilicon doped with N-type ions, so that the majority carriers in the N-type doped polysilicon layer are electrons.

2. The capacitor according to claim 1, wherein: The capacitor further comprises: A second dielectric layer is formed on the upper electrode plate.

3. The capacitor according to claim 2, characterized in that The lower plate and the first dielectric layer extend to the periphery of the upper plate; the capacitor further comprises: A third dielectric layer is formed on the substrate, and the third dielectric layer covers the second dielectric layer, the upper plate, the first dielectric layer and the lower plate; a first conductive plug and a second conductive plug, wherein the first conductive plug is electrically connected to the upper plate after passing through the third dielectric layer and the second dielectric layer, and the second conductive plug is electrically connected to the lower plate after passing through the third dielectric layer and the first dielectric layer at the periphery of the upper plate; A first pad and a second pad are formed on the third dielectric layer, the first pad is electrically connected to the first conductive plug, and the second pad is electrically connected to the second conductive plug.

4. The capacitor according to claim 1, wherein: The material of the metal layer includes metal and / or metal nitride.

5. The capacitor according to claim 1, wherein: The base comprises a substrate and a fourth dielectric layer located on the substrate.

6. A method for manufacturing a capacitor, characterized in that: include: providing a substrate; A lower plate, a first dielectric layer and an upper plate are formed on the substrate from bottom to top, wherein the lower plate includes a metal layer, and the upper plate includes an N-type doped polysilicon layer, so that when the upper plate is connected to a positive voltage, a portion of the thickness of the upper plate close to the first dielectric layer forms a depletion layer as an equivalent dielectric layer, and the first dielectric layer and the equivalent dielectric layer together serve as the dielectric layer of the capacitor; Alternatively, the lower plate includes an N-type doped polysilicon layer, and the upper plate includes a metal layer, so that when the lower plate is connected to a positive voltage, a portion of the thickness of the lower plate close to the first dielectric layer forms a depletion layer as an equivalent dielectric layer, and the first dielectric layer and the equivalent dielectric layer together serve as the dielectric layer of the capacitor; Alternatively, both the lower plate and the upper plate include an N-type doped polysilicon layer, so that when the lower plate is connected to a positive voltage, a portion of the thickness of the lower plate close to the first dielectric layer forms a depletion layer as an equivalent dielectric layer, and the first dielectric layer and the equivalent dielectric layer together serve as the dielectric layer of the capacitor, and when the upper plate is connected to a positive voltage, a portion of the thickness of the upper plate close to the first dielectric layer forms a depletion layer as an equivalent dielectric layer, and the first dielectric layer and the equivalent dielectric layer together serve as the dielectric layer of the capacitor; the material of the N-type doped polysilicon layer is polysilicon doped with N-type ions, so that the majority carriers in the N-type doped polysilicon layer are electrons.

7. The method for manufacturing a capacitor according to claim 6, wherein: The energy range of doping N-type ions is 50KeV~200KeV, and the dose range is 5*10 11 cm -2 ~5*10 14 cm -2 .

8. A method for operating a capacitor, characterized in that: The capacitor comprises a lower plate, a first dielectric layer and an upper plate formed on a substrate from bottom to top; Wherein, the lower plate includes a metal layer, the upper plate includes an N-type doped polysilicon layer, and the working method of the capacitor includes: Connecting the lower plate to a positive voltage so that the first dielectric layer serves as the dielectric layer of the capacitor; connecting the upper plate to a positive voltage so that a portion of the thickness of the upper plate close to the first dielectric layer forms a depletion layer as an equivalent dielectric layer, and the first dielectric layer and the equivalent dielectric layer together serve as the dielectric layer of the capacitor; Alternatively, the lower plate includes an N-type doped polysilicon layer, the upper plate includes a metal layer, and the working method of the capacitor includes: Connecting the upper plate to a positive voltage so that the first dielectric layer serves as the dielectric layer of the capacitor; connecting the lower plate to a positive voltage so that a portion of the thickness of the lower plate close to the first dielectric layer forms a depletion layer as an equivalent dielectric layer, and the first dielectric layer and the equivalent dielectric layer together serve as the dielectric layer of the capacitor; Alternatively, the lower plate and the upper plate both include an N-type doped polysilicon layer, and the working method of the capacitor includes: Connecting the lower plate to a positive voltage so that a portion of the thickness of the lower plate close to the first dielectric layer forms a depletion layer as an equivalent dielectric layer, and the first dielectric layer and the equivalent dielectric layer together serve as the dielectric layer of the capacitor; connecting the upper plate to a positive voltage so that a portion of the thickness of the upper plate close to the first dielectric layer forms a depletion layer as an equivalent dielectric layer, and the first dielectric layer and the equivalent dielectric layer together serve as the dielectric layer of the capacitor; The material of the N-type doped polysilicon layer is polysilicon doped with N-type ions, so that majority carriers in the N-type doped polysilicon layer are electrons.

9. The capacitor operating method according to claim 8, characterized in that: The capacitor further comprises: A second dielectric layer is formed on the upper electrode plate.

10. The capacitor operating method according to claim 9, characterized in that: The lower plate and the first dielectric layer extend to the periphery of the upper plate; the capacitor further comprises: A third dielectric layer is formed on the substrate, and the third dielectric layer covers the second dielectric layer, the upper plate, the first dielectric layer and the lower plate; a first conductive plug and a second conductive plug, wherein the first conductive plug is electrically connected to the upper plate after passing through the third dielectric layer and the second dielectric layer, and the second conductive plug is electrically connected to the lower plate after passing through the third dielectric layer and the first dielectric layer at the periphery of the upper plate; A first pad and a second pad are formed on the third dielectric layer, the first pad is electrically connected to the first conductive plug, and the second pad is electrically connected to the second conductive plug.

11. The capacitor operating method according to claim 8, characterized in that: The material of the metal layer includes metal and / or metal nitride.

12. The capacitor operating method according to claim 8, characterized in that: The base comprises a substrate and a fourth dielectric layer located on the substrate.

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