Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. The display panel comprises a display area, a fan-out area and a binding area. The fan-out area is located between the display area and the binding area along a first direction. The display area comprises a plurality of data signal lines extending along the first direction and arranged at intervals along a second direction. The second direction intersects the first direction. The binding area comprises a plurality of binding pads. The fan-out area comprises a plurality of fan-out lines and a plurality of multiplexer circuits. The plurality of fan-out lines are electrically connected to the plurality of binding pads one by one. The plurality of multiplexer circuits are located between the display area and the plurality of fan-out lines along the first direction. The plurality of multiplexer circuits comprise a plurality of multiplexer units. One fan-out line is electrically connected to at least two data signal lines through one multiplexer unit. Embodiments of the present application can reduce the number of fan-out lines and the frame of the display panel.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display, and particularly relates to a display panel and a display device. BACKGROUND

[0002] With the development of display panels, narrow-frame display technology is more and more popular. However, in the related art, a large number of signal lines need to be arranged in the frame area (i.e., the lower frame) of the display panel close to the driving chip, which makes it very difficult to further narrow the frame of the display panel, becoming a technical problem to be solved in the industry. SUMMARY

[0003] The display panel and the display device provided by the embodiments of the present application can reduce the number of fan-out lines and reduce the frame of the display panel.

[0004] In a first aspect, the embodiments of the present application provide a display panel, which comprises a display area, a fan-out area and a binding area. Along a first direction, the fan-out area is located between the display area and the binding area. The display area comprises a plurality of data signal lines extending along the first direction and arranged at intervals along a second direction, and the second direction intersects the first direction. The binding area comprises a plurality of binding pads. The fan-out area comprises a plurality of fan-out lines and a plurality of multiplexer circuits. The plurality of fan-out lines are electrically connected to the plurality of binding pads one by one. Along the first direction, the plurality of multiplexer circuits are located between the display area and the plurality of fan-out lines. The plurality of multiplexer circuits comprise a plurality of multiplexer units. One fan-out line is electrically connected to at least two data signal lines through one multiplexer unit.

[0005] In a second aspect, the embodiments of the present application provide a display device comprising the display panel provided in the first aspect.

[0006] The display panel and the display device provided by the embodiments of the present application comprise a display area, a fan-out area and a binding area arranged in sequence along a first direction. The fan-out area comprises a plurality of fan-out lines and a plurality of multiplexer circuits. The plurality of multiplexer circuits comprise a plurality of multiplexer units. One fan-out line is electrically connected to at least two data signal lines in the display area through one multiplexer unit. Since one fan-out line is electrically connected to at least two data signal lines through one multiplexer unit, the number of fan-out lines in the fan-out area can be reduced, and the frame of the display panel can be reduced, which is conducive to the narrow-frame design of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly introduced. For those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0008] Figure 1 A structural schematic diagram of a display panel in the related art;

[0009] Figure 2 A circuit schematic diagram of a display panel provided by an embodiment of the present application;

[0010] Figure 3 Another circuit schematic diagram of a display panel provided by an embodiment of the present application;

[0011] Figure 4 Still another circuit schematic diagram of a display panel provided by an embodiment of the present application;

[0012] Figure 5 Still another circuit schematic diagram of a display panel provided by an embodiment of the present application;

[0013] Figure 6 Still another circuit schematic diagram of a display panel provided by an embodiment of the present application;

[0014] Figure 7 A partial circuit schematic diagram of a display panel provided by an embodiment of the present application;

[0015] Figure 8 Still another circuit schematic diagram of a display panel provided by an embodiment of the present application;

[0016] Figure 9 Another partial circuit schematic diagram of a display panel provided by an embodiment of the present application;

[0017] Figure 10 Still another partial circuit schematic diagram of a display panel provided by an embodiment of the present application;

[0018] Figure 11 Still another partial circuit schematic diagram of a display panel provided by an embodiment of the present application;

[0019] Figure 12 Still another partial circuit schematic diagram of a display panel provided by an embodiment of the present application;

[0020] Figure 13 Still another partial circuit schematic diagram of a display panel provided by an embodiment of the present application;

[0021] Figure 14 A partial cross-sectional schematic diagram of a display panel provided by an embodiment of the present application;

[0022] Figure 15 A structural schematic diagram of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0023] The features and exemplary embodiments of the various aspects of the application will be described in detail below with reference to the figures. For the purpose of clarity, the description will be made with reference to the accompanying drawings in which the same reference numbers indicate similar features. It is to be understood that the following detailed description is merely exemplary and is not intended to limit the application. The application can be practiced with some of these specific details, which are set forth with the understanding that the same are capable of modification in various respects and that such changes are contemplated. The making and using of the application are discussed in detail below.

[0024] It should be noted that, in the present document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily implying any actual relationship or order between such entities or actions. Also, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0025] It should be noted that, in the present document, the term "and / or" is merely used to associate associated objects, and can represent three relationships, for example, A and / or B can represent three cases: A exists alone, A and B exist together, and B exists alone. In addition, the character " / " in the present document generally represents an "or" relationship between the front and rear associated objects.

[0026] It should be noted that the transistor in the embodiments of the present application can be an N-type transistor or a P-type transistor. For the N-type transistor, the on level is high level and the off level is low level. That is, when the gate of the N-type transistor is high level, the first electrode and the second electrode of the N-type transistor are turned on, and when the gate of the N-type transistor is low level, the first electrode and the second electrode of the N-type transistor are turned off. For the P-type transistor, the on level is low level and the off level is high level. That is, when the control electrode of the P-type transistor is low level, the first electrode and the second electrode of the P-type transistor are turned on, and when the control electrode of the P-type transistor is high level, the first electrode and the second electrode of the P-type transistor are turned off. In the specific implementation, the gate of each transistor is used as the control electrode thereof, and according to the signal of the gate of each transistor and the type of the transistor, the first electrode can be used as the source electrode and the second electrode can be used as the drain electrode, or the first electrode can be used as the drain electrode and the second electrode can be used as the source electrode, which is not distinguished herein. In addition, the on level and the off level in the embodiments of the present application are generic, the on level refers to any level that can turn on the transistor, and the off level refers to any level that can turn off / turn off the transistor.

[0027] In the embodiments of the present application, the term "electrically connected" can refer to that two components are directly electrically connected, or can refer to that two components are electrically connected via one or more other components.

[0028] Various modifications and changes can be made to the present application in matters of form and details without departing from the spirit and scope of the present application, which will be apparent to one skilled in the art. Therefore, the present application is intended to cover modifications and changes in the present application falling within the scope of the corresponding claims (claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in the present application can be combined with each other without contradiction.

[0029] Before the technical solutions provided by the embodiments of the present application are described, the problems existing in the related art will be specifically described to facilitate the understanding of the embodiments of the present application:

[0030] With the development of display panels, narrow frame display technology is more and more popular. However, in the related art, the frame area (i.e. the lower frame) of the display panel close to the driving chip needs to be provided with more signal lines, such as fan-out lines, which makes it very difficult to further narrow the frame of the display panel.

[0031] For ease of understanding, the following will be described in conjunction with the examples shown in Figure 1

[0032] Figure 1 A structure diagram of a display panel in the related art is shown. As shown in Figure 1 ​As shown, in the related art, the display panel 10' includes a display area AA' and a fan-out area NA1' located at one side of the display area AA'. The display area AA' includes a plurality of data lines data' extending along a first direction Y and arranged along a second direction X. The fan-out area NA1' is located at one side of the display area AA' along the first direction Y. Each data line data' extends to the bottom end of the display area AA' and is electrically connected with a fan-out line F'. A large number of fan-out lines F' occupy a large space and increase the frame of the display panel. Especially, the display panel 10' is usually provided with an R corner 110', and the length of the fan-out line F' connected at the R corner 110' is relatively long and is usually diagonal. Therefore, no matter in the first direction Y or in the second direction X, the fan-out line F' connected at the R corner 110' occupies a large space, which is not conducive to the narrow frame design of the display panel.

[0033] In view of the above research findings of the inventors, the embodiments of the present application provide a display panel and a display device, which can solve the technical problem of a large frame size of a display panel in the related art.

[0034] The technical concept of the embodiments of the present application is that a plurality of distributor circuits are arranged in the fan-out area, and each distributor circuit includes a plurality of distributor units. One fan-out line can be electrically connected with at least two data signal lines in the display area through one distributor unit. In this way, since one fan-out line is electrically connected with at least two data signal lines through one distributor unit, the number of fan-out lines in the fan-out area can be reduced, and thus the frame of the display panel can be reduced, which is conducive to the narrow frame design of the display panel.

[0035] Firstly, the display panel provided by the embodiments of the present application will be introduced.

[0036] Figure 2 A circuit schematic diagram of the display panel provided by the embodiments of the present application is shown. As shown, Figure 2 The display panel 20 provided by the embodiments of the present application can include a display area AA, a fan-out area NA1 and a binding area NA2. Along the first direction Y, the fan-out area NA1 can be located between the display area AA and the binding area NA2. The display area AA can include a plurality of data signal lines data extending along the first direction Y and arranged along the second direction X. The data signal line data can be used to provide a data signal to the sub-pixel in the display panel 20 to control the brightness of the sub-pixel. The second direction X intersects the first direction Y. For example, the first direction Y can be the column direction of the display panel 20, i.e. the vertical direction, and the second direction X can be the row direction of the display panel 20, i.e. the horizontal direction.

[0037] The bonding area NA2 may include multiple bonding pads 21. The bonding pads 21 can be used to bond with a flexible printed circuit board (FPC) or a driver chip to receive data signals provided by the driver chip. The fan-out area NA1 may include multiple fan-out lines F and a multiplexer circuit 22. The multiple fan-out lines F can be electrically connected one-to-one with the multiple bonding pads 21 used for transmitting data signals.

[0038] Along the first direction Y, the multiplexer circuit 22 can be located between the display area AA and the fan-out line F, that is, the multiplexer circuit 22 is located on the side of the fan-out line F closer to the display area AA. The multiplexer circuit 22 can include multiple multiplexer units 220. A fan-out line F can be electrically connected to at least two data signal lines through one multiplexer unit 220.

[0039] In this way, since a fan-out line F can be electrically connected to at least two data signal lines through a multiplexer unit 220, the number of fan-out lines F in the fan-out area NA1 can be reduced, thereby reducing the space occupied by the fan-out line F, reducing the bezel of the display panel (as shown in the lower bezel), which is beneficial for the narrow bezel design of the display panel.

[0040] To improve user experience, display panels are now evolving to support multiple refresh rates. At higher refresh rates, the duration of a single frame becomes shorter, and the data signal writing time also decreases, which may lead to insufficient charging.

[0041] Figure 3 This is a circuit diagram of a display panel provided in an embodiment of this application. Figure 3 As shown, according to some embodiments of this application, optionally, the display area AA may further include multiple columns of sub-pixels PX. A column of sub-pixels PX may include multiple sub-pixels PX arranged along the first direction Y. The data signal line data may include a first data signal line data1 and a second data signal line data2. A column of sub-pixels PX may correspond to one first data signal line data1 and one second data signal line data2. Specifically, odd-numbered rows of sub-pixels in the same column of sub-pixels PX may be electrically connected to the first data signal line data1, and even-numbered rows of sub-pixels in the same column of sub-pixels PX may be electrically connected to the second data signal line data2. For example, the first, third, and fifth rows of sub-pixels in the same column of sub-pixels PX may be electrically connected to the first data signal line data1, and the second, fourth, and sixth rows of sub-pixels in the same column of sub-pixels PX may be electrically connected to the second data signal line data2.

[0042] The first data signal line data1 and the second data signal line data2 can both extend along the first direction Y. For any i-th column sub-pixel PX, where i is a positive integer, the first data signal line data1 and the second data signal line data2 corresponding to the i-th column sub-pixel PX can be located on both sides of the i-th column sub-pixel PX, or they can be located on the same side of the i-th column sub-pixel PX. This application embodiment does not limit this.

[0043] In some embodiments, a fan-out line F can be electrically connected to a first data signal line data1 and a second data signal line data2 connected to the same column of sub-pixels PX via a multiplexer unit 220. That is, in Figure 3 In the illustrated embodiment, a "one-to-two" design can be adopted, where one column of sub-pixels PX can correspond to one fan-out line F and one multiplexer unit 220. For any i-th column of sub-pixels PX, the fan-out line F corresponding to the i-th column of sub-pixels PX can be electrically connected to the first data signal line data1 and the second data signal line data2 connected to the i-th column of sub-pixels PX through the multiplexer unit 220 corresponding to the i-th column of sub-pixels PX.

[0044] exist Figure 3 In the illustrated embodiment, each column of sub-pixels PX is connected to two data signal lines (a first data signal line data1 and a second data signal line data2), effectively doubling the number of data signal lines in the display panel. This has the advantage of allowing data writing to proceed in two processes: first, charging the data signal lines; and second, charging the sub-pixels via the data signal lines. Thus, while the i-th row of sub-pixels is being charged using the first data signal line data1, the second data signal line data2 can be pre-charged, meaning the data signal lines of the (i+1)-th row of sub-pixels are being charged simultaneously. This simultaneous operation of the two processes increases the data signal writing time for each row of sub-pixels, ensuring sufficient data signal writing.

[0045] On the other hand, since the distance between the first data signal line data1 and the second data signal line data2 connected to the same column of sub-pixels PX is relatively close, it is convenient to use the same multiplexer unit 220 to electrically connect the first data signal line data1 and the second data signal line data2 connected to the same column of sub-pixels PX, which facilitates wiring and timing control.

[0046] Of course, in other embodiments, the first data signal line data1 and the second data signal line data2 connected to the same column of sub-pixels PX can also be electrically connected to different fan-out lines F through different multiplexer units 220, and this application embodiment does not limit this.

[0047] As mentioned earlier, the fan-out cables connected at the rounded corners of the display panel are relatively long and are usually diagonally routed. Therefore, the fan-out cables connected at the rounded corners occupy a lot of space, which is not conducive to the narrow bezel design of the display panel.

[0048] In view of this, in some embodiments of this application, the multi-way splitter circuit and fan-out line are no longer provided in the edge area where the R-corner is located, but the multi-way splitter circuit and fan-out line are provided in the central area of ​​the display panel.

[0049] Figure 4 This is another circuit diagram of a display panel provided in an embodiment of this application. For example... Figure 4 As shown, according to some embodiments of this application, optionally, both the display area AA and the fan-out area NA1 may include a central area Z and edge areas B located on both sides of the central area Z, with the central area Z and edge areas B arranged along the second direction X. For ease of explanation, the central area Z of the display area AA may be represented by Z1, and the central area Z of the fan-out area NA1 by Z2. The edge area B of the display area AA may be represented by B1, and the edge area B of the fan-out area NA1 by B2. In some examples, for instance, the display panel may be divided into three parts along the second direction X, and the three parts may be of different sizes. The edge areas of the display area AA may be provided with arc-shaped R-angles 110, that is, the area where the R-angles 110 are located can be the edge areas B, and the area between the two edge areas B is the central area Z.

[0050] The multiplexer circuit 22 can be located in the central region Z2 of the fan-out area NA1. Similarly, the fan-out line F can also be located in the central region Z2 of the fan-out area NA1. The display area AA may also include a first connecting line L1 that spans the edge region B1 of the display area AA and the central region Z1 of the display area AA. The data signal line data in the edge region B1 of the display area AA can be electrically connected to the multiplexer circuit 22 located in the central region Z2 of the fan-out area NA1 through the first connecting line L1.

[0051] Thus, by using the first connection line L1 in the display area AA to lead the data signal line data of the edge area B1 of the display area AA to the center area Z1 of the display area AA, and then electrically connecting it with the multiplexer circuit 22 in the center area Z2 of the fan-out area NA1, it is possible to avoid setting the multiplexer circuit 22 and the fan-out line F in the edge area B2 of the fan-out area NA1, further reducing the bezel space occupied by the multiplexer circuit 22 and / or the fan-out line F, and realizing the narrow bezel design of the display panel.

[0052] Figure 5 This is another circuit diagram of a display panel provided in an embodiment of this application. For example... Figure 5As shown, according to some embodiments of this application, optionally, the data signal line data may include a first data signal line data1 and a second data signal line data2. A column of sub-pixels PX may correspond to one first data signal line data1 and one second data signal line data2. Specifically, odd-numbered rows of sub-pixels in the same column of sub-pixels PX may be electrically connected to the first data signal line data1, and even-numbered rows of sub-pixels in the same column of sub-pixels PX may be electrically connected to the second data signal line data2.

[0053] The multiplexer unit 220 may include an input terminal, a first output terminal a, and a second output terminal b. Correspondingly, the first connection line L1 may include a first sub-connection line L11 and a second sub-connection line L12. The first data signal line data1 of the edge region B1 of the display area AA can be electrically connected to the first output terminal a of the corresponding multiplexer unit 220 via the first sub-connection line L11, and the second data signal line data2 of the edge region B1 of the display area AA can be electrically connected to the second output terminal b of the corresponding multiplexer unit 220 via the second sub-connection line L12. The input terminal of the multiplexer unit 220 may be electrically connected to the fan-out line F.

[0054] That is, for the first data signal line data1 and the second data signal line data2 located in the edge area B1 of the display area AA, they can be led to the center area Z1 of the display area AA through different connecting lines, and then electrically connected to the multiplexer circuit 22 in the center area Z2 of the fan-out area NA1 through different connecting lines. This avoids setting the multiplexer circuit 22 and the fan-out line F in the edge area B2 of the fan-out area NA1, further reducing the bezel space occupied by the multiplexer circuit 22 and / or the fan-out line F, and realizing the narrow bezel design of the display panel.

[0055] Figure 6 This is another circuit diagram of a display panel provided in an embodiment of this application. For example... Figure 6 As shown, according to some embodiments of this application, optionally, both the first sub-connecting line L11 and the second sub-connecting line L12 may include a first trace portion 61 extending along a first direction Y and a second trace portion 62 extending along a second direction X. For either the first sub-connecting line L11 or the second sub-connecting line L12, the first trace portion 61 and the second trace portion 62 of the connecting line are electrically connected.

[0056] Combination Figure 5 and Figure 6 As shown, the inventors of this application further realized that, considering the different lengths of the different first connecting lines L1, the impedance (load) of the different first connecting lines L1 may be different, which may affect the uniformity of data signal transmission.

[0057] Therefore, asFigure 6 As shown, in some embodiments, the first wire part 61 can extend from the first edge b1 of the display area AA to the second edge b2 of the display area AA. Exemplarily, the first edge b1 can be the lower edge of the display area AA, and the second edge b2 can be the upper edge of the display area AA.

[0058] Thus, since the length difference of different first connection lines L1 is mainly caused by the length difference of the first wire part 61 of different first connection lines L1, the first wire part 61 of different first connection lines L1 can penetrate the entire display area AA along the first direction Y, which can make the length of the first wire part 61 of the same first connection line L1 equal, and further make the total length of different first connection lines L1 equal or similar, thereby improving the uniformity of data signal transmission and the display uniformity of the display panel.

[0059] Of course, in other embodiments, the first wire part 61 can also extend from the first edge b1 of the display area AA to the target position of the display area AA. The target position can be any position between the first edge b1 of the display area AA and the second edge b2 of the display area AA, such as Figure 5 As shown, the X position is not limited in the embodiments of the present application.

[0060] Figure 7 A partial circuit schematic diagram of the display panel provided by the embodiments of the present application is shown. As shown, Figure 7 As shown, according to some embodiments of the present application, the display panel 20 can also include a first clock signal line CK1 and a second clock signal line CK2. The first clock signal line CK1 can be used to transmit a first clock signal. The second clock signal line CK2 can be used to transmit a second clock signal. The first clock signal and the second clock signal can be different.

[0061] The multiplexer unit 220 can include a first transistor T1 and a second transistor T2. The control end of the multiplexer unit 220 can include the gate of the first transistor T1 and the gate of the second transistor T2, the input end of the multiplexer unit 220 includes the first electrode of the first transistor T1 and the first electrode of the second transistor T2, the first output end a of the multiplexer unit 220 can include the second electrode of the first transistor T1, and the second output end b of the multiplexer unit 220 includes the second electrode of the second transistor T2. Wherein:

[0062] The gate of the first transistor T1 is electrically connected with the first clock signal line CK1, the first electrode of the first transistor T1 is electrically connected with the fan-out line F, and the second electrode of the first transistor T1 is electrically connected with the first data signal line data1. The gate of the second transistor T2 is electrically connected with the second clock signal line CK2, the first electrode of the second transistor T2 is electrically connected with the fan-out line F, and the second electrode of the second transistor T2 is electrically connected with the second data signal line data2.

[0063] In some embodiments, the first transistor T1 and the second transistor T2 in the same demultiplexer unit 220 can be turned on at the same time or in time division. For example, when the first transistor T1 and the second transistor T2 are turned on at the same time, the i-th row of sub-pixels PX in the same column of sub-pixels PX can be charged through the data signal line, and the i+1-th row of sub-pixels PX in the same column of sub-pixels PX can charge the data signal line.

[0064] According to some other embodiments of the present application, the demultiplexer circuit 22 can be arranged in the center region of the display panel or in the edge region of the display panel, and specific embodiments will be described below.

[0065] Figure 8 Another circuit schematic diagram of a display panel according to an embodiment of the present application is provided. As shown in Figure 8 According to some embodiments of the present application, the display area AA and the fan-out area NA1 can each include a center region Z and an edge region B located on both sides of the center region Z, and the center region Z and the edge region B are arranged along the second direction X. For ease of description, the center region Z of the display area AA is denoted as Z1, and the center region Z of the fan-out area NA1 is denoted as Z2. The edge region B of the display area AA is denoted as B1, and the edge region B of the fan-out area NA1 is denoted as B2.

[0066] The demultiplexer circuit 22 can be distributed in the center region Z2 of the fan-out area NA1 and the edge region B2 of the fan-out area NA1. The fan-out line F can be located in the center region Z2 of the fan-out area NA1.

[0067] The data signal line data of the edge region B1 of the display area AA can be electrically connected with the output end of the demultiplexer unit 220 located in the edge region B2 of the fan-out area NA1. The display panel 20 can further include a second connection line L2, and the input end of the demultiplexer unit 220 in the edge region B2 of the fan-out area NA1 can be electrically connected with the fan-out line F through the second connection line L2. As Figure 7As shown, the second connection line L2 is at least partially located in the display area AA. For example, a portion of the second connection line L2 connected with the input end of the multiplexer unit 220 is located in the fan-out area NA1, and another portion of the second connection line L2 can be located in the display area AA, thereby reducing the number of wires in the fan-out area NA1 and further reducing the frame of the display panel.

[0068] In addition, in combination with Figure 2 、 Figure 3 and Figure 8 As described above, since the length of the fan-out line F connected at the R corner is relatively long and the fan-out line F is usually a diagonal wire, the fan-out line F connected at the R corner 110 occupies a large space in either the first direction Y or the second direction X, which is not conducive to the narrow frame design of the display panel. In some embodiments of the present application, the connection node of the input end of the multiplexer unit 220 in the edge area B2 of the fan-out area NA1 is led to the center area Z through the second connection line L2, and then connected with the fan-out line F in the center area Z2 of the fan-out area NA1, which can avoid setting the fan-out line F in the edge area B2 of the fan-out area NA1 (i.e. at the R corner), thereby further reducing the frame space occupied by the fan-out line F and achieving the narrow frame design of the display panel.

[0069] Continuing to refer to Figure 8 In some specific embodiments, the second connection line L2 can optionally include a third wire portion L23 extending along the second direction X and a fourth wire portion L24 extending along the first direction Y. At least a portion of the third wire portion L23 can be located in the display area AA, a first end of the third wire portion L23 can be electrically connected with the input end of the multiplexer unit 220, a second end of the third wire portion L23 can be electrically connected with a first end of the fourth wire portion L24, and a second end of the fourth wire portion L24 can be electrically connected with the fan-out line F located in the center area Z2 of the fan-out area NA1.

[0070] In some examples, the third wire portion L23 and the data signal line data can be located in different film layers to avoid shorting of the third wire portion L23 and the data signal line data. The fourth wire portion L24 and the data signal line data can be located in different film layers or in the same film layer, which is not limited in the embodiments of the present application.

[0071] In this way, the connection node of the input end of the multiplexer unit 220 in the edge area B2 of the fan-out area NA1 is led to the center area Z1 of the display area AA through the third wire portion L23, and then connected with the fan-out line F in the center area Z2 of the fan-out area NA1 through the fourth wire portion L24, which can avoid setting the fan-out line F in the edge area B2 of the fan-out area NA1, further reduce the frame space occupied by the fan-out line F, and achieve the narrow frame design of the display panel.

[0072] Continuing to refer to Figure 8 As shown, according to some embodiments of the present application, the display area further includes M columns of sub-pixels PX, M being a positive integer. The data signal lines data can include first data signal lines data1 and second data signal lines data2. One column of sub-pixels PX can correspond to one first data signal line data1 and one second data signal line data2. Among them, the odd-numbered rows of sub-pixels in the same column of sub-pixels PX can be electrically connected with the first data signal line data1, and the even-numbered rows of sub-pixels in the same column of sub-pixels PX can be electrically connected with the second data signal line data2.

[0073] In some embodiments, the demultiplexer circuit 22 can include M demultiplexer units 220, and the fan-out area NA1 can include M fan-out lines F. Among them, the M columns of sub-pixels PX can correspond to the M demultiplexer units 220 one by one, and the M demultiplexer units 220 can correspond to the M fan-out lines F one by one. For example, the i-th column of sub-pixels can correspond to the i-th demultiplexer unit, the i-th demultiplexer unit can correspond to the i-th fan-out line, 1≤i≤M and i is an integer.

[0074] The demultiplexer unit 220 can include an input end, a first output end and a second output end. The first data signal line data1 connected with the i-th column of sub-pixels in the edge region B1 of the display area AA can be electrically connected with the first output end of the i-th demultiplexer unit 220, the second data signal line data2 connected with the i-th column of sub-pixels in the edge region B1 of the display area AA can be electrically connected with the second output end of the i-th demultiplexer unit 220, and the input end of the i-th demultiplexer unit 220 is electrically connected with the i-th fan-out line F located in the center region Z2 of the fan-out area NA1 through the second connection line L2.

[0075] In this way, on the one hand, the odd-numbered rows of sub-pixels in the same column of sub-pixels PX can be electrically connected with the first data signal line data1, and the even-numbered rows of sub-pixels in the same column of sub-pixels PX can be electrically connected with the second data signal line data2, which is conducive to increasing the writing time of the data signal of each row of sub-pixels and ensuring sufficient writing of the data signal. On the other hand, by connecting the connection node of the input end of the demultiplexer unit 220 in the edge region B2 of the fan-out area NA1 to the center region Z through the second connection line L2, and then connecting with the fan-out line F in the center region Z2 of the fan-out area NA1, the fan-out line F in the edge region B2 of the fan-out area NA1 can be avoided, further reducing the frame space occupied by the fan-out line F, and realizing the narrow frame design of the display panel.

[0076] Figure 9 Another partial circuit schematic diagram of a display panel provided by embodiments of the present application is shown in FIG. 6. As shown in FIG. 6, the display panel can include a display area AA, a fan-out area NA1 and a demultiplexer circuit 22. The display area AA can include a plurality of sub-pixels PX arranged in a matrix form. The fan-out area NA1 can include a plurality of fan-out lines F. The demultiplexer circuit 22 can include a plurality of demultiplexer units 220. Figure 9As shown, according to some embodiments of the present application, optionally, the multiplexer unit 220 can include a first transistor T1 and a second transistor T2. The control end of the multiplexer unit 220 can include the gate of the first transistor T1 and the gate of the second transistor T2, the input end of the multiplexer unit 220 includes the first pole of the first transistor T1 and the first pole of the second transistor T2, the first output end a of the multiplexer unit 220 can include the second pole of the first transistor T1, and the second output end b of the multiplexer unit 220 includes the second pole of the second transistor T2. Wherein:

[0077] The gate of the first transistor T1 is electrically connected with the first clock signal line CK1, the first pole of the first transistor T1 is electrically connected with the fan-out line F through the second connection line L2, and the second pole of the first transistor T1 is electrically connected with the first data signal line data1. The gate of the second transistor T2 is electrically connected with the second clock signal line CK2, the first pole of the second transistor T2 is electrically connected with the fan-out line F through the second connection line L2, and the second pole of the second transistor T2 is electrically connected with the second data signal line data2.

[0078] In some embodiments, the first transistor T1 and the second transistor T2 in the same multiplexer unit 220 can be turned on at the same time, or can be turned on at different times.

[0079] The wiring mode and film layer structure of the fan-out line and the bonding pad will be illustrated below in combination with some specific application embodiments.

[0080] Figure 10 Another partial circuit schematic diagram of a display panel according to an embodiment of the present application is shown in FIG. 6. As shown in FIG. 6, according to some embodiments of the present application, optionally, the bonding area NA2 is provided with a bonding pad 21. The bonding pad 21 can include a plurality of first bonding pads 21a and a plurality of second bonding pads 21b. The first bonding pads 21a and the second bonding pads 21b are arranged alternately along the second direction X. In the embodiment shown in FIG. 6, the first bonding pads 21a and the second bonding pads 21b are arranged in a row along the second direction X, and any one of the second bonding pads 21b can be located between two adjacent first bonding pads 21a. Figure 10 Figure 10 In the embodiment shown in FIG. 6, the first bonding pads 21a and the second bonding pads 21b are arranged in a row along the second direction X, and any one of the second bonding pads 21b can be located between two adjacent first bonding pads 21a.

[0081] The first bonding pad 21a can be electrically connected with the input end of the multiplexer unit 220 located in the central region Z2 of the fan-out area NA1 through the fan-out line F. The second bonding pad 21b can be electrically connected with the input end of the multiplexer unit 220 located in the edge region B2 of the fan-out area NA1 through the fan-out line F and the second connection line L2.

[0082] As shown in FIG. 7, according to some embodiments of the present application, optionally, the bonding area NA2 is provided with a bonding pad 21. The bonding pad 21 can include a plurality of first bonding pads 21a and a plurality of second bonding pads 21b. The first bonding pads 21a and the second bonding pads 21b are arranged alternately along the second direction X. In the embodiment shown in FIG. 7, the first bonding pads 21a and the second bonding pads 21b are arranged in a row along the second direction X, and any one of the second bonding pads 21b can be located between two adjacent first bonding pads 21a. Figure 10 ​As shown, since the second binding pads 21b also need to be connected with the second connection lines L2, the length of the wire connected with the second binding pads 21b is relatively long, and the wire connected with the second binding pads 21b is also relatively complex. If the plurality of second binding pads 21b are arranged closely, the wires connected with the plurality of second binding pads 21b are also arranged closely, and short circuit is prone to occur between the relatively complex wires. According to the embodiment of the present application, the first binding pads 21a and the second binding pads 21b are alternately arranged, which is equivalent to increasing the distance between the two adjacent second binding pads 21b, thereby facilitating the arrangement of the wire connected with the second binding pad 21b, and effectively avoiding the short circuit between the wires connected with different second binding pads 21b.

[0083] Figure 11 Another partial circuit schematic diagram of the display panel is provided in the embodiment of the present application. As shown in Figure 11 different from the embodiment shown in Figure 10 According to some other embodiments of the present application, the first binding pads 21a and the second binding pads 21b can be arranged into two rows along the second direction X. Specifically, the first binding pads 21a can be arranged into a first row along the second direction X, and the second binding pads 21b can be arranged into a second row along the second direction X. Along the first direction Y, the row where the first binding pads 21a are located can be located between the row where the second binding pads 21b are located and the multiplexer circuit 22. Of course, in some other examples, along the first direction Y, the row where the second binding pads 21b are located can also be located between the row where the first binding pads 21a are located and the multiplexer circuit 22, which is not limited in the embodiment of the present application.

[0084] Taking the row where the second binding pads 21b are located as an example, the row is located between the row where the first binding pads 21a are located and the multiplexer circuit 22, any one of the first binding pads 21a in the first row can be aligned with the gap between any two adjacent second binding pads 21b in the second row, that is, the fan-out line F connected with the first binding pad 21a can pass through the gap between any two adjacent second binding pads 21b. In this way, the first binding pads 21a and the second binding pads 21b still constitute an alternately arranged structure, which is equivalent to increasing the distance between the two adjacent second binding pads 21b, thereby facilitating the arrangement of the wire connected with the second binding pad 21b, and effectively avoiding the short circuit between the wires connected with different second binding pads 21b. In addition, since the total number of the first binding pads 21a and the second binding pads 21b is unchanged, and the first binding pads 21a and the second binding pads 21b are arranged into two rows along the second direction X, the space occupied by the first binding pads 21a and the second binding pads 21b in the second direction X can be reduced, and the width of the binding area NA2 in the second direction X can be reduced.

[0085] Figure 12 Another partial circuit schematic diagram of a display panel is provided for embodiments of the present application. As shown, according to some embodiments of the present application, the binding area NA2 can optionally include a plurality of first binding pads 21a arranged along the second direction X and a plurality of second binding pads 21b arranged along the second direction X and spaced by the plurality of first binding pads 21a. The arrangement order of the first binding pads 21a and the second binding pads 21b is the same as the arrangement order of the data signal lines data connected thereto. For example, along the second direction X, a portion of the second binding pads 21b can be located at a first side of the plurality of first binding pads 21a, and another portion of the second binding pads 21b can be located at a second side of the plurality of first binding pads 21a. Figure 12

[0086] The first binding pads 21a are electrically connected to the input ends of the plurality of demultiplexer units 220 located at the center region Z2 of the fan-out area NA1 through the fan-out lines F, and the second binding pads 21b are electrically connected to the input ends of the plurality of demultiplexer units 220 located at the edge region B2 of the fan-out area NA1 through the fan-out lines F and the second connection lines L2.

[0087] Thus, since the arrangement order of the first binding pads 21a and the second binding pads 21b is the same as the arrangement order of the data signal lines data connected thereto, the first binding pads 21a are closer to the first data signal lines data1 connected thereto, and the second binding pads 21b are closer to the second data signal lines data2 connected thereto, which can reduce the length of the fan-out lines F between the first binding pads 21a and the first data signal lines data1, and reduce the length of the fan-out lines F and / or the second connection lines L2 between the second binding pads 21b and the second data signal lines data2, facilitating the wiring design.

[0088] Continuing to refer to Figure 10 , Figure 11 or Figure 12 As shown, according to some embodiments of the present application, the first binding pads 21a and the second binding pads 21b can be located at the same metal film layer, or the first binding pads 21a and the second binding pads 21b can be located at different metal film layers. When the first binding pads 21a and the second binding pads 21b are located at different metal film layers, the fan-out lines F can also be located at different film layers. Thus, the wiring of the binding pads and the fan-out lines is more flexible.

[0089] Specifically, continuing to refer to Figure 10 , Figure 11 or Figure 12 ​As shown, in some embodiments, the first bonding pad 21a and the second bonding pad 21b can be located in different metal film layers. The fan-out lines F can include a first fan-out line F1 and a second fan-out line F2. The first fan-out line F1 can be located in the same film layer as the first bonding pad 21a, and the second fan-out line F2 can be located in the same film layer as the second bonding pad 21b. That is, the first fan-out line F1 and the second fan-out line F2 can be located in different metal film layers.

[0090] The first bonding pad 21a can be electrically connected to the input end of the demultiplexer unit 220 located in the central region of the fan-out area NA1 through the first fan-out line F1, and the second bonding pad 21b can be electrically connected to the input end of the demultiplexer unit 220 located in the edge region of the fan-out area NA1 through the second fan-out line F2 and the second connection line L2.

[0091] In some embodiments, the second connection line L2 and the second fan-out line F2 can be located in the same film layer, that is, they do not need to be connected through a via.

[0092] Figure 13 Another partial circuit schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 6. As shown in FIG. 6, according to some embodiments of the present application, the display panel 20 can include a substrate 01, a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4 which are stacked. Figure 13 As shown, according to some embodiments of the present application, the first bonding pad 21a and the second bonding pad 21b can be located in the same film layer. The fan-out line F connected to the first bonding pad 21a and the fan-out line F connected to the second bonding pad 21b can be located in the same film layer. The fan-out line F connected to the second bonding pad 21b can be electrically connected to the fourth routing portion L24 of the second fan-out line F2 through the first via k1.

[0093] In this way, when the fan-out line F connected to the first bonding pad 21a and the fan-out line F connected to the second bonding pad 21b are located in the same film layer, the fourth routing portion L24 and the fan-out line F are located in different film layers, which can avoid the fourth routing portion L24 and the fan-out line F connected to the first bonding pad 21a from being short-circuited.

[0094] Figure 14 A partial cross-sectional schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 7. As shown in FIG. 7, according to some embodiments of the present application, the display panel 20 can include a substrate 01, a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4 which are stacked. Figure 14 As shown, according to some embodiments of the present application, the display panel 20 can include a substrate 01, a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4 which are stacked. It should be noted that the number of metal layers in the display panel 20 is not limited to four, and can be other numbers, such as three or five, etc., which are not limited in the embodiments of the present application.

[0095] In some embodiments, the first bonding pad 21a and the second bonding pad 21b can be located in different metal film layers. For example, one of the first bonding pad 21a and the second bonding pad 21b can be located in the third metal layer M3, and the other can be located in the fourth metal layer M4. For example, the first bonding pad 21a is located in the third metal layer M3, and the second bonding pad 21b is located in the fourth metal layer M4. Accordingly, the fan-out line F can be located in the third metal layer M3 and / or the fourth metal layer M4.

[0096] In some other embodiments, the first bonding pad 21a and the second bonding pad 21b can be located in the same metal film layer. For example, the first bonding pad 21a and the second bonding pad 21b can both be located in the third metal layer M3, or both be located in the fourth metal layer M4. The fan-out line F and the first bonding pad 21a and the second bonding pad 21b can be located in the same film layer or different film layers. For example, when the first bonding pad 21a and the second bonding pad 21b are both located in the third metal layer M3, the fan-out line F can be located in the third metal layer M3 or the fourth metal layer M4. Similarly, when the first bonding pad 21a and the second bonding pad 21b are both located in the fourth metal layer M4, the fan-out line F can be located in the third metal layer M3 or the fourth metal layer M4.

[0097] Figure 14 The first bonding pad 21a and the second bonding pad 21b are both located in the fourth metal layer M4, and the fan-out line F is located in the third metal layer M3, but this does not constitute a limitation on the embodiments of the present application.

[0098] Based on the display panel provided in the above embodiments, the present application also provides a display device comprising the display panel provided by the present application. Please refer to Figure 15 , Figure 15 A structural schematic diagram of the display device provided in the embodiments of the present application. Figure 15 The display device 1000 provided comprises the display panel 20 provided in any of the above embodiments of the present application. Figure 15 The embodiments are described by taking a mobile phone as an example, and it can be understood that the display device provided in the embodiments of the present application can be a wearable product, a computer, a television, a vehicle-mounted display device, or other display devices with display functions, and the present application does not specifically limit this. The display device provided in the embodiments of the present application has the beneficial effects of the display panel 20 provided in the embodiments of the present application, and specific descriptions can be referred to the specific descriptions of the display panel 20 in the above embodiments, which will not be described herein.

[0099] It should be understood that the specific structure of the circuit and the cross-sectional structure of the display panel provided by the drawings of the embodiments of the present application are merely some examples and are not intended to limit the present application. In addition, the above-mentioned embodiments of the present application can be combined with each other without contradiction.

[0100] It should be noted that each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In accordance with the above-described embodiments of the present application, these embodiments do not describe all the details and do not limit the application to the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. The embodiments are selected and described in the specification in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses based on the present application. The present application is limited by the claims and their full scope and equivalents.

[0101] Those skilled in the art should understand that the above embodiments are exemplary and not limiting. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Those skilled in the art can understand and implement other changed embodiments of the disclosed embodiments based on the drawings, the specification and the claims. In the claims, the term "comprising" does not exclude other structures; the number of "one" does not exclude multiple; the terms "first", "second" are used to mark the name and not to represent any specific order. Any reference signs in the claims should not be understood as limiting the scope of protection. The fact that certain technical features appear in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A display panel, characterized in that, It includes a display area, a fan-out area, and a binding area, wherein, along a first direction, the fan-out area is located between the display area and the binding area; The display area includes multiple data signal lines extending along the first direction and spaced apart along the second direction, wherein the second direction intersects the first direction; The bonding area includes multiple bonding pads; The fan-out area includes multiple fan-out lines and a multi-way distributor circuit, with each fan-out line electrically connected to a corresponding bonding pad. Along the first direction, the multiplexer circuit is located between the display area and the fan-out line. The multiplexer circuit includes multiple multiplexer units, and one fan-out line is electrically connected to at least two data signal lines through one of the multiplexer units. Both the display area and the fan-out area include a central area and edge areas located on both sides of the central area, and the central area and the edge areas are arranged along the second direction; The multiplexer circuit is distributed in the central region and the edge region of the fan-out area, and the fan-out line is located in the central region of the fan-out area; The data signal line in the edge region of the display area is electrically connected to the output terminal of the multiplexer unit located in the edge region of the fan-out area; The display panel also includes a second connecting line, wherein the input terminal of the multiplexer unit in the edge region of the fan-out area is electrically connected to the fan-out line via the second connecting line, and the second connecting line is at least partially located in the display area.

2. The display panel according to claim 1, characterized in that, The display area further includes multiple columns of sub-pixels, and the data signal lines include a first data signal line and a second data signal line. Each column of sub-pixels corresponds to one first data signal line and one second data signal line. In the same column of sub-pixels, odd-numbered rows of sub-pixels are electrically connected to the first data signal line, and even-numbered rows of sub-pixels are electrically connected to the second data signal line. One of the fan-out lines is electrically connected to the first data signal line and the second data signal line connected to the same column of sub-pixels via one of the multiplexer units.

3. The display panel according to claim 1, characterized in that, The display area further includes multiple columns of sub-pixels, and the data signal lines include a first data signal line and a second data signal line. Each column of sub-pixels corresponds to one first data signal line and one second data signal line. In the same column of sub-pixels, odd-numbered rows of sub-pixels are electrically connected to the first data signal line, and even-numbered rows of sub-pixels are electrically connected to the second data signal line. The multiplexer unit includes an input terminal, a first output terminal, and a second output terminal. The first data signal line in the edge region of the display area is electrically connected to the first output terminal of the corresponding multiplexer unit, and the second data signal line in the edge region of the display area is electrically connected to the second output terminal of the corresponding multiplexer unit. The input terminal of the multiplexer unit is electrically connected to the fan-out line.

4. The display panel according to claim 3, characterized in that, The display panel further includes a first clock signal line and a second clock signal line. The multiplexer unit includes a first transistor and a second transistor. The control terminal of the multiplexer unit includes the gate of the first transistor and the gate of the second transistor. The input terminal of the multiplexer unit includes the first terminal of the first transistor and the first terminal of the second transistor. The first output terminal of the multiplexer unit includes the second terminal of the first transistor, and the second output terminal of the multiplexer unit includes the second terminal of the second transistor, wherein: The gate of the first transistor is electrically connected to the first clock signal line, the first terminal of the first transistor is electrically connected to the fan-out line, and the second terminal of the first transistor is electrically connected to the first data signal line. The gate of the second transistor is electrically connected to the second clock signal line, the first terminal of the second transistor is electrically connected to the fan-out line, and the second terminal of the second transistor is electrically connected to the second data signal line.

5. The display panel according to claim 1, characterized in that, The second connecting line includes a third routing portion extending along the second direction and a fourth routing portion extending along the first direction. At least a portion of the routing of the third routing portion is located in the display area. A first end of the third routing portion is electrically connected to the input end of the multiplexer unit. A second end of the third routing portion is electrically connected to the first end of the fourth routing portion. A second end of the fourth routing portion is electrically connected to the fan-out line.

6. The display panel according to claim 1, characterized in that, The display area further includes M columns of sub-pixels. The data signal lines include a first data signal line and a second data signal line. Each column of sub-pixels corresponds to one first data signal line and one second data signal line. In the same column of sub-pixels, odd-numbered rows of sub-pixels are electrically connected to the first data signal line, and even-numbered rows of sub-pixels are electrically connected to the second data signal line. M is a positive integer. The multiplexer circuit includes M multiplexer units, the fan-out area includes M fan-out lines, M columns of sub-pixels correspond one-to-one with the M multiplexer units, and the M multiplexer units correspond one-to-one with the M fan-out lines. The multiplexer unit includes an input terminal, a first output terminal, and a second output terminal. The first data signal line connected to the i-th column of sub-pixels in the edge region of the display area is electrically connected to the first output terminal of the i-th multiplexer unit. The second data signal line connected to the i-th column of sub-pixels in the edge region of the display area is electrically connected to the second output terminal of the i-th multiplexer unit. The input terminal of the i-th multiplexer unit is electrically connected to the i-th fan-out line located in the center region of the fan-out area through the second connection line, where 1≤i≤M and i is an integer.

7. The display panel according to claim 5, characterized in that, The bonding area includes a plurality of first bonding pads and a plurality of second bonding pads, wherein the first bonding pads and the second bonding pads are arranged alternately along the second direction; The first bonding pad is electrically connected to the input terminal of the multiplexer unit located in the central region of the fan-out area via the fan-out line, and the second bonding pad is electrically connected to the input terminal of the multiplexer unit located in the edge region of the fan-out area via the fan-out line and the second connecting line.

8. The display panel according to claim 5, characterized in that, The bonding area includes a plurality of first bonding pads arranged along the second direction and a plurality of second bonding pads arranged along the second direction and spaced apart by the plurality of first bonding pads; the arrangement order of the first bonding pads and the second bonding pads is the same as the arrangement order of the data signal lines to which they are connected; The first bonding pad is electrically connected to the input terminal of the multiplexer unit located in the central region of the fan-out area via the fan-out line, and the second bonding pad is electrically connected to the input terminal of the multiplexer unit located in the edge region of the fan-out area via the fan-out line and the second connecting line.

9. The display panel according to claim 7 or 8, characterized in that, The first bonding pad and the second bonding pad are located in different metal film layers.

10. The display panel according to claim 9, characterized in that, The fan-out line includes a first fan-out line and a second fan-out line. The first fan-out line and the first bonding pad are located in the same film layer, and the second fan-out line and the second bonding pad are located in the same film layer. The first bonding pad is electrically connected to the input terminal of the multiplexer unit located in the central region of the fan-out area via the first fan-out line, and the second bonding pad is electrically connected to the input terminal of the multiplexer unit located in the edge region of the fan-out area via the second fan-out line and the second connecting line.

11. The display panel according to claim 7 or 8, characterized in that, The first bonding pad and the second bonding pad are located in the same film layer, and the fan-out line connected to the second bonding pad is electrically connected to the fourth trace section through the first via.

12. The display panel according to claim 9, characterized in that, The display panel includes at least a substrate, a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer stacked together; One of the first bonding pad and the second bonding pad is located in the third metal layer, and the other is located in the fourth metal layer; The fan-out line is located in the third metal layer or the fourth metal layer.

13. The display panel according to claim 1, characterized in that, The edge area of ​​the display area is provided with an arc-shaped R-angle.

14. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 13.

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