Image sensor and method of manufacturing the same

Abstract

The application provides a preparation method of an image sensor, comprising the steps of: providing a semiconductor structure, the semiconductor structure comprising a substrate and a gate electrode on the substrate, and a photodiode region formed in the substrate; forming a first sidewall on the sidewall of the gate electrode; performing ion implantation on the substrate to form a clamping region on the photodiode region; and forming a second sidewall on the sidewall of the first sidewall. The preparation method of the image sensor provided by the application forms the clamping region before forming the second sidewall, and the clamping region can cover the photodiode region under the second sidewall, thus increasing the coverage area of the clamping region on the photodiode region, effectively blocking the electron overflow of the photodiode region, and reducing the generation of white pixels. The application also provides an image sensor, and the clamping region of the image sensor can cover the photodiode region under the second sidewall, thus effectively blocking the electron overflow of the photodiode region and reducing the generation of white pixels.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically to image sensors and their fabrication methods. Background Technology

[0002] An image sensor is a device that converts optical images into electrical signals. It mainly includes CMOS image sensors and CCD image sensors. CMOS image sensors have gradually become the mainstream image sensor due to their compatibility with existing integrated circuit manufacturing processes and their advantages over CCD image sensors, such as lower manufacturing cost and lower power consumption. The number of white pixels in a CMOS image sensor is one of the key factors limiting its performance and quality; how to reduce white pixels to improve the performance of CMOS image sensors has always been a hot research topic. Summary of the Invention

[0003] The present invention aims to reduce the white pixels of an image sensor, thereby improving the performance of the image sensor.

[0004] To achieve the above objectives, the present invention provides a method for fabricating an image sensor, comprising the following steps:

[0005] A semiconductor structure is provided, the semiconductor structure including a substrate and a gate located on the substrate, wherein a photodiode region is formed in the substrate;

[0006] A first sidewall is formed on the sidewall of the gate;

[0007] Ion implantation is performed on the substrate to form a clamping region on the photodiode region;

[0008] The second side wall is formed on the side wall of the first side wall.

[0009] Preferably, the step of ion implantation into the substrate to form a clamping region on the photodiode region includes:

[0010] A first patterned photoresist layer is formed on the gate and the substrate, the first patterned photoresist layer exposing a portion of the substrate on one side of the gate, the portion of the substrate on the one side of the gate containing a portion of the photodiode region;

[0011] Using the first patterned photoresist layer as a mask, ion implantation is performed on the substrate to form a clamping region on the photodiode region;

[0012] Remove the first patterned photoresist layer.

[0013] Preferably, the semiconductor structure further includes a gate dielectric layer located between the substrate and the gate.

[0014] Preferably, the photodiode region includes a first sub-region, a second sub-region, and a third sub-region, wherein the first sub-region is located at the bottom layer of the photodiode region, the second sub-region is located above the first sub-region, and the third sub-region is located above the second sub-region.

[0015] Preferably, the substrate includes a well region adjacent to the photodiode region.

[0016] Preferably, the substrate includes a first doped substrate, the photodiode region includes a second doped photodiode region, and the clamping region includes a first doped clamping region.

[0017] Preferably, the first doping type includes P-type, and the second doping type includes N-type.

[0018] Preferably, the ion implantation dose in the step of ion implantation of the substrate is 10. 13 / cm 2 ~10 15 / cm 2 .

[0019] In addition, to achieve the above objectives, the present invention also provides an image sensor, comprising:

[0020] A substrate in which a photodiode region is formed;

[0021] Gate formed on the substrate;

[0022] The first and second sidewalls are formed on the gate sidewalls;

[0023] A clamping region is formed in the substrate, the clamping region is located on the photodiode region, and the clamping region covers the photodiode region below the second sidewall;

[0024] The image sensor is formed using the image sensor fabrication method described above.

[0025] Preferably, the photodiode region includes a first sub-region, a second sub-region, and a third sub-region, wherein the first sub-region is located at the bottom layer of the photodiode region, the second sub-region is located above the first sub-region, and the third sub-region is located above the second sub-region.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] Existing image sensor fabrication methods form a clamping region after the second sidewall is formed. However, this clamping region cannot cover the photodiode region below the second sidewall, causing electron leakage from the photodiode region below the second sidewall, resulting in white pixels. The image sensor fabrication method provided by this invention forms a clamping region before the second sidewall is formed. This clamping region extends below the second sidewall and covers the photodiode region below it, increasing the coverage area of ​​the photodiode region. This more effectively blocks electron leakage from the photodiode region, reducing the generation of white pixels and improving the performance of the image sensor. Furthermore, the image sensor fabrication method provided by this invention only requires appropriate optimization of the existing image sensor fabrication process steps, without significant modifications to the existing process flow, improving compatibility with existing processes. The image sensor provided by this invention has a clamping region that covers the photodiode region below the second sidewall. Compared to existing image sensors, the clamping region has a larger coverage area and can effectively block electron leakage from the photodiode region, reducing the generation of white pixels and improving the performance of the image sensor. Attached Figure Description

[0028] Figures 1A to 1C The diagram shows a schematic representation of the semiconductor structure of each step in the fabrication method of an image sensor.

[0029] Figure 2 A flowchart illustrating the steps of a method for fabricating an image sensor according to one embodiment;

[0030] Figures 3-6 The diagram shown is a schematic representation of the semiconductor structure of each step in the fabrication method of an image sensor provided in an embodiment.

[0031] The reference numerals in the attached figures are explained as follows:

[0032] Figures 1A to 1C In the diagram, 00-substrate; 01-gate dielectric layer; 02-gate; 03-photodiode region; 031-first sub-region; 032-second sub-region; 033-third sub-region; 04-isolation structure; 05-unit P-well; 06-deep P-well; 07-first sidewall; 08-second sidewall; 09-clamping region;

[0033] Figures 3-6 In the diagram, 10-substrate; 11-gate dielectric layer; 12-gate; 13-photodiode region; 131-first sub-region; 132-second sub-region; 133-third sub-region; 14-isolation structure; 15-unit P-well; 16-deep P-well; 17-first sidewall; 18-clamping region; 19-second sidewall. Detailed Implementation

[0034] To make the objectives, advantages, and features of the present invention clearer, the image sensor and its fabrication method provided by the present invention will be further described in detail below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clearly illustrate the objectives of the embodiments of the present invention.

[0035] Please see Figures 1A to 1C An existing method for fabricating an image sensor includes the following steps:

[0036] First, refer to Figure 1A A semiconductor structure is provided, comprising a substrate 00, a gate dielectric layer 01 formed on the substrate 00, and a gate electrode 02 formed on the gate dielectric layer 01. A photodiode region 03 is also formed in the substrate 00. The photodiode region 03 may be, for example, an N-type photodiode region. The photodiode region 03 may include a first sub-region 031, a second sub-region 032, and a third sub-region 033, wherein the first sub-region 031 is the lowest layer of the photodiode region 03, the second sub-region 032 is located on the first sub-region 031, and the third sub-region 033 is located on the second sub-region 032. An isolation structure 04 may also be formed in the substrate 00, which may be a shallow trench isolation (STI) structure. A well region for isolating the photodiode region 03 may also be formed in the substrate 00, and the well region may include, for example, a unit P-well 05 and a deep P-well 06.

[0037] Then, refer to Figure 1B A first sidewall 07 is formed on the sidewall of the gate 02, and a second sidewall 08 is formed on the sidewall of the first sidewall 07. The specific structure and forming process of the first sidewall 07 and the second sidewall 08 can be referred to the prior art, and will not be described in detail here.

[0038] Then, refer to Figure 1C A clamping region 09 is formed on the photodiode region 03. Specifically, the method includes: forming a patterned photoresist layer on the gate 02 and the gate dielectric layer 01, the patterned photoresist layer exposing the substrate 00 on one side of the gate 02, the substrate 00 on the gate 02 side containing at least a portion of the photodiode region 03; using the first patterned photoresist layer as a mask, performing a first ion implantation on the substrate 00 to form the clamping region 09 on the photodiode region 03. The clamping region 09 has a different doping type than the photodiode region 03, therefore the clamping region 09 and the photodiode region 03 form a PN junction, and the space charge region of the PN junction prevents electrons from the photodiode region 03 from overflowing onto the substrate 00.

[0039] In the above-mentioned image sensor fabrication method, since the clamping region 09 is formed after the second sidewall 08, the clamping region 09 cannot cover the photodiode region 03 below the second sidewall 08, causing electrons from the photodiode region 03 to overflow onto the substrate 00. The overflowed electrons will form a dark current, and the dark current will produce white pixels.

[0040] Based on the above analysis, the inventors, after research, provide a method for manufacturing an image sensor that can effectively reduce white pixels in the image sensor, thereby improving the performance of the image sensor.

[0041] Please see Figure 2 The present invention provides a method for fabricating an image sensor, comprising the following steps:

[0042] Step S1: Provide a semiconductor structure, the semiconductor structure including a substrate and a gate located on the substrate, wherein a photodiode region is formed in the substrate;

[0043] Step S2: Form a first sidewall on the sidewall of the gate;

[0044] Step S3: Ion implantation is performed on the substrate to form a clamping region on the photodiode region.

[0045] Step S4: Form a second sidewall on the sidewall of the first sidewall.

[0046] Please see Figure 3 Step S1 is executed to provide a semiconductor structure, the semiconductor structure including a substrate 10 and a gate 12 located on the substrate 10, and a photodiode region 13 is formed in the substrate 10.

[0047] In this embodiment, the substrate 10 includes a P-type substrate, but is not limited thereto; for example, it can also be an N-type substrate. The P-type substrate can be a P-type epitaxial layer formed on a substrate, or it can be a P-type substrate. The substrate includes a silicon substrate, but is not limited thereto; it can also be other suitable semiconductor substrates. An isolation structure 14 for defining an active region can also be formed in the substrate 10. The isolation structure 14 can be a shallow trench isolation (STI) structure. The formation process of the isolation structure 14 can refer to the prior art and will not be described in detail here.

[0048] In this embodiment, a gate dielectric layer 11 may also be formed on the substrate 10. The gate dielectric layer 11 may include a SiO2 layer. The gate dielectric layer 11 can be deposited on the substrate 10 using a corresponding thin-film deposition process, such as thermal oxidation. The gate dielectric layer 11 can be used to form an insulating medium between the gate 12 and the substrate 10, and can also serve as a sacrificial layer for subsequent ion implantation, protecting the substrate 10 from damage caused by ion implantation. After forming the gate dielectric layer 11, the gate 12 is formed on the gate dielectric layer 11. The gate 12 can serve as the gate of a transfer transistor. The gate 12 may include a polysilicon gate, but is not limited to this. The method for forming the gate 12 can be found in the prior art and will not be described in detail here.

[0049] A photodiode region 13 is also formed in the substrate 10. In this embodiment, the photodiode region 13 includes a first sub-region 131, a second sub-region 132, and a third sub-region 133. The first sub-region 131 is located at the bottom layer of the photodiode region 13, the second sub-region 132 is located on the first sub-region 131, and the third sub-region 133 is located on the second sub-region 132. The photodiode region 13 is an ion-doped region. By setting different concentrations of the first sub-region 131, the second sub-region 132, and the third sub-region 133, the ion concentration gradient of the photodiode region 13 can be reduced, and the doped ion concentration gradient at the interface between the photodiode region 13 and the substrate 10, and at the interface between the photodiode region 13 and the subsequently formed clamping region, can be adjusted to form a depletion layer that meets the expectations. In this embodiment, the first sub-region 131 can be a first deep N-well photodiode region (DNPPD1), the second sub-region 132 can be a second deep N-well photodiode region (DNPPD2), and the third sub-region 133 can be an N-type photodiode region (NPPD). The first sub-region 131 and the second sub-region 132 can be formed by corresponding well region ion implantation processes before forming the gate 12; the third sub-region 133 can be formed by corresponding ion implantation processes after forming the gate 12. The doping ion concentration and horizontal width of the first sub-region 131, the second sub-region 132, and the third sub-region 133 are not limited and can be determined according to actual process requirements.

[0050] In this embodiment, the gate 12 covers a portion of the photodiode region 13, or the gate 12 may completely cover the photodiode region 13. Since the gate dielectric layer 11 may also be included between the gate 12 and the photodiode region 13, the gate 12 may not directly cover the photodiode region 13. Instead, the projection area of ​​the gate 12 on the upper surface of the gate dielectric layer 11 may partially or completely cover the projection area of ​​the photodiode region 13 on the upper surface of the gate dielectric layer 11. This design ensures effective contact between the photodiode region 13 and the gate 12, thereby ensuring electrical connection between the photodiode region 13 and the gate 12 when the image sensor is operating.

[0051] Well regions can also be formed in the substrate 10; the doping type of the well regions is different from that of the photodiode regions. A plurality of photodiode regions 13 can be formed on an active region, and the well regions are used to isolate adjacent photodiode regions 13 to prevent crosstalk between adjacent photodiode regions 13. In this embodiment, preferably, the well regions are adjacent to the photodiode regions 13 to achieve better isolation, but this is not limited to this. In this embodiment, the photodiode regions 13 include N-type photodiode regions, and the well regions include P-type well regions. Further, the P-type well regions may include unit P-wells 15 (CPW) and deep P-wells 16 (DPW), with the deep P-wells 16 located in the substrate 10 deeper than the unit P-wells 15. In this embodiment, the isolation structure 14 is disposed separately from the unit P-wells 15; in another embodiment, the isolation structure 14 may be disposed within the unit P-wells 15. The unit P-well 15, the deep P-well, and the isolation structure 14 form an isolation region, which can more effectively electrically isolate the adjacent photodiode region 13 and the adjacent active region. The unit P-well 15 and the deep P-well 16 can be formed by corresponding well region ion implantation processes, which can be referred to in the prior art and will not be described in detail here.

[0052] Please see Figure 4 Step S2 is performed to form a first sidewall 17 on the sidewall of the gate 12.

[0053] In this embodiment, the first sidewall 17 may include a SiO2 / Si3N4 stacked structure (ON structure), and the formation method includes: firstly depositing a certain thickness (e.g., SiO2 is deposited on the substrate 10 and the gate 12, and then a certain thickness (e.g.) is deposited. The Si3N4 layer is etched using an anisotropic first dry etching process, with the dry etching stopping at the SiO2 layer to form the first sidewall 17. This first dry etching eliminates the need for a mask and photolithography, simplifying the process flow. The first sidewall 17 is not limited to an ON structure and can be other suitable structures; it can also be formed using other suitable methods, which will not be elaborated here.

[0054] Please see Figure 5 Step S3 is performed to implant ions into the substrate 10 to form a clamping region 18 on the photodiode region 13.

[0055] The clamping region 18, also known as the pinned layer, serves as a protective layer to prevent charge from the photodiode region 13 from leaking onto the substrate 10. The clamping region 18 typically has a different doping type than the photodiode region 13 to form a PN junction between them. The space charge region formed by the PN junction prevents charge leakage from the photodiode region 13.

[0056] The substrate 10 includes a first-doped substrate, the photodiode region 13 includes a second-doped photodiode region, and the clamping region 18 includes a first-doped clamping region. The first doping type includes P-type, and the second doping type includes N-type; or, the first doping type includes N-type, and the second doping type includes P-type. For example, in this embodiment, the first doping type is P-type, and the second doping type is N-type, meaning the substrate 10 includes a P-type substrate, the photodiode region 13 includes an N-type photodiode region, and the clamping region 18 includes a P-type clamping region. The substrate 10, the photodiode region 13, and the clamping region 18 form a PNP depletion region, which is the photosensitive region of the photodiode. The P-type doped impurity ions can be boron ions or boron fluoride ions, or other suitable elemental ions or compound ions; the N-type doped impurity ions can be arsenic ions or phosphorus ions, or other suitable elemental ions or compound ions.

[0057] The clamping region 18 is formed after the first sidewall 17 is formed, which ensures that the clamping region 18 (e.g., a P-type clamping region) will not cover the photodiode region 13 below the first sidewall 17, thus ensuring that the clamping region 18 and the well region (e.g., a P-type well region) are isolated by the photodiode region 13 (e.g., an N-type photodiode region).

[0058] In this embodiment, the step of forming the clamping region 18 on the photodiode region 13 includes: forming a first patterned photoresist layer on the gate 12 and the substrate 10, wherein the first patterned photoresist layer exposes a portion of the substrate 10 on one side of the gate 12, and the portion of the substrate 10 on one side of the gate 12 contains a portion of the photodiode region 13; performing a first ion implantation on the substrate 10 using the first patterned photoresist layer as a mask to form the clamping region 18 on the photodiode region 13; and removing the first patterned photoresist layer. The implantation dose of the first ion implantation is preferably 10. 13 / cm 2 ~10 15 / cm 2 In order to obtain a clamping region 18 with a suitable doping concentration, other process parameters of the first ion implantation can be determined according to actual process requirements, and are not limited here.

[0059] In this embodiment, the first ion implantation uses the first patterned photoresist layer as a mask, and simultaneously, the first ion implantation is shielded by the isolation structure 14 and the first sidewall 17. Therefore, one side of the clamping region 18 ( Figure 5 The left side of the structure extends to the isolation structure 14, and the other side ( Figure 5 The right side of the wall is aligned with the boundary of the first sidewall 17.

[0060] Please see Figure 6 Then, step S4 is executed to form a second sidewall 19 on the sidewall of the first sidewall 17.

[0061] In this embodiment, the second sidewall may include a SiO2 / Si3N4 / SiO2 stacked structure, i.e., an ONO structure, and the formation method includes: firstly depositing a certain thickness (e.g., on the substrate 10, gate 12, and first sidewall 17) on the substrate 10, gate 12, and first sidewall 17. A SiO2 layer is formed, and then a certain thickness (e.g., ) is deposited on the SiO2 layer. A Si3N4 layer is formed, followed by the deposition of a larger thickness (e.g., ) The SiO2 layer is etched a second time using a dry etching process, stopping at the Si3N4 layer, and then the Si3N4 layer is etched a third time using a dry etching process, stopping at the SiO2 layer. The second sidewall 19 is not limited to an ONO structure, but can also be other suitable structures; the second sidewall 19 can also be formed by other suitable methods, which will not be elaborated here.

[0062] In this embodiment, the clamping region 18 is formed before the second sidewall 19 is formed, such that the clamping region 18 extends below the second sidewall 19 and covers the photodiode region 13 below the second sidewall 19, thereby increasing the coverage area of ​​the clamping region 18 on the photodiode region 13, thus more effectively blocking the electron overflow of the photodiode region 13, reducing the generation of white pixels, and improving the performance of the device.

[0063] Based on the above-described method for fabricating an image sensor, this invention also provides an image sensor. Figure 6 This is a schematic diagram of a structure that can be considered an embodiment of the image sensor provided by the present invention.

[0064] Please see Figure 6 The present invention provides an image sensor comprising at least:

[0065] Substrate 10, wherein a photodiode region 13 is formed in the substrate 10;

[0066] Gate 12 formed on the substrate 10;

[0067] A first sidewall 17 and a second sidewall 19 are formed on the sidewall of the gate 12;

[0068] A clamping region 18 is formed in the substrate 10, the clamping region 18 is located on the photodiode region 13, and the clamping region 18 covers the photodiode region 13 below the second sidewall 19;

[0069] The image sensor is formed using the image sensor fabrication method described above.

[0070] In this embodiment, a gate dielectric layer 11 may also be formed on the substrate, and the gate 12 is formed on the gate dielectric layer 11. The gate dielectric layer 11 is used to electrically isolate the gate 12 from the substrate.

[0071] In this embodiment, preferably, the photodiode region 13 includes a first sub-region 131, a second sub-region 132, and a third sub-region 133. The first sub-region 131 is located at the bottom layer of the photodiode region 13, the second sub-region 132 is located on the first sub-region 131, and the third sub-region 133 is located on the second sub-region 132. The first sub-region, the second sub-region 132, and the third sub-region 133 can have different doping concentrations to adjust the ion concentration gradient of the photodiode region 13, and to adjust the doping concentration gradient at the interface between the photodiode region 13 and the substrate 10, and at the interface between the photodiode region 13 and the clamping region 18, thereby forming a depletion layer that meets the expectations. The first sub-region 131 can be a first deep N-well photodiode region (DNPPD1), the second sub-region 132 can be a second deep N-well photodiode region (DNPPD2), and the third sub-region 133 can be an N-type photodiode region (NPPD).

[0072] A well region may also be formed in the substrate 10. The doping type of the well region is different from that of the photodiode region. The well region is used to isolate the photodiode region. In this embodiment, the photodiode region is a P-type photodiode region, and the well region is a P-type well region. Further, the P-type well region may include a single-cell P-well 15 (CPW) and a deep P-well 16 (DPW). The deep P-well 16 is located in the substrate 10 at a greater depth below the single-cell P-well 15. An isolation structure 14 may also be formed in the substrate. The isolation structure may be a shallow trench isolation (STI) structure.

[0073] In existing image sensors, the clamping region cannot cover the photodiode region below the second sidewall, reducing the charge protection provided by the clamping region for the photodiode region. The image sensor provided in this embodiment, because the clamping region 18 covers the photodiode region 13 below the second sidewall 19, has a larger coverage area compared to existing image sensors. Therefore, the clamping region 18 can effectively prevent the charge of the photodiode region 13 from overflowing onto the substrate, thereby reducing the generation of white pixels and improving the performance of the image sensor.

[0074] In summary, the image sensor fabrication method provided by this invention forms a clamping region before forming the second sidewall. This clamping region extends below the second sidewall and covers the photodiode region below it, increasing the coverage area of ​​the photodiode region. This more effectively prevents electron leakage from the photodiode region, reduces the generation of white pixels, and improves the performance of the image sensor. Furthermore, the image sensor fabrication method provided by this invention only requires appropriate optimization of the existing image sensor fabrication process without significant modifications to the existing process flow, improving compatibility with existing processes. The image sensor provided by this invention, with its clamping region covering the photodiode region below the second sidewall, has a larger coverage area compared to existing image sensors, effectively preventing electron leakage from the photodiode region, reducing the generation of white pixels, and improving the performance of the image sensor.

[0075] Furthermore, it is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments with equivalent changes, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention are still within the scope of protection of the present invention. It should also be understood that the present invention is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein; these can vary. It should also be understood that the terminology described herein is used only to describe specific embodiments and is not intended to limit the scope of the invention. It must be noted that the singular forms “a,” “an,” and “the” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. Thus, for example, a reference to “a step” means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in the broadest sense. Therefore, the word "or" should be understood as having a logical definition of "or," not a logical definition of "exclusive or," unless the context explicitly indicates the opposite. The structure described here will be understood as also referencing its functional equivalent. Language that can be interpreted as approximate should be understood in that way, unless the context explicitly indicates the opposite.

Claims

1. A method for fabricating an image sensor, characterized in that, Includes the following steps: A semiconductor structure is provided, the semiconductor structure including a substrate and a gate located on the substrate, wherein a photodiode region is formed in the substrate; A first sidewall is formed on the sidewall of the gate; Ion implantation is performed on the substrate to form a clamping region on the photodiode region; A second sidewall is formed on the sidewall of the first sidewall.

2. The method for fabricating an image sensor as described in claim 1, characterized in that, The step of ion implantation into the substrate to form a clamping region on the photodiode region includes: A first patterned photoresist layer is formed on the gate and the substrate, the first patterned photoresist layer exposing a portion of the substrate on one side of the gate, the portion of the substrate on one side of the gate containing a portion of the photodiode region; Using the first patterned photoresist layer as a mask, ion implantation is performed on the substrate to form a clamping region on the photodiode region; Remove the first patterned photoresist layer.

3. The method for fabricating an image sensor as described in claim 1, characterized in that, The semiconductor structure further includes a gate dielectric layer located between the substrate and the gate.

4. The method for fabricating an image sensor as described in claim 1, characterized in that, The photodiode region includes a first sub-region, a second sub-region, and a third sub-region. The first sub-region is located at the bottom layer of the photodiode region, the second sub-region is located above the first sub-region, and the third sub-region is located above the second sub-region.

5. The method for fabricating an image sensor as described in claim 1, characterized in that, A well region is also formed in the substrate, and the well region is adjacent to the photodiode region.

6. The method for fabricating an image sensor as described in claim 1, characterized in that, The substrate includes a first doped substrate, the photodiode region includes a second doped photodiode region, and the clamping region includes a first doped clamping region.

7. The method for fabricating an image sensor as described in claim 6, characterized in that, The first doping type includes P-type, and the second doping type includes N-type.

8. The method for fabricating an image sensor as described in claim 1, characterized in that, The ion implantation dose in the step of ion implantation of the substrate is 10. 13 / cm 2 ~10 15 / cm 2 .

9. An image sensor, characterized in that, include: A substrate in which a photodiode region is formed; A gate formed on the substrate; The first sidewall and the second sidewall are formed on the gate sidewall; A clamping region is formed in the substrate, the clamping region is located on the photodiode region, and the clamping region covers the photodiode region below the second sidewall; The image sensor is formed using the image sensor fabrication method as described in any one of claims 1 to 8.

10. The image sensor as claimed in claim 9, characterized in that, The photodiode region includes a first sub-region, a second sub-region, and a third sub-region. The first sub-region is located at the bottom layer of the photodiode region, the second sub-region is located above the first sub-region, and the third sub-region is located above the second sub-region.

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