SGT power devices

Abstract

The present invention discloses an SGT power device, wherein shielding polysilicon is formed in a trench. When viewed from above, the trench arrangement includes: multiple active regions formed in the region surrounding the fourth trench, with a first trench distributed in the first active region and a second trench distributed in the second active region; the first and second trenches are perpendicular to each other. Each third trench surrounds the outer side of the active region. A first contact hole is provided at the top of the fourth trench, connecting the shielding polysilicon at the bottom to the drain; a second contact hole is provided at the top of the third trench, connecting the shielding polysilicon at the bottom to the source; and a third contact hole connected to the drain is formed on the surface of the semiconductor substrate outside the outer side of the fourth trench. A first spacing is defined between the third and fourth trenches, the first spacing being greater than or equal to half the longitudinal thickness of the drift region of the SGT power device. A second spacing region is provided between two adjacent third trenches. The present invention can reduce device stress and thereby prevent process problems caused by device stress.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit, in particular to an SGT power device. Background Art

[0002] Compared to trench MOSFETs, SGT power devices, such as SGT MOSFETs, incorporate a source field plate (a shielding polysilicon layer connected to the source) running longitudinally along the device. This laterally depletes the drift region, significantly increasing the drift region's doping concentration without reducing the device's breakdown voltage, thereby achieving extremely low specific on-resistance. Furthermore, compared to trench MOSFETs, SGT MOSFETs offer lower gate-to-drain coupling capacitance (Cgd) and faster switching speeds. Consequently, SGT MOSFETs are increasingly replacing trench MOSFETs.

[0003] like Figure 1 FIG. 1 is a schematic diagram of a device unit structure of a first type of existing SGT MOSFET. The first type of existing SGT MOSFET is formed by connecting multiple device unit structures in parallel in a primitive cell region. Each of the device unit structures includes:

[0004] A first gate structure is formed in a first trench, and includes a shielding polysilicon 103 and a polysilicon gate 108 stacked together; the first trench is formed in the first epitaxial layer 102 doped with a first conductive type, a shielding dielectric layer 104 is separated from the shielding polysilicon 103 and the first epitaxial layer 102, a gate dielectric layer 112 is separated from the polysilicon gate 108 and the first epitaxial layer 102, and a polysilicon inter-dielectric layer 107 is separated from the shielding polysilicon 103 and the polysilicon gate 108.

[0005] The shielding polysilicon 103 and the polysilicon gate 108 are in a stacked structure.

[0006] The drift region 102 is composed of the first epitaxial layer 102 , and the drift region is also denoted by reference numeral 2 here.

[0007] The body region 105 is composed of a second conductivity type doped region formed on the surface of the drift region 102 .

[0008] The source region 109 is composed of a heavily doped region of the first conductivity type formed on the surface of the body region 105 .

[0009] The drain region is composed of a heavily doped region of the first conductivity type formed on the back side of the drift region 102. The first epitaxial layer 102 is typically formed on the surface of the semiconductor substrate 101. The drain region is formed by thinning the back side of the semiconductor substrate 101. The semiconductor substrate 101 can directly adopt a heavily doped structure of the first conductivity type, so that the drain region can be directly formed after thinning the semiconductor substrate 101. Alternatively, the drain region is formed by thinning the semiconductor substrate 101 and then implanting heavily doped ions of the first conductivity type. The semiconductor substrate 101 is typically a silicon substrate, and the first epitaxial layer 102 is typically a silicon epitaxial layer.

[0010] The bottom of the first trench passes through the body region 105, and the source region 109 is self-aligned and formed on the surface of the body region 105 on the side of the polysilicon gate 108. The depth of the polysilicon gate 108 is greater than the depth of the body region 105, and the surface of the body region 105 covered by the side of the polysilicon gate 108 is used to form a channel.

[0011] The polysilicon gate 108 is connected to a gate composed of a front metal layer 111 through a contact hole 106 passing through the interlayer film 110 .

[0012] The source region 109 and the body region 105 are connected to a source electrode formed by a front metal layer 111 through a contact hole 106 .

[0013] The back surface of the drain region contacts the back surface metal layer and the back surface metal layer forms a drain electrode.

[0014] Take an N-type trench MOSFET as an example. The first epitaxial layer 102 is usually formed on a heavily doped N-type semiconductor substrate 101, such as a silicon substrate. The semiconductor substrate 101 will form a drain region after thinning. In order to reduce the back diffusion of the semiconductor substrate 101, an Arsenic substrate, i.e., an arsenic-doped semiconductor substrate 101, is usually selected. However, because the lowest resistivity that can be achieved in the current process of a Phosphorus substrate, i.e., a phosphorus-doped semiconductor substrate 101, is lower than that of an Arsenic substrate. Therefore, in situations where the substrate resistance accounts for a relatively high proportion, such as low-voltage devices below 40V, Phosphorus substrates are also often used. The thinner the substrate, the better the heat dissipation of the device, and the more significantly the substrate resistance can be reduced.

[0015] The shielding polysilicon 103 can achieve lateral depletion of the drift region 102 through the shielding dielectric layer 104 , ie, the field oxygen, so that the doping concentration of the drift region 102 can be significantly increased compared to the existing trench MOSFET without a shielding gate.

[0016] The shielding dielectric layer 104 needs to withstand the breakdown voltage of the device, so the higher the breakdown voltage required by the device, the thicker the shielding dielectric layer 104. In actual processes, the shielding polysilicon 103, like the polysilicon gate 108, is usually composed of heavily doped polysilicon.

[0017] like Figure 2 FIG. 1 is a schematic diagram of a device unit structure of the second type of existing SGT MOSFET. The differences between the device unit structure of the second type of existing SGT MOSFET and the device unit structure of the first type of existing SGT MOSFET are as follows:

[0018] The shielding polysilicon 103a and the polysilicon gate 108a are a left-right stacked structure, and the marks of the corresponding structures in the gate structure of the left-right stacked structure are added with a, such as the gate dielectric layer is represented by mark 112a, the shielding dielectric layer is represented by mark 104a, and the polysilicon inter-dielectric layer is represented by mark 107a.

[0019] The first type of existing SGT MOSFET and the second type of existing SGT MOSFET are referred to as the "up-down" structure and the "left-right" structure, respectively. The advantages and disadvantages of these two structures are as follows:

[0020] The process implementation of the "up and down" structure is more complicated because the shielding polysilicon cannot be directly connected to the contact hole, and additional photomasks and process steps are required.

[0021] The "left-right" structure is simple to implement and does not require complex process steps. All structures, including the polysilicon gate and shielding polysilicon, are located on the surface of semiconductor substrate 101, allowing for convenient direct connection. Compared to the "top-bottom" structure, the "left-right" structure has a larger overlap area between the polysilicon gate and shielding polysilicon, resulting in a larger input capacitance.

[0022] Compared to Trench MOSFETs, SGT MOSFETs are more difficult to implement. More importantly, for SGT MOSFETs, if they need to withstand a higher breakdown voltage, the shielding polysilicon must be deeper in the drift region, and the shielding dielectric layer, such as the oxide layer, that isolates the drift region must also be thicker. This not only greatly increases the difficulty of process implementation, but more importantly, the large amount of oxide layer filling the drift region also introduces a large amount of stress due to the mismatch in thermal expansion coefficients. This stress causes the wafer to warp, affecting the alignment of the lithography process and resulting in a decrease in alignment accuracy. Even more seriously, if the warping is severe, the lithography machine will not function, making subsequent wafer tapeout impossible. Summary of the Invention

[0023] The technical problem to be solved by the present invention is to provide an SGT power device, which can reduce the stress of the device and thereby prevent the process problems caused by the stress of the device.

[0024] In order to solve the above technical problems, the shielding polysilicon of the SGT power device provided by the present invention is formed in a trench, which is formed in a semiconductor substrate. A shielding dielectric layer is separated between the shielding polysilicon and the trench. The depth of the trench and the mismatch between the thermal expansion coefficients of the shielding dielectric layer and the semiconductor substrate material will generate stress in the semiconductor substrate.

[0025] In a top view, the grooves are divided into a first groove, a second groove, a third groove and a fourth groove, and the arrangement structure of the grooves includes:

[0026] The fourth trench is located in the terminal region and has a ring-shaped structure. A plurality of active regions are formed in the region surrounding the fourth trench. The active regions include at least one first active region and at least one second active region.

[0027] A plurality of first trenches are distributed in the first active area. Each of the first trenches is in a strip-shaped structure and is arranged parallel to each other.

[0028] A plurality of second trenches are distributed in the second active area. Each of the second trenches is in a strip-shaped structure and is arranged parallel to each other.

[0029] Each of the first trenches and each of the second trenches is perpendicular to each other. The vertical arrangement of the first trenches and the second trenches can avoid stress in the semiconductor substrate from concentrating in one direction and thus reduce the stress in the semiconductor substrate.

[0030] Each of the third trenches is annular in structure. Each active area is surrounded by a third trench. Each active area is located in an area surrounded by an inner side surface of the corresponding third trench. The outer side surface of each third trench is a terminal area.

[0031] A first contact hole is provided in a partial area of the annular structure of the fourth trench, a bottom of the first contact hole is connected to the shielding polysilicon in the fourth trench, and a top of the first contact hole is connected to the drain.

[0032] A second contact hole is provided in a partial area of the ring structure of each of the third trenches, the bottom of each of the second contact holes is connected to the shielding polysilicon in the corresponding third trench, and the top of the second contact hole is connected to the source.

[0033] A third contact hole is formed on the surface of the semiconductor substrate outside the outer side surface of the fourth trench, and the top of the third contact hole is connected to the drain.

[0034] There is a first distance between the inner side surface of the fourth trench and the outer side surface of each adjacent third trench, and the first distance is greater than half of the longitudinal thickness of the drift region of the SGT power device to achieve voltage resistance between the third trench and the fourth trench.

[0035] There is a second spacing region between two adjacent third trenches. The width of the second spacing region is a second spacing. The second spacing ensures that the depletion regions formed by the two adjacent third trenches on the drift region located in the second spacing region do not overlap.

[0036] A further improvement is that, in the area surrounded by the fourth trench, the ratio of the area occupied by each first trench to the area occupied by the second trench is adjusted according to layout requirements while satisfying the condition of reducing the stress in the semiconductor substrate to below the required value.

[0037] A further improvement is that, in the region surrounded by the fourth grooves, the ratio of the area occupied by each of the first grooves to the area occupied by the second grooves is 1:1.

[0038] A further improvement is that the spacing between each of the first grooves and the spacing between each of the second grooves are both a third spacing, and the second spacing is at least twice the third spacing.

[0039] A further improvement is that the annular structure of each of the third grooves is a closed ring, and the annular structure of each of the third grooves is a rectangular ring with four rounded corners.

[0040] A further improvement is that each of the first trenches and the corresponding third trenches are connected together, so that each of the first trenches has a closed-loop structure, and the shielding polysilicon in each of the first trenches and the shielding polysilicon in the third trench are conductive and connected to the source through the second contact hole at the top of the third trench.

[0041] Each of the second trenches and the corresponding third trenches are connected together, so that each of the second trenches has a closed-loop structure, and the shielding polysilicon in each of the second trenches and the shielding polysilicon in the third trench are conductive and connected to the source through the second contact hole at the top of the third trench.

[0042] A further improvement is that a fourth contact hole is formed at the top of the selected region of each first trench, the bottom of the fourth contact hole is connected to the shielding polysilicon in the first trench, and the top of the fourth contact hole is connected to the source;

[0043] A fifth contact hole is formed at the top of a selected region of each second trench, the bottom of the fifth contact hole is connected to the shielding polysilicon in the second trench, and the top of the fifth contact hole is connected to the source.

[0044] A further improvement is that both ends of each first groove are spaced from the adjacent third groove, and both ends of each second groove are spaced from the adjacent third groove, so that each first groove and each second groove are in an open loop structure.

[0045] A fourth contact hole is formed at the top of a selected region of each of the first trenches, the bottom of the fourth contact hole is connected to the shielding polysilicon in the first trench, and the top of the fourth contact hole is connected to the source;

[0046] A fifth contact hole is formed at the top of a selected region of each second trench, the bottom of the fifth contact hole is connected to the shielding polysilicon in the second trench, and the top of the fifth contact hole is connected to the source.

[0047] A further improvement is that there is a gap between one end of each first groove and the adjacent third groove, and the other end of each first groove is connected to the adjacent third groove, and there is a gap between one end of each second groove and the adjacent third groove, and the other end of each second groove is connected to the adjacent third groove, so that each first groove and each second groove are in a semi-open and semi-closed structure;

[0048] The shielding polysilicon in each of the first trenches and each of the second trenches is conductively connected to the shielding polysilicon in the third trench and is connected to the source through the second contact hole at the top of the third trench.

[0049] A further improvement is that a fourth contact hole is formed at the top of the selected region of each first trench, the bottom of the fourth contact hole is connected to the shielding polysilicon in the first trench, and the top of the fourth contact hole is connected to the source;

[0050] A fifth contact hole is formed at the top of a selected region of each second trench, the bottom of the fifth contact hole is connected to the shielding polysilicon in the second trench, and the top of the fifth contact hole is connected to the source.

[0051] A further improvement is that the annular structure of the fourth groove is a closed ring; the annular structure of the fourth groove is a rectangular ring with four rounded corners.

[0052] A further improvement is that the terminal area further includes one or more fifth grooves in an annular structure; the annular structure of the fifth groove is a closed ring; the annular structure of the fifth groove is a rectangular ring with four rounded corners;

[0053] Each of the fifth grooves surrounds a circumference of the corresponding third groove;

[0054] The number of the fifth grooves provided around each of the third grooves may be the same or different and may be greater than or equal to 0.

[0055] A further improvement is that each of the fifth trenches is a floating structure; or, a sixth contact hole is provided in a partial area of the annular structure of the fifth trench, the bottom of the sixth contact hole is connected to the shielding polysilicon in the fifth trench, and the top of the sixth contact hole is connected to the source.

[0056] A further improvement is that the third contact hole has a stripe structure and is located outside one or more sides of the rectangular ring of the fourth trench;

[0057] Alternatively, the third contact hole is in a ring structure surrounding the outer periphery of the fourth trench.

[0058] A further improvement is that a first epitaxial layer is formed on the semiconductor substrate, and each of the trenches is formed in the first epitaxial layer.

[0059] A further improvement is that, in the active region, the SGT power device further includes a polysilicon gate;

[0060] The polysilicon gate is a planar gate, and the polysilicon gate is located on the surface of the semiconductor substrate outside the first trench and the second trench, with a gate dielectric layer between the polysilicon gate and the semiconductor substrate;

[0061] Alternatively, the polysilicon gate is a trench gate, the polysilicon gate is formed in a gate trench located outside the first trench and the second trench, the depth of the gate trench is shallower than the depth of the trench, and a gate dielectric layer is interposed between the polysilicon gate and the side of the gate trench;

[0062] Alternatively, the polysilicon gate is formed in each of the first trenches and each of the second trenches, a gate dielectric layer is spaced between the polysilicon gate and the side of the corresponding trench, a polysilicon inter-dielectric layer is spaced between the polysilicon gate and the shielding polysilicon, and a gate structure is formed by superimposing the shielding dielectric layer, the shielding polysilicon, the gate dielectric layer, the polysilicon inter-dielectric layer and the polysilicon gate, the gate structure is an upper and lower structure, and the polysilicon gate is located on the top of the shielding polysilicon; alternatively, the gate structure is a left and right structure, and the polysilicon gate is located in the top area on the left and right sides of the shielding polysilicon.

[0063] A further improvement is that the width of the third groove is greater than or equal to the width of the second contact hole plus twice the alignment accuracy of the second contact hole, and the width of the fourth groove is greater than or equal to the width of the first contact hole plus twice the alignment accuracy of the first contact hole.

[0064] A further improvement is that the widths of the first contact hole and the second contact hole are equal, and the width of the third trench is equal to the width of the fourth trench.

[0065] A further improvement is that the width of each of the first grooves is equal to the width of each of the second grooves and is smaller than or equal to the width of the third groove.

[0066] A further improvement is that the top of each polysilicon gate is connected to a gate pad formed by patterning the front metal layer through a seventh contact hole;

[0067] In a top view, at least one gate pad is provided in the area surrounded by the fourth trench. At the formation position of the gate pad, the outer side surface of the area segment corresponding to the third trench surrounds the gate pad, so that the gate pad is located outside the active area.

[0068] The present invention makes a special arrangement for the arrangement structure of the trenches provided with shielding polysilicon, and arranges a plurality of active areas formed by the third trench in the surrounding area of the fourth trench, and the active areas include at least one first active area and at least one second active area. The first trench provided in the first active area and the second trench provided in the second active area exist with each other. The vertical arrangement of the first trench and the second trench can avoid the stress in the semiconductor substrate from being concentrated in one direction, that is, the stress will be dispersed in two directions, thereby reducing the stress in the semiconductor substrate.

[0069] The shielding polysilicon in the fourth trench and the surface of the semiconductor substrate outside the fourth trench will form a drain connected to the contact hole, and the shielding polysilicon in the third trench is connected to the source through the corresponding contact hole, namely the second contact hole. This structure can form good terminal protection outside the active area; at the same time, the third trench and the fourth trench are both annular structures, and the annular structure is also beneficial to the stress dispersion of the semiconductor substrate, and finally can further reduce the stress of the semiconductor substrate.

[0070] From the above, it can be seen that the groove arrangement of the active area and the terminal area of the present invention can not only meet the performance requirements of the device well, but also reduce the stress of the semiconductor substrate, and prevent the process problems caused by the stress of the device. For example, it can prevent the wafer composed of the semiconductor substrate from warping during the process, and avoid the influence of the wafer warping on the lithography alignment process, thereby improving the alignment accuracy and avoiding the serious wafer warping that makes the lithography machine unable to perform lithography. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0072] Figure 1 This is a schematic diagram of the device unit structure of the first existing SGT MOSFET;

[0073] Figure 2 It is a structural diagram of the device unit structure of the second existing SGT MOSFET;

[0074] Figure 3 This is the first trench layout of the SGT power device according to an embodiment of the present invention;

[0075] Figure 4 This is the second trench layout of the SGT power device according to an embodiment of the present invention;

[0076] Figure 5 This is the third trench layout of the SGT power device according to an embodiment of the present invention;

[0077] Figure 6 This is the fourth trench layout of the SGT power device according to an embodiment of the present invention;

[0078] Figure 7 This is the fifth trench layout of the SGT power device according to the embodiment of the present invention. DETAILED DESCRIPTION

[0079] like Figure 3 As shown in FIG. 1 , it is a first trench layout diagram of the SGT power device according to an embodiment of the present invention; Figure 4 As shown in FIG. 1 , it is a second trench layout of the SGT power device according to an embodiment of the present invention; Figure 5 As shown in FIG. 1 , it is a third trench layout of the SGT power device according to an embodiment of the present invention; Figure 6 As shown in FIG. 1 , it is a fourth trench layout of the SGT power device according to an embodiment of the present invention; Figure 7 Figure 2 shows the fifth trench layout for an SGT power device according to an embodiment of the present invention. The shielding polysilicon layer of the SGT power device is formed in a trench formed in a semiconductor substrate. A shielding dielectric layer is placed between the shielding polysilicon layer and the trench. The trench depth and the mismatch in thermal expansion coefficients between the shielding dielectric layer and the semiconductor substrate material can generate stress in the semiconductor substrate. In this embodiment of the present invention, the SGT power device is an SGT MOSFET.

[0080] In a top view, the grooves are divided into a first groove 1c, a second groove 1e, a third groove and a fourth groove 1a, and the arrangement structure of the grooves includes:

[0081] The fourth trench 1 a is located in the terminal region and has a ring-shaped structure. A plurality of active regions are formed in the region surrounding the fourth trench 1 a . The active regions include at least one first active region and at least one second active region.

[0082] A plurality of first trenches 1 c are distributed in the first active area. Each of the first trenches 1 c is in a strip-shaped structure and is arranged parallel to each other.

[0083] A plurality of second trenches 1e are distributed in the second active area. Each of the second trenches 1e is in a strip-shaped structure and is arranged parallel to each other.

[0084] Each of the first trenches 1c and the second trenches 1e is perpendicular to each other. The vertical arrangement of the first trenches 1c and the second trenches 1e can avoid stress in the semiconductor substrate from concentrating in one direction and thus reduce stress in the semiconductor substrate.

[0085] Each of the third trenches is annular in structure. Each active area is surrounded by a third trench. Each active area is located in an area surrounded by an inner side surface of the corresponding third trench. The outer side surface of each third trench is a terminal area. Figure 3 In FIG, the third trench on the peripheral side of the first active region is individually marked with a mark 1 b , and the third trench on the peripheral side of the second active region is individually marked with a mark 1 d .

[0086] A first contact hole 2a is provided in a partial area of the annular structure of the fourth trench 1a. The bottom of the first contact hole 2a is connected to the shielding polysilicon in the fourth trench 1a, and the top of the first contact hole 2a is connected to the drain.

[0087] A second contact hole is provided in a partial area of the ring structure of each of the third trenches, the bottom of each of the second contact holes is connected to the shielding polysilicon in the corresponding third trench, and the top of the second contact hole is connected to the source. Figure 3 In the figure, the second contact hole at the top of the third trench corresponding to mark 1b is separately marked with mark 2b, and the second contact hole corresponding to mark 1d is separately marked with mark 2d.

[0088] A third contact hole 2 c is formed on the surface of the semiconductor substrate outside the outer side surface of the fourth trench 1 a , and the top of the third contact hole 2 c is connected to the drain.

[0089] There is a first distance between the inner side surface of the fourth trench 1a and the outer side surface of each adjacent third trench, and the first distance is greater than half of the longitudinal thickness of the drift region of the SGT power device to achieve a withstand voltage between the third trench and the fourth trench 1a. Figure 3 In the figure, the first spacing between the inner side surface of the fourth groove 1a and the outer side surface of the third groove corresponding to 1b is represented by Space1, and the first spacing between the inner side surface of the fourth groove 1a and the outer side surface of the third groove corresponding to 1d is represented by Space2.

[0090] There is a second spacing region between two adjacent third trenches. The width of the second spacing region is a second spacing. The second spacing ensures that the depletion regions formed by the two adjacent third trenches on the drift region located in the second spacing region do not overlap. Figure 3 In some preferred embodiments, the spacing between the first grooves 1c and the spacing between the second grooves 1e are both the third spacing, and the second spacing is at least twice the third spacing.

[0091] Typically, the shielding polysilicon in the active region and the third trench is connected to the source, and is therefore also called a source polysilicon field plate. However, the shielding polysilicon in the fourth trench 1a is no longer connected to the source, but to the drain. Due to the large potential difference between the source and the drain, the third trench and the fourth trench 1a cannot be too close, that is, the first spacing cannot be too small. The first spacing must be at least greater than half the longitudinal thickness of the drift region. In practical applications, the first spacing can also be directly selected as the longitudinal thickness of the drift region. In a typical layout, this first spacing is at least greater than 6μm. In an embodiment of the present invention, a first epitaxial layer is formed on the semiconductor substrate, and each of the trenches is formed in the first epitaxial layer. The drift region is composed of the first epitaxial layer at the bottom of the body region, so the first spacing must be at least greater than half the thickness of the first epitaxial layer. In practical applications, the first spacing can also be directly selected as the thickness of the first epitaxial layer.

[0092] In an embodiment of the present invention, in the region surrounded by the fourth trench 1a, the ratio of the area occupied by each of the first trenches 1c to the area occupied by the second trenches 1e is adjusted based on layout requirements while ensuring that the stress in the semiconductor substrate is reduced below a required value. Preferably, in the region surrounded by the fourth trench 1a, the ratio of the area occupied by each of the first trenches 1c to the area occupied by the second trenches 1e is 1:1.

[0093] In the existing method, the strip arrangement of the grooves in the active area, that is, the cell area, has only one direction, either the horizontal direction as shown by the first groove 1c, or the vertical direction as shown by the second groove 1d. However, in the embodiment of the present invention, there are two grooves in different directions in the active area, namely the horizontal first groove 1c and the vertical second groove 1d. The grooves in different directions change the stress generation from the original single direction to two directions. In this way, the warping of the chip will be greatly alleviated. When the process production is carried out according to the existing method, if the strip arrangement of the grooves in the active area is all horizontal as shown by the first groove 1c, the existing method will cause the wafer corresponding to the semiconductor substrate to be too severely warped when the polysilicon gate (Gate Poly) is made after the trench is etched, and the subsequent process cannot be carried out. However, the layout structure of the embodiment of the present invention can smoothly complete the entire process flow during the process and achieve mass production. Therefore, the embodiment of the present invention can solve the stress problem very well.

[0094] In some preferred embodiments, the total area of each of the first active regions and the total area of each of the second active regions are roughly equal, which is the best solution to the stress; of course, the area of each of the first active regions and the area of each of the second active regions can also be set accordingly according to the layout requirements, as long as the stress of the semiconductor substrate meets the requirements. Figure 3 In the first structure shown, the number of the first active region and the number of the second active region are both one. Figure 4 In the second structure shown, the number of the first active region and the number of the second active region are both one. Figure 5 In the third structure shown, the number of the first active region and the number of the second active region are both one. Figure 6 In the fourth structure shown, the number of the first active regions is 2, and the number of the second active regions is only one. Figure 7 In the fifth structure shown, the number of the first active region and the number of the second active region are both one, wherein the second active region is interrupted by the gate pad 3 .

[0095] In the embodiment of the present invention, the annular structure of each of the third grooves is a closed ring, and the annular structure of each of the third grooves is a rectangular ring with four rounded corners.

[0096] In some embodiments, the Figure 3In the first structure shown, each first trench 1c is connected to the corresponding third trench, forming a closed-loop structure. The shield polysilicon in each first trench 1c is electrically conductive to the shield polysilicon in the third trench and connected to the source electrode through the second contact hole at the top of the third trench. Each second trench 1e is electrically conductive to the corresponding third trench, forming a closed-loop structure. The shield polysilicon in each second trench 1e is electrically conductive to the shield polysilicon in the third trench and connected to the source electrode through the second contact hole at the top of the third trench. Since the shield polysilicon in each first trench 1c and second trench 1e is connected to the source electrode through the second contact hole at the top of the corresponding third trench, it is generally not necessary to provide contact holes in the first trench 1c and second trench 1e to connect the shield polysilicon to the source electrode. In some embodiments, in order to reduce the lead-out resistance, i.e., the source resistance, of the shielding polysilicon in the first trench 1c and the second trench 1e, it can also be set as follows: a fourth contact hole is formed at the top of a selected area of each first trench 1c, the bottom of the fourth contact hole is connected to the shielding polysilicon in the first trench 1c, and the top of the fourth contact hole is connected to the source; a fifth contact hole is formed at the top of a selected area of each second trench 1e, the bottom of the fifth contact hole is connected to the shielding polysilicon in the second trench 1e, and the top of the fifth contact hole is connected to the source.

[0097] Figure 3 In the embodiment, the first trench 1c and the second trench 1e are connected to the third trench, forming a closed-loop structure. Usually, the closed-loop structure has the risk of over-depletion at the junction of the third trench and the first trench 1c or the third trench and the second trench 1e, resulting in a low breakdown voltage of the device.

[0098] In some embodiments, the Figure 4 In the second structure shown, a gap is formed between each first trench 1c and the adjacent third trench at both ends, and a gap is formed between each second trench 1e and the adjacent third trench at both ends, so that each first trench 1c and each second trench 1e form an open-loop structure. A fourth contact hole is formed at the top of a selected region of each first trench 1c, with the bottom of the fourth contact hole connected to the shielding polysilicon in the first trench 1c and the top of the fourth contact hole connected to the source. A fifth contact hole is formed at the top of a selected region of each second trench 1e, with the bottom of the fifth contact hole connected to the shielding polysilicon in the second trench 1e and the top of the fifth contact hole connected to the source. Figure 4In the open-loop structure shown, the distance between the trenches is crucial. If the distance is too small or too large, the breakdown voltage (BV) will be low. Furthermore, in the open-loop structure, the first trench 1c and the second trench 1e are not connected to the third trench. Therefore, separate contact holes must be formed on the top of the first trench 1c and the second trench 1e to connect to the source.

[0099] In some embodiments, the following structure is also adopted: there is a gap between one end of each first trench 1c and the adjacent third trench, and the other end of each first trench 1c is connected to the adjacent third trench; there is a gap between one end of each second trench 1e and the adjacent third trench, and the other end of each second trench 1e is connected to the adjacent third trench, so that each first trench 1c and each second trench 1e are in a semi-open and semi-closed structure; the shielding polysilicon in each first trench 1c and each second trench 1e is conductive with the shielding polysilicon in the third trench and is connected to the source through the second contact hole at the top of the third trench. Similar to the first structure, in the semi-open and semi-closed structure, it is usually not necessary to provide contact holes in the first trench 1c and the second trench 1e to connect the shielding polysilicon to the source. In some embodiments, in order to reduce the lead-out resistance, i.e., the source resistance, of the shielding polysilicon in the first trench 1c and the second trench 1e, the semi-open and semi-closed structure can also be set as follows: a fourth contact hole is formed at the top of a selected area of each first trench 1c, the bottom of the fourth contact hole is connected to the shielding polysilicon in the first trench 1c, and the top of the fourth contact hole is connected to the source; a fifth contact hole is formed at the top of a selected area of each second trench 1e, the bottom of the fifth contact hole is connected to the shielding polysilicon in the second trench 1e, and the top of the fifth contact hole is connected to the source.

[0100] like Figure 3 As shown, the annular structure of the fourth groove 1a is a closed ring; the annular structure of the fourth groove 1a is a rectangular ring with four rounded corners.

[0101] exist Figure 3 In the first structure shown, no other grooves are provided between the fourth groove 1 a and the third groove.

[0102] In some embodiments, the terminal region may further include one or more fifth grooves in an annular structure; the annular structure of the fifth grooves may be a closed ring; the annular structure of the fifth grooves may be a rectangular ring with four rounded corners; each fifth groove surrounds the corresponding third groove; and the number of the fifth grooves disposed around each third groove may be the same or different and may be at least zero. Figure 5The third structure shown uses two of the fifth grooves, and one fifth groove is arranged on the circumferential side of each of the third grooves; wherein, the fifth groove arranged on the circumferential side of the third groove corresponding to the mark 1b is separately indicated by the mark 1f, and the fifth groove arranged on the circumferential side of the third groove corresponding to the mark 1d is separately indicated by the mark 1g. Figure 5 In the embodiment, the spacing between the fourth groove 1a and the fifth groove corresponding to mark 1f is the first spacing corresponding to Space1, the spacing between the fourth groove 1a and the fifth groove corresponding to mark 1g is the first spacing corresponding to Space2; and the spacing between two fifth grooves is the second spacing corresponding to mark Space3. In other embodiments, more fifth grooves, such as two or three, may be provided between the fourth groove 1a and the third groove corresponding to mark 1b, and more fifth grooves, such as two or three, may be provided between the fourth groove 1a and the third groove corresponding to mark 1b. Alternatively, the fifth groove may be provided only between the fourth groove 1a and the third groove corresponding to mark 1b, and no fifth groove may be provided between the fourth groove 1a and the third groove corresponding to mark 1d, or the fifth groove may be provided only between the fourth groove 1a and the third groove corresponding to mark 1d, and no fifth groove may be provided between the fourth groove 1a and the third groove corresponding to mark 1b.

[0103] In some embodiments, each of the fifth trenches is a floating structure and is not connected to any potential. In other embodiments, a sixth contact hole is provided in a portion of the annular structure of the fifth trench, the bottom of the sixth contact hole being connected to the shielding polysilicon in the fifth trench, and the top of the sixth contact hole being connected to the source.

[0104] In some embodiments, the third contact hole 2c is in a line structure and is located outside one or more sides of the rectangular ring of the fourth trench 1a. Figure 3 As shown, the third contact hole 2c is located outside one side of the rectangular ring of the fourth trench 1a; Figure 4 As shown, the third contact hole 2c is located outside one side of the rectangular ring of the fourth trench 1a; Figure 5 As shown, the third contact hole 2c is located outside one side of the rectangular ring of the fourth trench 1a; Figure 6 As shown, the third contact hole 2c is located outside one side of the rectangular ring of the fourth trench 1a; Figure 7 As shown, the third contact hole 2c is located outside one side of the rectangular ring of the fourth trench 1a. In other embodiments, the third contact hole 2c may be in a ring structure surrounding the outer periphery of the fourth trench 1a.

[0105] In the active region, the SGT power device further includes a polysilicon gate;

[0106] In some embodiments, the polysilicon gate is a planar gate, and the polysilicon gate is located on the surface of the semiconductor substrate outside the first trench 1c and the second trench 1e, with a gate dielectric layer between the polysilicon gate and the semiconductor substrate;

[0107] In some embodiments, the polysilicon gate may be a trench gate, the polysilicon gate may be formed in a gate trench outside the first trench 1c and the second trench 1e, the depth of the gate trench may be shallower than the depth of the trench, and a gate dielectric layer may be provided between the polysilicon gate and the side of the gate trench.

[0108] In some embodiments, the polysilicon gate may be formed in each of the first trenches 1c and each of the second trenches 1e, a gate dielectric layer may be provided between the polysilicon gate and the side of the corresponding trench, a polysilicon inter-dielectric layer may be provided between the polysilicon gate and the shielding polysilicon, and a gate structure may be formed by superimposing the shielding dielectric layer, the shielding polysilicon, the gate dielectric layer, the polysilicon inter-dielectric layer and the polysilicon gate, wherein the gate structure is an upper and lower structure, and the polysilicon gate is located on the top of the shielding polysilicon; or, the gate structure is a left and right structure, and the polysilicon gate is located in the top area on the left and right sides of the shielding polysilicon.

[0109] In an embodiment of the present invention, the width of the third trench is greater than or equal to the width of the second contact hole plus twice the alignment accuracy of the second contact hole, and the width of the fourth trench 1a is greater than or equal to the width of the first contact hole 2a plus twice the alignment accuracy of the first contact hole 2a. Preferably, the widths of the first contact hole 2a and the second contact hole are equal, and the width of the third trench is equal to the width of the fourth trench 1a.

[0110] The width of each of the first trenches 1 c is equal to the width of each of the second trenches 1 e and is smaller than or equal to the width of the third trench.

[0111] The widths of the grooves can all be set to be the same. However, in the actual process, for the third trench and the fourth trench 1a, since through holes, i.e. contact holes, need to be drilled in the trenches to connect the shielding polysilicon. At this time, the width of the shielding polysilicon needs to be greater than the width of the through hole + 2* the alignment accuracy of the through hole. In some embodiments, the width of the through hole is 0.3μm, and the alignment accuracy of the through hole is 0.1μm; at this time, the width of the shielding polysilicon is required to be greater than 0.5μm. In order to make the width of the shielding polysilicon meet the requirements, the widths of the third trench and the fourth trench 1a can be widened. For example, the widths of the third trench and the fourth trench 1a can be set to increase the widths of the first trench 1c and the second trench 12 by 0.1 to 0.2μm. Preferably, it is 0.1μm.

[0112] In some embodiments, as Figure 7 As shown, the top of each polysilicon gate is connected to the gate pad 3 formed by the patterning of the front metal layer through the seventh contact hole. In the top view, at least one gate pad 3 is provided in the area surrounded by the fourth trench 1a. At the formation position of the gate pad 3, the outer side surface of the area segment corresponding to the third trench surrounds the gate pad 3, so that the gate pad 3 is located outside the active area. In practical applications, MOSFET, the polysilicon gate needs to be led out through one of the gate pads 3. There is no active area under the gate pad 3. Making a trench under the gate pad 3 will increase the capacitance of the device and cause additional losses. For this case, a trench may not be provided under the gate pad 3. In this case, the trench structure layout can be adopted. Figure 7 The layout shown.

[0113] The embodiment of the present invention makes a special arrangement of the trenches provided with shielding polysilicon, and a plurality of active areas formed by the third trenches are arranged in the surrounding area of the fourth trench 1a, and the active areas include at least one first active area and at least one second active area. The first trench 1c provided in the first active area and the second trench 1e provided in the second active area exist with each other. The vertical arrangement of the first trench 1c and the second trench 1e can avoid the stress in the semiconductor substrate from being concentrated in one direction, that is, the stress will be dispersed in two directions, thereby reducing the stress in the semiconductor substrate.

[0114] The shielding polysilicon in the fourth trench 1a and the surface of the semiconductor substrate outside the fourth trench 1a will form a drain connected to the contact hole, and the shielding polysilicon in the third trench is connected to the source through the corresponding contact hole, namely the second contact hole. This structure can form good terminal protection outside the active area; at the same time, the third trench and the fourth trench 1a are both annular structures, and the annular structure is also beneficial to the stress dispersion of the semiconductor substrate, and finally can further reduce the stress of the semiconductor substrate.

[0115] From the above, it can be seen that the groove arrangement in the active area and the terminal area of the embodiment of the present invention can not only well meet the performance requirements of the device, but also reduce the stress of the semiconductor substrate, and prevent the process problems caused by the stress of the device. For example, it can prevent the wafer composed of the semiconductor substrate from warping during the process, and avoid the influence of the wafer warping on the lithography alignment process, thereby improving the alignment accuracy and avoiding the serious wafer warping that makes the lithography machine unable to perform lithography.

[0116] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. An SGT power device, characterized in that: Shielding polysilicon is formed in a trench formed in a semiconductor substrate, a shielding dielectric layer is interposed between the shielding polysilicon and the trench, and a depth of the trench and a mismatch in thermal expansion coefficients between the shielding dielectric layer and the semiconductor substrate material may generate stress in the semiconductor substrate; In a top view, the grooves are divided into a first groove, a second groove, a third groove and a fourth groove, and the arrangement structure of the grooves includes: The fourth trench is located in the terminal region, the fourth trench is an annular structure, and a plurality of active regions are formed in the region surrounding the fourth trench, the active regions including at least one first active region and at least one second active region; A plurality of first trenches are distributed in the first active area, each of the first trenches is in a strip-shaped structure and is arranged parallel to each other; A plurality of second trenches are distributed in the second active area, each of the second trenches is in a strip-shaped structure and is arranged parallel to each other; Each of the first trenches and each of the second trenches is perpendicular to each other, and the first trenches and the second trenches are arranged perpendicularly to each other to avoid stress in the semiconductor substrate from concentrating in one direction and thereby reduce the stress in the semiconductor substrate; Each of the third trenches is annular in structure. Each active area is surrounded by a third trench. Each active area is located in an area surrounded by an inner side surface of the corresponding third trench. The outer side surface of each third trench serves as a terminal area. A first contact hole is provided in a partial area of the annular structure of the fourth trench, wherein the bottom of the first contact hole is connected to the shielding polysilicon in the fourth trench, and the top of the first contact hole is connected to the drain; A second contact hole is provided in a partial area of the ring structure of each of the third trenches, the bottom of each of the second contact holes is connected to the shielding polysilicon in the corresponding third trench, and the top of the second contact hole is connected to the source electrode; A third contact hole is formed on the surface of the semiconductor substrate outside the outer side surface of the fourth trench, and the top of the third contact hole is connected to the drain; A first distance is provided between an inner side surface of the fourth trench and an outer side surface of each adjacent third trench, wherein the first distance is greater than or equal to half of a longitudinal thickness of a drift region of the SGT power device, so as to achieve a withstand voltage between the third trench and the fourth trench; There is a second spacing region between two adjacent third trenches. The width of the second spacing region is a second spacing. The second spacing ensures that the depletion regions formed by the two adjacent third trenches on the drift region located in the second spacing region do not overlap.

2. The SGT power device according to claim 1, wherein: In the region surrounded by the fourth trench, the ratio of the area occupied by each of the first trenches to the area occupied by the second trenches is adjusted according to layout requirements while satisfying the condition of reducing the stress in the semiconductor substrate to below a required value.

3. The SGT power device according to claim 2, wherein: In a region surrounded by the fourth trenches, a ratio of an area occupied by each of the first trenches to an area occupied by the second trenches is 1:

1.

4. The SGT power device according to claim 1, wherein: The spacing between the first grooves and the spacing between the second grooves are both a third spacing, and the second spacing is at least twice the third spacing.

5. The SGT power device according to claim 4, wherein: The annular structure of each of the third grooves is a closed ring, and the annular structure of each of the third grooves is a rectangular ring with four rounded corners.

6. The SGT power device according to claim 5, wherein: Each of the first trenches and the corresponding third trenches are connected together, so that each of the first trenches forms a closed-loop structure, and the shielding polysilicon in each of the first trenches is conductively connected to the shielding polysilicon in the third trench and is connected to the source electrode through the second contact hole at the top of the third trench; Each of the second trenches and the corresponding third trenches are connected together, so that each of the second trenches has a closed-loop structure, and the shielding polysilicon in each of the second trenches and the shielding polysilicon in the third trench are conductive and connected to the source through the second contact hole at the top of the third trench.

7. The SGT power device according to claim 6, wherein: A fourth contact hole is formed at the top of a selected region of each of the first trenches, the bottom of the fourth contact hole is connected to the shielding polysilicon in the first trench, and the top of the fourth contact hole is connected to the source; A fifth contact hole is formed at the top of a selected region of each second trench, the bottom of the fifth contact hole is connected to the shielding polysilicon in the second trench, and the top of the fifth contact hole is connected to the source.

8. The SGT power device according to claim 5, wherein: Both ends of each first groove are spaced from the adjacent third groove, and both ends of each second groove are spaced from the adjacent third groove, so that each first groove and each second groove form an open loop structure; A fourth contact hole is formed at the top of a selected region of each of the first trenches, the bottom of the fourth contact hole is connected to the shielding polysilicon in the first trench, and the top of the fourth contact hole is connected to the source; A fifth contact hole is formed at the top of a selected region of each second trench, the bottom of the fifth contact hole is connected to the shielding polysilicon in the second trench, and the top of the fifth contact hole is connected to the source.

9. The SGT power device according to claim 5, wherein: There is a gap between one end of each first groove and the adjacent third groove, and the other end of each first groove is connected to the adjacent third groove. There is a gap between one end of each second groove and the adjacent third groove, and the other end of each second groove is connected to the adjacent third groove, so that each first groove and each second groove are in a semi-open and semi-closed structure. The shielding polysilicon in each of the first trenches and the shielding polysilicon in each of the second trenches are both conductively connected to the shielding polysilicon in the third trench and connected to the source through the second contact hole at the top of the third trench.

10. The SGT power device according to claim 9, wherein: A fourth contact hole is formed at the top of a selected region of each of the first trenches, the bottom of the fourth contact hole is connected to the shielding polysilicon in the first trench, and the top of the fourth contact hole is connected to the source; A fifth contact hole is formed at the top of a selected region of each second trench, the bottom of the fifth contact hole is connected to the shielding polysilicon in the second trench, and the top of the fifth contact hole is connected to the source.

11. The SGT power device according to claim 5, wherein: The annular structure of the fourth groove is a closed ring; the annular structure of the fourth groove is a rectangular ring with four rounded corners.

12. The SGT power device according to claim 11, wherein: The terminal area further includes one or more fifth grooves in an annular structure; the annular structure of the fifth groove is a closed ring; the annular structure of the fifth groove is a rectangular ring with four rounded corners; Each of the fifth grooves surrounds a circumference of the corresponding third groove; The number of the fifth grooves provided around each of the third grooves is the same or different and is greater than or equal to 0, and the total number of the fifth grooves provided around all of the third grooves is greater than or equal to 1.

13. The SGT power device according to claim 12, wherein: Each of the fifth trenches is a floating structure; or, a sixth contact hole is provided in a partial area of the annular structure of the fifth trench, the bottom of the sixth contact hole is connected to the shielding polysilicon in the fifth trench, and the top of the sixth contact hole is connected to the source.

14. The SGT power device according to claim 1, wherein: The third contact holes are in a strip-shaped structure, and corresponding third contact holes are provided on the outside of one or more sides of the rectangular ring of the fourth trench; Alternatively, the third contact hole is in a ring structure surrounding the outer periphery of the fourth trench.

15. The SGT power device according to claim 1, wherein: A first epitaxial layer is formed on the semiconductor substrate, and each of the trenches is formed in the first epitaxial layer.

16. The SGT power device according to claim 15, wherein: In each of the active regions, the SGT power device further includes a polysilicon gate; The polysilicon gate is a planar gate, and the polysilicon gate is located on the surface of the semiconductor substrate outside the first trench and the second trench, with a gate dielectric layer between the polysilicon gate and the semiconductor substrate; Alternatively, the polysilicon gate is a trench gate, the polysilicon gate is formed in a gate trench located outside the first trench and the second trench, the depth of the gate trench is shallower than the depth of the first trench, and the depth of the gate trench is shallower than the depth of the second trench, and a gate dielectric layer is interposed between the polysilicon gate and the side of the gate trench; Alternatively, the polysilicon gate is formed in each of the first trenches and each of the second trenches, a gate dielectric layer is spaced between the polysilicon gate and the side of the corresponding first trench or the second trench, a polysilicon inter-dielectric layer is spaced between the polysilicon gate and the shielding polysilicon, and a gate structure is formed by superimposing the shielding dielectric layer, the shielding polysilicon, the gate dielectric layer, the polysilicon inter-dielectric layer and the polysilicon gate, the gate structure is an upper and lower structure, and the polysilicon gate is located on the top of the shielding polysilicon; alternatively, the gate structure is a left and right structure, and the polysilicon gate is located in the top area on the left and right sides of the shielding polysilicon.

17. The SGT power device according to claim 1, wherein: The width of the third trench is greater than or equal to the width of the second contact hole plus twice the alignment accuracy of the second contact hole, and the width of the fourth trench is greater than or equal to the width of the first contact hole plus twice the alignment accuracy of the first contact hole.

18. The SGT power device according to claim 17, wherein: The first contact hole and the second contact hole have the same width, and the third trench has the same width as the fourth trench.

19. The SGT power device according to claim 18, wherein: The width of each of the first trenches is equal to the width of each of the second trenches and is smaller than or equal to the width of the third trench.

20. The SGT power device according to claim 16, wherein: The top of each polysilicon gate is connected to a gate pad formed by patterning the front metal layer through a seventh contact hole; In a top view, at least one gate pad is provided in the area surrounded by the fourth trench. At the formation position of the gate pad, the outer side surface of the area segment corresponding to the third trench surrounds the gate pad, so that the gate pad is located outside the corresponding active area.

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