Bandgap reference chip and its fabrication method, electronic equipment

Abstract

This invention relates to the field of semiconductor devices and provides a bandgap reference chip and its fabrication method, as well as an electronic device. The bandgap reference chip includes: a P-type silicon layer, an N-type silicon layer, an N-type silicon carbide layer, multiple P-type doped regions, an anode metal layer, and a cathode metal layer. A PN junction with a negative temperature coefficient is formed by the P-type silicon layer and the N-type silicon layer, and a Schottky junction with a positive temperature coefficient is formed by the N-type silicon carbide layer, the multiple P-type doped regions, and the anode metal layer. Thus, the PN junction and the Schottky junction are connected in series to cancel each other out their temperature characteristics, improving the temperature dependence of the on-state voltage drop of existing diode structures and achieving the accuracy of the voltage regulator circuit.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor devices, and particularly relates to a bandgap reference chip and its fabrication method, as well as electronic devices. Background Technology

[0002] In a voltage regulator circuit, an operational amplifier (OPA) is used to compare and provide feedback between the reference voltage (derived from the on-state voltage drop of the reference chip) and the output voltage, thereby stabilizing the output voltage. For example, when the output voltage waveform fluctuates, a difference appears between the reference voltage and the output voltage. The OPA is then activated to provide feedback and stabilize the output voltage. Therefore, the accuracy of the voltage regulator circuit is closely related to the stability of the reference voltage.

[0003] However, current voltage regulator circuits generally use the forward voltage drop of diodes as the reference power supply. But the forward voltage drop of diodes changes with temperature. When the output voltage changes, it is impossible to accurately perform OPA feedback to stabilize the output voltage. Summary of the Invention

[0004] The purpose of this invention is to provide a bandgap reference chip and its fabrication method, as well as an electronic device, in order to solve the problem that the on-state voltage drop of existing diodes is temperature-dependent and cannot provide an accurate reference voltage when the output voltage changes.

[0005] To address the aforementioned technical problems, this application provides a bandgap reference chip, which includes:

[0006] P-type silicon layer;

[0007] An N-type silicon layer is formed on the back side of the P-type silicon layer;

[0008] An N-type silicon carbide layer is formed on the front side of the P-type silicon layer;

[0009] Multiple P-type doped regions are formed on the front side of the N-type silicon carbide layer;

[0010] An anode metal layer is formed on the front side of the N-type silicon carbide layer and forms a Schottky contact with the N-type silicon carbide layer;

[0011] A cathode metal layer is formed on the back side of the N-type silicon layer.

[0012] In one embodiment, the thickness of the P-type silicon layer is equal to that of the N-type silicon layer.

[0013] In one embodiment, a plurality of the P-type doped regions are arranged in an array between the N-type silicon carbide layer and the anode metal layer.

[0014] In one embodiment, the N-type silicon layer has a concave structure, the P-type silicon layer is formed on the inner wall of the N-type silicon layer, and the P-type silicon layer also has a concave structure.

[0015] In one embodiment, the N-type silicon carbide layer has a concave structure, and the anode metal layer is formed within the groove of the N-type silicon carbide layer.

[0016] In one embodiment, a plurality of the P-type doped regions are formed on the inner wall of the groove of the N-type silicon carbide layer.

[0017] In one embodiment, the thickness of the N-type silicon carbide layer is greater than the sum of the thicknesses of the P-type silicon layer and the N-type silicon layer.

[0018] A second aspect of this application also provides a method for fabricating a bandgap reference chip, the method comprising:

[0019] A P-type silicon layer is formed on the front side of the N-type silicon layer;

[0020] An N-type silicon carbide layer is formed on the front side of the P-type silicon layer;

[0021] Multiple P-type doped regions are formed on the front side of the N-type silicon carbide layer;

[0022] An anode metal layer is formed on the front side of the N-type silicon carbide layer and on the plurality of P-type doped regions; wherein a Schottky contact is formed between the anode metal layer and the N-type silicon carbide layer;

[0023] A cathode metal layer is formed on the back side of the N-type silicon layer.

[0024] In one embodiment, the thickness of the N-type silicon carbide layer is greater than the sum of the thicknesses of the P-type silicon layer and the N-type silicon layer.

[0025] A third aspect of this application also provides an electronic device, the electronic device comprising a bandgap reference chip as described in any of the preceding claims.

[0026] This invention provides a bandgap reference chip, its fabrication method, and an electronic device. The bandgap reference chip includes a P-type silicon layer, an N-type silicon layer, an N-type silicon carbide layer, multiple P-type doped regions, an anode metal layer, and a cathode metal layer. A PN junction with a negative temperature coefficient is formed by the P-type and N-type silicon layers, and a Schottky junction with a positive temperature coefficient is formed by the N-type silicon carbide layer, multiple P-type doped regions, and the anode metal layer. The PN junction and the Schottky junction are connected in series to cancel each other out their temperature characteristics, improving the temperature dependence of the on-state voltage drop of existing diode structures and achieving the accuracy of the voltage regulator circuit. Attached Figure Description

[0027] Figure 1 A schematic diagram of the bandgap reference chip provided in an embodiment of the present invention. Figure 1 ;

[0028] Figure 2 A schematic diagram of the bandgap reference chip provided in an embodiment of the present invention. Figure 2 ;

[0029] Figure 3 This is a schematic flowchart of a bandgap reference chip provided in an embodiment of the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0031] In a voltage regulator circuit, an operational amplifier (OPA) is used to compare and provide feedback between the reference voltage (derived from the forward voltage drop of a reference chip) and the output voltage, thus stabilizing the output voltage. For example, when the output voltage waveform fluctuates, a difference appears between the reference voltage and the output voltage. The OPA is then activated to provide feedback and stabilize the output voltage. Therefore, the accuracy of the voltage regulator circuit is highly dependent on the stability of the reference voltage. Currently, voltage regulator circuits commonly use the forward voltage drop of a diode as the reference power supply. However, the forward voltage drop of a diode changes with temperature, making it impossible to accurately perform OPA feedback to stabilize the output voltage when changes occur.

[0032] To address the aforementioned technical problems, this application provides a bandgap reference chip, see [link to relevant documentation]. Figure 1 As shown, the bandgap reference chip includes: a P-type silicon layer 300, an N-type silicon layer 200, an N-type silicon carbide layer 400, multiple P-type doped regions 510, an anode metal layer 600, and a cathode metal layer 100.

[0033] Specifically, an N-type silicon layer 200 is formed on the back side of a P-type silicon layer 300, an N-type silicon carbide layer 400 is formed on the front side of a P-type silicon layer 300, multiple P-type doped regions 510 are formed on the front side of an N-type silicon carbide layer 400, an anode metal layer 600 is formed on the front side of an N-type silicon carbide layer 400 and forms a Schottky contact with the N-type silicon carbide layer 400, and a cathode metal layer 100 is formed on the back side of an N-type silicon layer 200.

[0034] In this embodiment, a PN junction with a negative temperature coefficient is formed by a P-type silicon layer 300 and an N-type silicon layer 200, and then a Schottky junction with a positive temperature coefficient is formed by an N-type silicon carbide layer 400, multiple P-type doped regions 510, and an anode metal layer 600. Thus, the PN junction and the Schottky junction are connected in series to cancel each other out their temperature characteristics, improve the temperature dependence of the on-state voltage drop of the existing diode structure, and achieve the accuracy of the voltage regulator circuit.

[0035] In one embodiment, an N-type substrate can be used as an N-type silicon layer 200. Then, P-type dopant ions are implanted or P-type silicon material is epitaxially grown on the front side of the N-type silicon layer 200 to form a P-type silicon layer 300 on the front side of the N-type silicon layer 200. Then, an N-type silicon carbide layer 400 is formed on the front side of the P-type silicon layer 300 by a deposition process, and P-type dopant ions are implanted in a designated area on the front side of the N-type silicon carbide layer 400 to form a plurality of P-type doped regions 510 on the front side of the N-type silicon carbide layer 400.

[0036] In one embodiment, the bandgap reference chip in this embodiment can be integrated into a low-dropout linear regulator, and the cathode metal layer 100 in the bandgap reference chip is connected to the reference signal pin of the low-dropout linear regulator.

[0037] In one embodiment, the thickness of the P-type silicon layer 300 is equal to that of the N-type silicon layer 200.

[0038] In one embodiment, the thickness of the P-type silicon layer 300 and the N-type silicon layer 200 is 10-1000 nm.

[0039] In one embodiment, the concentration of P-type doped ions in the P-type silicon layer 300 is equal to the concentration of N-type doped ions in the N-type silicon layer 200.

[0040] The diode device formed by the P-type silicon layer 300 and the N-type silicon layer 200 has a negative temperature coefficient characteristic. When the diode current is fixed (for example, the diode current is a constant 1mA), the voltage across the diode will decrease as the temperature increases.

[0041] In a silicon carbide Schottky diode, the anode metal layer 600 can be a Schottky metal material, such as gold, silver, aluminum, or platinum.

[0042] In one embodiment, because there are a large number of electrons in the N-type semiconductor (N-type silicon carbide layer 400) and only a very small number of free electrons in the anode metal layer 600, electrons diffuse from the high-concentration N-type silicon carbide layer 400 to the low-concentration anode metal layer 600.

[0043] Clearly, there are no holes in the anode metal layer 600, and therefore no diffusion of holes from the anode metal layer 600 to the N-type silicon carbide layer 400. As electrons continuously diffuse from the N-type silicon carbide layer 400 to the anode metal layer 600, the electron concentration on the surface of the N-type silicon carbide layer 400 gradually decreases, disrupting its surface charge neutrality and thus forming a potential barrier with an electric field direction from the N-type silicon carbide layer 400 to the anode metal layer 600. However, under the influence of this electric field, electrons in the anode metal layer 600 also drift from the anode metal layer 600 to the N-type silicon carbide layer 400, thereby weakening the electric field formed by diffusion. When a space charge region of a certain width is established, the electron drift caused by the electric field and the electron diffusion caused by the concentration difference reach a relative equilibrium, forming a Schottky barrier. The potential barrier formed on the contact surface between the anode metal layer 600 and the N-type silicon carbide layer 400 exhibits rectifying characteristics.

[0044] In one embodiment, a plurality of P-type doped regions 510 are arranged in an array between the N-type silicon carbide layer 400 and the anode metal layer 600.

[0045] In one embodiment, the cross-sectional area of ​​each P-type doped region 510 is no more than one percent of the cross-sectional area of ​​the N-type silicon carbide layer 400.

[0046] In one embodiment, the cross-sectional shape of the P-type doped region 510 can be square or circular, and the shape of the P-type doped region 510 can be rectangular or cylindrical.

[0047] In one embodiment, an isolation layer is formed around the N-type silicon carbide layer 400 and the anode metal layer 600, and the isolation layer may be silicon oxide.

[0048] In this embodiment, the isolation layer can be used to eliminate the electric field in the edge region of the Schottky diode, thereby improving the voltage withstand capability of the Schottky diode.

[0049] In one embodiment, the N-type silicon carbide layer 400 has a smaller on-state resistance, and the doping concentration of the N-type dopant ions inside it is greater than the doping concentration of the N-type silicon layer 200.

[0050] In one embodiment, see Figure 2 As shown, the N-type silicon layer 200 has a concave structure, and the P-type silicon layer 300 is formed on the inner wall of the N-type silicon layer 200, and the P-type silicon layer 300 also has a concave structure.

[0051] In one embodiment, see Figure 2 As shown, the N-type silicon carbide layer 400 has a concave structure, and the anode metal layer 600 is formed in the groove of the N-type silicon carbide layer 400.

[0052] In one embodiment, the temperature coefficient of the diode formed by the N-type silicon layer 200 and the P-type silicon layer 300 can be -2.5mV / degree. The PN junction is formed by a N-type doped region and a P-type doped region in close contact. At this time, the temperature coefficient of the PN junction is -2.5mV / degree, which means that for every 1 degree increase in temperature, the diode voltage drop will decrease by 2.5mV.

[0053] In one embodiment, by designing the N-type silicon carbide layer 400 as a concave structure, the anode metal layer 600 is formed within the groove of the N-type silicon carbide layer 400, thereby making the temperature coefficient of the Schottky diode formed by the N-type silicon carbide layer 400 and the anode metal layer 600 2.5mV / degree. The Schottky junction is formed by the close contact between the N-type silicon carbide doped region and the Schottky metal material. At this time, the temperature coefficient of the Schottky junction is 2.5mV / degree, which means that for every 1 degree increase in temperature, the voltage drop of the Schottky diode will decrease by 2.5mV.

[0054] In practical applications, by designing the N-type silicon carbide layer 400 as a concave structure and forming the anode metal layer 600 within the groove of the N-type silicon carbide layer 400, the contact area between the Schottky diode and the silicon-based diode can be increased, ensuring that the Schottky diode and the silicon-based diode have the same temperature.

[0055] In one embodiment, see Figure 2 As shown, multiple P-type doped regions 510 are formed on the inner wall of the groove of the N-type silicon carbide layer 400.

[0056] In one embodiment, the thickness of the N-type silicon carbide layer 400 is greater than the sum of the thicknesses of the P-type silicon layer 300 and the N-type silicon layer 200.

[0057] This application also provides a method for fabricating a bandgap reference chip, see [link to relevant documentation]. Figure 3 As shown, the preparation method includes steps S100 to S500.

[0058] In step S100, a P-type silicon layer 300 is formed on the front side of the N-type silicon layer 200.

[0059] In this embodiment, an N-type substrate can be directly used as the N-type silicon layer 200, and then a P-type silicon material can be epitaxially grown on the front side of the N-type silicon layer 200 to form a P-type silicon layer 300 on the front side of the N-type silicon layer 200.

[0060] In one embodiment, the thickness of the P-type silicon layer 300 is equal to that of the N-type silicon layer 200.

[0061] In step S200, an N-type silicon carbide layer 400 is formed on the front side of the P-type silicon layer 300.

[0062] In this embodiment, a silicon carbide layer can be formed on the front side of the P-type silicon layer 300 by depositing silicon carbide material, and then N-type dopant ions can be implanted on the silicon carbide layer to form an N-type silicon carbide layer 400.

[0063] In step S300, a plurality of P-type doped regions 510 are formed on the front side of the N-type silicon carbide layer 400.

[0064] In this embodiment, P-type dopant ions are implanted in a designated area on the front side of the N-type silicon carbide layer 400, thereby forming a plurality of P-type doped regions 510 on the front side of the N-type silicon carbide layer 400.

[0065] In step S400, an anode metal layer 600 is formed on the front side of the N-type silicon carbide layer 400 and on a plurality of P-type doped regions 510.

[0066] In this embodiment, a Schottky contact is formed between the anode metal layer 600 and the N-type silicon carbide layer 400.

[0067] In one embodiment, a plurality of P-type doped regions 510 are arranged in an array between the N-type silicon carbide layer 400 and the anode metal layer 600.

[0068] In step S500, a cathode metal layer 100 is formed on the back side of the N-type silicon layer 200.

[0069] In one embodiment, the thickness of the N-type silicon carbide layer 400 is greater than the sum of the thicknesses of the P-type silicon layer 300 and the N-type silicon layer 200.

[0070] In one embodiment, in step S200, a P-type silicon layer 300 is formed on the N-type silicon layer 200 by a deposition process. The temperature coefficient of the formed diode can be -2.5mV / degree. The PN junction is composed of an N-type doped region and a P-type doped region in close contact. At this time, the temperature coefficient of the PN junction is -2.5mV / degree, which means that for every 1 degree increase in temperature, the diode voltage drop will decrease by 2.5mV.

[0071] In one embodiment, in step S400, by designing the N-type silicon carbide layer 400 as a concave structure, the anode metal layer 600 is formed in the groove of the N-type silicon carbide layer 400, thereby making the temperature coefficient of the Schottky diode formed by the N-type silicon carbide layer 400 and the anode metal layer 600 2.5mV / degree. The Schottky junction is formed by the close contact between the N-type silicon carbide doped region and the Schottky metal material. At this time, the temperature coefficient of the Schottky junction is 2.5mV / degree, which means that for every 1 degree increase in temperature, the voltage drop of the Schottky diode will decrease by 2.5mV.

[0072] In practical applications, by designing the N-type silicon carbide layer 400 as a concave structure and forming the anode metal layer 600 within the groove of the N-type silicon carbide layer 400, the contact area between the Schottky diode and the silicon-based diode can be increased, ensuring that the Schottky diode and the silicon-based diode have the same temperature.

[0073] In one embodiment, the cross-sectional area of ​​each P-type doped region 510 is no more than one percent of the cross-sectional area of ​​the N-type silicon carbide layer 400.

[0074] In one embodiment, the cross-sectional shape of the P-type doped region 510 can be square or circular, and the shape of the P-type doped region 510 can be rectangular or cylindrical.

[0075] In one embodiment, an isolation layer is formed around the N-type silicon carbide layer 400 and the anode metal layer 600, and the isolation layer may be silicon oxide.

[0076] In this embodiment, the isolation layer can be used to eliminate the electric field in the edge region of the Schottky diode, thereby improving the voltage withstand capability of the Schottky diode.

[0077] In one embodiment, the N-type silicon carbide layer 400 has a smaller on-state resistance, and the doping concentration of the N-type dopant ions inside it is greater than the doping concentration of the N-type silicon layer 200.

[0078] This application also provides an electronic device, which includes a bandgap reference chip as described in any of the preceding embodiments.

[0079] In this embodiment, the electronic device may be an operational amplifier or a chip containing an operational amplifier.

[0080] Specifically, the bandgap reference chip can be formed on a chip substrate, on which other peripheral devices can also be integrated.

[0081] This invention provides a bandgap reference chip, its fabrication method, and an electronic device. The bandgap reference chip includes a P-type silicon layer, an N-type silicon layer, an N-type silicon carbide layer, multiple P-type doped regions, an anode metal layer, and a cathode metal layer. A PN junction with a negative temperature coefficient is formed by the P-type and N-type silicon layers, and a Schottky junction with a positive temperature coefficient is formed by the N-type silicon carbide layer, multiple P-type doped regions, and the anode metal layer. The PN junction and the Schottky junction are connected in series to cancel each other out their temperature characteristics, improving the temperature dependence of the on-state voltage drop of existing diode structures and achieving the accuracy of the voltage regulator circuit.

[0082] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions is used as an example. In practical applications, the above-described functional areas can be assigned to different doped regions as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above.

[0083] In the embodiments, the doped regions can be integrated into one functional region, or each doped region can exist independently, or two or more doped regions can be integrated into one functional region. The integrated functional region can be implemented using the same type of dopant ion or multiple types of dopant ions. Furthermore, the specific names of each doped region are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the doped region in the fabrication method of the above device can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0084] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A bandgap reference chip, characterized in that, The bandgap reference chip includes: P-type silicon layer; An N-type silicon layer is formed on the back side of the P-type silicon layer; the P-type silicon layer and the N-type silicon layer form a PN junction with a negative temperature coefficient. An N-type silicon carbide layer is formed on the front side of the P-type silicon layer; Multiple P-type doped regions are formed on the front side of the N-type silicon carbide layer; the P-type doped regions are formed by implanting P-type dopant ions into a designated area on the front side of the N-type silicon carbide layer. An anode metal layer is formed on the front side of the N-type silicon carbide layer and forms a Schottky contact with the N-type silicon carbide layer; the N-type silicon carbide layer, the plurality of P-type doped regions, and the anode metal layer form a Schottky junction with a positive temperature coefficient; A cathode metal layer is formed on the back side of the N-type silicon layer.

2. The bandgap reference chip as described in claim 1, characterized in that, The thickness of the P-type silicon layer is equal to that of the N-type silicon layer.

3. The bandgap reference chip as described in claim 1, characterized in that, Multiple P-type doped regions are arranged in an array between the N-type silicon carbide layer and the anode metal layer.

4. The bandgap reference chip as described in claim 1, characterized in that, The N-type silicon layer has a concave structure, and the P-type silicon layer is formed on the inner wall of the N-type silicon layer, and the P-type silicon layer also has a concave structure.

5. The bandgap reference chip as described in claim 4, characterized in that, The N-type silicon carbide layer has a concave structure, and the anode metal layer is formed within the groove of the N-type silicon carbide layer.

6. The bandgap reference chip as described in claim 5, characterized in that, Multiple P-type doped regions are formed on the inner wall of the grooves in the N-type silicon carbide layer.

7. The bandgap reference chip according to any one of claims 1-6, characterized in that, The thickness of the N-type silicon carbide layer is greater than the sum of the thicknesses of the P-type silicon layer and the N-type silicon layer.

8. A method for fabricating a bandgap reference chip, characterized in that, The preparation method includes: A P-type silicon layer is formed on the front side of the N-type silicon layer; the P-type silicon layer and the N-type silicon layer form a PN junction with a negative temperature coefficient. An N-type silicon carbide layer is formed on the front side of the P-type silicon layer; Multiple P-type doped regions are formed on the front side of the N-type silicon carbide layer; the P-type doped regions are formed by implanting P-type dopant ions into a designated area on the front side of the N-type silicon carbide layer. An anode metal layer is formed on the front side of the N-type silicon carbide layer and on the plurality of P-type doped regions; wherein, a Schottky contact is formed between the anode metal layer and the N-type silicon carbide layer; the N-type silicon carbide layer, the plurality of P-type doped regions, and the anode metal layer form a Schottky junction with a positive temperature coefficient; A cathode metal layer is formed on the back side of the N-type silicon layer.

9. The preparation method according to claim 8, characterized in that, The thickness of the N-type silicon carbide layer is greater than the sum of the thicknesses of the P-type silicon layer and the N-type silicon layer.

10. An electronic device, characterized in that, The electronic device includes a bandgap reference chip as described in any one of claims 1-7.

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