Semiconductor structure

Abstract

This disclosure relates to the semiconductor field and provides a semiconductor structure comprising: a substrate including adjacent first and second well regions; a first transistor including a first gate located on a portion of the substrate in the first well region and first doped regions located on opposite sides of the first gate, the first doped regions being located within the first well region; a first guard gate located in the first well region, and the orthographic projection of the first guard gate onto the substrate surface at least aligns with the orthographic projection of the second well region onto the substrate surface; and a second doped region located on the side of the first guard gate away from the second well region and within the first well region, the second doped region having the same conductivity type as the first doped region and being electrically insulated from the first doped region, wherein the second doped region is electrically connected to the first gate. The semiconductor structure provided by this disclosure at least improves the stability of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure. Background Technology

[0002] Memory is a storage component used to store programs and various data information. Random Access Memory (RAM) used in general computer systems can be divided into two types: Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). DRAM is a commonly used semiconductor storage device in computers, consisting of many repeating storage cells.

[0003] A memory cell typically includes a capacitor and a transistor. The drain of the transistor is connected to the bit line structure, and the source is connected to the capacitor. The capacitor includes a capacitor contact structure and a capacitor. The word line structure of the memory cell can control the opening or closing of the transistor's channel region, thereby reading data information stored in the capacitor through the bit line structure, or writing data information into the capacitor for storage through the bit line structure. Summary of the Invention

[0004] This disclosure provides a semiconductor structure that improves the plasma-induced damage effect in semiconductor structures.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a substrate, the substrate including adjacent first well regions and second well regions, wherein the dopant ion type in the first well region is different from the dopant ion type in the second well region; a first transistor, the first transistor including a first gate located on a portion of the substrate in the first well region and first doped regions located on opposite sides of the first gate, the first doped regions being located within the first well region; a first guard gate, the first guard gate being located in the first well region, and the orthographic projection of the first guard gate on the substrate surface is at least in contact with the orthographic projection of the second well region on the substrate surface; a second doped region, the second doped region being located on the side of the first guard gate away from the second well region and located within the first well region, the second doped region having the same conductivity type as the first doped region and being electrically insulated from the first doped region, the orthographic projection of the second doped region on the substrate surface intersecting with the orthographic projection of the first guard gate on the substrate surface, wherein the second doped region is electrically connected to the first gate.

[0006] In some embodiments, the projected area of ​​the first protective gate on the substrate surface is greater than the projected area of ​​the first gate on the substrate surface.

[0007] In some embodiments, the number of first transistors is greater than or equal to 2, and the first gate of each first transistor is electrically connected to the second doped region.

[0008] In some embodiments, the number of first transistors is greater than or equal to 2, the number of first protection gates is equal to the number of first transistors, and each first protection gate corresponds to a second doped region, wherein the first gate of each first transistor is electrically connected to a second doped region.

[0009] In some embodiments, the number of first protection gates is greater than or equal to 2, and each first protection gate corresponds to a second doped region, wherein each second doped region is electrically connected to the first gate.

[0010] In some embodiments, the semiconductor structure further includes: a second transistor, the second transistor including a second gate located on a portion of the substrate of the second well region and third doped regions located on opposite sides of the second gate, the third doped regions being located within the second well region; a second guard gate, the second guard gate being located in the first well region, and the orthographic projection of the second guard gate onto the substrate surface being at least in contact with the orthographic projection of the second well region onto the substrate surface; a fourth doped region, the fourth doped region being located on the side of the second guard gate away from the first well region and being located within the second well region, the fourth doped region having the same conductivity type as the third doped region and being electrically insulated from the third doped region, the orthographic projection of the fourth doped region onto the substrate surface intersecting with the orthographic projection of the second guard gate onto the substrate surface, wherein the fourth doped region is electrically connected to the second gate.

[0011] In some embodiments, the first protective gate spans the boundary between the first well region and the second well region. The semiconductor structure further includes: a second transistor, the second transistor including a second gate located on a portion of the substrate of the second well region and third doped regions located on opposite sides of the second gate, the third doped regions being located within the second well region; and a fourth doped region, the fourth doped region being located on the side of the first protective gate away from the second doped region and within the second well region, the fourth doped region having the same conductivity type as the third doped region and being electrically insulated from the third doped region, the orthographic projection of the fourth doped region onto the substrate surface intersecting the orthographic projection of the first protective gate onto the substrate surface, wherein the fourth doped region is electrically connected to the second gate.

[0012] In some embodiments, the semiconductor structure further includes a metal layer comprising a first metal line and a second metal line spaced apart from each other, the first metal line being electrically connected to a first gate and the second metal line being electrically connected to a first guard gate, wherein the projected area of ​​the second metal line on the substrate surface is greater than the projected area of ​​the first metal line on the substrate surface.

[0013] In some embodiments, the semiconductor structure further includes: a first test pad electrically connected to a first gate and a second doped region; a second test pad electrically connected to a first guard gate; a third test pad electrically connected to a first doped region on one side of the first transistor; a fourth test pad electrically connected to a first doped region on the other side of the first transistor; and a fifth test pad electrically connected to a first well region.

[0014] In some embodiments, the projected area of ​​the second test pad on the substrate surface is greater than the projected area of ​​the first test pad on the substrate surface.

[0015] In some embodiments, the first protective gate is electrically connected to the substrate.

[0016] In some embodiments, the first protective gate is electrically connected to one end of a resistor, and the other end of the resistor is electrically connected to the substrate.

[0017] In some embodiments, a first protective gate is electrically connected to one end of a diode, the other end of the diode is electrically connected to a substrate, and the forward direction of the diode points towards the substrate.

[0018] In some embodiments, the first protection gate is electrically connected to the source of a grounded transistor, and the drain of the grounded transistor is electrically connected to the substrate.

[0019] In some embodiments, the substrate has a plurality of isolation structures, the first transistor is located between the isolation structures of the first well region, and the first protection gate and the corresponding second doped region are located between the isolation structures of the first well region and the isolation structures of the second well region.

[0020] The technical solution provided by the embodiments of this disclosure has at least the following advantages: the first protective gate is located in the first well region and is at least connected to the second well region, and the second doped region is located in the first well region on the side of the first protective gate away from the second well region. The second doped region is electrically connected to the first gate of the first transistor. When both the first gate and the first protective gate collect charge due to the plasma process, a large amount of charge accumulates on the first protective gate. The charge on the first gate can be discharged from the second doped region to the second well region through the inversion channel layer formed on the surface of the first well region below the first protective gate; or, the charge on the first gate can be discharged to the first well region through the PN junction formed by the second doped region and the first well region, so as to avoid excessive charge collected on the first gate causing the gate dielectric layer of the first gate to be broken down, reducing the plasma-induced effect and improving the stability of the semiconductor structure. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 For Figure 10 This is a schematic diagram of various semiconductor structures provided in one embodiment of the present disclosure. Detailed Implementation

[0023] Analysis reveals that plasma-induced damage (PID) to semiconductor devices during the manufacturing process of semiconductor integrated circuits leads to performance deviations. In a plasma environment, the discharge generates a large number of ions and electrons. These ions are accelerated towards the wafer surface due to electrode potential or plasma self-bias, physically bombarding the wafer and promoting chemical reactions on the surface. These ion and electron currents are collected by the metal layer exposed to the plasma environment on the wafer and accumulate on the gate. In this case, the metal layer functions like an "antenna," and the gate dielectric layer can be considered a capacitor. As the charge collected on the gate increases, the gate voltage rises, leading to Fowler-Nordheim tunneling (FN tunneling) in the gate dielectric layer. Under the influence of FN current, defects are generated in the gate dielectric layer and interface, reducing the yield of semiconductor devices and accelerating hot carrier degradation and time-dependent dielectric breakdown (TDDB), causing reliability issues in semiconductor devices.

[0024] Several factors that cause PID effect: (1) Plasma density: Higher plasma density means greater current, which makes it easier to cause PID problems; (2) Non-uniform local distribution of plasma: In a uniform plasma, the ion and electron currents maintain a local balance in one cycle, so the potential of the gate dielectric layer is very small. However, in a non-uniform plasma, the potential imbalance in a local range will generate current paths on the wafer surface, thereby causing damage to the gate dielectric layer; (3) Electron shielding effect: Electrons in plasma are less directional than ions, that is, the incident angle distribution of electrons is larger than that of ions, and they are more easily shielded by photoresist. Positive ions accumulate at the etching front end to form a positive potential for the device; (4) Reverse electron shielding effect: Electrons are isotropic. Some electrons are collected by the metal to be etched, while ions are not, which leads to the accumulation of negative charges on the metal sidewalls to form a negative potential for the device.

[0025] According to some embodiments of this disclosure, one embodiment of this disclosure provides a semiconductor structure that at least helps to improve the plasma-induced damage effect in the semiconductor structure.

[0026] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0027] Figure 1 For Figure 10 The following is a schematic diagram of various semiconductor structures provided in an embodiment of the present disclosure. The semiconductor structures provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0028] refer to Figures 1 to 10The semiconductor structure includes: a substrate 100, which includes an adjacent first well region 101 and a second well region 102, wherein the dopant ion type in the first well region 101 is different from the dopant ion type in the second well region 102, and the dopant ion type includes N-type or P-type; a first transistor 200, which includes a first gate 201 located on a portion of the substrate 100 in the first well region 101 and first doped regions 202 located on opposite sides of the first gate 201, wherein the first doped regions 202 are located within the first well region 101; and a first protective gate 301 located in the first well region 101. 01, and the orthographic projection of the first protective gate 301 on the surface of the substrate 100 is at least in contact with the orthographic projection of the second well region 102 on the surface of the substrate 100; the second doped region 302 is located on the side of the first protective gate 301 away from the second well region 102, and is located within the first well region 101. The second doped region 302 has the same conductivity type as the first doped region and is electrically insulated from the first doped region 202. The orthographic projection of the second doped region 302 on the surface of the substrate 100 intersects with the orthographic projection of the first protective gate 301 on the surface of the substrate 100. The second doped region 302 is electrically connected to the first gate 201.

[0029] The first protective gate 301 is located in the first well region 101 and is at least connected to the second well region 102. The second doped region 302 is located in the first well region 101 on the side of the first protective gate 301 away from the second well region 102. The second doped region 302 is electrically connected to the first gate 201 of the first transistor 200. When both the first gate 201 and the first protective gate 301 collect charge due to the plasma process, a large amount of charge accumulates on the first protective gate 301. The charge on the first gate 201 can be discharged from the second doped region 302 to the second well region 102 through the inversion channel layer formed on the surface of the first well region 101 below the first protective gate 301. Alternatively, the charge on the first gate 201 can be discharged into the first well region 101 through the PN junction formed by the second doped region 302 and the first well region 101. This is to avoid excessive charge accumulation on the first gate 201, which could cause the gate dielectric layer of the first gate 201 to be broken down, thereby reducing the plasma-induced effect and improving the stability of the semiconductor structure.

[0030] It should be noted that, in Figures 1 to 10In the examples provided, the second doped region 302 and the first gate 201 are electrically connected via a metal line 600. Specifically, one end of the metal line 600 is in electrical contact with the second doped region 302, and the other end is in electrical contact with the first gate 201. This does not limit the specific method of electrical connection between the second doped region 302 and the first gate 201. In some embodiments, the second doped region and the first gate can be electrically connected via a conductive plug and a metal line. For example, the first conductive plug extends vertically and its bottom is in electrical contact with the surface of the second doped region; the second conductive plug extends vertically and its bottom is in electrical contact with the surface of the first gate; one end of the metal line is in electrical contact with the top of the first conductive plug, and the other end is in electrical contact with the top of the second conductive plug.

[0031] In some embodiments, the first protective gate may span the boundary between the first well region and the second well region, that is, the orthographic projection of the first protective gate on the substrate surface intersects with the orthographic projection of the first well region on the substrate surface, and the orthographic projection of the first protective gate on the substrate surface intersects with the orthographic projection of the second well region on the substrate surface.

[0032] For the substrate 100, the material of the substrate 100 includes basic semiconductors, compound semiconductors, or alloy semiconductors. For example, basic semiconductors include germanium (Ge); compound semiconductors include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or group III-V semiconductor materials; alloy semiconductors include silicon germanium (SiGe), silicon germanium carbide, germanium tin, silicon germanium tin, gallium arsenide phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide, aluminum indium arsenide, and / or aluminum gallium arsenide. In some embodiments, the substrate 100 may also be a silicon-on-insulator structure, a germanium-silicon-on-insulator structure, a germanium-on-insulator structure, or a combination thereof.

[0033] In some embodiments, the first well region 101 may contain P-type doped ions, and the second well region 102 may contain N-type doped ions; in other embodiments, the first well region 101 may contain N-type doped ions, and the second well region 102 may contain P-type doped ions. For example, the N-type ions may specifically be phosphorus ions, arsenic ions, or antimony ions; the P-type ions may specifically be boron ions, indium ions, or gallium ions.

[0034] For the first transistor 200, the first transistor 200 is located in the first well region 101. When the doped ion type in the first well region 101 is P-type, the doped ion type in the first doped region 202 is N-type, that is, the first transistor 200 is an NMOS transistor; when the doped ion type in the first well region 101 is N-type, the doped ion type in the first doped region 202 is P-type, that is, the first transistor 200 is a PMOS transistor.

[0035] For the second doped region 302, the type of doped ions in the second doped region 302 is the same as the type of doped ions in the first doped region 202. When the first transistor 200 is a PMOS transistor, the type of doped ions in the second doped region 302 is P-type doped ions; when the first transistor 200 is an NMOS transistor, the type of doped ions in the second doped region 302 is N-type doped ions.

[0036] refer to Figure 2 and Figure 3 When the doped ions in the first well region 101 are P-type and the doped ions in the second well region 102 are N-type, the first transistor 200 is an NMOS transistor, and both the first doped region 202 and the second doped region 302 contain N-type doped ions. (Reference) Figure 2 When positive charges are collected on both the first gate 201 and the first protective gate 301 by plasma processing, an inversion channel layer 103 is generated on the surface of the first well region 101 below the first protective gate 301. The first protective gate 301 and its two sides, the second doped region 302 and the second well region 102, can then form a transistor-like structure. The first gate 201 can be connected to the second well region 102 via the metal line 600, the second doped region 302, and the inversion channel layer 103. Due to the potential difference between the first gate 201 and the second well region 102, electrons in the second well region 102 move from the second well region 102 through the inversion channel layer 103, the second doped region 302, and the metal layer 600 towards the first gate 201, thus forming a current path opposite to the direction of electron movement (e.g., ...). Figure 2 (as indicated by the arrow in the image), thus the positive charge on the first gate 201 can be discharged to the second well region 102; Reference Figure 3 When negative charges are collected on both the first gate 201 and the first guard gate 301 by plasma processing, an inversion channel layer cannot be formed on the surface of the first well region 101 below the first guard gate 301. However, the PN junction formed between the second doped region 302 and the first well region 101 can constitute a diode with the first well region 101 pointing to the second doped region 302 in a forward direction. Electrons on the first gate 201 can move from the first gate 201 to the first well region 101 via the metal line 600 and the second doped region 302 (e.g., Figure 3 In the path indicated by the middle arrow, so that the negative charge on the first gate 201 is discharged.

[0037] refer to Figure 4 and Figure 5 When the doped ions in the first well region 101 are N-type and the doped ions in the second well region 102 are P-type, the first transistor 200 is a PMOS transistor, and both the first doped region 202 and the second doped region 302 contain P-type doped ions. (Reference) Figure 4When negative charges are collected on both the first gate 201 and the first protective gate 301 by plasma processing, an inversion channel layer 103 is generated on the surface of the first well region 101 below the first protective gate 301. Then, the first protective gate 301 and its two sides, the second doped region 302 and the second well region 102, can form a transistor-like structure. The first gate 201 can be connected to the second well region 102 via the metal line 600, the second doped region 302, and the inversion channel layer 103. Electrons in the first gate 201 can move to the second well region 102 via the metal line 600, the second doped region 302, and the inversion channel layer 103 (e.g., Figure 4 (As indicated by the arrow in the diagram), the negative charge on the first gate 201 can be discharged into the second well region 102. It is understood that during the discharge of negative charge from the first gate to the second well region 102, a small number of electrons may be trapped by holes in the second doped region 302 and the inversion channel layer 103. (See reference...) Figure 5 When positive charges are collected on both the first gate 201 and the first guard gate 301 by plasma processing, an inversion channel layer cannot be formed on the surface of the first well region 101 below the first guard gate 301. However, the PN junction formed between the second doped region 302 and the first well region 101 can constitute a diode with the direction from the second doped region 302 to the first well region 101 being forward-biased. Electrons in the first well region 101 can move to the first gate 201 through the second doped region 302 and the metal line 600 to form a current path from the first gate 201 to the first well region 101 (e.g., ...). Figure 5 (as indicated by the arrow in the diagram), so that the positive charge on the first gate 201 can be discharged into the first well region 101.

[0038] It should be noted that, in Figures 1 to 5 In all embodiments, the first gate 201 is located on a portion of the substrate 100 surface of the first well region 101, which is an example of a planar transistor structure and does not constitute a limitation on the structure of the first transistor 200. In some embodiments, the first gate is located within a portion of the substrate of the first well region, i.e., the first transistor is a transistor with a buried gate structure. This is beneficial for increasing the contact area between the gate and the channel region of the transistor, which can prevent the threshold voltage from decreasing and improve the stability of the semiconductor device. In some embodiments, the substrate of the first well region may have a fin structure, and the first gate covers the top and sidewalls of the fin structure, i.e., the first transistor is a fin field-effect transistor structure. This increases the control area of ​​the gate on the channel, greatly enhancing the gate control capability, thereby effectively suppressing the short-channel effect and reducing the subthreshold leakage current.

[0039] In some embodiments, the first gate includes a first gate conductive layer and a first gate dielectric layer, the first gate dielectric layer being located on a portion of the substrate of the first well region, and the first gate conductive layer being located on the side surface of the first gate dielectric layer away from the substrate.

[0040] The material of the first gate conductive layer includes at least one of polycrystalline silicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

[0041] For the first gate dielectric layer, the material of the first gate dielectric layer includes silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, antiferroelectric material, or a combination thereof. For example, the gate dielectric layer may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, or HfSiON, etc.

[0042] In some embodiments, the first protective gate includes a first protective gate conductive layer and a first protective gate dielectric layer, the first protective gate dielectric layer spanning the boundary between the first well region and the second well region, and the first protective gate conductive layer covering the side surface of the first protective gate dielectric layer away from the substrate.

[0043] The material of the first protective gate conductive layer includes at least one of polycrystalline silicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

[0044] For the first guard gate dielectric layer, the material of the first guard gate dielectric layer includes silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, antiferroelectric material, or a combination thereof. For example, the gate dielectric layer may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, or HfSiON, etc.

[0045] In some embodiments, the material of the first gate conductive layer can be the same as the material of the first protective gate conductive layer. When the materials of the first gate conductive layer and the first protective gate conductive layer are the same, the first gate conductive layer and the first protective gate conductive layer have the same probability of collecting charge in the same plasma process. This avoids the situation where the first gate conductive layer is more likely to collect charge while the first protective gate conductive layer is less likely to absorb charge, which could prevent the formation of an inversion channel under the first protective gate and thus prevent the charge on the first gate from being unable to dissipate to the second well region. In some embodiments, the material of the first gate conductive layer can be different from the material of the first protective gate conductive layer. When the materials of the first gate conductive layer and the first protective gate conductive layer are different, the material of the first protective gate conductive layer can be set to be a material that is more likely to collect charge in the plasma process, which is conducive to the formation of an inversion channel layer on the surface of the first well region under the first protective gate and facilitates the discharge of charge on the first gate to the second well region.

[0046] In some embodiments, the projected area of ​​the first protective gate 301 on the surface of the substrate 100 is larger than the projected area of ​​the first gate 201 on the surface of the substrate 100. When the first protective gate 301 and the first gate 201 are in the same plasma process environment, the projected area of ​​the first protective gate 301 on the surface of the substrate 100 is larger than that of the first gate 201 on the surface of the substrate 100. This allows the amount of charge collected on the first protective gate 301 to be greater than that on the first gate 201, which is more conducive to having sufficient charge on the first protective gate 301 to form an inversion channel layer, so that all the charge on the first gate 201 can be discharged into the second well region 102.

[0047] In some embodiments, reference Figure 6 The number of first transistors 200 is greater than or equal to 2, and the first gate 201 of each first transistor 200 is electrically connected to the second doped region 302. That is, when the first gates 201 of the multiple first transistors 200 in the first well region 101 have collected charges due to the plasma process, the charges collected on the multiple first gates 201 can be discharged from the second doped region 302 into the second well region 102 through the inversion channel layer formed on the surface of the first well region 101 below the same first protective gate 301, or discharged into the first well region 101 through the PN junction formed by the same second doped region 302 and the first well region 101.

[0048] It should be noted that, in Figure 6 In this example, the number of first transistors 200 is two, which does not constitute a limitation on the number of first transistors 200. In some embodiments, the number of first transistors can be three, six, nine, or fifteen, etc.

[0049] In some embodiments, reference Figure 7The number of first transistors 200 is greater than or equal to 2, the number of first protective gates 301 is equal to the number of first transistors 200, and each first protective gate 301 corresponds to a second doped region 302. Each first gate 201 of each first transistor 200 is electrically connected to a second doped region 302. That is, each first gate 201 of each first transistor 200 within the first well region 101 can correspond to a second doped region 302. When multiple first gates 201 and multiple first protective gates 301 collect charge, the charge on each first gate 201 can be discharged from the corresponding second doped region 302 into the second well region 102 through the inversion channel layer formed on the surface of the first well region 101 below its corresponding first protective gate 301, or through the PN junction formed by the respective second doped region 302 and the first well region 101 into the first well region 101. In this way, the charge on the first gate 201 in each first transistor 200 can be discharged through different paths, thereby increasing the discharge rate of the charge on each first gate 201, avoiding the breakdown of the gate dielectric layer in the first gate 201 due to untimely discharge, and improving the stability of the semiconductor structure.

[0050] It should be noted that, in Figure 7 In this example, if the number of first transistors 200 is two, the corresponding number of first protective gates 301 is also two, which does not constitute a limitation on the number of first transistors 200 and the number of first protective gates 301. In some embodiments, the number of first transistors can be three, six, nine, or 15, etc., and the corresponding number of first protective gates can be three, six, nine, or 15, etc.

[0051] In some embodiments, reference Figure 8 The number of first protective gates 301 is greater than or equal to two, and each first protective gate 301 corresponds to a second doped region 302, wherein each second doped region 302 is electrically connected to the first gate 201. That is, the first gate 201 of a first transistor 200 can be connected to multiple second doped regions 302, so that the charge on the first gate 201 can be discharged from the corresponding second doped region 302 to the second well region 102 through the inversion channel layer formed on the surface of the first well region 101 below the multiple first protective gates 301, or discharged to the first well region 101 through the PN junction formed by the corresponding second doped region 302 and the first well region 101. In this way, the charge on the first gate 201 of a first transistor 200 can be discharged to the first well region 101 or the second well region 102 through multiple discharge paths, thereby improving the protection capability of a single transistor and improving the stability of the semiconductor structure.

[0052] It should be noted that, in Figure 8In this example, the number of first protective gates 301 is two, which does not constitute a limitation on the number of first protective gates 301. In one embodiment, the number of first protective gates can be three, six, nine, or fifteen, etc.

[0053] It is understood that in the above embodiments, the connection methods of different numbers of first transistors 200 and different numbers of first protective gates 301 and their corresponding second doped regions 302 can be arbitrarily combined without conflict to obtain new embodiments.

[0054] In some embodiments, reference Figure 9 The semiconductor structure further includes: a second transistor 400, which includes a second gate 401 located on a portion of the substrate 100 of the second well region 102 and third doped regions 402 located on opposite sides of the second gate 401, the third doped regions 402 being located within the second well region 102; a second guard gate 304 located in the first well region 101, and the orthographic projection of the second guard gate 304 onto the surface of the substrate 100 is at least in contact with the orthographic projection of the second well region 102 onto the surface of the substrate 102; and a fourth doped region 303 located on the side of the second guard gate 304 away from the first well region 101 and within the second well region 102, the fourth doped region 303 having the same conductivity type as the third doped region 402 and being electrically insulated from the third doped region 402, wherein the fourth doped region 303 is electrically connected to the second gate 401. In other words, the second well region 102 may contain a second transistor 400. The type of the second transistor 400 is different from that of the first transistor 200. The charge collected by the second gate 401 of the second transistor 400 during the plasma process can be discharged from the fourth doped region 303 into the first well region 101 through the inversion channel layer formed on the surface of the second well region 102 below the second protective gate 304, or released into the second well region 102 through the PN junction formed by the fourth doped region 303 and the second well region 102. The first transistor 200 in the first well region 101 and the second transistor 400 in the second well region 102 are protected by different discharge paths formed by protective gates to improve the stability of the semiconductor structure.

[0055] It should be noted that, in Figure 9For ease of explanation, the second protective gate 304 is located in the second well region 102 where the second transistor 400 is located, and is connected to the first well region 101 where the first transistor 200 is located. This does not constitute a limitation on the positional relationship between the second protective gate 304 and the first well region 101 and the second well region 102 where the second transistor 200 is located. In some embodiments, the second protective gate may also be located in the second well region where the second transistor is located, and connected to another first well region on the side of the second well region away from the first well region where the first transistor is located.

[0056] In some embodiments, the second protective gate may also span the boundary between the first well region and the second well region, that is, the orthographic projection of the second protective gate on the substrate surface intersects with the orthographic projection of the first well region on the substrate surface, and the orthographic projection of the second protective gate on the substrate surface intersects with the orthographic projection of the second well region on the substrate surface.

[0057] In some embodiments, the number of second transistors can be multiple, such as 2, 4, 8, or 16. In some embodiments, the number of second protective gates and their corresponding fourth doped regions can be multiple, such as 2, 4, 8, or 16. It is understood that, referring to the above-described connection methods of different numbers of first transistors and different numbers of first protective gates and their corresponding second doped regions, different numbers of second transistors and different numbers of second protective gates and their corresponding fourth doped regions can have multiple connection methods to obtain new embodiments, thereby facilitating the formation of multiple different discharge paths to protect the second transistors.

[0058] In some embodiments, reference Figure 10When the first protective gate 301 spans the boundary between the first well region 101 and the second well region 102, the semiconductor structure further includes: a second transistor 400, the second transistor 400 including a second gate 401 located on a portion of the substrate 100 of the second well region 102 and third doped regions 402 located on opposite sides of the second gate 401, the third doped regions 402 being located within the second well region 102; and a fourth doped region 303, the fourth doped region 303 being located on the side of the first protective gate 301 away from the second doped region 302 and within the second well region 102, the fourth doped region 303 having the same conductivity type as the third doped region 402 and being electrically insulated from the third doped region 402, wherein the fourth doped region 303 is electrically connected to the second gate 401. In other words, the second well region 102 may contain a second transistor 400. The type of the second transistor 400 is different from that of the first transistor 200. The charge collected by the second gate 401 of the second transistor 400 during the plasma process can be discharged from the fourth doped region 303 to the first well region 101 through the inversion channel layer formed on the surface of the second well region 102 below the first protective gate 301, or through the PN junction formed by the fourth doped region 303 and the second well region 102 to the second well region 102. The second doped region 302 and the fourth doped region 303 are located on opposite sides of the first protective gate 301. The first transistor 200 and the second transistor 400 can share the same first protective gate 301 to form corresponding inversion channel layers to achieve charge discharge, thereby reducing the fabrication steps of the protective gate, improving the semiconductor structure manufacturing efficiency, and simultaneously improving the stability of the semiconductor structure.

[0059] In some embodiments, the number of second transistors can be multiple, such as 2, 4, 8, or 16. Referring to the above-described connection methods of different numbers of first transistors and different numbers of first protective gates and their corresponding second doped regions, different numbers of second transistors can be connected to different numbers of first protective gates and their corresponding fourth doped regions in various ways to obtain new embodiments, thereby facilitating the formation of multiple different discharge paths to protect the second transistors.

[0060] In some embodiments, the semiconductor structure further includes a metal layer comprising a first metal line and a second metal line spaced apart from each other. The first metal line is electrically connected to a first gate, and the second metal line is electrically connected to a first protective gate. The projected area of ​​the second metal line on the substrate surface is larger than that of the first metal line on the substrate surface. The first transistor can be electrically connected to other devices in the semiconductor structure via the first metal line. However, during plasma processing, the first metal line acts as an "antenna" for the first gate, making it easier for the first gate to collect charge. Therefore, by providing a second metal line spaced apart from the first metal line as an "antenna" for the first protective gate, charge can be collected on the first protective gate as well. This facilitates the formation of an inversion channel layer on the surface of the first well region below the first protective gate. The charge collected by the first metal line, which is electrically connected to the first gate, is discharged into the second well region through a second doped region, or through the PN junction formed by the second doped region and the first well region. This prevents the charge collected on the first metal line from causing the gate dielectric layer in the first gate to break down, thereby improving the stability of the semiconductor structure.

[0061] In some embodiments, the material of the metal layer includes at least one of copper, nickel, palladium, gold, silver, tin, titanium, or lead.

[0062] In some embodiments, the semiconductor structure further includes: a first test pad electrically connected to a first gate and a second doped region; a second test pad electrically connected to a first guard gate; a third test pad electrically connected to a first doped region on one side of the first transistor; a fourth test pad electrically connected to a first doped region on the other side of the first transistor; and a fifth test pad electrically connected to a first well region. A test structure is typically provided in the dicing area of ​​the semiconductor structure, with multiple test pads respectively connected to the first gate, the first doped regions on both sides of the first gate, the first guard gate, and the first well region. This facilitates the reflection of the internal electrical performance of the semiconductor structure based on electrical performance tests within the test structure, thereby enabling electrical performance testing of the semiconductor structure.

[0063] In some embodiments, the projected area of ​​the second test pad on the substrate surface is larger than that of the first test pad on the substrate surface. It is understood that the materials of the multiple test pads are typically metallic, and they readily collect charge during plasma processing. When excessive charge is collected on the first gate of the first transistor in the test structure, it can easily lead to the breakdown of the gate dielectric layer in the first gate, thus preventing the test structure from reflecting the internal electrical performance state of the semiconductor structure. When the projected area of ​​the second test pad on the substrate surface is larger than that of the first test pad, the amount of charge collected on the second test pad is greater than that on the first test pad. Consequently, more charge is collected on the first protective gate, which is more conducive to the formation of an inversion channel layer on the surface of the first well region below the first protective gate. This makes it easier for the charge on the first gate to dissipate from the second doped region into the second well region, or through the PN junction formed by the second doped region and the first well region into the first well region.

[0064] In some embodiments, the materials of the first test pad, the second test pad, the third test pad, the fourth test pad, and the fifth test pad all include at least one of copper, nickel, palladium, gold, silver, tin, titanium, or lead.

[0065] In some embodiments, the first protective gate is electrically connected to the substrate. This allows the potential of the first protective gate to be switched to ground without generating PID charge, preventing the charge on the first protective gate from affecting the actual use of the first transistor and improving the stability of the semiconductor structure.

[0066] In some embodiments, the first protective gate is electrically connected to one end of a resistor, and the other end of the resistor is electrically connected to a substrate. In some embodiments, the first protective gate is electrically connected to one end of a diode, and the other end of the diode is electrically connected to the substrate, with the forward direction of the diode pointing towards the substrate. In some embodiments, the first protective gate is electrically connected to the source of a grounded transistor, and the drain of the grounded transistor is electrically connected to the substrate.

[0067] In other words, by placing a resistor, diode, or transistor between the first protective gate and the substrate, the first protective gate can act as a resistor when current flows between the first protective gate and the substrate, and act as a ground potential when no current flows, so as to avoid short circuits between the first protective gate and the substrate and improve the reliability of the semiconductor structure.

[0068] In some embodiments, reference Figures 1 to 5 as well as Figure 10The substrate 100 has multiple isolation structures 500. The first transistor 200 is located between the isolation structures 500 of the first well region 101. The first protection gate 301 and the corresponding second doped region 302 are located between the isolation structures 500 of the first well region 101 and the isolation structures 500 of the second well region 102. The isolation structure 500 within the first well region 101 can separate the first transistor 200 from other devices, preventing leakage between adjacent semiconductor devices. The first protective gate 301 and the corresponding second doped region 302 are located between the isolation structure 500 of the first well region 101 and the isolation structure 500 of the second well region 102. This can separate the devices in the first well region 101 or the devices in the second well region 102 from the second doped region 302 or the first protective gate 301, preventing leakage between the second doped region 302 and the devices in the first well region 101 or the second well region 102, and simultaneously preventing leakage between the first protective gate 301 and the devices in the first well region 101 or the second well region 102, thereby improving the stability of the semiconductor structure.

[0069] In some embodiments, the material of the isolation structure 404 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0070] In some embodiments, the isolation structure may be a single-layer structure. In other embodiments, the isolation structure may be a multi-layer structure, for example, the isolation structure may be a silicon oxide layer-silicon nitride layer-silicon oxide layer (i.e., Oxide-Nitride-Oxide, ONO) structure stacked sequentially. Since the density of the silicon nitride layer is higher than that of the silicon oxide layer, the ONO structure can improve the insulation performance of the isolation structure, thereby helping to improve the stability of the semiconductor structure.

[0071] In the semiconductor structure provided in this embodiment, the first protective gate 301 is located in the first well region 101 and is at least connected to the second well region 102. The second doped region 302 is located in the first well region 101 on the side of the first protective gate 301 away from the second well region 102. The second doped region 302 is electrically connected to the first gate 201 of the first transistor 200. When both the first gate 201 and the first protective gate 301 collect charge due to plasma processing, a large amount of charge accumulates on the first protective gate 301. The charge on the first gate 201 can be discharged from the second doped region 302 to the second well region 102 through the inversion channel layer formed on the surface of the first well region 101 below the first protective gate 301, or through the PN junction formed by the second doped region 302 and the first well region 101 to the first well region 101. This is to avoid excessive charge collected on the first gate 201 causing the gate dielectric layer of the first gate 201 to be broken down, thereby reducing the plasma-induced effect and improving the stability of the semiconductor structure.

[0072] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized by, The application comprises: a substrate comprising adjacent first and second well regions, the first well region having a different type of doping ion than the second well region; a first transistor comprising a first gate on a portion of the substrate in the first well region and first doped regions on opposite sides of the first gate, the first doped regions being in the first well region; a first protection gate in the first well region, a projection of the first protection gate on a surface of the substrate at least meeting a projection of the second well region on the surface of the substrate; a second doped region in the first well region on a side of the first protection gate away from the second well region, the second doped region being of the same conductivity type as the first doped regions and electrically isolated from the first doped regions, a projection of the second doped region on the surface of the substrate intersecting a projection of the first protection gate on the surface of the substrate, wherein the second doped region is electrically connected to the first gate.

2. The semiconductor structure of claim 1, wherein, The first protection gate has a larger area of the projection on the surface of the substrate than the first gate.

3. The semiconductor structure of claim 1, wherein, The number of the first transistors is greater than or equal to two, and the first gate of each of the first transistors is electrically connected to the second doped region.

4. The semiconductor structure of claim 1, wherein, The number of the first transistors is greater than or equal to two, the number of the first protection gates is equal to the number of the first transistors, and each of the first protection gates corresponds to a second doped region, wherein the first gate of each of the first transistors is electrically connected to a second doped region.

5. The semiconductor structure of claim 1, wherein, The number of the first protection gates is greater than or equal to two, and each of the first protection gates corresponds to a second doped region, wherein each of the second doped regions is electrically connected to the first gate.

6. The semiconductor structure of claim 1, wherein, The application further comprises: a second transistor comprising a second gate on a portion of the substrate in the second well region and third doped regions on opposite sides of the second gate, the third doped regions being in the second well region; a second protection gate in the first well region, a projection of the second protection gate on a surface of the substrate at least meeting a projection of the second well region on the surface of the substrate; a fourth doped region in the second well region on a side of the second protection gate away from the first well region, the fourth doped region being of the same conductivity type as the third doped regions and electrically isolated from the third doped regions, a projection of the fourth doped region on the surface of the substrate intersecting a projection of the second protection gate on the surface of the substrate, wherein the fourth doped region is electrically connected to the second gate.

7. The semiconductor structure of claim 1, wherein, The first protection gate spans the junction of the first and second well regions, and the application further comprises: a second transistor comprising a second gate on a portion of the substrate in the second well region and third doped regions on opposite sides of the second gate, the third doped regions being in the second well region; A fourth doped region is located in the second well region, away from the first protection gate on the side of the first protection gate, the fourth doped region is of the same conductivity type as the third doped region and is electrically insulated from the third doped region, and a projection of the fourth doped region on the substrate surface intersects a projection of the first protection gate on the substrate surface, wherein the fourth doped region is electrically connected to the second gate.

8. The semiconductor structure of claim 1, wherein, Further comprising: A metal layer includes a first metal line and a second metal line spaced apart, the first metal line is electrically connected to the first gate, and the second metal line is electrically connected to the first protection gate, wherein the second metal line has a larger projection area on the substrate surface than the first metal line.

9. The semiconductor structure of claim 1, wherein, Further comprising: A first test pad is electrically connected to the first gate and the second doped region; A second test pad is electrically connected to the first protection gate; A third test pad is electrically connected to the first doped region on one side of the first transistor; A fourth test pad is electrically connected to the first doped region on the other side of the first transistor; A fifth test pad is electrically connected to the first well region.

10. The semiconductor structure of claim 9, wherein, The second test pad has a larger projection area on the substrate surface than the first test pad.

11. The semiconductor structure of claim 1, wherein, The first protection gate is electrically connected to the substrate.

12. The semiconductor structure of claim 11, wherein, The first protection gate is electrically connected to one end of a resistor, and the other end of the resistor is electrically connected to the substrate.

13. The semiconductor structure of claim 11, wherein, The first protection gate is electrically connected to one end of a diode, and the other end of the diode is electrically connected to the substrate, and the forward direction of the diode is directed to the substrate.

14. The semiconductor structure of claim 11, wherein, The first protection gate is electrically connected to the source of a ground transistor, and the drain of the ground transistor is electrically connected to the substrate.

15. The semiconductor structure of claim 1, wherein, The substrate has a plurality of isolation structures, the first transistor is located between the isolation structures of the first well region, and the first protection gate and the corresponding second doped region are located between the isolation structures of the first well region and the isolation structures of the second well region.

Images