Semiconductor device and semiconductor memory device

Abstract

The embodiments provide a semiconductor device and a semiconductor memory device capable of reducing on-resistance. The semiconductor device of the embodiments includes: a first electrode; a second electrode; an oxide semiconductor layer disposed between the first electrode and the second electrode; a gate electrode surrounding the oxide semiconductor layer; a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer; a first insulating layer disposed between the first electrode and the gate electrode; and a second insulating layer disposed between the second electrode and the gate electrode. In a cross-section parallel to a first direction from the first electrode toward the second electrode, the direction connecting the first end of the interface between the first electrode and the first insulating layer and the second end of the interface between the second electrode and the second insulating layer is defined as a second direction. In the cross-section, a first portion of the oxide semiconductor layer is disposed between the gate insulating layer and the first electrode in the second direction, and a second portion of the oxide semiconductor layer is disposed between the gate insulating layer and the second electrode in the second direction.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-205699 (filed on December 20, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] Embodiments of the present invention relate to semiconductor devices and semiconductor memory devices. Background Technology

[0003] Oxide-semiconductor transistors (OSTs) with channels formed in an oxide semiconductor layer possess the excellent characteristic of extremely low channel leakage current during off-state operation. To apply OSTs to memory devices, it is desirable to reduce on-state resistance. Summary of the Invention

[0004] The present invention provides a semiconductor device and a semiconductor memory device capable of reducing on-resistance.

[0005] A semiconductor device according to an embodiment includes: a first electrode; a second electrode; an oxide semiconductor layer disposed between the first electrode and the second electrode; a gate electrode surrounding at least a portion of the oxide semiconductor layer; a gate insulating layer disposed at least a portion between the gate electrode and the oxide semiconductor layer; a first insulating layer disposed between the first electrode and the gate electrode; and a second insulating layer disposed between the second electrode and the gate electrode. In a cross-section parallel to a first direction from the first electrode toward the second electrode and including the oxide semiconductor layer, the direction connecting the first end and the second end is defined as a second direction. The first end is the end on the oxide semiconductor layer side of the interface between the first electrode and the first insulating layer, and the second end is the end on the oxide semiconductor layer side of the interface between the second electrode and the second insulating layer. In the cross-section, a first portion of the oxide semiconductor layer is disposed between the gate insulating layer and the first electrode in the second direction, and a second portion of the oxide semiconductor layer is disposed between the gate insulating layer and the second electrode in the second direction. Attached Figure Description

[0006] Figures 1-5 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0007] Figures 6 to 11 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment.

[0008] Figure 12 This is a schematic cross-sectional view of a comparative example semiconductor device.

[0009] Figure 13 This is a schematic cross-sectional view of a semiconductor device of the first variation of the first embodiment.

[0010] Figure 14 This is a schematic cross-sectional view of a semiconductor device in the second variation of the first embodiment.

[0011] Figure 15 This is a schematic cross-sectional view of a semiconductor device in the third variation of the first embodiment.

[0012] Figure 16 This is a schematic cross-sectional view of a semiconductor device in the fourth variation of the first embodiment.

[0013] Figure 17 This is a schematic cross-sectional view of a semiconductor device in the fifth variation of the first embodiment.

[0014] Figure 18 , Figure 19 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0015] Figure 20 This is a schematic cross-sectional view of a semiconductor device, a variation of the second embodiment.

[0016] Figure 21 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0017] Figure 22 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment.

[0018] Figure 23 This is a schematic cross-sectional view of a semiconductor device, a variation of the fourth embodiment.

[0019] Figure 24 This is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment.

[0020] Figure 25 This is a schematic cross-sectional view of a semiconductor device, a variation of the fifth embodiment.

[0021] Figure 26 This is a block diagram of the semiconductor memory device according to the sixth embodiment.

[0022] Figure 27 , Figure 28 This is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the sixth embodiment.

[0023] Figure 29 This is a schematic cross-sectional view of the first memory cell of the semiconductor memory device according to the sixth embodiment.

[0024] Figure 30 This is a schematic cross-sectional view of the second memory cell of the semiconductor memory device according to the sixth embodiment.

[0025] Figures 31-34 This is a schematic cross-sectional view of the semiconductor device according to the seventh embodiment.

[0026] Figure 35 This is a schematic cross-sectional view of a comparative example semiconductor device.

[0027] Figure 36 This is a schematic cross-sectional view of a semiconductor device in the first variation of the seventh embodiment.

[0028] Figure 37 This is a schematic cross-sectional view of a semiconductor device in the second variation of the seventh embodiment.

[0029] Figure 38 This is a schematic cross-sectional view of the semiconductor device of the third variation of the seventh embodiment.

[0030] Figure 39 This is a schematic cross-sectional view of the semiconductor device of the fourth variation of the seventh embodiment.

[0031] Figure 40 This is a schematic cross-sectional view of the semiconductor device of the fifth variation of the seventh embodiment.

[0032] Figures 41-43 This is a schematic cross-sectional view of the semiconductor device according to the eighth embodiment.

[0033] Figure 44 This is a schematic cross-sectional view of a semiconductor device of the first variation of the eighth embodiment.

[0034] Figure 45 This is a schematic cross-sectional view of a semiconductor device in the second variation of the eighth embodiment.

[0035] Figure 46 This is a schematic cross-sectional view of the semiconductor device of the third variation of the eighth embodiment.

[0036] Figure 47 This is a schematic cross-sectional view of the semiconductor device of the fourth variation of the eighth embodiment.

[0037] Figure 48 This is a schematic cross-sectional view of the semiconductor device of the fifth variation of the eighth embodiment.

[0038] Figure 49 This is a schematic cross-sectional view of the first memory cell of the semiconductor memory device according to the ninth embodiment.

[0039] Figure 50 This is a schematic cross-sectional view of the second memory cell of the semiconductor memory device according to the ninth embodiment.

[0040] Label Explanation

[0041] 10. Lower electrode (electrode 1)

[0042] 12. Upper electrode (second electrode)

[0043] 14 Oxide semiconductor layer

[0044] 14a Part 1

[0045] 14b Part 2

[0046] 16 gate electrodes

[0047] 18 Gate insulating layer

[0048] 18a, Region 1

[0049] 18b Region 2

[0050] 18x Level 1

[0051] 18y, second floor

[0052] 18z, 3rd floor

[0053] 20 First interlayer insulation layer (first insulation layer)

[0054] 22 Second interlayer insulation layer (second insulation layer)

[0055] 20 Gate electrode

[0056] 22 Gate insulating layer

[0057] 100 transistors (semiconductor devices)

[0058] 200 Semiconductor memory (semiconductor storage device)

[0059] 201 Capacitor

[0060] 300 transistors (semiconductor devices)

[0061] 400 transistors (semiconductor devices)

[0062] E1 First end

[0063] E2, second end Detailed Implementation

[0064] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be labeled with the same reference numerals, and descriptions of components that have been described once before will be appropriately omitted.

[0065] In addition, the terms "upper" or "lower" are sometimes used in this specification for ease of explanation. "Upper" or "lower" are merely terms indicating relative positional relationships within the accompanying drawings, and are not terms specifying positional relationships relative to gravity.

[0066] Qualitative and quantitative analyses of the chemical composition of the components constituting the semiconductor device and semiconductor memory device described in this specification can be performed, for example, by secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), and Rutherford back-scattering spectroscopy (RBS). Furthermore, measurements of the thickness of the components constituting the semiconductor device and semiconductor memory device, the distance between components, etc., can be performed, for example, by transmission electron microscopy (TEM).

[0067] (First Embodiment)

[0068] The semiconductor device of the first embodiment includes: a first electrode; a second electrode; an oxide semiconductor layer disposed between the first electrode and the second electrode; a gate electrode surrounding at least a portion of the oxide semiconductor layer; a gate insulating layer disposed at least a portion between the gate electrode and the oxide semiconductor layer; a first insulating layer disposed between the first electrode and the gate electrode; and a second insulating layer disposed between the second electrode and the gate electrode. In a cross-section parallel to a first direction from the first electrode toward the second electrode and including the oxide semiconductor layer, the direction connecting the first end and the second end is defined as a second direction. The first end is the end on the oxide semiconductor layer side of the interface between the first electrode and the first insulating layer, and the second end is the end on the oxide semiconductor layer side of the interface between the second electrode and the second insulating layer. In the above cross-section, a first portion of the oxide semiconductor layer is disposed between the gate insulating layer and the first electrode in the second direction, and a second portion of the oxide semiconductor layer is disposed between the gate insulating layer and the second electrode in the second direction.

[0069] Figures 1-5 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 2 This is an explanatory diagram for the first and second directions. Figure 3 yes Figure 1 AA' sectional view. Figure 4 yes Figure 1 BB' sectional view. Figure 5 yes Figure 1 CC' section view.

[0070] The semiconductor device in the first embodiment is a transistor 100. The transistor 100 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor. The gate electrode of the transistor 100 is configured to surround the oxide semiconductor in which the channel is formed. The transistor 100 is a so-called gate-all-around transistor (SGT). The transistor 100 is a so-called vertical transistor.

[0071] The transistor 100 includes a lower electrode 10, an upper electrode 12, an oxide semiconductor layer 14, a gate electrode 16, a gate insulating layer 18, a first interlayer insulating layer 20, and a second interlayer insulating layer 22. The oxide semiconductor layer 14 includes a first portion 14a and a second portion 14b.

[0072] The lower electrode 10 is an example of the first electrode. The upper electrode 12 is an example of the second electrode. The first interlayer insulating layer 20 is an example of the first insulating layer. The second interlayer insulating layer 22 is an example of the second insulating layer.

[0073] like Figure 2 As shown, the direction from the lower electrode 10 toward the upper electrode 12 is defined as the first direction. Furthermore, in a cross-section parallel to the first direction and containing the oxide semiconductor layer 14, the first end ( Figure 2 E1) and the second end ( Figure 2 The direction of E2 in the diagram is defined as the second direction. The first end is the end on the oxide semiconductor layer 14 side of the interface between the lower electrode 10 and the first interlayer insulating layer 20, and the second end is the end on the oxide semiconductor layer 14 side of the interface between the upper electrode 12 and the second interlayer insulating layer 22. Furthermore, in a cross-section parallel to the first direction and containing the oxide semiconductor layer 14, the direction perpendicular to the first direction is defined as the third direction.

[0074] exist Figure 2 In the middle, the second direction is the same as the first direction.

[0075] The lower electrode 10 functions as either the source electrode or the drain electrode of the transistor 100.

[0076] The lower electrode 10 is a conductor. The lower electrode 10 may contain, for example, an oxide conductor or a metal. The lower electrode 10 may be, for example, a metal, a metal nitride, or a metal oxide.

[0077] The lower electrode 10 is, for example, an oxide conductor containing at least one element selected from indium (In), tin (Sn), zinc (Zn), and titanium (Ti) and oxygen (O). The lower electrode 10 is, for example, an oxide conductor containing indium (In), tin (Sn), and oxygen (O). The lower electrode 10 is, for example, indium tin oxide. The lower electrode 10 is, for example, a metal containing tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta).

[0078] The lower electrode 10 may also have a stacked structure of multiple conductors, for example.

[0079] The upper electrode 12 functions as either the source electrode or the drain electrode of the transistor 100.

[0080] The upper electrode 12 is a conductor. The upper electrode 12 may contain, for example, an oxide conductor or a metal. The upper electrode 12 may be, for example, a metal, a metal nitride, or a metal oxide.

[0081] The upper electrode 12 is, for example, an oxide conductor containing at least one element selected from indium (In), tin (Sn), zinc (Zn), and titanium (Ti) and oxygen (O). The upper electrode 12 is, for example, an oxide conductor containing indium (In), tin (Sn), and oxygen (O). The upper electrode 12 is, for example, indium tin oxide. The upper electrode 12 is, for example, a metal containing tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta).

[0082] The upper electrode 12 may also have a stacked structure of multiple conductors, for example.

[0083] For example, the lower electrode 10 and the upper electrode 12 are formed of the same material. For example, the lower electrode 10 and the upper electrode 12 are oxide conductors containing at least one element selected from indium (In), tin (Sn), zinc (Zn), and titanium (Ti) and oxygen (O). For example, the lower electrode 10 and the upper electrode 12 are oxide conductors containing indium (In), tin (Sn), and oxygen (O).

[0084] An oxide semiconductor layer 14 is disposed between the lower electrode 10 and the upper electrode 12. The oxide semiconductor layer 14 is, for example, connected to the lower electrode 10. The oxide semiconductor layer 14 is, for example, connected to the upper electrode 12.

[0085] The oxide semiconductor layer 14 forms a channel that becomes a current path when the transistor 100 is turned on.

[0086] The oxide semiconductor layer 14 is an oxide semiconductor. The oxide semiconductor layer 14 is, for example, amorphous.

[0087] The oxide semiconductor layer 14 contains, for example, at least one element selected from indium (In), gallium (Ga), and aluminum (Al) and zinc (Zn).

[0088] The oxide semiconductor layer 14 contains, for example, oxygen holes. The oxygen holes in the oxide semiconductor layer 14 function as donors.

[0089] The length of the oxide semiconductor layer 14 in the first direction is, for example, 80 nm or more and 200 nm or less. The width of the oxide semiconductor layer 14 in the third direction is, for example, 20 nm or more and 100 nm or less.

[0090] like Figure 3 As shown, the gate electrode 16 is configured to surround the oxide semiconductor layer 14. The gate electrode 16 is disposed around the oxide semiconductor layer 14.

[0091] The gate electrode 16 is, for example, a metal, a metal compound, or a semiconductor. The gate electrode 16 is, for example, tungsten (W). The length of the gate electrode 16 in the second direction is, for example, 20 nm or more and 100 nm or less. The length of the gate electrode 16 in the second direction is the gate length of the transistor 100.

[0092] The gate electrode 16 is, for example, a metal, a metal compound, or a semiconductor. The gate electrode 16 is, for example, tungsten (W).

[0093] A gate insulating layer 18 is disposed between the gate electrode 16 and the oxide semiconductor layer 14. The gate insulating layer 18 is configured to surround the oxide semiconductor layer 14.

[0094] The gate insulating layer 18 is not disposed between the first interlayer insulating layer 20 and the oxide semiconductor layer 14. The gate insulating layer 18 is not disposed between the second interlayer insulating layer 22 and the oxide semiconductor layer 14.

[0095] The gate insulating layer 18 is, for example, plano-convex in a cross-section parallel to the first direction and containing the oxide semiconductor layer 14. The gate insulating layer 18 has a planar surface on the gate electrode 16 side and a convex surface on the oxide semiconductor layer 14 side, for example.

[0096] The gate insulating layer 18 may comprise, for example, an oxide, a nitride, or an oxide oxynitride. The gate insulating layer 18 may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. The gate insulating layer 18 may be, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or an aluminum oxide layer. The thickness of the gate insulating layer 18 in the direction perpendicular to the second direction ( Figure 1 The t1 in the example is 3nm or more and 10nm or less.

[0097] The length of the interface between the gate insulating layer 18 and the first interlayer insulating layer 20 in the second direction ( Figure 1d1 in the figure is, for example, the thickness of the gate insulating layer 18 in the direction perpendicular to the second direction. Figure 1 The length of t1 in the second direction of the interface between the gate insulating layer 18 and the second insulating layer 22 is small. Figure 1 d2) is, for example, the thickness of the gate insulating layer 18 in the direction perpendicular to the second direction. Figure 1 The thickness of the gate insulating layer 18 in the direction perpendicular to the second direction is small (t1). Figure 1 t1 in the figure is, for example, the maximum thickness in the direction perpendicular to the second direction.

[0098] A first portion 14a of the oxide semiconductor layer 14 is disposed in the second direction between the gate insulating layer 18 and the lower electrode 10. The first portion 14a is, for example, connected to the first interlayer insulating layer 20.

[0099] The second portion 14b of the oxide semiconductor layer 14 is disposed in the second direction between the gate insulating layer 18 and the upper electrode 12. The second portion 14b is, for example, connected to the second interlayer insulating layer 22.

[0100] The first interlayer insulating layer 20 is disposed between the lower electrode 10 and the gate electrode 16. The first interlayer insulating layer 20 is disposed around the oxide semiconductor layer 14.

[0101] The first interlayer insulating layer 20 is, for example, an oxide, a nitride, or a oxynitride. The first interlayer insulating layer 20 is, for example, silicon oxide.

[0102] The second interlayer insulating layer 22 is disposed between the upper electrode 12 and the gate electrode 16. The second interlayer insulating layer 22 is disposed around the oxide semiconductor layer 14.

[0103] The second interlayer insulating layer 22 is, for example, an oxide, a nitride, or a oxynitride. The second interlayer insulating layer 22 is, for example, silicon oxide.

[0104] Next, an example of a method for manufacturing a semiconductor device according to the first embodiment will be described.

[0105] Figures 6 to 11 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment. Figures 6 to 11 Is with Figure 1 The corresponding cross section.

[0106] First, these films are formed in the order of the first indium tin oxide film 30, the first silicon oxide film 31, the tungsten film 32, and the second silicon oxide film 33. Figure 6The first indium tin oxide film 30, the first silicon oxide film 31, the tungsten film 32, and the second silicon oxide film 33 are formed, for example, by chemical vapor deposition (CVD).

[0107] Next, an opening 34 is formed from the surface of the second silicon oxide film 33, extending to the first indium tin oxide film 30. Figure 7 The opening 34 is formed, for example, using photolithography and reactive ion etching (RIE).

[0108] Next, a silicon nitride film 35 is selectively formed on the surface of the tungsten film 32 exposed on the inner surface of the opening 34. Figure 8 ).

[0109] Next, the opening 34 is filled with an oxide semiconductor film 36. Figure 9 The oxide semiconductor film 36 contains, for example, indium (In), gallium (Ga), and zinc (Zn). The oxide semiconductor film 36 is formed, for example, by a CVD method.

[0110] Next, the upper part of the oxide semiconductor film 36 is removed, exposing the surface of the second silicon oxide film 33. Figure 10 The oxide semiconductor film 36 is etched and removed, for example, using a re-etching process (RIE).

[0111] Next, a second indium tin oxide film 37 is formed. Figure 11 The second indium tin oxide film 37 is formed, for example, by CVD.

[0112] Through the above manufacturing methods, a Figure 1 The transistor 100 shown.

[0113] Next, the function and effects of the semiconductor device of the first embodiment will be explained.

[0114] Figure 12 This is a schematic cross-sectional view of a comparative example semiconductor device. The comparative example semiconductor device is transistor 900. Transistor 900 is an oxide semiconductor transistor with a channel formed in oxide semiconductor. The gate electrode of transistor 900 is configured to surround the oxide semiconductor forming the channel. Transistor 900 is a so-called SGT. Transistor 900 is a so-called vertical transistor.

[0115] The transistor 900 differs from the transistor 100 of the first embodiment in that, in the second direction, a portion of the oxide semiconductor layer 14 is not disposed between the gate insulating layer 18 and the lower electrode 10. Furthermore, the transistor 900 differs from the transistor 100 in that, in the second direction, a portion of the oxide semiconductor layer 14 is not disposed between the gate insulating layer 18 and the upper electrode 12.

[0116] Transistor 100 has a first portion 14a of oxide semiconductor layer 14 between gate insulating layer 18 and lower electrode 10. Therefore, the contact area between oxide semiconductor layer 14 and lower electrode 10 of transistor 100 is larger than that between oxide semiconductor layer 14 and lower electrode 10 of transistor 900. Consequently, the contact resistance between oxide semiconductor layer 14 and lower electrode 10 of transistor 100 is smaller than that between oxide semiconductor layer 14 and lower electrode 10 of transistor 900.

[0117] Similarly, transistor 100 has a second portion 14b of oxide semiconductor layer 14 between gate insulating layer 18 and upper electrode 12. Therefore, the contact area between oxide semiconductor layer 14 and upper electrode 12 of transistor 100 is larger than that of transistor 900. Consequently, the contact resistance between oxide semiconductor layer 14 and upper electrode 12 of transistor 100 is smaller than that of transistor 900.

[0118] As the contact resistance between the oxide semiconductor layer 14 and the lower electrode 10 and the contact resistance between the oxide semiconductor layer 14 and the upper electrode 12 decrease, the parasitic resistance of the transistor 100 decreases, and the on-resistance decreases.

[0119] For example, consider increasing the contact area between the oxide semiconductor layer 14 and the lower electrode 10 and the contact area between the oxide semiconductor layer 14 and the upper electrode 12 by thinning the gate insulating layer 18 in the transistor 900, thereby reducing the contact resistance between the oxide semiconductor layer 14 and the lower electrode 10 and the contact resistance between the oxide semiconductor layer 14 and the upper electrode 12.

[0120] In this case, due to the thinning of the gate insulating layer 18, oxygen diffusion from the oxide semiconductor layer 14 through the gate insulating layer 18 to the gate electrode 16 is facilitated. When oxygen diffusion and the increase of oxygen holes in the oxide semiconductor layer 14 occur, for example, the threshold voltage of the transistor will decrease, thus becoming a problem.

[0121] In the transistor 100 of the first embodiment, the thickness of the gate insulating layer 18 between the gate electrode 16 and the oxide semiconductor layer 14 is thicker than that of the transistor 900 of the comparative example. Therefore, the decrease in the threshold voltage of the transistor, which accompanies the increase of oxygen holes in the oxide semiconductor layer 14, is not generated.

[0122] Furthermore, in the transistor 100 of the first embodiment, since it has a first portion 14a, the distance between the side of the gate electrode 16 and the oxide semiconductor layer 14 facing the first interlayer insulating layer 20 is closer than that in the transistor 900. Therefore, compared to the transistor 900, the accumulation or reversal of electrons in the oxide semiconductor layer 14 facing the first interlayer insulating layer 20 is promoted by the edge electric field of the gate electrode 16. As a result, the resistance of the oxide semiconductor layer 14 facing the first interlayer insulating layer 20 is lower than that of the transistor 900.

[0123] Similarly, in the transistor 100 of the first embodiment, due to the presence of the second portion 14b, the distance between the side of the gate electrode 16 and the oxide semiconductor layer 14 facing the second interlayer insulating layer 22 is closer than that in the transistor 900. Therefore, compared to the transistor 900, the accumulation or reversal of electrons in the oxide semiconductor layer 14 facing the second interlayer insulating layer 22 is promoted by the edge electric field of the gate electrode 16. Consequently, the resistance of the oxide semiconductor layer 14 facing the second interlayer insulating layer 22 is lower than that of the transistor 900.

[0124] As the resistance of the oxide semiconductor layer 14 opposite to the first interlayer insulating layer 20 and the resistance of the oxide semiconductor layer 14 opposite to the second interlayer insulating layer 22 decrease, the parasitic resistance of the transistor 100 decreases, and the on-resistance decreases.

[0125] In the first embodiment, the parasitic resistance of the transistor 100 is reduced, and the on-resistance is reduced.

[0126] The gate insulating layer 18 is preferably plano-convex in a cross-section parallel to the first direction and containing the oxide semiconductor layer 14. Because the interface between the oxide semiconductor layer 14 and the gate insulating layer 18 is a curved shape without corners, the uniformity of the resistance in the channel region formed in the oxide semiconductor layer 14 increases when the transistor 100 is turned on. Therefore, for example, the deviation in the on-resistance of the transistor 100 is reduced.

[0127] (First variation)

[0128] Figure 13 This is a schematic cross-sectional view of a semiconductor device of the first variation of the first embodiment. Figure 13 It is the same as the first embodiment. Figure 1 The corresponding diagram.

[0129] The difference between the transistor of the first variant of the first embodiment and the transistor 100 of the first embodiment is that the central portion of the interface between the gate insulating layer 18 and the oxide semiconductor layer 14 in a cross section parallel to the first direction and including the oxide semiconductor layer 14 is a straight line shape.

[0130] According to the transistor of the first modification, the area with a certain thickness of gate insulating layer 18 increases, for example, the deviation of the threshold voltage of the transistor decreases.

[0131] (Second variation)

[0132] Figure 14 This is a schematic cross-sectional view of a semiconductor device in the second variation of the first embodiment. Figure 14 It is the same as the first embodiment. Figure 1 The corresponding diagram.

[0133] The difference between the transistor of the second variation of the first embodiment and the transistor 100 of the first embodiment lies in the length of the interface between the gate insulating layer 18 and the first interlayer insulating layer 20 in the second direction. Figure 14 d1) is the thickness of the gate insulating layer 18 in the direction perpendicular to the second direction. Figure 14 The length of t1 in the second direction of the interface between the gate insulating layer 18 and the second interlayer insulating layer 22 is larger. Furthermore, the difference from the transistor 100 of the first embodiment lies in the length of t1 in the second direction of the interface between the gate insulating layer 18 and the second interlayer insulating layer 22. Figure 14 d2) is the thickness of the gate insulating layer 18 in the direction perpendicular to the second direction. Figure 14 The thickness of the gate insulating layer 18 in the direction perpendicular to the second direction is large (t1). Figure 14 t1 in the figure is, for example, the maximum thickness in the direction perpendicular to the second direction.

[0134] According to the transistor of the second variation, for example, the effective gate length is lengthened, which can suppress the short-channel effect of the transistor.

[0135] (3rd variation)

[0136] Figure 15 This is a schematic cross-sectional view of a semiconductor device in the third variation of the first embodiment. Figure 15 It is the same as the first embodiment. Figure 1 The corresponding diagram.

[0137] The difference between the transistor of the third variation of the first embodiment and the transistor 100 of the first embodiment is that the gate insulating layer 18 is rectangular in a cross section parallel to the first direction and containing the oxide semiconductor layer 14.

[0138] According to the transistor of the third modification, the area with a certain thickness of gate insulating layer 18 increases, for example, the deviation of the threshold voltage of the transistor decreases.

[0139] (4th variation)

[0140] Figure 16 This is a schematic cross-sectional view of a semiconductor device in the fourth variation of the first embodiment. Figure 16 It is the same as the first embodiment. Figure 1 The corresponding diagram.

[0141] The transistor in the fourth variation of the first embodiment differs from the transistor 100 of the first embodiment in that the gate electrode 16 is undercut in a cross-section parallel to the first direction and containing the oxide semiconductor layer 14. The length of the gate electrode 16 in the first direction is, for example, shortest at the interface with the gate insulating layer 18. The length of the gate electrode 16 in the first direction decreases, for example, as it approaches the gate insulating layer 18.

[0142] According to the transistor of the fourth modification, by making the gate electrode 16 undercut, the electric field concentration at the end of the gate electrode 16 is mitigated. Therefore, for example, leakage current of the gate insulating layer 18 can be suppressed.

[0143] (5th variation)

[0144] Figure 17 This is a schematic cross-sectional view of a semiconductor device in the fifth variation of the first embodiment. Figure 17 It is the same as the first embodiment. Figure 1 The corresponding diagram.

[0145] The transistor in the fifth variation of the first embodiment differs from the transistor 100 of the first embodiment in that, in a cross-section parallel to the first direction and containing the oxide semiconductor layer 14, the gate electrode 16 has an outwardly extending (skirt) shape. The length of the gate electrode 16 in the first direction is, for example, longest at the interface with the gate insulating layer 18. The length of the gate electrode 16 in the first direction increases, for example, as it approaches the gate insulating layer 18.

[0146] According to the transistor of the fifth modification, by making the gate electrode 16 into an outward-extending shape, the accumulation or reversal of electrons in the oxide semiconductor layer 14 facing the first interlayer insulating layer 20, achieved by the edge electric field of the gate electrode 16, is promoted. Furthermore, the accumulation or reversal of electrons in the oxide semiconductor layer 14 facing the second interlayer insulating layer 22, achieved by the edge electric field of the gate electrode 16, is also promoted. Therefore, for example, the on-resistance of the transistor is further reduced.

[0147] Based on the first embodiment and its variations, a transistor capable of reducing on-resistance can be realized.

[0148] (Second Implementation)

[0149] The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the second direction intersects the first direction. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0150] Figure 18 and Figure 19 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment. Figure 19 This is an explanatory diagram for the first and second directions. Figure 18 It is the same as the first embodiment. Figure 1 The corresponding diagram. Figure 19 It is the same as the first embodiment. Figure 2 The corresponding diagram.

[0151] like Figure 19 As shown, the direction from the lower electrode 10 toward the upper electrode 12 is defined as the first direction. Furthermore, in a cross-section parallel to the first direction and containing the oxide semiconductor layer 14, the first end ( Figure 19 E1) and the second end ( Figure 19 The direction of E2 in the diagram is defined as the second direction. The first end is the end on the oxide semiconductor layer 14 side of the interface between the lower electrode 10 and the first interlayer insulating layer 20, and the second end is the end on the oxide semiconductor layer 14 side of the interface between the upper electrode 12 and the second interlayer insulating layer 22. Furthermore, in a cross-section parallel to the first direction and containing the oxide semiconductor layer 14, the direction perpendicular to the first direction is defined as the third direction.

[0152] exist Figure 19 In the middle, the second direction intersects with the first direction.

[0153] In a cross-section parallel to the first direction and including the oxide semiconductor layer 14, the oxide semiconductor layer 14 has a positive conical shape. In a cross-section parallel to the first direction and including the oxide semiconductor layer 14, the length of the interface between the lower electrode 10 and the oxide semiconductor layer 14 is smaller than the length of the interface between the upper electrode 12 and the oxide semiconductor layer 14.

[0154] (Modified Example)

[0155] Figure 20 This is a schematic cross-sectional view of a semiconductor device, a variation of the second embodiment. Figure 20 It is the same as the second embodiment. Figure 19 The corresponding diagram.

[0156] The transistor in the modified example of the second embodiment differs from the transistor of the second embodiment in that, in a cross-section parallel to the first direction and including the oxide semiconductor layer 14, the oxide semiconductor layer 14 has an inverted conical shape. In the cross-section parallel to the first direction and including the oxide semiconductor layer 14, the length of the interface between the lower electrode 10 and the oxide semiconductor layer 14 is greater than the length of the interface between the upper electrode 12 and the oxide semiconductor layer 14.

[0157] As described above, according to the second embodiment and its variations, a transistor capable of reducing on-resistance can be realized in the same way as the first embodiment.

[0158] (Third Implementation)

[0159] The semiconductor device of the third embodiment differs from the semiconductor device of the first embodiment in that a first region having a gate insulating layer disposed between the first insulating layer and the first portion, and a second region having a gate insulating layer disposed between the second insulating layer and the second portion. Hereinafter, descriptions that are repeated in the first embodiment will sometimes be omitted.

[0160] Figure 21 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment. Figure 21 It is the same as the first embodiment. Figure 1 The corresponding diagram.

[0161] The transistor of the third embodiment includes a lower electrode 10, an upper electrode 12, an oxide semiconductor layer 14, a gate electrode 16, a gate insulating layer 18, a first interlayer insulating layer 20, and a second interlayer insulating layer 22. The oxide semiconductor layer 14 includes a first portion 14a and a second portion 14b. The gate insulating layer 18 includes a first region 18a and a second region 18b.

[0162] The lower electrode 10 is an example of the first electrode. The upper electrode 12 is an example of the second electrode. The first interlayer insulating layer 20 is an example of the first insulating layer. The second interlayer insulating layer 22 is an example of the second insulating layer.

[0163] A first region 18a of the gate insulating layer 18 is disposed between the first interlayer insulating layer 20 and the first portion 14a of the oxide semiconductor layer 14. The thickness of the first region 18a of the gate insulating layer 18 in the direction from the first interlayer insulating layer 20 toward the first portion 14a is (…). Figure 21 t2) is the thickness of the gate insulating layer 18 between the gate electrode 16 and the oxide semiconductor layer 14 in the direction from the gate electrode 16 toward the oxide semiconductor layer 14. Figure 21 The thickness of t1 in the first region 18a of the gate insulating layer 18 in the direction from the first interlayer insulating layer 20 toward the first portion 14a is thin. Figure 21 In this context, t2) represents the thickness of the gate insulating layer 18 between the gate electrode 16 and the oxide semiconductor layer 14 in the direction from the gate electrode 16 toward the oxide semiconductor layer 14. Figure 21 Less than half of t1). Here, the thickness of the gate insulating layer 18 between the gate electrode 16 and the oxide semiconductor layer 14 in the direction from the gate electrode 16 toward the oxide semiconductor layer 14 ( Figure 21 t1 in the figure is, for example, the maximum thickness in the direction from the gate electrode 16 toward the oxide semiconductor layer 14.

[0164] The second region 18b of the gate insulating layer 18 is disposed between the second interlayer insulating layer 22 and the second portion 14b of the oxide semiconductor layer 14. The thickness of the second region 18b of the gate insulating layer 18 in the direction from the second interlayer insulating layer 22 toward the second portion 14b is (…). Figure 21 t3) is the thickness of the gate insulating layer 18 between the gate electrode 16 and the oxide semiconductor layer 14 in the direction from the gate electrode 16 toward the oxide semiconductor layer 14. Figure 21 The thickness of t1 in the middle is thin. For example, the thickness of the second region 18b of the gate insulating layer 18 in the direction from the second interlayer insulating layer 22 toward the second portion 14b is thin. Figure 21 In this context, t3) represents the thickness of the gate insulating layer 18 between the gate electrode 16 and the oxide semiconductor layer 14 in the direction from the gate electrode 16 toward the oxide semiconductor layer 14. Figure 21 Less than half of t1). Here, the thickness of the gate insulating layer 18 between the gate electrode 16 and the oxide semiconductor layer 14 in the direction from the gate electrode 16 toward the oxide semiconductor layer 14 ( Figure 21 t1 in the figure is, for example, the maximum thickness in the direction from the gate electrode 16 toward the oxide semiconductor layer 14.

[0165] According to the third embodiment, similar to the first embodiment, a transistor with reduced on-resistance can be realized.

[0166] (Fourth implementation)

[0167] The semiconductor device of the fourth embodiment differs from that of the semiconductor device of the first embodiment in that the gate insulating layer includes a first layer and a second layer with a different chemical composition than the first layer and disposed between the first layer and the oxide semiconductor layer. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0168] Figure 22 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment. Figure 22 It is the same as the first embodiment. Figure 1 The corresponding diagram.

[0169] The transistor of the fourth embodiment includes a lower electrode 10, an upper electrode 12, an oxide semiconductor layer 14, a gate electrode 16, a gate insulating layer 18, a first interlayer insulating layer 20, and a second interlayer insulating layer 22. The oxide semiconductor layer 14 includes a first portion 14a and a second portion 14b. The gate insulating layer 18 includes a first layer 18x and a second layer 18y.

[0170] The lower electrode 10 is an example of the first electrode. The upper electrode 12 is an example of the second electrode. The first interlayer insulating layer 20 is an example of the first insulating layer. The second interlayer insulating layer 22 is an example of the second insulating layer.

[0171] A gate insulating layer 18 is disposed between the gate electrode 16 and the oxide semiconductor layer 14. The gate insulating layer 18 is not disposed between the first interlayer insulating layer 20 and the oxide semiconductor layer 14. The gate insulating layer 18 is not disposed between the second interlayer insulating layer 22 and the oxide semiconductor layer 14.

[0172] The second layer 18y of the gate insulating layer 18 is disposed between the first layer 18x and the oxide semiconductor layer. The chemical composition of the second layer 18y is different from that of the first layer 18x.

[0173] For example, layer 18x contains silicon (Si) and nitrogen (N), and layer 28y contains silicon (Si) and oxygen (O). For example, layer 18x contains silicon nitride, and layer 28y contains silicon oxide. For example, layer 18x is a silicon nitride layer, and layer 28y is a silicon oxide layer.

[0174] The transistor of the fourth embodiment includes a first layer 18x and a second layer 18y through the gate insulating layer 18, which, for example, can balance ease of manufacture and excellent transistor characteristics.

[0175] (Modified Example)

[0176] Figure 23 This is a schematic cross-sectional view of a semiconductor device, a variation of the fourth embodiment. Figure 23 It is the same as the fourth embodiment. Figure 22 The corresponding diagram.

[0177] The transistor in the variant of the fourth embodiment differs from the transistor in the fourth embodiment in that it includes a third layer disposed between the second layer and the oxide semiconductor layer, and the third layer has a different chemical composition than the second layer. For example, the chemical composition of the third layer differs from that of the first layer.

[0178] For example, layer 18x contains silicon (Si) and nitrogen (N), layer 2 18y contains silicon (Si) and oxygen (O), and layer 3 18z contains aluminum (Al) and oxygen (O). For example, layer 18x contains silicon nitride, layer 2 18y contains silicon oxide, and layer 3 18z contains aluminum oxide. For example, layer 18x is a silicon nitride layer, layer 2 18y is a silicon oxide layer, and layer 3 18z is an aluminum oxide layer.

[0179] The transistor of the modified embodiment 4 includes a first layer 18x, a second layer 18y, and a third layer 18z in the gate insulating layer 18, which, for example, can balance ease of manufacture and excellent transistor characteristics.

[0180] According to the fourth embodiment, similar to the first embodiment, a transistor with reduced on-resistance can be realized.

[0181] (Fifth Embodiment)

[0182] The semiconductor device of the fifth embodiment differs from that of the semiconductor device of the fourth embodiment in that: the first layer is disposed between the gate electrode and the oxide semiconductor layer, and the second layer is disposed between the first insulating layer and the first portion and between the second insulating layer and the second portion. Hereinafter, some descriptions that are repeated in the fourth embodiment will be omitted.

[0183] Figure 24 This is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment. Figure 24 It is the same as the first embodiment. Figure 1 The corresponding diagram.

[0184] The transistor of the fifth embodiment includes a lower electrode 10, an upper electrode 12, an oxide semiconductor layer 14, a gate electrode 16, a gate insulating layer 18, a first interlayer insulating layer 20, and a second interlayer insulating layer 22. The oxide semiconductor layer 14 includes a first portion 14a and a second portion 14b. The gate insulating layer 18 includes a first layer 18x and a second layer 18y.

[0185] The lower electrode 10 is an example of the first electrode. The upper electrode 12 is an example of the second electrode. The first interlayer insulating layer 20 is an example of the first insulating layer. The second interlayer insulating layer 22 is an example of the second insulating layer.

[0186] The first layer 18x of the gate insulating layer 18 is disposed between the gate electrode 16 and the oxide semiconductor layer 14.

[0187] A second layer 18y of the gate insulating layer 18 is disposed between the gate electrode 16 and the oxide semiconductor layer 14. The second layer 18y of the gate insulating layer 18 is disposed between the first layer 18x and the oxide semiconductor layer. Additionally, the second layer 18y is disposed between the first interlayer insulating layer 20 and the first portion 14a of the oxide semiconductor layer 14. Furthermore, the second layer 18y is disposed between the second interlayer insulating layer 22 and the second portion 14b of the oxide semiconductor layer 14. The chemical composition of the second layer 18y is different from that of the first layer 18x.

[0188] For example, layer 18x contains silicon (Si) and nitrogen (N), and layer 28y contains silicon (Si) and oxygen (O). For example, layer 18x contains silicon nitride, and layer 28y contains silicon oxide. For example, layer 18x is a silicon nitride layer, and layer 28y is a silicon oxide layer.

[0189] The transistor of the fifth embodiment includes a first layer 18x and a second layer 18y through the gate insulating layer 18, which, for example, can balance ease of manufacture and excellent transistor characteristics.

[0190] (Modified Example)

[0191] Figure 25 This is a schematic cross-sectional view of a semiconductor device, a variation of the fifth embodiment. Figure 25 It is the same as the fifth embodiment. Figure 24 The corresponding diagram.

[0192] The transistor in the modified example of the fifth embodiment differs from the transistor of the fifth embodiment in that it includes a third layer disposed between the second layer and the oxide semiconductor layer, and the third layer has a different chemical composition than the second layer. For example, the chemical composition of the third layer differs from that of the first layer.

[0193] For example, layer 18x contains silicon (Si) and nitrogen (N), layer 2 18y contains silicon (Si) and oxygen (O), and layer 3 18z contains aluminum (Al) and oxygen (O). For example, layer 18x contains silicon nitride, layer 2 18y contains silicon oxide, and layer 3 18z contains aluminum oxide. For example, layer 18x is a silicon nitride layer, layer 2 18y is a silicon oxide layer, and layer 3 18z is an aluminum oxide layer.

[0194] The transistor in the modified embodiment of the fifth embodiment includes a first layer 18x, a second layer 18y, and a third layer 18z through a gate insulating layer 18, which can, for example, balance ease of manufacture and excellent transistor characteristics.

[0195] According to the fifth embodiment, similarly to the first embodiment, a transistor with reduced on-resistance can be realized.

[0196] (Sixth Embodiment)

[0197] The semiconductor memory device of the sixth embodiment includes a capacitor electrically connected to either the first electrode or the second electrode of the semiconductor device of the first embodiment. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0198] The semiconductor memory device of the sixth embodiment is a semiconductor memory 200. The semiconductor memory device of the sixth embodiment is a dynamic random access memory (DRAM). The semiconductor memory 200 uses the transistor 100 of the first embodiment as the switching transistor of the memory cell of the DRAM.

[0199] Figure 26 This is a block diagram of the semiconductor memory device according to the sixth embodiment.

[0200] like Figure 26 As shown, the semiconductor memory 200 includes a memory cell array 210, a word line driver circuit 212, a row decoder circuit 214, a sense amplifier circuit 215, a column decoder circuit 217, and a control circuit 221.

[0201] Figure 27 and Figure 28 This is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the sixth embodiment. Figure 27 It is a cross-sectional view including the planes in the first and third directions. Figure 28 This is a cross-sectional view including the second and third directions. The first and second directions intersect. The first and second directions are, for example, perpendicular. The third direction is perpendicular to both the first and second directions. The third direction is, for example, perpendicular to the substrate.

[0202] The memory cell array 210 of the sixth embodiment has a three-dimensional structure in which memory cells are arranged in a three-dimensional manner. Figure 27 and Figure 28 The areas enclosed by dashed lines represent one storage unit each.

[0203] The memory cell array 210 includes a silicon substrate 250.

[0204] The memory cell array 210 has, for example, multiple bit lines BL and multiple word lines WL on the silicon substrate 250. The bit lines BL extend in a first direction. The word lines WL extend in a second direction.

[0205] Bit line BL and word line WL intersect, for example, perpendicularly. Memory cells are configured in the region where bit line BL intersects word line WL. The memory cells include a first memory cell MC1 and a second memory cell MC2.

[0206] The bit line BL connected to the first memory cell MC1 and the second memory cell MC2 is called bit line BLx. The word line WL connected to the first memory cell MC1 is called word line WLx.

[0207] The word line WL connected to the second memory cell MC2 is called word line WLy. Word line WLx is located on one side of bit line BLx. Word line WLy is located on the other side of bit line BLx.

[0208] The memory cell array 210 has multiple plate electrode lines PL. The plate electrode lines PL are connected to the plate electrodes 72 of each memory cell.

[0209] The memory cell array 210 has an interlayer insulating layer 260 for electrical separation of each wiring and each electrode.

[0210] Multiple word lines WL are electrically connected to the row decoder circuit 214. Multiple bit lines BL are electrically connected to the sense amplifier circuit 215.

[0211] The row decoder circuit 214 has the function of selecting word lines WL according to the input row address signal. The word line driver circuit 212 has the function of applying a predetermined voltage to the word lines WL selected by the row decoder circuit 214.

[0212] The column decoder circuit 217 has the function of selecting the bit line BL according to the input column address signal. The sense amplifier circuit 215 has the function of applying a predetermined voltage to the bit line BL selected by the column decoder circuit 217. In addition, it has the function of detecting the potential of the bit line BL and amplifying it.

[0213] The control circuit 221 has the function of controlling the word line driver circuit 212, the row decoder circuit 214, the sense amplifier circuit 215, the column decoder circuit 217, and other circuits not shown.

[0214] The word line driver circuit 212, row decoder circuit 214, sense amplifier circuit 215, column decoder circuit 217, control circuit 221, and other circuits are composed, for example, of transistors and wiring layers (not shown). The transistors are formed, for example, using a silicon substrate 250.

[0215] Bit lines BL and word lines WL are, for example, metals. Bit lines BL and word lines WL are, for example, titanium nitride, tungsten, or a stacked structure of titanium nitride and tungsten.

[0216] Figure 29 This is a schematic cross-sectional view of the first memory cell of the semiconductor memory device according to the sixth embodiment. Figure 30 This is a schematic cross-sectional view of the second memory cell of the semiconductor memory device according to the sixth embodiment.

[0217] The first memory cell MC1 is disposed between the silicon substrate 250 and the bit line BLx. The bit line BLx is disposed between the silicon substrate 250 and the second memory cell MC2.

[0218] The first memory cell MC1 is located below the bit line BLx. The second memory cell MC2 is located above the bit line BLx.

[0219] The first memory cell MC1 is located on one side of bit line BLx. The second memory cell MC2 is located on the other side of bit line BLx.

[0220] The second storage cell MC2 has a structure that flips the first storage cell MC1 upside down.

[0221] The first storage unit MC1 and the second storage unit MC2 each have a transistor 100 and a capacitor 201.

[0222] The transistor 100 includes a lower electrode 10, an upper electrode 12, an oxide semiconductor layer 14, a gate electrode 16, a gate insulating layer 18, a first interlayer insulating layer 20, and a second interlayer insulating layer 22. The first interlayer insulating layer 20 and the second interlayer insulating layer 22 are part of the interlayer insulating layer 260.

[0223] The lower electrode 10 is an example of the first electrode. The upper electrode 12 is an example of the second electrode. The first interlayer insulating layer 20 is an example of the first insulating layer. The second interlayer insulating layer 22 is an example of the second insulating layer.

[0224] The transistor 100 has the same structure as the transistor 100 in the first embodiment. The capacitor 201 includes a unit electrode 71, a plate electrode 72, and a capacitor insulating film 73. The unit electrode 71 and the plate electrode 72 are, for example, titanium nitride. In addition, the capacitor insulating film 73 has, for example, a stacked structure of zirconium oxide, aluminum oxide, and zirconium oxide.

[0225] The unit electrode 71 of capacitor 201 is connected to the lower electrode 10, for example. The plate electrode 72 is connected to the plate electrode line PL.

[0226] The upper electrode 12 is connected to the bit line BL. The gate electrode 16 is connected to the word line WL.

[0227] In addition, Figure 27 , Figure 28 , Figure 29 as well as Figure 30 In this example, the bit line BL, the upper electrode 12, the word line WL, and the gate electrode 16 are all formed from the same material. However, the bit line BL, the upper electrode 12, the word line WL, and the gate electrode 16 can also be formed from different materials.

[0228] The gate electrode 16 of the first memory cell MC1 is electrically connected to the word line WLx. Additionally, the gate electrode 16 of the second memory cell MC2 is electrically connected to the word line WLy.

[0229] According to the sixth embodiment, by using the transistor 100 of the first embodiment as a switching transistor for DRAM, a semiconductor memory with improved memory characteristics is realized.

[0230] (Seventh Embodiment)

[0231] The semiconductor device of the seventh embodiment includes a first electrode, a second electrode, an oxide semiconductor layer disposed between the first electrode and the second electrode, a gate electrode surrounding at least a portion of the oxide semiconductor layer, and a gate insulating layer disposed at least a portion between the gate electrode and the oxide semiconductor layer. In a cross-section perpendicular to a first direction from the first electrode toward the second electrode, the first electrode surrounds the oxide semiconductor layer, and the second electrode surrounds the oxide semiconductor layer.

[0232] Figures 31-34 This is a schematic cross-sectional view of the semiconductor device according to the seventh embodiment. Figure 32 yes Figure 31 DD' sectional view. Figure 33 yes Figure 31 EE' sectional view. Figure 34 yes Figure 31 FF' section view.

[0233] The semiconductor device in the seventh embodiment is a transistor 300. The transistor 300 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor. The gate electrode of the transistor 300 is configured to surround the oxide semiconductor in which the channel is formed. The transistor 300 is a so-called SGT (Structured Ground Tunnel). The transistor 300 is a so-called vertical transistor.

[0234] The transistor 300 includes a lower electrode 10, an upper electrode 12, an oxide semiconductor layer 14, a gate electrode 16, a gate insulating layer 18, a first interlayer insulating layer 20, and a second interlayer insulating layer 22. The lower electrode 10 is an example of the first electrode. The upper electrode 12 is an example of the second electrode.

[0235] like Figure 31 As shown, the direction from the lower electrode 10 toward the upper electrode 12 is defined as the first direction.

[0236] The lower electrode 10 functions as either the source or drain electrode of the transistor 300.

[0237] The lower electrode 10 is a conductor. The lower electrode 10 may contain, for example, an oxide conductor or a metal. The lower electrode 10 may be, for example, a metal, a metal nitride, or a metal oxide.

[0238] The lower electrode 10 is, for example, an oxide conductor containing at least one element selected from indium (In), tin (Sn), zinc (Zn), and titanium (Ti) and oxygen (O). The lower electrode 10 is, for example, an oxide conductor containing indium (In), tin (Sn), and oxygen (O). The lower electrode 10 is, for example, indium tin oxide. The lower electrode 10 is, for example, a metal containing tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta).

[0239] The lower electrode 10 may also have a stacked structure of multiple conductors, for example.

[0240] The upper electrode 12 functions as either the source electrode or the drain electrode of the transistor 300.

[0241] The upper electrode 12 is a conductor. The upper electrode 12 may contain, for example, an oxide conductor or a metal. The upper electrode 12 may be, for example, a metal, a metal nitride, or a metal oxide.

[0242] The upper electrode 12 is, for example, an oxide conductor containing at least one element selected from indium (In), tin (Sn), zinc (Zn), and titanium (Ti) and oxygen (O). The upper electrode 12 is, for example, an oxide conductor containing indium (In), tin (Sn), and oxygen (O). The upper electrode 12 is, for example, indium tin oxide. The upper electrode 12 is, for example, a metal containing tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta).

[0243] The upper electrode 12 may also have a stacked structure of multiple conductors, for example.

[0244] For example, the lower electrode 10 and the upper electrode 12 are formed of the same material. For example, the lower electrode 10 and the upper electrode 12 are oxide conductors containing at least one element selected from indium (In), tin (Sn), zinc (Zn), and titanium (Ti) and oxygen (O). For example, the lower electrode 10 and the upper electrode 12 are oxide conductors containing indium (In), tin (Sn), and oxygen (O).

[0245] An oxide semiconductor layer 14 is disposed between the lower electrode 10 and the upper electrode 12. The oxide semiconductor layer 14 is, for example, connected to the lower electrode 10. The oxide semiconductor layer 14 is, for example, connected to the upper electrode 12.

[0246] A channel is formed in the oxide semiconductor layer 14, which becomes a current path when the transistor 300 is turned on.

[0247] The oxide semiconductor layer 14 is an oxide semiconductor. The oxide semiconductor layer 14 is, for example, amorphous.

[0248] The oxide semiconductor layer 14 contains, for example, at least one element selected from indium (In), gallium (Ga), and aluminum (Al) and zinc (Zn).

[0249] The oxide semiconductor layer 14 contains, for example, oxygen holes. The oxygen holes in the oxide semiconductor layer 14 function as donors.

[0250] The length of the oxide semiconductor layer 14 in the first direction is, for example, 80 nm or more and 200 nm or less. The width of the oxide semiconductor layer 14 in the direction perpendicular to the first direction is, for example, 20 nm or more and 100 nm or less.

[0251] like Figure 32 As shown, the gate electrode 16 is configured to surround the oxide semiconductor layer 14. The gate electrode 16 is disposed around the oxide semiconductor layer 14.

[0252] The gate electrode 16 is, for example, a metal, a metal compound, or a semiconductor. The gate electrode 16 is, for example, tungsten (W). The length of the gate electrode 16 in the first direction is, for example, 20 nm or more and 100 nm or less. The length of the gate electrode 16 in the first direction is the gate length of the transistor 300.

[0253] The gate electrode 16 is, for example, a metal, a metal compound, or a semiconductor. The gate electrode 16 is, for example, tungsten (W).

[0254] A gate insulating layer 18 is disposed between the gate electrode 16 and the oxide semiconductor layer 14. The gate insulating layer 18 is configured to surround the oxide semiconductor layer 14.

[0255] The gate insulating layer 18 may comprise, for example, an oxide, a nitride, or an oxide oxynitride. The gate insulating layer 18 may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. The gate insulating layer 18 may be, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or an aluminum oxide layer. The thickness of the gate insulating layer 18 may be, for example, 3 nm or more and 10 nm or less.

[0256] The first interlayer insulating layer 20 is disposed between the lower electrode 10 and the gate electrode 16. The first interlayer insulating layer 20 is disposed around the oxide semiconductor layer 14.

[0257] The first interlayer insulating layer 20 is, for example, an oxide, a nitride, or a oxynitride. The first interlayer insulating layer 20 is, for example, silicon oxide.

[0258] The second interlayer insulating layer 22 is disposed between the upper electrode 12 and the gate electrode 16. The second interlayer insulating layer 22 is disposed around the oxide semiconductor layer 14.

[0259] The second interlayer insulating layer 22 is, for example, an oxide, a nitride, or a oxynitride. The second interlayer insulating layer 22 is, for example, silicon oxide.

[0260] like Figure 33 As shown, in a cross-section perpendicular to the first direction from the lower electrode 10 to the upper electrode 12, the lower electrode 10 surrounds the oxide semiconductor layer 14. Furthermore, as... Figure 34 As shown, in a cross-section perpendicular to the first direction, the upper electrode 12 surrounds the oxide semiconductor layer 14.

[0261] Next, the function and effects of the semiconductor device in the seventh embodiment will be explained.

[0262] Figure 35 This is a schematic cross-sectional view of a comparative example semiconductor device. The comparative example semiconductor device is transistor 900. Transistor 900 is an oxide semiconductor transistor with a channel formed in oxide semiconductor. The gate electrode of transistor 900 is configured to surround the oxide semiconductor forming the channel. Transistor 900 is a so-called SGT. Transistor 900 is a so-called vertical transistor.

[0263] The difference between transistor 900 and transistor 300 in the seventh embodiment is that, in a cross section perpendicular to the first direction from the lower electrode 10 toward the upper electrode 12, the lower electrode 10 does not surround the oxide semiconductor layer 14, and the upper electrode 12 does not surround the oxide semiconductor layer 14.

[0264] The lower electrode 10 of transistor 300 surrounds the oxide semiconductor layer 14. Therefore, the contact area between the oxide semiconductor layer 14 and the lower electrode 10 of transistor 300 is larger than that between the oxide semiconductor layer 14 and the lower electrode 10 of transistor 900. Consequently, the contact resistance between the oxide semiconductor layer 14 and the lower electrode 10 of transistor 300 is smaller than that between the oxide semiconductor layer 14 and the lower electrode 10 of transistor 900.

[0265] Similarly, the upper electrode 12 of transistor 300 surrounds the oxide semiconductor layer 14. Therefore, the contact area between the oxide semiconductor layer 14 of transistor 300 and the upper electrode 12 is larger than that between the oxide semiconductor layer 14 of transistor 900 and the upper electrode 12. Therefore, the contact resistance between the oxide semiconductor layer 14 of transistor 300 and the upper electrode 12 is smaller than that between the oxide semiconductor layer 14 of transistor 900 and the upper electrode 12.

[0266] As the contact resistance between the oxide semiconductor layer 14 and the lower electrode 10 and the contact resistance between the oxide semiconductor layer 14 and the upper electrode 12 decrease, the parasitic resistance of the transistor 300 decreases, and the on-resistance decreases.

[0267] In the above, the parasitic resistance and on-resistance of the transistor 300 in the seventh embodiment are reduced.

[0268] From the viewpoint of improving the symmetry of transistor characteristics, it is preferable that the lower electrode 10 and the upper electrode 12 are formed of the same material.

[0269] (First variation)

[0270] Figure 36 This is a schematic cross-sectional view of a semiconductor device in the first variation of the seventh embodiment. Figure 36 It is the same as the 7th embodiment. Figure 31 The corresponding diagram.

[0271] The difference between the transistor of the first variant of the seventh embodiment and the transistor 300 of the seventh embodiment is that, in a cross section perpendicular to the first direction from the lower electrode 10 toward the upper electrode 12, the upper electrode 12 does not surround the oxide semiconductor layer 14.

[0272] (Second variation)

[0273] Figure 37 This is a schematic cross-sectional view of a semiconductor device in the second variation of the seventh embodiment. Figure 37 It is the same as the 7th embodiment. Figure 31 The corresponding diagram.

[0274] The difference between the transistor of the second variation of the seventh embodiment and the transistor 300 of the seventh embodiment is that, in a cross section perpendicular to the first direction from the lower electrode 10 toward the upper electrode 12, the lower electrode 10 does not surround the oxide semiconductor layer 14.

[0275] (3rd variation)

[0276] Figure 38 This is a schematic cross-sectional view of the semiconductor device of the third variation of the seventh embodiment. Figure 38 It is the same as the 7th embodiment. Figure 31 The corresponding diagram.

[0277] The difference between the transistor of the third variation of the seventh embodiment and the transistor 300 of the seventh embodiment is that the interface between the lower electrode 10 and the oxide semiconductor layer 14 and the interface between the upper electrode 12 and the oxide semiconductor layer 14 are curved surfaces.

[0278] (4th variation)

[0279] Figure 39 This is a schematic cross-sectional view of the semiconductor device of the fourth variation of the seventh embodiment. Figure 39 It is the same as the 7th embodiment. Figure 31 The corresponding diagram.

[0280] The transistor of the fourth variation of the seventh embodiment differs from the transistor of the third variation of the seventh embodiment in that, in a cross-section perpendicular to the first direction from the lower electrode 10 toward the upper electrode 12, the upper electrode 12 does not surround the oxide semiconductor layer 14.

[0281] (5th variation)

[0282] Figure 40 This is a schematic cross-sectional view of the semiconductor device of the fifth variation of the seventh embodiment. Figure 40 It is the same as the 7th embodiment. Figure 31 The corresponding diagram.

[0283] The transistor of the fifth variation of the seventh embodiment differs from the transistor of the third variation of the seventh embodiment in that, in a cross-section perpendicular to the first direction from the lower electrode 10 toward the upper electrode 12, the lower electrode 10 does not surround the oxide semiconductor layer 14.

[0284] According to the seventh embodiment and its variations, a transistor that can reduce on-resistance can be realized.

[0285] (Eighth Embodiment)

[0286] The semiconductor device of the eighth embodiment differs from that of the semiconductor device of the seventh embodiment in that the oxide semiconductor layer surrounds the first electrode, and the oxide semiconductor layer surrounds the second electrode. Hereinafter, some descriptions that are repeated in the seventh embodiment will be omitted.

[0287] Figures 41-43 This is a schematic cross-sectional view of the semiconductor device according to the eighth embodiment. Figure 42 yes Figure 41 GG' sectional view. Figure 43 yes Figure 41 HH' sectional view.

[0288] The semiconductor device in the eighth embodiment is a transistor 400. The transistor 400 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor. The gate electrode of the transistor 400 is configured to surround the oxide semiconductor in which the channel is formed. The transistor 400 is a so-called SGT (Structured Ground Tunnel). The transistor 400 is a so-called vertical transistor.

[0289] Transistor 400 includes a lower electrode 10, an upper electrode 12, an oxide semiconductor layer 14, a gate electrode 16, a gate insulating layer 18, a first interlayer insulating layer 20, and a second interlayer insulating layer 22. The lower electrode 10 is an example of the first electrode. The upper electrode 12 is an example of the second electrode.

[0290] like Figure 41As shown, the direction from the lower electrode 10 toward the upper electrode 12 is defined as the first direction.

[0291] like Figure 42 As shown, in a cross-section perpendicular to the first direction from the lower electrode 10 toward the upper electrode 12, the oxide semiconductor layer 14 surrounds the lower electrode 10. Furthermore, as... Figure 43 As shown, in a cross-section perpendicular to the first direction, the oxide semiconductor layer 14 surrounds the upper electrode 12.

[0292] Next, the function and effects of the semiconductor device in the eighth embodiment will be explained.

[0293] The seventh embodiment Figure 35 The transistor 900 shown is used as a comparative example.

[0294] The difference between transistor 900 and transistor 400 in the eighth embodiment is that, in a cross section perpendicular to the first direction from the lower electrode 10 toward the upper electrode 12, the oxide semiconductor layer 14 does not surround the lower electrode 10 and the upper electrode 12.

[0295] The oxide semiconductor layer 14 of transistor 400 surrounds the lower electrode 10. Therefore, the contact area between the oxide semiconductor layer 14 of transistor 400 and the lower electrode 10 is larger than that between the oxide semiconductor layer 14 of transistor 900 and the lower electrode 10. Therefore, the contact resistance between the oxide semiconductor layer 14 of transistor 400 and the lower electrode 10 is smaller than that between the oxide semiconductor layer 14 of transistor 900 and the lower electrode 10.

[0296] Similarly, the oxide semiconductor layer 14 of transistor 400 surrounds the upper electrode 12. Therefore, the contact area between the oxide semiconductor layer 14 of transistor 400 and the upper electrode 12 is larger than that between the oxide semiconductor layer 14 of transistor 900 and the upper electrode 12. Therefore, the contact resistance between the oxide semiconductor layer 14 of transistor 400 and the upper electrode 12 is smaller than that between the oxide semiconductor layer 14 of transistor 900 and the upper electrode 12.

[0297] As the contact resistance between the oxide semiconductor layer 14 and the lower electrode 10 and the contact resistance between the oxide semiconductor layer 14 and the upper electrode 12 decrease, the parasitic resistance of the transistor 400 decreases, and the on-resistance decreases.

[0298] In the above, the parasitic resistance of the transistor 400 in the eighth embodiment is reduced, and the on-resistance is reduced.

[0299] From the viewpoint of improving the symmetry of transistor characteristics, it is preferable that the lower electrode 10 and the upper electrode 12 are formed of the same material.

[0300] (First variation)

[0301] Figure 44 This is a schematic cross-sectional view of a semiconductor device of the first variation of the eighth embodiment. Figure 44 It is the same as the 8th embodiment. Figure 41 The corresponding diagram.

[0302] The difference between the transistor of the first variant of the eighth embodiment and the transistor 400 of the eighth embodiment is that the oxide semiconductor layer 14 does not surround the upper electrode 12 in a cross section perpendicular to the first direction from the lower electrode 10 toward the upper electrode 12.

[0303] (Second variation)

[0304] Figure 45 This is a schematic cross-sectional view of a semiconductor device in the second variation of the eighth embodiment. Figure 45 It is the same as the 8th embodiment. Figure 41 The corresponding diagram.

[0305] The difference between the transistor of the second variation of the eighth embodiment and the transistor 400 of the eighth embodiment is that the oxide semiconductor layer 14 does not surround the lower electrode 10 in a cross section perpendicular to the first direction from the lower electrode 10 toward the upper electrode 12.

[0306] (3rd variation)

[0307] Figure 46 This is a schematic cross-sectional view of the semiconductor device of the third variation of the eighth embodiment. Figure 46 It is the same as the 8th embodiment. Figure 41 The corresponding diagram.

[0308] The difference between the transistor of the third variation of the eighth embodiment and the transistor 400 of the eighth embodiment is that the interface between the lower electrode 10 and the oxide semiconductor layer 14 and the interface between the upper electrode 12 and the oxide semiconductor layer 14 are curved surfaces.

[0309] (4th variation)

[0310] Figure 47 This is a schematic cross-sectional view of the semiconductor device of the fourth variation of the eighth embodiment. Figure 47 It is the same as the 8th embodiment. Figure 41 The corresponding diagram.

[0311] The transistor of the fourth variation of the eighth embodiment differs from the transistor of the third variation of the eighth embodiment in that the oxide semiconductor layer 14 does not surround the upper electrode 12 in a cross section perpendicular to the first direction from the lower electrode 10 toward the upper electrode 12.

[0312] (5th variation)

[0313] Figure 48 This is a schematic cross-sectional view of the semiconductor device of the fifth variation of the eighth embodiment. Figure 48 It is the same as the 8th embodiment. Figure 41 The corresponding diagram.

[0314] The transistor of the fifth variation of the eighth embodiment differs from the transistor of the third variation of the eighth embodiment in that the oxide semiconductor layer 14 does not surround the lower electrode 10 in a cross section perpendicular to the first direction from the lower electrode 10 toward the upper electrode 12.

[0315] According to the eighth embodiment and its variations, a transistor that can reduce on-resistance can be realized.

[0316] (9th embodiment)

[0317] The semiconductor memory device of the ninth embodiment differs from that of the semiconductor memory device of the sixth embodiment in that it includes a capacitor electrically connected to either the first or second electrode of the semiconductor device of the seventh embodiment. Hereinafter, descriptions that are repeated in the sixth and seventh embodiments will sometimes be omitted.

[0318] Figure 49 This is a schematic cross-sectional view of the first memory cell of the semiconductor memory device according to the ninth embodiment. Figure 50 This is a schematic cross-sectional view of the second memory cell of the semiconductor memory device according to the ninth embodiment.

[0319] The second memory cell MC2 has a structure that flips the first memory cell MC1 upside down. The first memory cell MC1 and the second memory cell MC2 each have a transistor 300 and a capacitor 201.

[0320] The transistor 300 includes a lower electrode 10, an upper electrode 12, an oxide semiconductor layer 14, a gate electrode 16, a gate insulating layer 18, a first interlayer insulating layer 20, and a second interlayer insulating layer 22.

[0321] The lower electrode 10 is an example of the first electrode. The upper electrode 12 is an example of the second electrode. The first interlayer insulating layer 20 is an example of the first insulating layer. The second interlayer insulating layer 22 is an example of the second insulating layer.

[0322] The transistor 300 has the same structure as the transistor 300 in the seventh embodiment. The capacitor 201 includes a unit electrode 71, a plate electrode 72, and a capacitor insulating film 73.

[0323] The unit electrode 71 of capacitor 201 is connected to the lower electrode 10, for example. The plate electrode 72 is connected to the plate electrode line PL.

[0324] The upper electrode 12 is connected to the bit line BL. The gate electrode 16 is connected to the word line WL.

[0325] According to the ninth embodiment, by using the transistor 300 of the seventh embodiment as a switching transistor for DRAM, a semiconductor memory with improved memory characteristics is realized.

[0326] In the semiconductor memory device of the sixth embodiment, the case in which the transistor 100 of the first embodiment is used as a switching transistor of DRAM is described as an example. However, the transistor of the modified example of the first embodiment, the transistor of the second embodiment or the modified example, the transistor of the third embodiment, the transistor of the fourth embodiment or the modified example, or the transistor of the fifth embodiment or the modified example may be used instead of the transistor 100 of the first embodiment.

[0327] In the semiconductor device of the 7th embodiment or the semiconductor device of the 8th embodiment, the oxide semiconductor layer 14 may also be configured to have a positive cone shape or an inverted cone shape.

[0328] In the semiconductor memory device of the ninth embodiment, the case in which the transistor 300 of the seventh embodiment is used as a switching transistor for DRAM is described as an example. However, the transistor of the modified example of the seventh embodiment, the transistor of the eighth embodiment, or the modified example of the seventh embodiment may also be used instead of the transistor 300 of the seventh embodiment.

[0329] In the semiconductor devices of embodiments 1 to 5, 7 or 8, a structure having a core insulating layer surrounded by an oxide semiconductor layer 14 may also be provided.

[0330] The foregoing has described several embodiments of the present invention, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment can be substituted or modified to be constituent elements of other embodiments. These embodiments and / or their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device comprising: Electrode 1; Second electrode; An oxide semiconductor layer is disposed between the first electrode and the second electrode; A gate electrode that surrounds at least a portion of the oxide semiconductor layer; A gate insulating layer, at least a portion of which is disposed between the gate electrode and the oxide semiconductor layer; A first insulating layer is disposed between the first electrode and the gate electrode; as well as A second insulating layer is disposed between the second electrode and the gate electrode. In a cross-section parallel to a first direction from the first electrode toward the second electrode and including the oxide semiconductor layer, the direction connecting the first end and the second end is defined as the second direction, where the first end is the end on the oxide semiconductor layer side of the interface between the first electrode and the first insulating layer, and the second end is the end on the oxide semiconductor layer side of the interface between the second electrode and the second insulating layer. In the cross-section, a first portion of the oxide semiconductor layer is disposed in the second direction between the gate insulating layer and the first electrode. In the cross-section, the second portion of the oxide semiconductor layer is disposed between the gate insulating layer and the second electrode in the second direction. A first region of the gate insulating layer is disposed between the first insulating layer and the first portion, and a second region of the gate insulating layer is disposed between the second insulating layer and the second portion.

2. The semiconductor device according to claim 1, In the cross-section, the gate insulating layer has a shape that is planar on the gate electrode side and convex on the oxide semiconductor layer side.

3. The semiconductor device according to claim 1, The first part is in contact with the first insulating layer, and the second part is in contact with the second insulating layer.

4. The semiconductor device according to claim 1, The thickness of the first region of the gate insulating layer in the direction from the first insulating layer toward the first portion is less than half the thickness of the gate insulating layer between the gate electrode and the oxide semiconductor layer in the direction from the gate electrode toward the oxide semiconductor layer. The thickness of the second region of the gate insulating layer in the direction from the second insulating layer toward the second portion is less than half the thickness of the gate insulating layer between the gate electrode and the oxide semiconductor layer in the direction from the gate electrode toward the oxide semiconductor layer.

5. The semiconductor device according to claim 1, The gate insulating layer includes a first layer and a second layer, wherein the second layer is disposed between the first layer and the oxide semiconductor layer, and has a different chemical composition than the first layer.

6. The semiconductor device according to claim 5, The first layer is disposed between the gate electrode and the oxide semiconductor layer. The second layer is disposed between the gate electrode and the oxide semiconductor layer, between the first insulating layer and the first portion, and between the second insulating layer and the second portion.

7. The semiconductor device according to claim 5, The first layer contains silicon (Si) and nitrogen (N), and the second layer contains silicon (Si) and oxygen (O).

8. The semiconductor device according to claim 1, The second direction intersects with the first direction.

9. The semiconductor device according to claim 1, The oxide semiconductor layer contains at least one element selected from indium (In), gallium (Ga), and aluminum (Al) and zinc (Zn).

10. A semiconductor memory device comprising: The semiconductor device according to claim 1; and A capacitor electrically connected to either the first electrode or the second electrode.

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