A semiconductor device and its fabrication method

Abstract

This invention discloses a semiconductor device and its fabrication method. The semiconductor device includes: a substrate; a multilayer epitaxial layer located on one side of the substrate; the multilayer epitaxial layer including a barrier layer on the side away from the substrate; an isolation layer, a source, a gate, and a drain located on the side of the barrier layer away from the substrate, with the gate located between the source and the drain; the gate including a gate bottom surface near the substrate, the gate bottom surface including a first bottom surface portion and a second bottom surface portion; wherein, the isolation layer is located between the second bottom surface portion and the drain, the isolation layer is in contact with the gate, and the isolation layer is in contact with the multilayer epitaxial layer. The semiconductor device provided by this invention can improve the high electric field distribution on the side of the gate near the drain, and improve the reliability of the device under high temperature and high pressure.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and more particularly to a semiconductor device and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), a semiconductor material, has become a research hotspot due to its large bandgap, high electron saturation drift velocity, high breakdown field strength, and good thermal conductivity. In electronic devices, GaN is more suitable than silicon and gallium arsenide for manufacturing high-temperature, high-frequency, high-voltage, and high-power devices, thus GaN-based electronic devices have excellent application prospects. Gallium nitride high electron mobility transistors (GaN HEMTs) offer advantages such as high speed and low power consumption, making them a potential next-generation low-power power supply device. However, they are prone to failure under high temperature and high voltage conditions, leading to reduced device lifespan. Therefore, improving this failure problem is of great significance.

[0003] In existing GaN HEMT structures, a Schottky structure is typically formed by direct contact between the gate and the semiconductor. However, in this traditional structure, when the device is reverse biased, a high electric field is formed near the drain below the gate. When the device is reverse biased for a long time, the semiconductor material near the drain below the gate relaxes under the high electric field, resulting in an inverse piezoelectric effect, which eventually leads to breakdown and device failure. High temperatures accelerate this effect. Summary of the Invention

[0004] This invention provides a semiconductor device and its fabrication method to improve the high electric field distribution near the drain side of the gate and enhance the reliability of the semiconductor device under high temperature and high pressure.

[0005] This invention provides a semiconductor device, comprising:

[0006] Substrate;

[0007] A multilayer epitaxial layer located on one side of the substrate; the multilayer epitaxial layer includes a barrier layer on the side away from the substrate;

[0008] An isolation layer, a source, a gate, and a drain are located on the side of the barrier layer away from the substrate, with the gate located between the source and the drain; the gate includes a gate bottom surface near the substrate, the gate bottom surface including a first bottom surface portion and a second bottom surface portion, the first bottom surface portion being located on the side of the second bottom surface portion near the drain; wherein, the isolation layer is located between the second bottom surface portion and the drain, the isolation layer is in contact with the gate, and the isolation layer is in contact with the multiple epitaxial layers.

[0009] Optionally, the barrier layer is provided with a first opening, the first opening including a first side surface near the drain electrode, and the isolation layer includes a first isolation portion, the first isolation portion covering at least part of the first side surface;

[0010] At least a portion of the gate is located within the first opening, and the first bottom portion contacts the first isolation portion.

[0011] Optionally, the first opening further includes a bottom surface near the substrate, the bottom surface being connected to the first side surface;

[0012] The isolation layer further includes a second isolation portion, which is connected to the first isolation portion and covers a portion of the bottom surface;

[0013] The first bottom portion also contacts the second isolation portion.

[0014] Optionally, the length of the second isolation section is L1, and the length of the bottom surface is Lgs, where 1 / 4*Lgs≤L1≤1 / 3*Lgs.

[0015] Optionally, the isolation layer further includes a third isolation portion, which is connected to the first isolation portion and contacts the surface of the barrier layer away from the substrate;

[0016] The gate includes a first gate portion and a second gate portion that are connected to each other. The first gate portion is located inside the first opening, and the second gate portion is located outside the first opening and covers the first gate portion. The first bottom portion includes a first bottom portion C, which is in contact with the third isolation portion.

[0017] Optionally, the length of the first bottom surface C portion is Lfgd1, and the length of the third isolation portion is L2, where 1 / 2*Lfgd1 < L2 < Lfgd1.

[0018] Optionally, the semiconductor device further includes a passivation layer located on the side of the barrier layer away from the substrate; the barrier layer has a first opening, the first opening including a first side surface near the drain; the passivation layer has a second opening, the second opening including a second side surface near the drain; the first opening communicates with the second opening; the first side surface and the second side surface are located in the same plane.

[0019] The isolation layer includes a first isolation portion and a fourth isolation portion that are interconnected, the first isolation portion covering the first side surface, and the fourth isolation portion covering at least a portion of the second side surface;

[0020] At least a portion of the gate is located within the first opening and the second opening, and the first bottom portion contacts the first isolation portion and the fourth isolation portion.

[0021] Optionally, the isolation layer further includes a fifth isolation portion, which is connected to the fourth isolation portion and contacts the surface of the passivation layer away from the substrate;

[0022] The gate includes a third gate portion and a fourth gate portion that are interconnected. The third gate portion is located inside the first opening and the second opening, and the fourth gate portion is located outside the first opening and the second opening and covers the third gate portion. The first bottom portion is also in contact with the fifth isolation portion.

[0023] Optionally, the thickness h of the isolation layer satisfies: 2nm ≤ h ≤ 15nm.

[0024] Based on the same inventive concept, embodiments of the present invention also provide a method for fabricating a semiconductor device, the method comprising:

[0025] Provide substrate;

[0026] A multilayer epitaxial layer is fabricated on one side of the substrate; the multilayer epitaxial layer includes a barrier layer on the side away from the substrate;

[0027] A source and a drain are fabricated on the side of the barrier layer away from the substrate, and both the source and the drain form an ohmic contact with the barrier layer.

[0028] An isolation layer is prepared on the side of the barrier layer away from the substrate;

[0029] A gate is fabricated on the side of the barrier layer away from the substrate; the gate is located between the source and the drain; the gate includes a gate bottom surface near the substrate, the gate bottom surface includes a first bottom surface portion and a second bottom surface portion, the first bottom surface portion being located on the side of the second bottom surface portion near the drain; wherein, the isolation layer is located between the second bottom surface portion and the drain, the isolation layer is in contact with the gate, and the isolation layer is in contact with the multiple epitaxial layers.

[0030] Optionally, before fabricating the isolation layer on the side of the barrier layer away from the substrate, the method further includes:

[0031] A first opening is formed in the barrier layer, the first opening including a first side surface near the drain electrode;

[0032] The isolation layer includes a first isolation portion, and the fabrication of the isolation layer on the side of the barrier layer away from the substrate includes:

[0033] At least a portion of the first side surface is prepared as a first isolation portion;

[0034] The fabrication of the gate on the side of the barrier layer away from the substrate includes:

[0035] A gate is formed at least within the first opening, and the first bottom portion contacts the first isolation portion.

[0036] The semiconductor device provided in this invention improves device reliability by placing an isolation layer between the first corner and the drain, and at a position where it contacts the gate and barrier layer, resulting in different contact types at the two corners of the gate. This increases the barrier near the drain side of the gate. Specifically, an isolation layer is placed near the second corner below the gate, i.e., between the first bottom surface portion and the barrier layer, such that at least a portion of the second corner or at least a portion of the first bottom surface portion contacts the isolation layer. This forms a metal-dielectric-semiconductor (MIS) structure with the isolation layer and the barrier layer. Compared to a metal-semiconductor Schottky structure, the MIS structure has a higher barrier, increasing the barrier near the drain side of the gate. When the device is reverse biased, this reduces the electric field near the drain below the gate, improves the high electric field distribution near the drain side of the gate, and prevents device failure due to the inverse piezoelectric effect, thereby improving device reliability under high temperature and high pressure. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, although the drawings described below are some specific embodiments of the present invention, those skilled in the art can extend and extend the basic concepts of the device structure, driving method and manufacturing method disclosed and indicated by various embodiments of the present invention to other structures and drawings. Undoubtedly, these should all be within the scope of the claims of the present invention.

[0038] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention;

[0042] Figure 5 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0043] Figure 6 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0044] Figure 7 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention;

[0045] Figure 8 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention;

[0046] Figure 9 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0047] Figure 10 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0048] Figure 11 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0049] Figure 12 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention;

[0050] Figure 13 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this invention. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the basic concepts disclosed and indicated in the embodiments of this invention, all other embodiments obtained by those skilled in the art are within the scope of protection of this invention.

[0052] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention, such as... Figure 1As shown, the semiconductor device provided in this embodiment of the invention includes: a substrate 100; a multilayer epitaxial layer 200 located on one side of the substrate 100; the multilayer epitaxial layer 200 includes a barrier layer 210 on the side away from the substrate 100; an isolation layer 300, a source 400, a gate 500, and a drain 600 located on the side of the barrier layer 210 away from the substrate 100, the gate 500 being located between the source 400 and the drain 600; the gate 500 includes a gate bottom surface 510 on the side near the substrate 100, the gate bottom surface 510 including a first bottom surface portion 511 and a second bottom surface portion 512, the first bottom surface portion 511 being located on the side of the second bottom surface portion 512 near the drain 600; wherein, the isolation layer 300 is located between the second bottom surface portion 512 and the drain 600, the isolation layer 300 is in contact with the gate 500, and the isolation layer 300 is in contact with the multilayer epitaxial layer 200.

[0053] For example, refer to Figure 1 The semiconductor device provided in this embodiment of the invention includes a substrate 100, an epitaxial layer 200, an isolation layer 300, a source 400, a gate 500, and a drain 600. The substrate 100 can be one or more of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (GaInN), aluminum indium gallium nitride (AlGaInN), gallium arsenide (GaAs), silicon carbide (SiC), sapphire (Sap), and silicon (Si), or any other material capable of growing group III nitrides. The epitaxial layer 200 includes a barrier layer 210, which can be a group III nitride material such as aluminum gallium nitride (AlGaN) or aluminum indium gallium nitride (AlGaInN). The source 400 and drain 600 can be a Ti / Al / Ni / Au stack, and the barrier layer 210 forms ohmic contacts with the source 400 and drain 600, respectively. The gate 500 is located between the source 400 and the drain 600. The gate 500 includes a gate bottom surface 510, which includes a first bottom surface portion 511 and a second bottom surface portion 512. The first bottom surface portion 511 is located on the side of the second bottom surface portion 512 closer to the drain 600. An isolation layer 300 is located between the second bottom surface portion 512 and the drain 600. Specifically, a first corner is formed at the connection point of the first bottom surface portion 511 and the second bottom surface portion 512, and the isolation layer 300 is located between the first corner and the drain 600. The position of the isolation layer 300 effectively addresses the inverse piezoelectric effect near the gate.

[0054] To facilitate the explanation of the specific positional relationship between the first bottom surface portion 511 and the isolation layer 300, this embodiment of the invention divides the first bottom surface portion 511 into different portions to distinguish the portions located at different positions within the first bottom surface portion 511. Specifically, in this embodiment, the first bottom surface portion 511 includes a first bottom surface A portion 51 and a first bottom surface B portion 52 that are connected to each other. The first bottom surface A portion 51 is located on the side of the first bottom surface B portion 52 near the drain 600. A second corner is formed at the connection point between the first bottom surface A portion 51 and the first bottom surface B portion 52. When the semiconductor device is reverse biased, a high electric field is easily formed near the location of this second corner, which can lead to the inverse piezoelectric effect and cause device failure. To avoid the above situation, an isolation layer 300 can be provided at the location of the second corner. For example, refer to Figure 1 An isolation layer 300 can be provided on a portion of the first bottom surface B portion 52 located near the second corner, so that this portion of the first bottom surface B portion 52 contacts the isolation layer 300. Then, a portion of the first bottom surface B portion 52 in the first bottom surface B portion 511 on the side near the drain 600 in the gate 500 forms a metal-dielectric-semiconductor MIS structure with the isolation layer 300 and the barrier layer 210. Meanwhile, a portion of the first bottom surface B portion 52 in the first bottom surface B portion 511 on the side near the source 400 in the gate 500 directly contacts the barrier layer 210, forming a metal-semiconductor Schottky structure. Compared to the metal-semiconductor Schottky structure, the metal-dielectric-semiconductor MIS structure has a higher potential barrier. Specifically, by setting the isolation layer 300, the potential barrier on the side of the gate 500 near the drain 600 can be increased. When the device is reverse biased, the electric field near the drain 600 below the gate 500, i.e., near the location of the second corner, can be reduced, improving the high electric field distribution on the side of the gate 500 near the drain 600. This avoids the inverse piezoelectric effect that could cause device failure, thereby improving the reliability of the device under high temperature and high pressure.

[0055] The semiconductor device provided in this invention improves device reliability by placing an isolation layer between the first corner and the drain, and at the position where it contacts the gate, resulting in different contact types at the two corners of the gate. Specifically, an isolation layer is disposed near the second corner on the drain side below the gate, i.e., between the first bottom surface portion and the barrier layer, such that at least a portion of the second corner or at least a portion of the first bottom surface portion contacts the isolation layer. This forms a metal-dielectric-semiconductor (MIS) structure with the isolation layer and the barrier layer. Compared to a metal-semiconductor Schottky structure, the MIS structure has a higher barrier, thus increasing the barrier on the drain side of the gate. When the device is reverse biased, it reduces the electric field near the drain below the gate, improves the high electric field distribution on the drain side of the gate, and avoids device failure due to the inverse piezoelectric effect, thereby improving device reliability under high temperature and high pressure.

[0056] Figure 2 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention, such as... Figure 2 As shown, optionally, a first opening 10 is provided in the barrier layer 210, the first opening 10 includes a first side surface 11 near the drain 600, the isolation layer 300 includes a first isolation portion 310, the first isolation portion 310 covers at least a portion of the first side surface 11; at least a portion of the gate 500 is located in the first opening 10, and the first bottom portion 511 is in contact with the first isolation portion 310.

[0057] Specifically, in this embodiment, a first opening 10 is provided in the barrier layer 210, and at least a portion of the gate 500 is located within the first opening 10, that is, a portion of the gate 500 can be located within the first opening 10 (see reference). Figure 2 Alternatively, all of the gates 500 can be located within the first opening 10. The first opening 10 includes a first side surface 11 near the drain 600. The first isolation portion 310 of the isolation layer 300 contacts the first side surface 11 and covers at least part of the first side surface 11. The first bottom surface portion 511 of the gate 500 near the drain 600 contacts the first isolation portion 310. This allows the first bottom surface portion 511 of the gate 500 near the drain 600, the first isolation portion 310, and the barrier layer 210 to form a metal-dielectric-semiconductor MIS structure. Compared to the metal-semiconductor Schottky structure, the metal-dielectric-semiconductor MIS structure has a higher barrier, which can increase the barrier of the gate 500 near the drain 600. When the device is reverse biased, it can reduce the electric field near the drain 600 below the gate 500, i.e., near the location of the second corner, to avoid the reverse piezoelectric effect that could cause device failure, thereby improving the reliability of the device under high temperature and high pressure.

[0058] It should be noted that, Figure 2 The first isolation portion 310 is shown to be in contact with the first bottom portion 511 and the first side portion 11, and the first isolation portion 310 covers the entire first side portion 11 of the first opening 10. In other embodiments, the first isolation portion 310 may cover only part of the first side portion 11, as long as the first bottom portion 51 of the gate 500 near the drain 600 forms a metal-dielectric-semiconductor MIS structure with the first isolation portion 310 and the barrier layer 210.

[0059] Figure 3 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention, such as... Figure 3 As shown, based on the above embodiment, optionally, the first opening 10 further includes a bottom surface 12 near the substrate 100, the bottom surface 12 being connected to the first side surface 11; the isolation layer 300 further includes a second isolation portion 320, the second isolation portion 320 being connected to the first isolation portion 310 and covering part of the bottom surface 12; the first bottom surface portion 511 is also in contact with the second isolation portion 320.

[0060] Considering that the width of the first isolation portion 310 of the isolation layer 300 is small and the process is not easy to control during actual fabrication, this embodiment adds a second isolation portion 320. The setting of the second isolation portion 320 can not only regulate the high electric field on the side of the gate 500 near the drain 600, avoiding the inverse piezoelectric effect of the material under long-term high temperature and high stress, which would lead to device failure, but also increase the width of the isolation layer 300, reduce process requirements, and improve process accuracy.

[0061] Specifically, the first opening 10 includes a first side surface 11 near the drain 600 and a bottom surface 12 near the substrate 100. The isolation layer 300 includes a first isolation portion 310 and a second isolation portion 320 connected to each other. The first isolation portion 310 covers at least a portion of the first side surface 11, and the second isolation portion 320 covers a portion of the bottom surface 12. The first bottom surface A portion 51 of the gate 500 is in contact with the first isolation portion 310, and the first bottom surface B portion 52 of the gate 500 is in contact with the second isolation portion 320. This allows the first bottom surface A portion 51 of the gate 500 near the drain 600 to form a metal-dielectric-semiconductor MIS structure with the first isolation portion 310 and the barrier layer 210. The portion of the first bottom surface B portion 52 of the gate 500 near the drain 600 forms a metal-dielectric-semiconductor MIS structure with the second isolation portion 320 and the barrier layer 210. Compared to the metal-semiconductor Schottky structure, the metal-dielectric-semiconductor MIS structure has a higher barrier, which can increase the barrier of the gate 500 near the drain 600. When the device is reverse biased, it can reduce the electric field near the drain 600 below the gate 500, i.e., near the second corner, thus improving the reliability of the device under high temperature and high pressure.

[0062] refer to Figure 3 Optionally, the length of the second isolation section 320 is L1, and the length of the bottom surface 12 is Lgs, where 1 / 4*Lgs≤L1≤1 / 3*Lgs.

[0063] The length L1 of the second isolation portion 320 not only affects the electric field on the side below the gate 500 near the drain 600, but also the threshold voltage of the semiconductor device. Specifically, if L1 is too short, its modulation effect on the electric field on the side below the gate 500 near the drain 600 is small, while if L1 is too long, it will affect the threshold voltage. Therefore, by setting the length L1 of the second isolation portion 320 to be 1 / 4 to 1 / 3 times the length Lgs of the bottom surface 12 of the first opening 10 in the barrier layer 210, the electric field on the side below the gate 500 near the drain 600 can be controlled to the maximum extent. At the same time, since the second isolation layer 320 occupies a small proportion of the bottom surface 12, it has almost no effect on the threshold voltage and saturation current.

[0064] Figure 4 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention, as shown below. Figure 4As shown, optionally, the isolation layer 300 further includes a third isolation portion 330, which is connected to the first isolation portion 310 and contacts the side surface of the barrier layer 210 away from the substrate 100; the gate 500 includes a first gate portion and a second gate portion connected to each other, the first gate portion being located inside the first opening 10, and the second gate portion being located outside the first opening 10 and covering the first gate portion; the first bottom surface portion 511 includes a first bottom surface portion C 53, which contacts the third isolation portion 330.

[0065] In this embodiment, the gate 500 includes a first gate portion and a second gate portion connected to each other. The first gate portion is located within the first opening 10 of the barrier layer 210, and the second gate portion is located outside the first opening 10, covering the first gate portion, i.e. Figure 4 As shown, the gate 500 is a T-type gate. The portion of the second gate branch extending towards the drain is the equivalent gate field plate of the gate 500. Considering that a high electric field will also be formed at the location of the equivalent gate field plate when the semiconductor device is reverse biased, affecting the performance of the semiconductor device, the structure of the isolation layer 300 is designed in this embodiment.

[0066] Specifically, the isolation layer 300 includes a first isolation portion 310 and a third isolation portion 330 interconnected. The first isolation portion 310 contacts the first side surface 11 and covers the first side surface 11 of the first opening 10 in the barrier layer 210. The third isolation portion 330 contacts the surface of the barrier layer 210 away from the substrate 100 and covers at least a portion of the surface of the barrier layer 210 away from the substrate 100. Both the first isolation portion 310 and the third isolation portion 330 are in contact with the first bottom surface portion 511. Specifically, the first bottom surface portion 511 includes a first bottom surface A portion 51 and a first bottom surface C portion 53 interconnected, wherein the first bottom surface A portion 51 contacts the first isolation portion 310, and the first bottom surface C portion 53 contacts the third isolation portion 330. This allows the first bottom surface portion A 51 of the gate 500 near the drain 600 to form a metal-dielectric-semiconductor (MIS) structure with the first isolation portion 310 and the barrier layer 210. Similarly, the first bottom surface portion C 53 of the gate 500, the third isolation portion 330, and the barrier layer 210 form a metal-dielectric-semiconductor (MIS) structure. Compared to a metal-semiconductor Schottky structure, the metal-dielectric-semiconductor (MIS) structure has a higher barrier, increasing the barrier on the side of the gate 500 near the drain 600. When the device is reverse biased, this reduces the electric field near the drain 600 (the location of the second corner) below the gate 500, improving device reliability under high temperature and high pressure. Furthermore, since the third isolation portion 330 is located between the equivalent gate field plate and the barrier layer 210, it can also adjust the high electric field below the equivalent gate field plate on the side of the gate 500 near the drain 600, further improving the reliability of the semiconductor device. Meanwhile, the third isolation section 330 can also increase the width of the isolation layer 300, reduce process requirements, and improve process accuracy.

[0067] Figure 5 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention, such as... Figure 5As shown, in this embodiment, the isolation layer 300 includes a first isolation portion 310, a second isolation portion 320, and a third isolation portion 330. The gate 500 includes a first bottom surface portion A 51, a second bottom surface portion B 52, and a third bottom surface portion C 53. The first bottom surface portion A 51, together with the first isolation portion 310 and the barrier layer 210, forms a metal-dielectric-semiconductor (MIS) structure. The portion of the first bottom surface portion B 52 near the drain 600 forms a metal-dielectric-semiconductor (MIS) structure with the second isolation portion 320 and the barrier layer 210. The first bottom surface portion C 53 forms a metal-dielectric-semiconductor (MIS) structure with the third isolation portion 330 and the barrier layer 210. This allows for comprehensive adjustment of the high electric field on the side of the gate 500 near the drain 600, improving device reliability. It also allows for reasonable setting of the width of the isolation layer 300, improving process accuracy. The length of the second isolation section 320 is L1 and the length of the bottom surface 12 of the first opening 10 is Lgs, which can also satisfy the following relationship: 1 / 4*Lgs≤L1≤1 / 3*Lgs.

[0068] refer to Figure 4 Optionally, the length of the first bottom surface C portion 53 is Lfgd1, and the length of the third isolation portion 330 is L2, where 1 / 2*Lfgd1 < L2 < Lfgd1.

[0069] In this embodiment, the length L2 of the third isolation section 330 and the length Lfgd1 of the first bottom surface C section 53 of the gate 500 must satisfy: 1 / 2*Lfgd1<L2<Lfgd1. If L2 is too short, the subsequent coverage of the gate 500 will be poor, affecting the quality of the gate 500, and the process window requirements will be high. If L2 is too long, it will reduce the two-dimensional electron gas concentration in the epitaxial layer 200.

[0070] Figure 6 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. For example, refer to... Figure 6 Optionally, the length of the third isolation section 330 is L2, the length of the first bottom surface section 53 is Lfgd1, the shortest distance between the drain 600 and the first opening 10 is Lgd1, and Lfgd1≤L2≤Lgd1.

[0071] In this embodiment, the position where the third isolation portion 330 extends towards the drain 600 can be flush with the position where the second gate portion of the gate 500 extends towards the drain 600. That is, the length L2 of the second isolation portion 320 can be equal to the length Lfgd1 of the first bottom surface portion C 53. This can adjust the high electric field below the equivalent gate field plate on the side of the gate 500 near the drain 600, thereby improving the reliability of the semiconductor device. Based on this, the third isolation portion 330 can continue to extend towards the drain 600 until it contacts the drain 600. That is, the length L2 of the second isolation portion 320 can be greater than the length Lfgd1 of the first bottom surface portion C 53, and less than or equal to the shortest distance Lgd1 between the drain 600 and the first opening 10. In addition to adjusting the high electric field below the equivalent gate field plate, the portion of the third isolation portion 330 that extends beyond the length Lfgd1 of the first bottom surface portion C 53 can also be reused as a passivation layer to reduce the surface states of the device, reduce leakage current, and improve device performance.

[0072] Figure 7 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention, such as... Figure 7 As shown, optionally, the semiconductor device further includes a passivation layer 700, which is located on the side of the barrier layer 210 away from the substrate 100; a second opening 20 is provided in the passivation layer 700, and at least a portion of the gate 500 is located in the second opening 20.

[0073] For example, refer to Figure 7 A passivation layer 700 is disposed on the side of the barrier layer 210 away from the substrate 100. The passivation layer 700 may be SiN. x or SiO x The passivation layer 700, made of an insulating material containing nitrogen or oxygen, has a second opening 20. The gate 500 may be partially or entirely located within the second opening 20. The passivation layer 700 reduces the surface states of the semiconductor device, decreases leakage current, and thus improves device performance.

[0074] Figure 8 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention, as shown below. Figure 8As shown, based on the above embodiment, optionally, the barrier layer 210 is provided with a first opening 10, the first opening 10 including a first side surface 11 near the drain 600; the second opening 20 including a second side surface 21 near the drain 600, the first opening 10 and the second opening 20 are connected, the first side surface 11 and the second side surface 21 are located on the same plane; the isolation layer 300 includes a first isolation portion 310 and a fourth isolation portion 340 connected to each other, the first isolation portion 310 covers the first side surface 11, and the fourth isolation portion 340 covers at least part of the second side surface 21; at least part of the gate 500 is located in the first opening 10 and the second opening 20, and the first bottom surface portion 511 is in contact with the first isolation portion 310 and the fourth isolation portion 340.

[0075] Specifically, a first opening 10 is provided in the barrier layer 210, and the first opening 10 includes a second side 21 near the drain 600. A second opening 20 is provided in the passivation layer 700, and the second opening 20 includes a second side 21 near the drain 600. The first opening 10 and the second opening 20 are connected, and the first side 11 and the second side 21 are located on the same plane. The gate 500 may be partially located within the first opening 10 and the second opening 20 (see reference). Figure 8 The gate 500 can also be entirely located within the first opening 10 and the second opening 20. The isolation layer 300 includes a first isolation portion 310 and a fourth isolation portion 340 interconnected. The first isolation portion 310 covers the first side 11 of the first opening 10, and the fourth isolation portion 340 can cover part of the second side 21 of the second opening 20, or it can cover all of the second side 21 (see reference). Figure 8 The first bottom surface portion 511 of the gate 500 contacts the first isolation portion 310 and the fourth isolation portion 340. Specifically, the first bottom surface 511 of the gate 500 includes a first bottom surface A portion 51 and a first bottom surface D portion 54 connected to each other. The first bottom surface A portion 51 contacts the first isolation portion 310, and the first bottom surface D portion 54 contacts the fourth isolation portion 340. In this way, the first bottom surface A portion 51, the first isolation portion 310, and the barrier layer 210 form a metal-dielectric-semiconductor (MIS) structure, which can reduce the high electric field near the drain 600 side of the gate 500, i.e., near the location of the second corner, and improve the reliability of the device.

[0076] Figure 9 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention, such as... Figure 9As shown, based on the above embodiments, optionally, the isolation layer 300 further includes a fifth isolation portion 350, which is connected to the fourth isolation portion 340 and contacts the surface of the passivation layer 700 away from the substrate 100; the gate 500 includes a third gate portion and a fourth gate portion connected to each other, the third gate portion being located inside the first opening 10 and the second opening 20, and the fourth gate portion being located outside the first opening 10 and the second opening 20 and covering the third gate portion; the first bottom surface portion 511 also contacts the fifth isolation portion 350.

[0077] Considering the limited width of the first isolation layer 310 and the difficulty in controlling the actual process, a fifth isolation portion 350 is added to the isolation layer 300 in this embodiment to reduce the process difficulty. Specifically, the isolation layer 300 includes a first isolation portion 310, a fourth isolation portion 340, and a fifth isolation portion 350 that are interconnected. The first isolation portion 310 covers the first side 11 of the first opening 10 in the barrier layer 210, the fourth isolation portion 340 covers the second side 21 of the second opening 20 in the passivation layer 700, and the fifth isolation portion 350 is located on the surface of the passivation layer 700 away from the substrate 100.

[0078] Gate 500 includes a third gate portion and a fourth gate portion interconnected. The third gate portion is located within the first opening 10 of the barrier layer 210 and the second opening 20 of the passivation layer 700. The fourth gate portion is located outside the first opening 10 and the second opening 20, and the fourth gate portion covers the third gate portion, i.e. Figure 9 As shown, the gate 500 is a T-shaped gate. The first bottom surface portion 511 of the gate 500 includes a first bottom surface A portion 51, a first bottom surface D portion 54, and a first bottom surface E portion 55 connected in sequence. The first bottom surface A portion 51 contacts the first isolation portion 310, the first bottom surface D portion 54 contacts the fourth isolation portion 340, and the first bottom surface E portion 55 contacts the fifth isolation portion 350. The first bottom surface A portion 51 near the drain 600 in the gate 500, together with the first isolation portion 310 and the barrier layer 210, forms a metal-dielectric-semiconductor (MIS) structure, which can reduce the electric field near the drain 600 below the gate 500 and improve the reliability of the device under high temperature and high pressure. Simultaneously, the fifth isolation portion 350 can increase the width of the isolation layer 300, reduce process requirements, and improve process accuracy.

[0079] refer to Figure 9 Optionally, the length of the first bottom part 55 is Lfgd2, and the length of the fifth isolation part 350 is L3, where 1 / 2*Lfgd2 < L3 < Lfgd2.

[0080] It should be noted that the embodiments of the present invention are only explained by taking the gate 500 as a T-shaped gate or a rectangular gate as an example, and are not limited thereto. Those skilled in the art can set the shape of the gate 500 according to actual needs.

[0081] In this embodiment, the length L3 of the fifth isolation section 350 and the length Lfgd2 of the first bottom surface section 55 of the gate 500 must satisfy: 1 / 2*Lfgd2<L3<Lfgd2. If L3 is too short, the subsequent coverage of the gate 500 will be poor, affecting the quality of the gate 500, and the process window requirements will be high. If L3 is too long, it will reduce the two-dimensional electron gas concentration in the epitaxial layer 200.

[0082] Optionally, the length of the fifth isolation portion 350 is L3, the length of the first bottom portion 55 is Lfgd2, the shortest distance between the drain 600 and the second opening 20 is Lgd2, and Lfgd2≤L3≤Lgd2.

[0083] In this embodiment, the position where the fifth isolation portion 350 extends towards the drain 600 can be flush with the position where the fourth gate portion of the gate 500 extends towards the drain 600. That is, the length L3 of the fifth isolation portion 350 can be equal to the length Lfgd2 of the first bottom surface portion 55. Based on this, the fifth isolation portion 350 can continue to extend towards the drain 600 until it contacts the drain 600. That is, the length L3 of the fifth isolation portion 350 can be greater than the length Lfgd2 of the first bottom surface portion 55, and less than or equal to the shortest distance Lgd2 between the drain 600 and the second opening 20. In addition to increasing the width of the isolation layer 300 and reducing the process difficulty, the portion of the fifth isolation portion 350 that exceeds the length Lfgd2 of the first bottom surface portion 55 can also be reused as a passivation layer. This is equivalent to having an additional passivation layer, namely the fifth isolation portion 350, on the passivation layer 700. Therefore, the passivation effect on the device surface is better, which can further reduce the surface state of the device, reduce leakage current, and improve device performance.

[0084] refer to Figure 1 Optionally, the thickness h of the isolation layer 300 satisfies: 2nm≤h≤15nm.

[0085] The thickness h of the isolation layer 300 can range from 2nm to 15nm. If the isolation layer 300 is too thin, it will not be able to modulate the electric field below the gate 500 and the drain 600. If the isolation layer 300 is too thick, the ability to modulate the electric field will reach saturation, and there is no point in increasing the thickness.

[0086] refer to Figure 1 Optionally, the material of the insulating layer 300 includes SiNx, SiO2, and HfO. x and AlO x At least one of them.

[0087] The material of the isolation layer 300 can be SiNx, SiO2, or HfO. x One or more of AlOx, or other materials, are acceptable as long as they can achieve the corresponding function.

[0088] refer to Figure 1 Optionally, the multilayer epitaxial layer 200 further includes a channel layer 220 located on the side of the barrier layer 210 near the substrate 100, and the channel layer 220 and the barrier layer 210 form a heterojunction structure.

[0089] In this embodiment, the multilayer epitaxial layer 200 may include a barrier layer 210 and a channel layer 220. The barrier layer 210 and the channel layer 220 form a heterojunction structure, and a two-dimensional electron gas is generated at the interface of the channel layer 220 near the barrier layer 210. The material of the channel layer 220 may be a group III nitride material such as aluminum gallium nitride (AlGaN), gallium nitride (GaN), or aluminum indium gallium nitride (AlGaInN), or it may be carbon-doped gallium nitride (GaN).

[0090] Figure 10 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention, such as... Figure 10 As shown, optionally, based on the above embodiments, the multilayer epitaxial layer 200 further includes a nucleation layer 230 located on the side of the channel layer 220 away from the barrier layer 210.

[0091] The nucleation layer 230 affects parameters such as crystal quality, surface morphology, and electrical properties of other films located above the nucleation layer 230 in the epitaxial layer 200. The nucleation layer 230 varies with different substrate materials and mainly serves to match the substrate material and the semiconductor material layer in the heterojunction structure of the epitaxial layer 200. The nucleation layer 230 can be aluminum gallium nitride (AlGaN), aluminum nitride (AlN), or any other material capable of growing group III nitrides.

[0092] Based on the same inventive concept, embodiments of the present invention also provide a method for fabricating a semiconductor device. Figure 11 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention, such as... Figure 11 As shown, the preparation method includes:

[0093] S110 provides a substrate.

[0094] S120. Prepare a multilayer epitaxial layer on one side of the substrate; the multilayer epitaxial layer includes a barrier layer on the side away from the substrate.

[0095] S130. The source and drain are fabricated on the side of the barrier layer away from the substrate, and both the source and drain form ohmic contacts with the barrier layer.

[0096] The source and drain can be fabricated directly on the surface of the barrier layer, or a groove can be formed on the side of the barrier layer away from the substrate first, and then the source and drain can be fabricated in the corresponding groove.

[0097] S140. An isolation layer is prepared on the side of the barrier layer away from the substrate.

[0098] The isolation layer can be fabricated using processes such as metal oxide chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), atomic layer chemical vapor deposition (ALD), or magnetron sputtering. S150: A gate is fabricated on the side of the barrier layer away from the substrate; the gate is located between the source and drain; the gate includes a gate bottom surface near the substrate, the gate bottom surface including a first bottom surface portion and a second bottom surface portion, the first bottom surface portion being located on the side of the second bottom surface portion near the drain; wherein, the isolation layer is located between the second bottom surface portion and the drain, the isolation layer is in contact with the gate, and the isolation layer is in contact with the multilayer epitaxial layers.

[0099] Specifically, a first corner is formed at the connection point of the first bottom surface portion and the second bottom surface portion of the gate, and an isolation layer is located between the first corner and the drain.

[0100] The semiconductor device fabrication method provided in this invention improves device reliability by placing an isolation layer between the first corner and the drain, and at the location where it contacts the gate and the barrier layer, resulting in different contact types at the two corners of the gate. Specifically, an isolation layer is placed near the second corner on the drain side below the gate, i.e., between the first bottom surface portion and the barrier layer, such that at least a portion of the second corner or at least a portion of the first bottom surface portion contacts the isolation layer. This forms a metal-dielectric-semiconductor (MIS) structure with the isolation layer and the barrier layer. Compared to a metal-semiconductor Schottky structure, the MIS structure has a higher barrier, increasing the barrier on the drain side of the gate. When the device is reverse biased, this reduces the electric field near the drain below the gate, improves the high electric field distribution on the drain side of the gate, and prevents device failure due to the inverse piezoelectric effect, thereby improving device reliability under high temperature and high pressure.

[0101] Figure 12 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention, such as... Figure 12 As shown, the preparation method includes:

[0102] S210 provides a substrate.

[0103] S220. Prepare a multilayer epitaxial layer on one side of the substrate; the multilayer epitaxial layer includes a barrier layer on the side away from the substrate.

[0104] S230. The source and drain are fabricated on the side of the barrier layer away from the substrate, and both the source and drain form ohmic contacts with the barrier layer.

[0105] S240. A first opening is formed in the barrier layer, the first opening including a first side surface near the drain electrode.

[0106] The first opening can be formed in the barrier layer by dry etching. The shape of the first opening can be trapezoidal or rectangular, or other shapes, without limitation.

[0107] S250, at least a first isolation portion is prepared on a portion of the first side.

[0108] The isolation layer may include a first isolation portion, which may cover part or all of the first side surface. When preparing the isolation layer, a full-length isolation layer may first be deposited within the first opening, and then a dry etching process may be used to form the final isolation layer with the first isolation portion.

[0109] S260, A gate is formed at least within the first opening, and the first bottom portion contacts the first isolation portion.

[0110] The first bottom surface A portion of the first bottom surface portion near the drain side of the gate, together with the first isolation portion and the barrier layer, forms a metal-dielectric-semiconductor MIS structure. Compared with the metal-semiconductor Schottky structure, the metal-dielectric-semiconductor MIS structure has a higher barrier, which can increase the barrier on the drain side of the gate. When the device is reverse biased, it can reduce the electric field near the drain below the gate, i.e., near the location of the second corner, and improve the reliability of the device under high temperature and high pressure.

[0111] Figure 13 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention, such as... Figure 13 As shown, the preparation method includes:

[0112] S310 provides a substrate.

[0113] S320. Prepare a multilayer epitaxial layer on one side of the substrate; the multilayer epitaxial layer includes a barrier layer on the side away from the substrate.

[0114] S330. The source and drain are fabricated on the side of the barrier layer away from the substrate, and both the source and drain form ohmic contacts with the barrier layer.

[0115] S340. Prepare a passivation layer on the side of the barrier layer away from the substrate.

[0116] The application of passivation layers can reduce the surface states of semiconductor devices, reduce leakage current, and thus improve device performance.

[0117] S350. A second opening is formed in the passivation layer, the second opening including a second side near the drain electrode; at the same time, a first opening is formed in the barrier layer, the first opening including a first side near the drain electrode; the first opening and the second opening are connected, and the first side and the second side are located in the same plane.

[0118] After depositing the passivation layer, a second opening can be formed in the passivation layer by a dry etching process, while a first opening is formed in the barrier layer. The first opening and the second opening are connected, and the first side of the first opening and the second side of the second opening are located on the same plane.

[0119] S360, a first isolation portion is prepared on the first side surface, and a fourth isolation portion is prepared on at least a portion of the second side surface.

[0120] The isolation layer includes a first isolation portion and a fourth isolation portion that are interconnected, and the first isolation portion and the fourth isolation portion can be fabricated using the same process. Specifically, the isolation layer can be deposited first in the first opening and the second opening, and then the first isolation portion covering the first side and the fourth isolation portion covering at least part of the second side can be formed by an etching process.

[0121] S370, A gate is formed at least within the first opening and the second opening, and the first bottom portion contacts the first isolation portion and the fourth isolation portion.

[0122] The gate can be partially or entirely located within the first and second openings. The first bottom surface of the gate contacts the first isolation portion and the fourth isolation portion. Specifically, the first bottom surface includes two interconnected portions: a first bottom surface A portion and a first bottom surface D portion. The first bottom surface A portion contacts the first isolation portion, and the first bottom surface D portion contacts the fourth isolation portion. The first bottom surface A portion, the first isolation portion, and the barrier layer form a metal-dielectric-semiconductor (MIS) structure, which reduces the high electric field near the drain side of the gate, i.e., near the second corner, thus improving device reliability. The fourth isolation portion can increase the width of the isolation layer, reducing fabrication complexity.

[0123] Based on the above description, a specific method for fabricating a semiconductor device is now provided:

[0124] Step 1: Growing a nucleation layer on the substrate using MOCVD epitaxy;

[0125] Step 2: Prepare a channel layer on the above nucleation layer;

[0126] Step 3: Prepare an AlGaN barrier layer on the above-mentioned channel layer;

[0127] Step 4: Coat the multilayer epitaxial layer composed of the above substrate / nucleation layer / channel layer / barrier layer with photoresist, and form the source and drain opening regions through exposure, development and etching steps;

[0128] Step 5: Evaporate the ohmic metal, peel off and remove the adhesive, and then perform high-temperature annealing to make the source and drain metals form ohmic contacts with the barrier layer respectively.

[0129] Step 6: Deposit a passivation layer on the above barrier layer;

[0130] Step 7: Apply photoresist to the passivation layer, expose, develop, and dry etch out the gate region (first opening and / or second opening), and then dry etch or wet etch away the photoresist.

[0131] Step 8: Deposit an isolation layer on the above wafer, coat it with photoresist, expose the area except for a part of the isolation layer near the gate and drain, after development and dry etching, finally only a part of the isolation layer near the gate and drain (each isolation section) is retained.

[0132] Step 9: Clean the above discs to remove any residual foreign matter from the surface;

[0133] Step 10: After metal evaporation and stripping on the above-mentioned wafer, a gate is formed.

[0134] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A multilayer epitaxial layer located on one side of the substrate; The multilayer epitaxial layer includes a barrier layer on the side away from the substrate; An isolation layer, a source, a gate, and a drain are located on the side of the barrier layer away from the substrate, with the gate located between the source and the drain; the gate includes a gate bottom surface near the substrate, the gate bottom surface including a first bottom surface portion and a second bottom surface portion, the first bottom surface portion being located on the side of the second bottom surface portion near the drain; wherein, the isolation layer is located between the second bottom surface portion and the drain, the isolation layer is in contact with the gate, and the isolation layer is in contact with the multiple epitaxial layers; The barrier layer is provided with a first opening, the first opening including a first side surface near the drain electrode, and the isolation layer includes a first isolation portion, the first isolation portion covering at least part of the first side surface. At least a portion of the gate is located within the first opening, and the first bottom portion contacts the first isolation portion; The isolation layer further includes a third isolation portion, which is connected to the first isolation portion and contacts the surface of the barrier layer away from the substrate. The gate includes a first gate portion and a second gate portion connected to each other. The first gate portion is located inside the first opening, and the second gate portion is located outside the first opening and covers the first gate portion. The first bottom portion includes a first bottom portion C, which is in contact with the third isolation portion.

2. The semiconductor device according to claim 1, characterized in that, The first opening also includes a bottom surface near the substrate, the bottom surface being connected to the first side surface; The isolation layer further includes a second isolation portion, which is connected to the first isolation portion and covers a portion of the bottom surface; The first bottom portion also contacts the second isolation portion.

3. The semiconductor device according to claim 2, characterized in that, The length of the second isolation section is L1, and the length of the bottom surface is Lgs, where 1 / 4*Lgs≤L1≤1 / 3*Lgs.

4. The semiconductor device according to claim 1, characterized in that, The length of the first bottom surface C portion is Lfgd1, and the length of the third isolation portion is L2, where 1 / 2*Lfgd1 < L2 < Lfgd1.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a passivation layer located on the side of the barrier layer away from the substrate; The barrier layer is provided with a first opening, and the first opening includes a first side surface near the drain electrode. The passivation layer is provided with a second opening, the second opening includes a second side surface near the drain electrode, the first opening is connected to the second opening, and the first side surface and the second side surface are located on the same plane; The isolation layer includes a first isolation portion and a fourth isolation portion that are interconnected, the first isolation portion covering the first side surface, and the fourth isolation portion covering at least a portion of the second side surface; At least a portion of the gate is located within the first opening and the second opening, and the first bottom portion contacts the first isolation portion and the fourth isolation portion.

6. The semiconductor device according to claim 5, characterized in that, The isolation layer further includes a fifth isolation portion, which is connected to the fourth isolation portion and contacts the surface of the passivation layer away from the substrate; The gate includes a third gate portion and a fourth gate portion that are interconnected. The third gate portion is located inside the first opening and the second opening, and the fourth gate portion is located outside the first opening and the second opening and covers the third gate portion. The first bottom portion is also in contact with the fifth isolation portion.

7. The semiconductor device according to claim 1, characterized in that, The thickness h of the isolation layer satisfies: 2nm≤h≤15nm.

8. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A multilayer epitaxial layer is fabricated on one side of the substrate; The multilayer epitaxial layer includes a barrier layer on the side away from the substrate; A source and a drain are fabricated on the side of the barrier layer away from the substrate, and both the source and the drain form an ohmic contact with the barrier layer. An isolation layer is prepared on the side of the barrier layer away from the substrate; A gate is fabricated on the side of the barrier layer away from the substrate; the gate is located between the source and the drain; the gate includes a gate bottom surface near the substrate, the gate bottom surface includes a first bottom surface portion and a second bottom surface portion, the first bottom surface portion being located on the side of the second bottom surface portion near the drain; wherein, an isolation layer is located between the second bottom surface portion and the drain, the isolation layer is in contact with the gate, and the isolation layer is in contact with the multiple epitaxial layers; Before fabricating the isolation layer on the side of the barrier layer away from the substrate, the method further includes: A first opening is formed in the barrier layer, the first opening including a first side surface near the drain electrode; The isolation layer includes a first isolation portion, and the fabrication of the isolation layer on the side of the barrier layer away from the substrate includes: At least a portion of the first side surface is prepared as a first isolation portion; The fabrication of the gate on the side of the barrier layer away from the substrate includes: A gate is formed at least within the first opening, and the first bottom portion contacts the first isolation portion; The method for fabricating the semiconductor device further includes: A third isolation portion is prepared; the third isolation portion is connected to the first isolation portion and is in contact with the surface of the barrier layer away from the substrate; The gate includes a first gate portion and a second gate portion connected to each other. The first gate portion is located inside the first opening, and the second gate portion is located outside the first opening and covers the first gate portion. The first bottom portion includes a first bottom portion C, which is in contact with the third isolation portion.

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