A semi-enclosed MOSFET device and a preparation method and chip thereof

Abstract

The application belongs to the technical field of semiconductor, and provides a semi-enclosed MOSFET device and a preparation method and a chip thereof, wherein an N-type drift layer is formed on the front surface of an N-type substrate, then a P-type base region and a P-type shielding region are formed on the N-type drift layer, N-type heavy doped regions are formed by injecting N-type doped ions into the P-type base region, a Schottky metal layer is formed by modifying the P-type shielding region to reach the N-type drift layer, a gate dielectric layer is formed between the P-type shielding region and the P-type base region, thereby forming an integrated semi-enclosed MOSFET device, the diode opening voltage and the dead time of the device during freewheeling are reduced, the current peak generated by the semi-enclosed MOSFET device during conduction is greatly reduced, the switching loss of the semi-enclosed MOSFET device is effectively reduced, and the performance and stability of the semi-enclosed MOSFET device are enhanced.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor device technology, and in particular relates to a semi-enclosed MOSFET device, a preparation method thereof, and a chip. Background Art

[0002] Metal Oxide Semiconductor Field Effect Transistor (MOSFET) can be widely used in analog and digital circuits. Currently, there are two main types of MOSFET structures: trench gate type and planar type. Among them, trench gate MOSFET uses the trench gate to effectively increase the channel density. However, when the device withstands voltage, the curvature effect causes extremely high peak electric fields at the corners of the gate dielectric layer, which reduces the reliability of the gate dielectric layer after long-term operation. In order to reduce the electric field strength near the gate dielectric layer when the device is blocked and improve the reliability of the gate dielectric layer, a common solution is to sacrifice the channel on one side of the trench gate and form a grounded P-type shielding region at the bottom of the trench, forming a half-enclosed MOSFET.

[0003] However, the parasitic diode of the current half-enclosed MOSFET has the disadvantages of high turn-on voltage, slow reverse recovery speed and large switching loss during freewheeling. Therefore, it needs to be further improved. Summary of the Invention

[0004] The present application provides a half-enclosed MOSFET device and its preparation method and chip, aiming to solve the problems of the parasitic diode of the current half-enclosed MOSFET having high turn-on voltage, slow reverse recovery speed and large switching loss during freewheeling.

[0005] In order to solve the above technical problems, a first aspect of an embodiment of the present application provides a half-enclosed MOSFET device, wherein the half-enclosed MOSFET comprises:

[0006] N-type substrate;

[0007] An N-type drift layer is formed on the front surface of the N-type substrate;

[0008] A P-type base region and a P-type shield region are respectively formed on the N-type drift layer; wherein the N-type drift layer has an L-shaped structure, the P-type base region is located on the vertical portion of the N-type drift layer, and the P-type shield region is located on the horizontal portion of the N-type drift layer, and the P-type shield region has an L-shaped structure;

[0009] a gate dielectric layer formed between the vertical portion of the P-type shielding region and the vertical portion of the N-type drift layer and located on the horizontal portion of the P-type shielding region; the gate dielectric layer has a concave structure;

[0010] An N-type heavily doped region is formed on the P-type base region and contacts the gate dielectric layer;

[0011] A P-type polycrystalline layer formed in the groove of the gate dielectric layer;

[0012] a Schottky metal layer formed in a through hole in the vertical portion of the P-type shielding region and in contact with the N-type drift layer;

[0013] a source metal layer formed on the vertical portion of the P-type shielding region and the N-type heavily doped region;

[0014] a drain metal layer formed on the back side of the N-type substrate;

[0015] A gate metal layer is formed on the P-type polycrystalline layer.

[0016] In one embodiment, the P-type base region has an L-shaped structure, and the N-type heavily doped region is located between the source metal layer and a horizontal portion of the P-type base region.

[0017] In one embodiment, the thickness of the P-type base region is less than one-third of the height of the gate dielectric layer, and the doping concentration of the P-type base region is less than the doping concentration of the P-type shielding region.

[0018] In one embodiment, the doping concentration of the N-type drift layer is lower than the doping concentration of the N-type substrate, and the doping concentration of the N-type drift layer is lower than the doping concentration of the N-type heavily doped region.

[0019] In one embodiment, the gate dielectric layer is silicon oxide.

[0020] In one embodiment, the Schottky metal layer comprises nickel and gold.

[0021] In one embodiment, the N-type substrate and the N-type drift layer are both made of N-type silicon carbide material.

[0022] A second aspect of the present application further provides a method for preparing a half-enclosed MOSFET device, the method comprising:

[0023] forming an N-type drift layer on the front surface of the N-type substrate;

[0024] Implanting P-type dopant ions into a first predetermined region on the N-type drift layer to form a P-type base region;

[0025] Implanting N-type dopant ions into a predetermined area on the P-type base region to form an N-type heavily doped region;

[0026] Implanting P-type dopant ions into a second predetermined region on the N-type drift layer to form a P-type shielding region, and making the N-type drift layer have an L-shaped structure; wherein the doping concentration of the P-type shielding region is greater than the doping concentration of the P-type base region, and the depth of the P-type shielding region is greater than the depth of the P-type base region;

[0027] forming a gate trench on the P-type shielding region so that the P-type shielding region has an L-shaped structure; wherein the gate trench is located between the vertical portion of the P-type shielding region and the vertical portion of the N-type drift layer, and is located on the horizontal portion of the P-type shielding region;

[0028] forming a gate dielectric layer on an inner wall of the gate trench;

[0029] forming a P-type polycrystalline layer in the groove of the gate dielectric layer;

[0030] forming a contact through-hole in the vertical portion of the P-type shielding region, and forming a Schottky metal layer in the contact through-hole; wherein the Schottky metal layer is in contact with the N-type drift layer;

[0031] forming a source metal layer on the vertical portion of the P-type shielding region and the N-type heavily doped region, and forming a drain metal layer on the back side of the N-type substrate;

[0032] A gate metal layer is formed on the P-type polycrystalline layer.

[0033] In one embodiment, the width of the P-type shield region is greater than the width of the P-type base region.

[0034] A third aspect of the embodiments of the present application further provides a chip comprising a half-enclosed MOSFET device as described in any one of the above embodiments; or comprising a half-enclosed MOSFET device prepared by the preparation method described in any one of the above embodiments.

[0035] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0036] An N-type drift layer is formed on the front side of an N-type substrate, a P-type base region and a P-type shielding region are formed on the N-type drift layer, N-type dopant ions are implanted into the P-type base region to form an N-type heavily doped region, the P-type shielding region is modified to form a Schottky metal layer that penetrates into the N-type drift layer, and a gate dielectric layer is formed between the P-type shielding region and the P-type base region, thereby forming an integrated half-enclosed MOSFET device. This reduces the diode turn-on voltage and dead time of the half-enclosed MOSFET device during freewheeling. The integrated half-enclosed MOSFET device has the characteristics of faster reverse recovery speed, greatly reduces the current spike generated by the half-enclosed MOSFET device when it is turned on, effectively reduces the switching loss of the half-enclosed MOSFET device, and enhances the stability of the half-enclosed MOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic structural diagram of a half-enclosed MOSFET device provided in an embodiment of the present application is shown;

[0038] Figure 2 A schematic diagram of the implementation process of the method for preparing a half-enclosed MOSFET device provided in an embodiment of the present application is shown;

[0039] Figure 3 Schematic diagram of forming the drift layer 200 provided in an embodiment of the present application.

[0040] Figure 4 It is a schematic diagram of forming a P-type base region 300 provided in an embodiment of the present application.

[0041] Figure 5 3 is a schematic diagram of forming an N-type heavily doped region 310 provided in an embodiment of the present application.

[0042] Figure 6 Schematic diagram of forming a P-type shielding region 400 provided in an embodiment of the present application.

[0043] Figure 7 4 is a schematic diagram of forming a gate trench 410 provided in an embodiment of the present application.

[0044] Figure 8 4 is a schematic diagram of forming a gate dielectric layer 420 provided in an embodiment of the present application.

[0045] Figure 9 Schematic diagram of forming a P-type polycrystalline layer 432 provided in an embodiment of the present application.

[0046] Figure 10 4 is a schematic diagram of forming a contact through hole 441 in a vertical portion of a P-type shielding region 400 according to an embodiment of the present application.

[0047] Figure 11 4 is a schematic diagram of forming a Schottky metal layer 442 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0049] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0050] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0052] In order to solve the above technical problems, the present invention provides a semi-enclosed MOSFET device. Figure 1 As shown, the half-enclosed MOSFET device in this embodiment includes: an N-type substrate 100, an N-type drift layer 200, a P-type base region 300, a P-type shielding region 400, a gate dielectric layer 420, an N-type heavily doped region 310, a P-type polycrystalline layer 432, a Schottky metal layer 442, a source metal layer 500, a drain metal layer 600, and a gate metal layer 700.

[0053] Specifically, the N-type drift layer 200 is formed on the front side of the N-type substrate 100, and the P-type base region 300 and the P-type shield region 400 are respectively formed on the N-type drift layer 200, wherein the N-type drift layer 200 has an L-shaped structure, the P-type base region 300 is located on the vertical portion of the N-type drift layer 200, and the P-type shield region 400 is located on the horizontal portion of the N-type drift layer 200. The P-type shield region 400 has an L-shaped structure, and the vertical portion of the P-type shield region 400 is opposite to the vertical portion of the N-type drift layer 200. The gate dielectric layer 420 is formed between the vertical portion of the P-type shield region 400 and the vertical portion of the N-type drift layer 200, and is located on the horizontal portion of the P-type shield region 400. The gate dielectric layer 420 has a concave structure.

[0054] An N-type heavily doped region 310 is formed on the P-type base region 300 and contacts the gate dielectric layer 420 ; a P-type polycrystalline layer 432 is formed in a groove of the gate dielectric layer 420 ; a Schottky metal layer 442 is formed in a through hole in the vertical portion of the P-type shielding region 400 , and the Schottky metal layer 442 contacts the N-type drift layer 200 and forms a Schottky contact with the N-type drift layer 200 ; a source metal layer 500 is formed on the vertical portion of the P-type shielding region 400 and on the N-type heavily doped region 310 ; a drain metal layer 600 is formed on the back side of the N-type substrate 100 ; and a gate metal layer 700 is formed on the P-type polycrystalline layer 432 .

[0055] In this embodiment, by setting the N-type drift layer 200 as an L-shaped structure, a P-type shield region 400 and a P-type base region 300 with different thicknesses can be formed on the N-type drift layer 200, and the thickness of the P-type shield region 400 is greater than that of the P-type base region 300. By setting the P-type shield region 400 as an L-shaped structure, a gate structure is formed between the vertical portion of the P-type shield region 400 and the N-type drift layer 200, and a Schottky metal layer 442 is formed in the vertical portion of the P-type shield region 400 that penetrates into the N-type drift layer 200, so that the P-type shield region 400 can protect both the gate structure of the device and the Schottky diode structure integrated in the device, and reduce the current density of the half-enclosed MOSFET device in this embodiment, greatly reduce the diode turn-on voltage and dead time of the half-enclosed MOSFET device during freewheeling, and enhance the performance and stability of the half-enclosed MOSFET device.

[0056] In one embodiment, the P-type base region 300 has an L-shaped structure, and the N-type heavily doped region 310 is located between the source metal layer 500 and a horizontal portion of the P-type base region 300 .

[0057] In this embodiment, the P-type base region 300 can be used to isolate the N-type heavily doped region 310 from the N-type drift layer 200. At this time, a PN junction is formed between the P-type base region 300 and the N-type drift layer 200, and a PN junction is formed between the P-type base region 300 and the N-type heavily doped region 310, thereby forming a relative PN junction structure in the device.

[0058] In a specific application, N-type doping ions may be injected into the portion of the P-type base region 300 close to the gate dielectric layer 420 to form an N-type heavily doped region 310 in the P-type base region 300 , so that the P-type base region 300 has an L-shaped structure.

[0059] In one embodiment, the doping concentration of the N-type dopant ions in the N-type heavily doped region 310 is at least 100 times the doping concentration of the P-type dopant ions in the P-type base region 300 .

[0060] In one embodiment, the N-type dopant ions may be phosphorus ions or nitrogen ions.

[0061] In one embodiment, the P-type dopant ions may be aluminum ions.

[0062] In one embodiment, the thickness of the P-type base region 300 is less than one-third of the height of the gate dielectric layer 420 , and the doping concentration of the P-type base region 300 is less than the doping concentration of the P-type shielding region 400 .

[0063] In one embodiment, the thickness of the P-type base region 300 is less than one-third of the thickness of the P-type shield region 400 .

[0064] In one embodiment, the doping concentration of the N-type drift layer 200 is lower than the doping concentration of the N-type substrate 100 , and the doping concentration of the N-type drift layer 200 is lower than the doping concentration of the N-type heavily doped region 310 .

[0065] In one embodiment, the thickness of the horizontal portion of the N-type drift layer 200 is greater than the width of the vertical portion of the N-type drift layer 200 .

[0066] In one embodiment, the gate dielectric layer 420 is silicon oxide.

[0067] In one embodiment, Schottky metal layer 442 includes nickel and gold.

[0068] In a specific application, the Schottky metal layer 442 may be cylindrical and may be formed of a stacked structure of nickel and gold.

[0069] In one embodiment, the Schottky metal layer 442 may also be composed of a nickel layer and a gold layer, and the two ends of the nickel layer and the gold layer are in contact with the N-type drift layer 200 and the source metal layer 500 respectively, thereby forming two Schottky contacts between the Schottky metal layer 442 and the N-type drift layer 200, which can ensure that the device has a faster reverse recovery speed and reduce the current spike when the device is turned on.

[0070] In one embodiment, the width of the P-type shielding region 400 between the Schottky metal layer 442 and the gate dielectric layer 420 is greater than the distance between the bottom of the gate dielectric layer 420 and the N-type drift layer 200, thereby preventing the P-type polysilicon from affecting the Schottky metal layer 442 when voltage is applied.

[0071] In one embodiment, the source metal layer 500 is in contact with both the Schottky metal layer 442 and the N-type heavily doped region 310 , and the source metal layer 500 is an ohmic metal material.

[0072] In one embodiment, both the N-type substrate 100 and the N-type drift layer 200 are made of N-type silicon carbide material.

[0073] In a specific application, the N-type drift layer 200 can be formed by growing silicon carbide material on the N-type substrate 100, the P-type base region 300 and the P-type shielding region 400 can be obtained by injecting P-type dopant ions into the N-type drift layer 200, and the N-type heavily doped region 310 can be obtained by injecting N-type dopant ions into the P-type base region 300.

[0074] The present application also provides a method for preparing a semi-enclosed MOSFET device, see Figure 2 As shown, the preparation method in this embodiment includes steps S100 to S900.

[0075] In step S100 , an N-type drift layer is formed on the front surface of an N-type substrate.

[0076] In this embodiment, combined with Figure 3 As shown, an N-type drift layer 200 may be formed on an N-type substrate 100 by an N-type semiconductor material growth process. The thickness of the N-type drift layer 200 is greater than that of the N-type substrate 100 .

[0077] In one embodiment, the thickness of the N-type drift layer 200 is at least five times the thickness of the N-type substrate 100 .

[0078] In one embodiment, the N-type drift layer 200 and the N-type substrate 100 are made of the same semiconductor material.

[0079] In one embodiment, both the N-type substrate 100 and the N-type drift layer 200 are made of N-type silicon carbide material. In a specific application, the N-type drift layer 200 can be formed by growing silicon carbide material on the N-type substrate 100 .

[0080] In one embodiment, the doping concentration of the N-type dopant ions in the N-type drift layer 200 is lower than the doping concentration of the N-type dopant ions in the N-type substrate 100 .

[0081] In step S200 , P-type dopant ions are implanted into a first predetermined region on the N-type drift layer to form a P-type base region.

[0082] In this embodiment, combined with Figure 4 As shown, a P-type base region 300 can be formed on the N-type drift layer 200 by implanting P-type dopant ions into a first preset region on the N-type drift layer 200. During the ion implantation process, a second preset region on the N-type drift layer 200 can be protected by a mask. At this time, the N-type drift layer 200 has an L-shaped structure, and a PN junction is formed at the interface between the P-type base region 300 and the N-type drift layer 200.

[0083] In step S300 , N-type dopant ions are implanted into a predetermined region on the P-type base region to form an N-type heavily doped region.

[0084] In this embodiment, combined with Figure 5 As shown, N-type dopant ions are implanted into a preset area on the P-type base region 300 through an ion implantation process to form an N-type heavily doped region 310 on the P-type base region 300. The doping concentration of the N-type dopant ions in the N-type heavily doped region 310 is at least 100 times the doping concentration of the P-type dopant ions in the P-type base region 300.

[0085] In a specific application embodiment, the N-type heavily doped region 310 is located in the edge area of ​​the P-type base region 300 and contacts the N-type drift layer 200 , wherein the doping concentration of the N-type doping ions in the N-type heavily doped region 310 is at least 1000 times the doping concentration of the N-type doping ions in the N-type drift layer 200 .

[0086] In step S400 , P-type dopant ions are implanted into a second predetermined region on the N-type drift layer to form a P-type shielding region, and the N-type drift layer is formed into an L-shaped structure.

[0087] Combine Figure 6 As shown, a P-type shielding region 400 adjacent to the P-type base region 300 is formed by implanting P-type dopant ions into a second preset region on the N-type drift layer 200, and the depth of the P-type shielding region 400 is greater than the depth of the P-type base region 300, so that the N-type drift layer 200 has an L-shaped structure.

[0088] In this embodiment, the doping concentration of the P-type shield region 400 is greater than the doping concentration of the P-type base region 300 , and a PN junction is formed in the interface region between the P-type shield region 400 and the N-type drift layer 200 .

[0089] In a specific embodiment, the doping concentration of the P-type dopant ions in the P-type shielding region 400 is at least 100 times the doping concentration of the P-type dopant ions in the P-type base region 300 .

[0090] In step S500 , a gate trench is formed on the P-type shielding region so that the P-type shielding region has an L-shaped structure.

[0091] In this embodiment, combined with Figure 7 As shown, a gate trench 410 adjacent to the P-type base region 300 is formed by etching a portion of the P-type shielding region 400. The P-type shielding region 400 is L-shaped after etching. The gate trench is located between the vertical portion of the P-type shielding region 400 and the vertical portion of the N-type drift layer 200, and is located on the horizontal portion of the P-type shielding region 400.

[0092] In step S600 , a gate dielectric layer is formed on the inner wall of the gate trench.

[0093] In this embodiment, combined with Figure 8As shown, a gate dielectric layer 420 may be formed on the inner wall of the gate trench 410 by depositing a gate dielectric material. In this case, the thickness of the gate dielectric layer 420 is relatively small, and the gate dielectric layer 420 has a concave structure.

[0094] In one embodiment, the gate dielectric layer 420 may have a thickness of 2-20 nm.

[0095] In step S700 , a P-type polycrystalline layer is formed in the groove of the gate dielectric layer.

[0096] In this embodiment, combined with Figure 8 and Figure 9 As shown, a P-type polycrystalline layer 432 may be formed in the groove 431 of the gate dielectric layer 420 by depositing a P-type polysilicon material.

[0097] In step S800 , a contact hole is formed in the vertical portion of the P-type shielding region, and a Schottky metal layer is formed in the contact hole.

[0098] In this embodiment, combined with Figure 10 and Figure 11 As shown, the contact hole 441 extends from the upper surface of the P-type shielding region 400 to the N-type drift layer 200 , and the Schottky metal layer 442 formed in the contact hole 441 contacts the N-type drift layer 200 , and a Schottky contact is formed between the Schottky metal layer 442 and the N-type drift layer 200 .

[0099] In a specific embodiment, the Schottky metal layer 442 may be formed in the contact hole by depositing a Schottky metal material.

[0100] In step S900 , a source metal layer is formed on the vertical portion of the P-type shielding region and the N-type heavily doped region, a drain metal layer is formed on the back side of the N-type substrate, and a gate metal layer is formed on the P-type polycrystalline layer 432 .

[0101] In this embodiment, combined with Figure 1 As shown, a source metal layer 500 can be formed on the vertical portion of the P-type shielding region 400 and the N-type heavily doped region 310 by depositing an ohmic metal material. Similarly, a drain metal layer 600 can be formed on the back side of the N-type substrate 100 by depositing an ohmic metal material, and a gate metal layer 700 can be formed on the P-type polycrystalline layer 432.

[0102] In one embodiment, an encapsulation layer may be formed by depositing an insulating dielectric material to encapsulate and protect the device, and then the source electrode, the drain electrode, and the gate electrode are respectively led out through contact holes.

[0103] In one embodiment, the width of the P-type shield region 400 is greater than the width of the P-type base region 300 .

[0104] The embodiment of the present application also provides a chip comprising the semi-enclosed MOSFET device according to any one of the above embodiments.

[0105] In one embodiment, the chip in the embodiment comprises the semi-enclosed MOSFET device prepared by the preparation method according to any one of the above embodiments.

[0106] Compared with the prior art, the embodiment of the present application has the beneficial effects that:

[0107] By forming the N-type drift layer 200 on the front surface of the N-type substrate 100, then forming the P-type base region 300 and the P-type shielding region 400 on the N-type drift layer 200 respectively, then implanting N-type doping ions into the P-type base region 300 to form the N-type heavily doped region 310, and then forming the Schottky metal layer 442 extending into the N-type drift layer 200 by modifying the P-type shielding region 400, and forming the gate dielectric layer 420 between the P-type shielding region 400 and the P-type base region 300, an integrated semi-enclosed MOSFET device is formed, the diode opening voltage and the dead time of the device during freewheeling are reduced, the current spike generated by the semi-enclosed MOSFET device during conduction is greatly reduced, and the stability of the semi-enclosed MOSFET device is enhanced.

[0108] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit the same; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalent ones; and these modifications or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A half-enclosed MOSFET device, characterized in that: The half-package MOSFET includes: N-type substrate; An N-type drift layer is formed on the front surface of the N-type substrate; A P-type base region and a P-type shield region are respectively formed on the N-type drift layer; wherein the N-type drift layer has an L-shaped structure, the P-type base region is located on the vertical portion of the N-type drift layer, and the P-type shield region is located on the horizontal portion of the N-type drift layer, and the P-type shield region has an L-shaped structure; a gate dielectric layer formed between the vertical portion of the P-type shielding region and the vertical portion of the N-type drift layer and located on the horizontal portion of the P-type shielding region; the gate dielectric layer has a concave structure; An N-type heavily doped region is formed on the P-type base region and contacts the gate dielectric layer; A P-type polycrystalline layer formed in the groove of the gate dielectric layer; a Schottky metal layer formed in a through hole in the vertical portion of the P-type shielding region and in contact with the N-type drift layer; a source metal layer formed on the vertical portion of the P-type shielding region and the N-type heavily doped region; a drain metal layer formed on the back side of the N-type substrate; A gate metal layer is formed on the P-type polycrystalline layer.

2. The half-enclosed MOSFET device according to claim 1, wherein: The P-type base region has an L-shaped structure, and the N-type heavily doped region is located between the source metal layer and a horizontal portion of the P-type base region.

3. The half-enclosed MOSFET device according to claim 1, wherein: The thickness of the P-type base region is less than one-third of the height of the gate dielectric layer, and the doping concentration of the P-type base region is less than the doping concentration of the P-type shielding region.

4. The half-enclosed MOSFET device according to claim 1, wherein: The doping concentration of the N-type drift layer is lower than the doping concentration of the N-type substrate, and the doping concentration of the N-type drift layer is lower than the doping concentration of the N-type heavily doped region.

5. The half-enclosed MOSFET device according to any one of claims 1 to 4, characterized in that: The gate dielectric layer is silicon oxide.

6. The half-enclosed MOSFET device according to any one of claims 1 to 4, characterized in that: The Schottky metal layer includes nickel and gold.

7. The half-enclosed MOSFET device according to any one of claims 1 to 4, characterized in that: The N-type substrate and the N-type drift layer are both made of N-type silicon carbide materials.

8. A method for preparing a half-enclosed MOSFET device, characterized in that: The preparation method comprises: forming an N-type drift layer on the front surface of the N-type substrate; Implanting P-type dopant ions into a first predetermined region on the N-type drift layer to form a P-type base region; Implanting N-type dopant ions into a predetermined area on the P-type base region to form an N-type heavily doped region; Implanting P-type dopant ions into a second predetermined region on the N-type drift layer to form a P-type shielding region, and making the N-type drift layer have an L-shaped structure; wherein the doping concentration of the P-type shielding region is greater than the doping concentration of the P-type base region, and the depth of the P-type shielding region is greater than the depth of the P-type base region; forming a gate trench on the P-type shielding region so that the P-type shielding region has an L-shaped structure; wherein the gate trench is located between the vertical portion of the P-type shielding region and the vertical portion of the N-type drift layer, and is located on the horizontal portion of the P-type shielding region; forming a gate dielectric layer on an inner wall of the gate trench; forming a P-type polycrystalline layer in the groove of the gate dielectric layer; forming a contact through-hole in the vertical portion of the P-type shielding region, and forming a Schottky metal layer in the contact through-hole; wherein the Schottky metal layer is in contact with the N-type drift layer; forming a source metal layer on the vertical portion of the P-type shielding region and the N-type heavily doped region, and forming a drain metal layer on the back side of the N-type substrate; A gate metal layer is formed on the P-type polycrystalline layer.

9. The preparation method according to claim 8, characterized in that The width of the P-type shielding region is greater than the width of the P-type base region.

10. A chip, characterized in that: The invention comprises a half-enclosed MOSFET device according to any one of claims 1 to 7; or comprises a half-enclosed MOSFET device prepared by the preparation method according to claim 8 or 9.

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