Super junction trench gate MOSFET layout structure and preparation method thereof

Abstract

The application provides a super-junction trench gate MOSFET layout structure and a preparation method thereof. The layout structure comprises a substrate, a gate dielectric layer, a main gate, a first auxiliary gate, a ring-shaped second auxiliary gate, a ring-shaped pseudo gate, a body region, a source doped region, an interlayer dielectric layer, a first conductive plug, a second conductive plug, a third conductive plug, a fourth conductive plug, a deep layer injection region, a first conductive layer and a second conductive layer. The deep layer injection region is designed at the bottom of the first to fourth conductive plugs, so that the injection of the deep layer injection region can be completed by using a mask for preparing all contact holes, thereby saving the mask, simplifying the preparation process and reducing the manufacturing cost. Further, the pseudo gate in the peripheral terminal region and the second auxiliary gate and the third conductive plug in the gate end lead-out region are all arranged in a continuous ring-shaped structure, so that the problem of charge balance deviation of the device is avoided, and the breakdown voltage of the device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a superjunction trench gate MOSFET layout structure and its fabrication method. Background Technology

[0002] Trench gate MOSFETs are widely used in power conversion circuits, often as power switching devices. The on-resistance (Rsp) and breakdown voltage (BV) of the trench gate are among its important parameters; achieving higher breakdown voltage and lower on-resistance can improve product competitiveness. To improve the on-resistance of medium- to high-voltage (50–200V) trench gate MOSFETs, the concept of a superjunction-trench gate achieved through injection has been proposed.

[0003] Taking the N-channel trench gate as an example, in order to improve the characteristics of the superjunction trench gate device, the bottom of the P-pillar (PPL) used to assist the depletion of the N-drift region is as close as possible to the highly doped substrate so that the depletable N-type drift region is long.

[0004] However, in the current ion implantation step in the deep implantation region, an additional layer is introduced for PPL implantation. This can be understood as the current deep implantation region requiring a separate mask layer and photomask. However, the implantation of the additional layer increases the manufacturing cost, reducing the advantages of superjunctions. In addition, current superjunction-trench gate devices also have problems such as insufficient breakdown voltage (BV) and large chip area. Summary of the Invention

[0005] This application provides a superjunction trench gate MOSFET layout structure and its fabrication method, which can solve at least one of the following problems: high manufacturing cost, cumbersome manufacturing process, insufficient breakdown voltage (BV), and large chip area occupied by superjunction trench gate devices.

[0006] On one hand, embodiments of this application provide a superjunction trench gate MOSFET layout structure, including:

[0007] A substrate having an epitaxial layer formed on its front side, wherein the epitaxial layer includes: a source lead-out region, a gate lead-out region surrounding the source lead-out region, and a peripheral terminal region surrounding the gate lead-out region;

[0008] Multiple trenches, the trenches being located within the epitaxial layer;

[0009] A gate dielectric layer, the gate dielectric layer covering the bottom wall and sidewalls of the trench;

[0010] Multiple main gates, the main gates covering the gate dielectric layer of the source terminal lead-out region and filling the corresponding trenches, the main gates being spaced apart along a first direction and parallel to a second direction, the first direction and the second direction being perpendicular to each other;

[0011] A first auxiliary gate, the first auxiliary gate covering a portion of the gate dielectric layer of the gate lead-out region and filling the corresponding trench, the first auxiliary gate being located on one side of the source lead-out region along a first direction;

[0012] A plurality of second auxiliary gates are arranged in a ring shape, the second auxiliary gates covering the remaining gate dielectric layer of the gate lead-out region and filling the corresponding trenches, the second auxiliary gates being spaced apart around the gate lead-out region, wherein the main gate, the first auxiliary gate and the second auxiliary gate are interconnected through the trenches;

[0013] Multiple dummy gates arranged in a ring shape, the dummy gates covering the gate dielectric layer of the peripheral terminal region and filling the corresponding trenches, the dummy gates being arranged at intervals around the center of the substrate;

[0014] A body region, wherein the body region is located in the epitaxial layer between the trenches and is close to the surface of the epitaxial layer;

[0015] A source doped region, wherein the source doped region is located on the surface of the body region on the main gate side;

[0016] An interlayer dielectric layer covers the epitaxial layer, the main gate, the first auxiliary gate, the second auxiliary gate, and the dummy gate;

[0017] A plurality of first conductive plugs are located in the body region between the main gates;

[0018] A plurality of second conductive plugs are located in the first auxiliary gate and in the body region between the first auxiliary gate;

[0019] A plurality of third conductive plugs arranged in a ring shape, the third conductive plugs being located in the second auxiliary gate;

[0020] A plurality of fourth conductive plugs arranged in a ring shape, wherein the fourth conductive plugs are respectively located in the body region on each of the dummy gate sides;

[0021] The deep injection region is located in the epitaxial layer from the bottom of the first conductive plug, the second conductive plug to the bottom of the fourth conductive plug;

[0022] A first conductive layer covers a portion of the first conductive plug in the source lead-out region to lead out the source doped region;

[0023] A second conductive layer covers a portion of the second conductive plug and a portion of the third conductive plug in the gate lead-out region to lead out the main gate in the source lead-out region.

[0024] Optionally, in the superjunction trench gate MOSFET layout structure, the outer edge of the second conductive layer is located at the midpoint of the region between the third conductive plug in the outermost second auxiliary gate of the gate lead-out region and the fourth conductive plug at the innermost peripheral terminal region.

[0025] Optionally, in the superjunction trench gate MOSFET layout structure, the first auxiliary gate includes: two first trench gates arranged parallel to the first direction and along the second direction, a plurality of second trench gates arranged parallel to the second direction and spaced apart along the first direction, and a plurality of third trench gates arranged parallel to the second direction and spaced apart along the first direction. The two first trench gates are respectively located at both ends of the plurality of second trench gates to form a closed structure, and the third trench gates are located on both sides of the closed structure along the second direction so that the closed structure is connected to the second auxiliary gate.

[0026] Optionally, in the superjunction trench gate MOSFET layout structure, the closed structure and the second conductive plugs in the closed structure constitute a charge balance structure, wherein, in the closed structure, the two outermost second conductive plugs parallel to the second direction are connected to the second conductive plugs parallel to the first direction in the first trench gate; the second conductive plugs parallel to the second direction inside the closed structure are not connected to the second conductive plugs parallel to the first direction in the first trench gate.

[0027] Optionally, in the superjunction trench gate MOSFET layout structure, along the first direction, the inner edge of the second conductive layer is located at the middle position of the region between the two second auxiliary gates near the source lead-out region; along the second direction, a portion of the inner edge of the second conductive layer is located on the second conductive plug in the second trench gate, and the portion of the inner edge of the second conductive layer does not cover both ends of the second conductive plug in the second trench gate; the remaining inner edge of the second conductive layer covers the innermost third conductive plug.

[0028] Optionally, in the superjunction trench gate MOSFET layout structure, the second trench gate closest to the source terminal lead-out region has a lateral dimension in width that is greater than or equal to the lateral dimension in width of the remaining second trench gates.

[0029] Optionally, in the superjunction trench gate MOSFET layout structure, the second trench gate closest to the source lead-out region has a lateral dimension in width that is larger than the lateral dimension in width of the second conductive plug.

[0030] Optionally, in the superjunction trench gate MOSFET layout structure, the conductivity type of the ions doped in the substrate, the epitaxial layer, and the source doped region is a first conductivity type; the conductivity type of the ions doped in the deep implantation region and the body region is a second conductivity type.

[0031] Optionally, in the superjunction trench gate MOSFET layout structure, the superjunction trench gate MOSFET layout structure further includes: a heavily doped region, the heavily doped region being located in the body region between the first conductive plug and the deep implantation region, in the body region between the second conductive plug and the deep implantation region, between the third conductive plug and the second auxiliary gate, and in the body region between the fourth conductive plug and the deep implantation region.

[0032] On the other hand, embodiments of this application also provide a method for fabricating a superjunction trench gate MOSFET layout structure, including:

[0033] A substrate is provided, wherein an epitaxial layer is formed on the front side of the substrate, wherein the epitaxial layer includes: a source terminal lead-out region, a gate terminal lead-out region disposed around the source terminal lead-out region, and a peripheral terminal region disposed around the gate terminal lead-out region;

[0034] Multiple trenches are formed, and the trenches are located in the epitaxial layer;

[0035] A gate dielectric layer is formed, which covers the bottom and sidewalls of the trench;

[0036] The system comprises multiple main gates, a first auxiliary gate, multiple second auxiliary gates arranged in a ring, and multiple dummy gates arranged in a ring. The main gates cover the gate dielectric layer of the source terminal lead-out region and fill corresponding trenches. The main gates are spaced apart along a first direction and parallel to a second direction, which are perpendicular to each other. The first auxiliary gates cover a portion of the gate dielectric layer of the gate terminal lead-out region and fill corresponding trenches. The first auxiliary gates are located on one side of the source terminal lead-out region along the first direction. The second auxiliary gates cover the remaining gate dielectric layer of the gate terminal lead-out region and fill corresponding trenches. The second auxiliary gates are spaced apart around the gate terminal lead-out region. The main gates, the first auxiliary gates, and the second auxiliary gates are interconnected through the trenches. The dummy gates cover the gate dielectric layer of the peripheral terminal region and fill corresponding trenches. The dummy gates are spaced apart around the center of the substrate.

[0037] A global ion implantation process is performed to form a body region located in the epitaxial layer between the trenches and close to the surface of the epitaxial layer;

[0038] A selective ion implantation process is performed to form a source doped region located on the surface of the body region on the main gate side;

[0039] An interlayer dielectric layer is formed, which covers the epitaxial layer, the main gate, the first auxiliary gate, the second auxiliary gate, and the dummy gate;

[0040] A first contact hole, a second contact hole, a third contact hole, and a fourth contact hole in an annular shape are formed, wherein the first contact hole penetrates the interlayer dielectric layer and the body region located between the main gates, the second contact hole penetrates the interlayer dielectric layer and is located in the first auxiliary gate, the third contact hole penetrates the interlayer dielectric layer and is located in the second auxiliary gate, and the fourth contact hole penetrates the interlayer dielectric layer and is located in the body region located between adjacent dummy gates;

[0041] A deep injection region is formed, which is located in the epitaxial layer from the bottom of the first contact hole, the second contact hole to the fourth contact hole;

[0042] A first conductive plug, a second conductive plug, a third conductive plug, and a plurality of fourth conductive plugs in an annular shape are formed, wherein the first conductive plug fills the first contact hole, the second conductive plug fills the second contact hole, the third conductive plug fills the third contact hole, and the fourth conductive plug fills the fourth contact hole;

[0043] A first conductive layer and a second conductive layer are formed. The first conductive layer covers a portion of the first conductive plug in the source terminal lead-out region to lead out the source doped region. The second conductive layer covers a portion of the second conductive plug and a portion of the third conductive plug in the gate terminal lead-out region to lead out the main gate in the source terminal lead-out region.

[0044] Optionally, in the method for fabricating the superjunction trench gate MOSFET layout structure, the outer edge of the second conductive layer is formed at the midpoint of the region between the third conductive plug in the outermost second auxiliary gate of the gate lead-out region and the fourth conductive plug in the innermost peripheral terminal region.

[0045] Optionally, in the fabrication method of the superjunction trench gate MOSFET layout structure, the first auxiliary gate includes: two first trench gates arranged parallel to the first direction and along the second direction, a plurality of second trench gates arranged parallel to the second direction and spaced apart along the first direction, and a plurality of third trench gates arranged parallel to the second direction and spaced apart along the first direction, wherein the two first trench gates are respectively located at both ends of the plurality of second trench gates to form a closed structure, and the third trench gates are located on both sides of the closed structure along the second direction so that the closed structure is connected to the second auxiliary gate.

[0046] Optionally, in the fabrication method of the superjunction trench gate MOSFET layout structure, the closed structure and the second conductive plugs in the closed structure constitute a charge balance structure, wherein, in the closed structure, the two outermost second conductive plugs parallel to the second direction are connected to the second conductive plugs parallel to the first direction in the first trench gate; the second conductive plugs parallel to the second direction inside the closed structure are not connected to the second conductive plugs parallel to the first direction in the first trench gate.

[0047] Optionally, in the method for fabricating the superjunction trench gate MOSFET layout structure, along the first direction, the inner edge of the second conductive layer is located at the middle position of the region between the two second auxiliary gates near the source lead-out region; along the second direction, a portion of the inner edge of the second conductive layer is located on the second conductive plug in the second trench gate, and the portion of the inner edge of the second conductive layer does not cover both ends of the second conductive plug in the second trench gate; the remaining inner edge of the second conductive layer covers the innermost third conductive plug.

[0048] Optionally, in the fabrication method of the superjunction trench gate MOSFET layout structure, the lateral dimension of the second trench gate closest to the source terminal lead-out region is greater than or equal to the lateral dimension of the remaining second trench gates.

[0049] The technical solution of this application has at least the following advantages:

[0050] First, by designing the deep injection region at the bottom of the first conductive plug (first contact hole), the bottom of the second conductive plug (second contact hole), the bottom of the third conductive plug (third contact hole), and the bottom of the fourth conductive plug (fourth contact hole), the deep injection region can be completed using the photomask used to prepare all the contact holes (first to fourth contact holes), saving photomasks, simplifying the preparation process, and reducing manufacturing costs.

[0051] Secondly, this application sets the dummy gate, the fourth conductive plug in the peripheral terminal region, and the second auxiliary gate and the third conductive plug in the gate lead-out region as a continuous ring structure. The ring-shaped dummy gate and the second auxiliary gate do not need to be disconnected, which avoids the problem of charge balance shift in the device and improves the breakdown voltage of the device.

[0052] Third, this application achieves a better charge balance effect by disconnecting the second conductive plug parallel to the second direction inside the closed structure from the second conductive plug parallel to the first direction in the first trench gate.

[0053] Fourth, the outer edge of the second conductive layer is placed at the midpoint between the third conductive plug in the second auxiliary gate at the outermost edge of the gate lead-out region and the fourth conductive plug at the innermost edge of the peripheral terminal region. Additionally, a portion of the inner edge of the second conductive layer along the longitudinal direction is placed on the second conductive plug in the second trench gate. Specifically, the inner edge of the second conductive layer does not cover both ends of the second conductive plug in the second trench gate, thus exposing both ends of the second conductive plug in the second trench gate. This optimizes the design window for the second conductive layer and the contact hole process, improving the yield of the fabrication process for the superjunction trench gate MOSFET layout structure.

[0054] Fifth, the second trench gate closest to the source terminal lead-out area has a lateral dimension in width that is greater than or equal to the lateral dimension in width of the other second trench gates to its left, and the lateral dimension in width of the second trench gate closest to the source terminal lead-out area is greater than the lateral dimension in width of the second conductive plug. This means that the second trench gate needs to cover the second contact hole / second conductive plug / deep injection area in the process. For small-sized devices, this design allows the second trench gate closest to the source terminal lead-out area to be merged with its adjacent trench, taking into account the trench-to-trench design rules in the process, while achieving isolation between the deep injection area and the body area below the trench, thus achieving better charge balance requirements. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0056] Figure 1 This is a top view of a semiconductor structure with an epitaxial layer formed according to an embodiment of the present invention;

[0057] Figure 2 This is along the NN' direction in the embodiments of the present invention. Figure 1 A cross-sectional view of the semiconductor structure shown;

[0058] Figure 3 This is a top view of the semiconductor structure after the first to fourth conductive plugs are formed according to an embodiment of the present invention;

[0059] Figure 4 This is an embodiment of the invention along the LL' direction. Figure 3 A partial cross-sectional view of the semiconductor structure shown;

[0060] Figure 5This is an embodiment of the invention along the MM' direction. Figure 3 A partial cross-sectional view of the semiconductor structure shown;

[0061] Figure 6 This is a partial top view of a semiconductor structure having a first auxiliary gate and a second conductive plug according to an embodiment of the present invention;

[0062] Figure 7 This is a top view of the semiconductor structure after the formation of the first conductive layer and the second conductive layer in an embodiment of the present invention;

[0063] The reference numerals in the attached figures are explained as follows:

[0064] A - Peripheral terminal area, B - Gate terminal lead-out area, C - Source terminal lead-out area;

[0065] 101-Substrate, 102-Epipolar layer, 103-Deep implantation region, 104-Gate dielectric layer, 105-Main gate, 205-First auxiliary gate, 2051-First trench gate, 2052-Second trench gate, 2053-Third trench gate, 305-Second auxiliary gate, 405-Dummy gate, 106-Bulk region, 107-Source doped region, 108-Heavily doped region, 109-First conductive plug, 209-Second conductive plug, 309-Third conductive plug, 409-Fourth conductive plug, 110-Interlayer dielectric layer, 111-First conductive layer, 112-Second conductive layer. Detailed Implementation

[0066] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0067] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0068] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0069] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0070] This application provides a superjunction trench gate MOSFET layout structure, which includes: a substrate 101, an epitaxial layer 102, multiple trenches, a gate dielectric layer 104, multiple main gates 105, a first auxiliary gate 205, multiple annular second auxiliary gates 305, multiple annular dummy gates 405, a body region 106, a source doped region 107, an interlayer dielectric layer 110, multiple first conductive plugs 109, multiple second conductive plugs 209, multiple annular third conductive plugs 309, multiple annular fourth conductive plugs 409, a deep implantation region 103, a first conductive layer 111, and a second conductive layer 112, etc.

[0071] refer to Figure 1 and Figure 2 , Figure 1 This is a top view of a semiconductor structure with an epitaxial layer formed according to an embodiment of the present invention. Figure 2 This is along the NN' direction in the embodiments of the present invention. Figure 1 The cross-sectional view of the semiconductor structure shown shows that the epitaxial layer 102 is formed on the front side of the substrate 101. The epitaxial layer 102 includes: a source terminal lead-out region C, a gate terminal lead-out region B surrounding the source terminal lead-out region C, and a peripheral terminal region A surrounding the gate terminal lead-out region B.

[0072] In this embodiment, the substrate 101 is made of silicon. In other embodiments, the substrate 101 may be made of silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI) or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements may include InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0073] In this embodiment, the ions doped in the substrate 101 have a first conductivity type, and the ions doped in the epitaxial layer 102 have a first conductivity type. This embodiment uses an N-channel superjunction trench gate MOSFET as an example; therefore, in this embodiment, the ions doped in the substrate 101 have an N-type conductivity type, and the ions doped in the epitaxial layer 102 have an N-type conductivity type.

[0074] refer to Figures 3-5 , Figure 3 This is a top view of the semiconductor structure after the first to fourth conductive plugs are formed according to an embodiment of the present invention. Figure 4 This is an embodiment of the invention along the LL' direction. Figure 3 The diagram shows a partial cross-sectional view of the semiconductor structure. Figure 5 This is an embodiment of the invention along the MM' direction. Figure 3 A partial cross-sectional view of the semiconductor structure shown. The trench is located in the epitaxial layer 102, and the trench is used to deposit the gate dielectric layer 104 and all trench gates (main gate 105, first auxiliary gate 205, a plurality of annular second auxiliary gates 305 and a plurality of annular dummy gates 405).

[0075] Furthermore, the gate dielectric layer 104 covers the bottom and sidewalls of the trench, and the material of the gate dielectric layer 104 may be silicon oxide. By encapsulating all trench gates with the gate dielectric layer 104, all trench gates (main gate 105, first auxiliary gate 205, a plurality of annular second auxiliary gates 305, and a plurality of annular dummy gates 405) are disconnected from their respective bottom deep implantation regions 103.

[0076] like Figure 4 As shown, a plurality of main gates 105 cover the gate dielectric layer 104 of the source lead-out region C and fill the corresponding trenches. The main gates 105 are arranged at intervals along a first direction (X direction) and parallel to a second direction (Y direction). The first direction (X direction) and the second direction (Y direction) are perpendicular to each other.

[0077] like Figure 3 As shown, the first auxiliary gate 205 covers part of the gate dielectric layer 104 of the gate lead-out region B and fills the corresponding trench. The first auxiliary gate 205 is located on one side of the source lead-out region C along the first direction (X direction, lateral direction). In this embodiment, the first auxiliary gate 205 is located on the left side of the source lead-out region C.

[0078] Better, for reference Figure 6 , Figure 6This is a partial top view of a semiconductor structure having a first auxiliary gate and a second conductive plug according to an embodiment of the present invention. The first auxiliary gate 205 includes: two first trench gates 2051 arranged parallel to a first direction (X direction) and along a second direction (Y direction), a plurality of second trench gates 2052 arranged parallel to the second direction and spaced apart along the first direction, and a plurality of third trench gates 2053 arranged parallel to the second direction and spaced apart along the first direction. The two first trench gates 2051 are respectively located at both ends of the plurality of second trench gates 2052 to form a closed structure. The third trench gates 2053 are located on both sides of the closed structure along the second direction so that the closed structure (first auxiliary gate 205) is connected to the second auxiliary gate 305.

[0079] Furthermore, the closed structure and the second conductive plug 209 within the closed structure constitute a charge balance structure. Specifically, in the closed structure, the two outermost second conductive plugs parallel to the second direction are connected to the second conductive plug parallel to the first direction in the first trench gate 2051. As shown by the dashed circle a, the second conductive plug 209 parallel to the second direction inside the closed structure is not connected to the second conductive plug parallel to the first direction in the first trench gate 2051. This application achieves a better charge balance effect by disconnecting the second conductive plug parallel to the second direction inside the closed structure from the second conductive plug parallel to the first direction in the first trench gate.

[0080] Preferably, as shown by the dashed circle b, the second trench gate 2052 closest to the source end lead-out region has a lateral dimension in width that is greater than or equal to the lateral dimension in width of the other second trench gates 2052 to its left.

[0081] Preferably, as shown by the dashed circle b, the lateral dimension of the second trench gate 2052 closest to the source lead-out region is larger than the lateral dimension of the second conductive plug 209. That is, the width of the second trench gate 2052 needs to cover the second contact hole / second conductive plug 209 / deep injection region 103 in the manufacturing process. For small-sized devices, this design allows the second trench gate 2052 closest to the source lead-out region and its adjacent trenches (see details) to be more compact. Figure 6 The positions circled by the dashed line (b) are combined together, taking into account the design rules between trenches in the process, while also achieving isolation between the deep injection area and the body area below the trench, thus achieving better charge balance requirements.

[0082] like Figure 3 and Figure 4As shown, a plurality of annular second auxiliary gates 305 cover the remaining gate dielectric layer of the gate lead-out region B and fill the corresponding trenches. The second auxiliary gates 305 are spaced apart around the gate lead-out region B. In this embodiment, the plurality of second auxiliary gates 305 are arranged in a concentric square annular shape within the gate lead-out region B. The main gate 105, the first auxiliary gate 205, and the second auxiliary gates 305 are interconnected through the trenches.

[0083] like Figure 3 and Figure 4 As shown, a plurality of ring-shaped dummy gates 405 cover the gate dielectric layer 104 of the peripheral terminal region A and fill the corresponding trenches. The dummy gates 405 are arranged at intervals around the center of the substrate 101.

[0084] In this embodiment, the main gate 105, the first auxiliary gate 205, the second auxiliary gate 305, and the dummy gate 405 can be made of polysilicon. In this embodiment, P-type heavy doping is also implanted into the doped polysilicon in part of the trench gate. However, since the concentration of N-type heavy doped polysilicon is higher, the subsequently implanted heavy doped region 107 will not invert the N-type heavy doped polysilicon trench gate.

[0085] In this application, by setting the dummy gate 405 and the fourth conductive plug 409 in the peripheral terminal region A and the second auxiliary gate 305 and the third conductive plug 309 in the gate lead-out region B as continuous ring structures, the ring-shaped dummy gate 405 and the second auxiliary gate 305 do not need to be disconnected, thus avoiding the problem of charge balance shift in the device and improving the breakdown voltage of the device.

[0086] Furthermore, the body region 106 is located in the epitaxial layer 102 between the trenches and close to the surface of the epitaxial layer 102. The conductivity type of the ions doped in the body region 106 is the second conductivity type. In this embodiment, the conductivity type of the ions doped in the body region 106 is P-type.

[0087] Preferably, the source doped region 108 is located on the surface of the body region 106 on the side of the main gate 105. The conductivity type of the ions doped in the source doped region 108 is the same as the conductivity type of the ions doped in the epitaxial layer. In this embodiment, the conductivity type of the ions doped in the source doped region 108 is N-type.

[0088] Furthermore, the interlayer dielectric layer 110 covers the epitaxial layer 102, the main gate 105, the first auxiliary gate 205, the second auxiliary gate 305, and the dummy gate 405.

[0089] Preferably, the superjunction trench gate MOSFET layout structure may further include: a first contact hole, a second contact hole, an annular third contact hole, and an annular fourth contact hole. The first contact hole penetrates the interlayer dielectric layer 110 and the body region 106 located between the main gate 105; the second contact hole penetrates the interlayer dielectric layer 110 and the body region 106 located between the first auxiliary gate 205 or the first auxiliary gate 205; the third contact hole penetrates the interlayer dielectric layer 110 and is located in the second auxiliary gate 305; and the fourth contact hole penetrates the interlayer dielectric layer 110 and is located in the body region between adjacent dummy gates 405 (or, each of the fourth contact holes is located in the body region 106 on the side of each dummy gate 405). The first contact hole, the second contact hole, the annular third contact hole, and the annular fourth contact hole may be formed simultaneously for subsequent formation of the first to fourth conductive plugs 109.

[0090] Preferred, such as Figure 4 and Figure 5 As shown, after forming the first contact hole, the second contact hole, the annular third contact hole, and the annular fourth contact hole, an ion implantation process is performed to obtain the deep implantation region 103 at the bottom of the first contact hole, the bottom of the second contact hole, the bottom of the annular third contact hole, and the bottom of the annular fourth contact hole. Figure 4 As shown, in the source lead-out region C, the deep implantation region 103 is located at the bottom of the source doped region 108. In the gate lead-out region B, the deep implantation region 103 is located at the bottom of the second auxiliary gate 305. The depth of the second auxiliary gate 305 is greater than the implantation depth of the body region 106. The body region 106 is isolated into an independent floating body block by the second auxiliary gate 305 and the deep implantation region 103, which improves the breakdown voltage performance of the gate lead-out region B and enhances the electrical performance of the device.

[0091] The conductivity type of the ions doped in the deep implantation region 103 is the same as that of the ions doped in the body region 106. The conductivity type of the ions doped in the deep implantation region 103 is the second conductivity type. In this embodiment, the conductivity type of the ions doped in the deep implantation region 103 is P-type.

[0092] In this application, by designing the deep injection region 103 at the bottom of the first contact hole, the bottom of the second contact hole, the bottom of the third contact hole, and the bottom of the fourth contact hole, the injection of the deep injection region 103 can be completed using the photomask used to prepare all the contact holes (first to fourth contact holes), saving photomasks, simplifying the preparation process, and reducing manufacturing costs.

[0093] Preferred, such as Figure 4 and Figure 5As shown, the superjunction trench gate MOSFET layout structure may further include a heavily doped region 107, which is located in the body region 106 at the bottom of the first contact hole, the bottom of the second contact hole, the bottom of the annular third contact hole, and the bottom of the annular fourth contact hole. Specifically, the heavily doped region 107 is located in the body region 106 between the first conductive plug 109 and the deep implantation region 103, in the body region between the second conductive plug 209 and the deep implantation region 103, between the third conductive plug 309 and the second auxiliary gate 305, and in the body region between the fourth conductive plug 409 and the deep implantation region 103.

[0094] In this embodiment, the heavily doped region 107 and the source doped region 108 in the source lead-out region C are subsequently shorted and led out through the first conductive plug 109 / first conductive layer 111.

[0095] Furthermore, such as Figure 3 As shown, the first conductive plug 109 is located in the body region 106 between the main gates 105; the second conductive plug 209 is located in the first auxiliary gate 205 and the body region 106 between the first auxiliary gate 205; a plurality of annular third conductive plugs 309 are located in the annular second auxiliary gate 305; and a plurality of annular fourth conductive plugs 409 are respectively located in the body region 106 on each side of the dummy gate 405.

[0096] Better, for reference Figure 7 , Figure 7 This is a top view of the semiconductor structure after the formation of the first conductive layer and the second conductive layer in an embodiment of the present invention. The first conductive layer 111 covers a portion of the first conductive plug 109 in the source lead-out region C to lead out the source doped region 108; the second conductive layer 112 covers a portion of the second conductive plug 209 and a portion of the third conductive plug 309 in the gate lead-out region B to lead out the main gate 105 in the source lead-out region C.

[0097] Better, such as Figure 4 and Figure 7 As shown, the outer edge of the second conductive layer 112 is located in the middle of the region between the third conductive plug 309 in the outermost second auxiliary gate 305 of the gate lead-out region B and the fourth conductive plug 409 in the innermost peripheral terminal region C. Further, as... Figure 4 and Figure 7As shown, along the first direction (lateral, X direction), the inner edge of the second conductive layer 112 is located in the middle of the region between the two second auxiliary gates 305 near the source lead-out region B; along the second direction (longitudinal, Y direction), a portion of the inner edge of the second conductive layer 112 is located on the second conductive plug 209 in the second trench gate 2052, and the portion of the inner edge of the second conductive layer 112 does not cover both ends of the second conductive plug 209 in the second trench gate 2052, that is, a portion of the inner edge of the second conductive layer 112 retreats into the interior of the charge balance structure; the remaining inner edge of the second conductive layer 112 covers the innermost third conductive plug 309, that is, the remaining inner edge of the second conductive layer 112 is located in the middle of the region between the third conductive plug 309 in the innermost second auxiliary gate 305 and the outermost second conductive plug 209.

[0098] In this application, the outer edge of the second conductive layer 112 is placed at the midpoint between the third conductive plug 309 in the outermost second auxiliary gate 305 of the gate lead-out region B and the fourth conductive plug 409 in the innermost peripheral terminal region A. Additionally, a portion of the inner edge of the second conductive layer 112 along the longitudinal direction is placed on the second conductive plug 209 in the second trench gate 2052. That is, a portion of the inner edge of the second conductive layer 112 does not cover both ends of the second conductive plug 209 in the second trench gate 2052, deliberately exposing both ends of the second conductive plug 209 in the second trench gate 2052. This optimizes the design window for the second conductive layer 112 / first conductive layer 111 and the contact hole process, improving the yield of the fabrication process for the superjunction trench gate MOSFET layout structure.

[0099] Based on the same inventive concept, this application also provides a method for fabricating a superjunction trench gate MOSFET layout structure, including:

[0100] First step: Provide a substrate 101, such as Figure 1 and Figure 2 As shown, an epitaxial layer 102 is formed on the front side of the substrate 101, wherein the epitaxial layer 102 includes: a source lead-out region C, a gate lead-out region B surrounding the source lead-out region C, and a peripheral terminal region A surrounding the gate lead-out region B.

[0101] Second step: As Figure 3-5 As shown, multiple trenches are formed in the epitaxial layer 102. The trenches are used to deposit the gate dielectric layer 104 and all the trench gates (main gate 105, first auxiliary gate 205, multiple second auxiliary gates 305 in a ring, and multiple dummy gates 405 in a ring).

[0102] Third step: Forming a gate dielectric layer 104, which covers the bottom and sidewalls of the trench.

[0103] Fourth step: Forming multiple main gates 105, first auxiliary gates 205, multiple annular second auxiliary gates 305, and multiple annular dummy gates 405, wherein the main gates 105 cover the gate dielectric layer 104 of the source lead-out region and fill the corresponding trenches, the main gates 105 are spaced apart along the first direction (X direction) and parallel to the second direction (Y direction); the first auxiliary gates 205 cover part of the gate dielectric layer 104 of the gate lead-out region B and fill the corresponding trenches, the first auxiliary gates 205 are located on one side of the source lead-out region C along the first direction (X direction, lateral direction), in this embodiment, the first auxiliary gates 205 are located on the left side of the source lead-out region C; the multiple annular second auxiliary gates 305 cover the remaining gate dielectric layer of the gate lead-out region B and fill the corresponding trenches, the second auxiliary gates 305 are spaced apart around the gate lead-out region B, and the dummy gates 405 are spaced apart around the center of the substrate 101.

[0104] The main gate 105, the first auxiliary gate 205, and the second auxiliary gate 305 are interconnected through the trench.

[0105] Better, such as Figure 6 As shown, the first auxiliary gate 205 includes: two first trench gates 2051 arranged parallel to the first direction (X direction) and along the second direction (Y direction), a plurality of second trench gates 2052 arranged parallel to the second direction and spaced apart along the first direction, and a plurality of third trench gates 2053 arranged parallel to the second direction and spaced apart along the first direction. The two first trench gates 2051 are respectively located at both ends of the plurality of second trench gates 2052 to form a closed structure. The third trench gates 2053 are located on both sides of the closed structure along the second direction so that the closed structure (first auxiliary gate 205) is connected to the second auxiliary gate 305.

[0106] Furthermore, the closed structure and the second conductive plug 209 within the closed structure constitute a charge balance structure. Specifically, in the closed structure, the two outermost second conductive plugs parallel to the second direction are connected to the second conductive plug parallel to the first direction in the first trench gate 2051. As shown by the dashed circle a, the second conductive plug 209 parallel to the second direction inside the closed structure is not connected to the second conductive plug parallel to the first direction in the first trench gate 2051. This application achieves a better charge balance effect by disconnecting the second conductive plug parallel to the second direction inside the closed structure from the second conductive plug parallel to the first direction in the first trench gate.

[0107] Preferably, as shown by the dashed circle b, the second trench gate 2052 closest to the source end lead-out region has a lateral dimension in width that is greater than or equal to the lateral dimension in width of the other second trench gates 2052 to its left.

[0108] Preferably, as shown by the dotted circle b, the lateral dimension of the second trench gate 2052 closest to the source end lead-out area is greater than the lateral dimension of the second conductive plug 209 in width. That is, the width of the second trench gate 2052 needs to cover the second contact hole / second conductive plug 209 / deep injection area 103 in terms of process.

[0109] Step 5: Perform a global ion implantation process to form a body region 106, which is located in the epitaxial layer 102 between the trenches and close to the surface of the epitaxial layer 102. This application utilizes a global ion implantation process to form the body region 106 in the source-end lead-out region C, the gate-end lead-out region B, and the peripheral terminal region A, reducing the number of photomasks required for body region ion implantation, simplifying the fabrication process, and lowering manufacturing costs.

[0110] Step 6: Perform selective ion implantation to form a source doped region 108, which is located on the body surface of the main gate 105.

[0111] Step 7: Form an interlayer dielectric layer 110, which covers the epitaxial layer 102, the main gate 105, the first auxiliary gate 205, the second auxiliary gate 305, and the dummy gate 405. Specifically, the material of the interlayer dielectric layer 110 can be silicon oxide.

[0112] Step 8: Forming a first contact hole, a second contact hole, a third contact hole, and a fourth contact hole in an annular shape. The first contact hole penetrates the interlayer dielectric layer 110 and the body region 106 located between the main gate 105. The second contact hole penetrates the interlayer dielectric layer 110 and the body region 106 located between the first auxiliary gate 205 or the first auxiliary gate 205. The third contact hole penetrates the interlayer dielectric layer 110 and is located in the second auxiliary gate 305. The fourth contact hole penetrates the interlayer dielectric layer 110 and is located in the body region between adjacent dummy gates 405 (or, each of the fourth contact holes is located in the body region 106 on the side of each dummy gate 405). The first contact hole, the second contact hole, the annular third contact hole, and the annular fourth contact hole can be formed simultaneously for subsequent formation of the first to fourth conductive plugs 109.

[0113] Step 9: Forming a deep implantation region 103. In the source lead-out region C, the deep implantation region 103 is formed at the bottom of the first contact hole (the source doped region 108); in the peripheral terminal region A, the deep implantation region 103 is formed at the bottom of the fourth contact hole. In the gate lead-out region B, the deep implantation region 103 is formed at the bottom of the third contact hole (the second auxiliary gate 305) or the bottom of the second contact hole. The depth of the second auxiliary gate 305 is greater than the implantation depth of the body region 106. The body region 106 is isolated into an independent floating body block by the second auxiliary gate 305 and the deep implantation region 103, improving the breakdown voltage performance of the gate lead-out region B and enhancing the electrical performance of the device.

[0114] Furthermore, before forming the first conductive plug, the second conductive plug, the third conductive plug, and the multiple annular fourth conductive plugs, the fabrication method of the superjunction trench gate MOSFET layout structure may further include: performing a selective ion implantation process to form a heavily doped region 107, wherein the heavily doped region 107 is located in the body region 106 at the bottom of the first contact hole, the bottom of the second contact hole, the bottom of the annular third contact hole, and the bottom of the annular fourth contact hole. That is, the heavily doped region 107 is located in the body region 106 between the first conductive plug 109 and the deep implantation region 103, in the body region between the second conductive plug 209 and the deep implantation region 103, between the third conductive plug 309 and the second auxiliary gate 305, and in the body region between the fourth conductive plug 409 and the deep implantation region 103.

[0115] Step 10: Form a first conductive plug 109, a second conductive plug 209, a third conductive plug 309, and a plurality of fourth conductive plugs 409 in an annular shape, wherein the first conductive plug 109 fills the first contact hole, the second conductive plug 209 fills the second contact hole, the third conductive plug 309 fills the third contact hole, and the fourth conductive plug 409 fills the fourth contact hole.

[0116] Step 11: As Figure 7 As shown, a first conductive layer 111 and a second conductive layer 112 are formed. The first conductive layer 111 covers a portion of the first conductive plug 109 in the source lead-out region C to lead out the source doped region 108. The second conductive layer 112 covers a portion of the second conductive plug 209 and a portion of the third conductive plug 309 in the gate lead-out region B to lead out the main gate 105 in the source lead-out region C.

[0117] Better, such as Figure 4 and Figure 7As shown, the outer edge of the second conductive layer 112 is located in the middle of the region between the third conductive plug 209 in the outermost second auxiliary gate 305 of the gate lead-out region B and the fourth conductive plug 409 in the innermost peripheral terminal region C. Further, as... Figure 4 and Figure 7 As shown, along the first direction (lateral, X direction), the inner edge of the second conductive layer 112 is located in the middle of the region between the two second auxiliary gates 305 near the source lead-out region B; along the second direction (longitudinal, Y direction), a portion of the inner edge of the second conductive layer 112 is located on the second conductive plug 209 in the second trench gate 2052, and the portion of the inner edge of the second conductive layer 112 does not cover both ends of the second conductive plug 209 in the second trench gate 2052, that is, a portion of the inner edge of the second conductive layer 112 retreats into the interior of the charge balance structure; the remaining inner edge of the second conductive layer 112 covers the innermost third conductive plug 309, that is, the remaining inner edge of the second conductive layer 112 is located in the middle of the region between the third conductive plug 309 in the innermost second auxiliary gate 305 and the outermost second conductive plug 209.

[0118] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A superjunction trench gate MOSFET layout structure, characterized in that, include: A substrate having an epitaxial layer formed on its front side, wherein the epitaxial layer includes: a source lead-out region, a gate lead-out region surrounding the source lead-out region, and a peripheral terminal region surrounding the gate lead-out region; Multiple trenches, the trenches being located within the epitaxial layer; A gate dielectric layer, the gate dielectric layer covering the bottom wall and sidewalls of the trench; Multiple main gates, the main gates covering the gate dielectric layer of the source terminal lead-out region and filling the corresponding trenches, the main gates being spaced apart along a first direction and parallel to a second direction, the first direction and the second direction being perpendicular to each other; A first auxiliary gate, the first auxiliary gate covering a portion of the gate dielectric layer of the gate lead-out region and filling the corresponding trench, the first auxiliary gate being located on one side of the source lead-out region along a first direction; A plurality of second auxiliary gates are arranged in a ring shape, the second auxiliary gates covering the remaining gate dielectric layer of the gate lead-out region and filling the corresponding trenches, the second auxiliary gates being spaced apart around the gate lead-out region, wherein the main gate, the first auxiliary gate and the second auxiliary gate are interconnected through the trenches; Multiple dummy gates arranged in a ring shape, the dummy gates covering the gate dielectric layer of the peripheral terminal region and filling the corresponding trenches, the dummy gates being arranged at intervals around the center of the substrate; A body region, wherein the body region is located in the epitaxial layer between the trenches and is close to the surface of the epitaxial layer; A source doped region, wherein the source doped region is located on the surface of the body region on the main gate side; An interlayer dielectric layer covers the epitaxial layer, the main gate, the first auxiliary gate, the second auxiliary gate, and the dummy gate; A plurality of first conductive plugs are located in the body region between the main gates; A plurality of second conductive plugs are located in the first auxiliary gate and in the body region between the first auxiliary gate; A plurality of third conductive plugs arranged in a ring shape, the third conductive plugs being located in the second auxiliary gate; A plurality of fourth conductive plugs arranged in a ring shape, wherein the fourth conductive plugs are respectively located in the body region on each of the dummy gate sides; The deep injection region is located in the epitaxial layer from the bottom of the first conductive plug, the second conductive plug to the bottom of the fourth conductive plug; A first conductive layer covers a portion of the first conductive plug in the source lead-out region to lead out the source doped region; A second conductive layer covers a portion of the second conductive plug and a portion of the third conductive plug in the gate lead-out region to lead out the main gate in the source lead-out region.

2. The superjunction trench gate MOSFET layout structure according to claim 1, characterized in that, The outer edge of the second conductive layer is located in the middle of the region between the third conductive plug in the second auxiliary gate at the outermost side of the gate lead-out region and the fourth conductive plug at the innermost side of the peripheral terminal region.

3. The superjunction trench gate MOSFET layout structure according to claim 1, characterized in that, The first auxiliary gate includes: two first trench gates arranged parallel to a first direction and along a second direction, a plurality of second trench gates arranged parallel to the second direction and spaced apart along the first direction, and a plurality of third trench gates arranged parallel to the second direction and spaced apart along the first direction. The two first trench gates are respectively located at both ends of the plurality of second trench gates to form a closed structure, and the third trench gates are located on both sides of the closed structure along the second direction so that the closed structure is connected to the second auxiliary gate.

4. The superjunction trench gate MOSFET layout structure according to claim 3, characterized in that, The closed structure and the second conductive plugs in the closed structure constitute a charge balance structure. In the closed structure, the two outermost second conductive plugs parallel to the second direction are connected to the second conductive plugs parallel to the first direction in the first trench gate. The second conductive plugs parallel to the second direction inside the closed structure are not connected to the second conductive plugs parallel to the first direction in the first trench gate.

5. The superjunction trench gate MOSFET layout structure according to claim 3, characterized in that, Along the first direction, the inner edge of the second conductive layer is located in the middle of the region between the two second auxiliary gates near the source lead-out region; along the second direction, a portion of the inner edge of the second conductive layer is located on the second conductive plug in the second trench gate, and the portion of the inner edge of the second conductive layer does not cover both ends of the second conductive plug in the second trench gate; the remaining inner edge of the second conductive layer covers the innermost third conductive plug.

6. The superjunction trench gate MOSFET layout structure according to claim 3, characterized in that, The second trench gate closest to the source end lead-out region has a lateral dimension in width that is greater than or equal to the lateral dimension in width of the remaining second trench gate.

7. The superjunction trench gate MOSFET layout structure according to claim 3, characterized in that, The second trench gate closest to the source end lead-out region has a lateral dimension in width that is greater than the lateral dimension in width of the second conductive plug.

8. The superjunction trench gate MOSFET layout structure according to claim 1, characterized in that, The conductivity type of the ions doped in the substrate, the epitaxial layer, and the source doped region is a first conductivity type; the conductivity type of the ions doped in the deep implantation region and the body region is a second conductivity type.

9. The superjunction trench gate MOSFET layout structure according to claim 1, characterized in that, The superjunction trench gate MOSFET layout structure further includes: a heavily doped region located in the body region between the first conductive plug and the deep implantation region, in the body region between the second conductive plug and the deep implantation region, between the third conductive plug and the second auxiliary gate, and in the body region between the fourth conductive plug and the deep implantation region.

10. A method for fabricating a superjunction trench gate MOSFET layout structure, characterized in that, include: A substrate is provided, wherein an epitaxial layer is formed on the front side of the substrate, wherein the epitaxial layer includes: a source terminal lead-out region, a gate terminal lead-out region disposed around the source terminal lead-out region, and a peripheral terminal region disposed around the gate terminal lead-out region; Multiple trenches are formed, and the trenches are located in the epitaxial layer; A gate dielectric layer is formed, which covers the bottom and sidewalls of the trench; The system comprises multiple main gates, a first auxiliary gate, multiple second auxiliary gates arranged in a ring, and multiple dummy gates arranged in a ring. The main gates cover the gate dielectric layer of the source terminal lead-out region and fill corresponding trenches. The main gates are spaced apart along a first direction and parallel to a second direction, which are perpendicular to each other. The first auxiliary gates cover a portion of the gate dielectric layer of the gate terminal lead-out region and fill corresponding trenches. The first auxiliary gates are located on one side of the source terminal lead-out region along the first direction. The second auxiliary gates cover the remaining gate dielectric layer of the gate terminal lead-out region and fill corresponding trenches. The second auxiliary gates are spaced apart around the gate terminal lead-out region. The main gates, the first auxiliary gates, and the second auxiliary gates are interconnected through the trenches. The dummy gates cover the gate dielectric layer of the peripheral terminal region and fill corresponding trenches. The dummy gates are spaced apart around the center of the substrate. A global ion implantation process is performed to form a body region located in the epitaxial layer between the trenches and close to the surface of the epitaxial layer; A selective ion implantation process is performed to form a source doped region located on the surface of the body region on the main gate side; An interlayer dielectric layer is formed, which covers the epitaxial layer, the main gate, the first auxiliary gate, the second auxiliary gate, and the dummy gate; A first contact hole, a second contact hole, a third contact hole, and a fourth contact hole in an annular shape are formed, wherein the first contact hole penetrates the interlayer dielectric layer and the body region located between the main gates, the second contact hole penetrates the interlayer dielectric layer and is located in the first auxiliary gate, the third contact hole penetrates the interlayer dielectric layer and is located in the second auxiliary gate, and the fourth contact hole penetrates the interlayer dielectric layer and is located in the body region located between adjacent dummy gates; A deep injection region is formed, which is located in the epitaxial layer from the bottom of the first contact hole, the second contact hole to the fourth contact hole; A first conductive plug, a second conductive plug, a third conductive plug, and a plurality of fourth conductive plugs in an annular shape are formed, wherein the first conductive plug fills the first contact hole, the second conductive plug fills the second contact hole, the third conductive plug fills the third contact hole, and the fourth conductive plug fills the fourth contact hole; A first conductive layer and a second conductive layer are formed. The first conductive layer covers a portion of the first conductive plug in the source terminal lead-out region to lead out the source doped region. The second conductive layer covers a portion of the second conductive plug and a portion of the third conductive plug in the gate terminal lead-out region to lead out the main gate in the source terminal lead-out region.

11. The method for fabricating the superjunction trench gate MOSFET layout structure according to claim 10, characterized in that, The outer edge of the second conductive layer is formed at the midpoint of the region between the third conductive plug in the outermost second auxiliary gate of the gate lead-out region and the fourth conductive plug in the innermost peripheral terminal region.

12. The method for fabricating the superjunction trench gate MOSFET layout structure according to claim 10, characterized in that, The first auxiliary gate includes: two first trench gates arranged parallel to a first direction and along a second direction, a plurality of second trench gates arranged parallel to the second direction and spaced apart along the first direction, and a plurality of third trench gates arranged parallel to the second direction and spaced apart along the first direction. The two first trench gates are respectively located at both ends of the plurality of second trench gates to form a closed structure, and the third trench gates are located on both sides of the closed structure along the second direction so that the closed structure is connected to the second auxiliary gate.

13. The method for fabricating the superjunction trench gate MOSFET layout structure according to claim 12, characterized in that, The closed structure and the second conductive plugs in the closed structure constitute a charge balance structure. In the closed structure, the two outermost second conductive plugs parallel to the second direction are connected to the second conductive plugs parallel to the first direction in the first trench gate. The second conductive plugs parallel to the second direction inside the closed structure are not connected to the second conductive plugs parallel to the first direction in the first trench gate.

14. The method for fabricating the superjunction trench gate MOSFET layout structure according to claim 12, characterized in that, Along the first direction, the inner edge of the second conductive layer is located in the middle of the region between the two second auxiliary gates near the source lead-out region; along the second direction, a portion of the inner edge of the second conductive layer is located on the second conductive plug in the second trench gate, and the portion of the inner edge of the second conductive layer does not cover both ends of the second conductive plug in the second trench gate; the remaining inner edge of the second conductive layer covers the innermost third conductive plug.

15. The method for fabricating the superjunction trench gate MOSFET layout structure according to claim 12, characterized in that, The second trench gate closest to the source end lead-out region has a lateral dimension in width that is greater than or equal to the lateral dimension in width of the remaining second trench gate.

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