An N-type TopCon bifacial cell structure and its preparation method

Abstract

The present invention relates to an N-type TopCon bifacial cell structure and a preparation method thereof. The cell structure from top to bottom is as follows: front grid lines, SiC<subgt;x< / subgt;O<subgt;y< / subgt> layer, TCO layer, polysilicon passivation layer P<supgt;++< / supgt>, boron diffusion layer P<supgt;+< / supgt>, N-type crystalline silicon substrate, silicon dioxide tunneling layer, polysilicon passivation layer N<supgt;++< / supgt>, TCO layer, SiC<subgt;x< / subgt>O<subgt;y< / subgt> layer, and back grid lines; the preparation method includes double-sided texturing and cleaning, front boron diffusion for junction formation, back tunneling silicon dioxide layer formation, back phosphorus-doped amorphous silicon layer formation, front boron-doped amorphous silicon layer formation, high-temperature annealing, plasma hydrogen passivation, double-sided preparation of fluorine-doped tin oxide layer TCO film, double-sided deposition of antireflection and antireflection film, screen printing and sintering. The present invention adopts an electrode structure with double conductive media, has a higher one-dimensional carrier transport rate, small conductance loss, and at the same time takes into account good surface and electric field passivation performance, and can better reduce two kinds of burn-through phenomena in the processes of amorphous silicon annealing and grid line preparation.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic power generation, and particularly relates to an N-type TopCon bifacial cell structure and a preparation method thereof. Background Art

[0002] Photovoltaic power generation has become one of the cleanest energy sources with the lowest cost and the best safety and environmental protection in the world. In the future, with the continuous adjustment of the energy structure of various countries, the proportion of renewable energy in energy consumption is bound to be higher and higher. Among many types of renewable energy, photovoltaic power generation technology has the greatest potential for cost reduction and efficiency improvement.

[0003] Currently, commercially available high-efficiency crystalline silicon cells are mainly divided into perc, TopCon, IBC, and HJT according to their structures. Comparatively speaking, the biggest advantage of Topcon-structured cells lies in their highest potential efficiency, which is closest to the theoretical limit efficiency of crystalline silicon cells. Therefore, the industry has great hopes for it, and the TOPCon-structured cells have also become one of the key research directions for current industrialized high-efficiency solar cells. However, restricted by various factors such as production process design, the passivation contact technology on the front surface of Topcon cells is not clear. Although the passivation contact technology on the back surface has been applied, the effect is not ideal and is still in continuous technical exploration. In addition, problems such as high recombination caused by the contact between metal grid lines and semiconductors have not been well solved, resulting in the potential efficiency of TopCon-structured cells not being well exerted. Summary of the Invention

[0004] In order to effectively improve the passivation contact effect of bifacial cells, increase the carrier lifetime, and greatly reduce the internal resistance and improve the carrier mobility, the present invention proposes an N-type TopCon bifacial cell structure and a preparation method thereof.

[0005] An N-type TopCon bifacial cell structure, from top to bottom: front grid lines, SiCxOy layer, TCO layer, polysilicon passivation layer P ++ , boron diffusion layer P + , N-type crystalline silicon substrate, silicon dioxide tunneling layer, polysilicon passivation layer N ++ , TCO layer, SiCxOy layer, and back grid lines.

[0006] Preferably, the boron doping concentration of the polysilicon passivation layer P ++ is 7×10 15 ~9×10 15 cm -3 , and the thickness is 40~70nm. The phosphorus doping concentration of the polysilicon passivation layer N ++ is 5×10 15 ~6×10 15 cm -3, with a thickness of 90 - 120 nm.

[0007] Preferably, the thickness of the silicon dioxide tunneling layer is 1 - 2 nm; the thickness of the TCO layer is 800 - 950 nm; the SiC x O y layer has a thickness of 75 - 85 nm and a refractive index of 1.71 - 1.74; the TCO layer has a refractive index of 2.0 - 2.2 and a sheet resistance of 8.5 - 10 Ω / cm 2 .

[0008] The preparation method of the present invention includes the following steps:

[0009] (1) Surface texturing and cleaning. First, put the silicon wafer into a concentrated alkali solution for rough etching, then transfer it to a dilute alkali solution for fine etching. After forming a textured surface, clean the silicon wafer;

[0010] (2) Diffusion junction formation. Put the silicon wafer after step (1) into a tube diffusion furnace, heat it up in a nitrogen atmosphere, and introduce nitrogen, oxygen, and BBr3 to perform boron doping diffusion and propulsion on the front side of the silicon substrate to form a boron diffusion layer P + ;

[0011] (3) Back tunneling layer formation. First, put the silicon wafer after step (2) into a mixed solution of hydrogen fluoride and hydrogen chloride for etching to remove BSG (borosilicate glass) and the side and back wrap-around coatings, and then perform shallow oxidation on the back to obtain a nano-silicon dioxide thin film to generate a nano-silicon dioxide tunneling layer;

[0012] (4) Back heavily doped phosphorus amorphous silicon layer formation. Prepare a heavily doped phosphorus amorphous silicon layer on the nano-silicon dioxide tunneling layer;

[0013] (5) Front heavily doped boron amorphous silicon layer formation. Remove the front amorphous silicon film, and then deposit a heavily doped boron amorphous silicon layer on the front side of the silicon substrate;

[0014] (6) Annealing crystallization. Place the silicon wafer in a tube furnace for heating, introduce nitrogen, and convert the double-sided amorphous silicon layer into a polycrystalline structure;

[0015] (7) Passivate the silicon wafer in a hydrogen plasma atmosphere to repair the crystallization defects existing in the silicon wafer; obtain a polycrystalline passivation layer P ++ and a polycrystalline passivation layer N ++ ;

[0016] (8) Prepare a fluorine-doped tin oxide TCO layer on both sides;

[0017] (9) Deposit an antireflection and antireflection-reducing film on both sides of the silicon wafer to obtain a SiC x O y film layer;

[0018] (10) Screen-print and sinter to form grid line electrodes.

[0019] Preferably, in step (1), the mass percentage of the concentrated alkali solution is 13%, and the mass percentage of the dilute alkali solution is 1.5%. The concentrated alkali solution and the dilute alkali solution are aqueous NaOH solutions.

[0020] Preferably, in step (2), the temperature is raised to 1080 °C, the nitrogen flow rate is 15 - 20 L / min, the oxygen flow rate is 0.8 - 1.2 L / min, and the BBr3 flow rate is 10 - 15 L / min, to obtain a boron diffusion layer P + The sheet resistance is 85 - 95 Ω / sq.

[0021] Preferably, in step (3), the concentration of the mixed solution of hydrogen fluoride and hydrogen chloride is 0.002 mol / L - 0.0035 mol / L, and the etching time is 4 - 6 min; the specific process of shallow oxidation is to continuously introduce dry pure oxygen at a temperature of 940 - 960 °C for 20 - 30 min, and the oxygen flow rate is 0.5 L / min.

[0022] Preferably, the specific process of step (4) is as follows: using a PECVD device, the temperature is 400 - 450 °C, the volume ratio of PH3:SiH4:H2 gas is 3:700:10000, the static pressure is 220 Pa, and the time is about 3 - 4 min; the specific process of step (5) is as follows: using a PECVD device, the temperature is 400 - 450 °C, the volume ratio of TMB:SiH4:H2 gas is 1:800:10000, the static pressure is 250 Pa, and the time is 2 - 3 min.

[0023] Preferably, in step (6), the annealing temperature is 850 - 900 °C, the nitrogen flow rate is 2.5 L / min, and the time is 15 - 20 min; in step (7), the specific passivation process is as follows: placing the silicon substrate in a PECVD, raising the temperature in the chamber to 300 - 350 °C, introducing hydrogen at a flow rate of 30 - 40 mL / min, the chamber pressure is 90 - 110 Pa, the power of the radio frequency power supply is 30 - 40 w, and the residence time is 10 - 15 minutes.

[0024] Preferably, the TCO film in step (8) is made from TFA, MBTC, MeOH, oxygen, and water vapor as raw materials in an LPCVD device, and the mass ratio of TFA, MBTC, MeOH, oxygen, and water vapor is 2:10:1:10. Step (9) SiC x O y The SiC film layer is made from C2H4, CO2, SiH4, and N2 as raw materials in an LPCVD device, and the volume ratio of C2H4, CO2, SiH4, and N2 is 2:4:1:10.

[0025] In the present invention, the fluorine ions doped in the front TCO layer have the ability to capture free electrons, reducing the electron density at the interface between the TCO and the front passivated polysilicon layer, greatly reducing the recombination of electrons and holes at the interface, thereby increasing the Voc of the battery; the front and back TCO layers have good electrical conductivity, and most of the effective carriers can enter the TCO layer through longitudinal one-dimensional transmission within the polysilicon layer, and then converge to the electrodes through the TCO layer, thus reducing the lateral transmission loss of carriers in the polysilicon body and greatly reducing the electrical loss.

[0026] In the present invention, the differential design of the thickness of the front and back polysilicon passivation layers not only ensures good passivation contact effect on the front side, but also minimizes the absorption loss of photons by the passivation layer; by adjusting the ratio of the process gases, it is convenient to control the refractive index of the SiCxOy layer to the best antireflection and antireflection enhancement effect. In addition, the SiCxOy layer has better barrier properties than the SiO2 and SiNx stacked layers, and can better prevent metal ions such as sodium ions and water molecules from entering the silicon wafer, thereby playing a good protective role for the battery chip.

[0027] The battery structure of the present invention is deposited with a TCO film layer. The number and width of the grid lines of the battery chip are less and narrower than those of the conventional TopCon battery, which can reduce the grid line shading loss by 15-25%; the double-sided battery structure of the present application combines the N-type crystalline silicon technology with the amorphous technology, which can significantly reduce the gate metal contact resistance and the recombination loss of photo-generated carriers on the front and back sides of the battery, and improve the open circuit voltage and fill factor. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of the N-type TopCon double-sided battery structure provided by the present invention;

[0029] Figure 2 It is a schematic diagram of the preparation process flow of the N-type TopCon double-sided battery structure provided by the present invention.

[0030] DESCRIPTION OF THE REFERENCE NUMERALS:

[0031] 1 - Grid line, 2 - SiCxOy layer, 3 - TCO layer, 4 - Polysilicon passivation layer P ++ , 5 - Boron diffusion layer P + , 6 - N-type crystalline silicon substrate, 7 - Silicon dioxide tunneling layer, 8 - Polysilicon passivation layer N ++ . DETAILED DESCRIPTION OF THE INVENTION

[0032] The present invention will be further described below in conjunction with embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0033] Embodiment 1

[0034] An N-type TopCon double-sided battery structure, as Figure 1 shown, from top to bottom in sequence are: front grid line 1, SiC x O y layer 2, TCO layer 3, polysilicon passivation layer P ++ 4, boron diffusion layer P + 5, N-type crystalline silicon substrate 6, silicon dioxide tunneling layer 7, polysilicon passivation layer N ++ 8, TCO layer 3, SiC x O y layer 2 and back grid line 1, and its preparation process steps are as Figure 2 shown, and the specific process is as follows:

[0035] (1) Double-sided texturing and cleaning. In an etching and cleaning machine, an N-type monocrystalline silicon substrate with a length and width of 156 mm and a thickness of 190 μm is placed in an NaOH aqueous solution with a mass percentage of 13% and a temperature of 85 °C for rough etching for 40 s, and then placed in an NaOH aqueous solution with a mass percentage of 1.5% for fine etching for 10 min. After forming a "pyramid" structure on the surface, the silicon wafer is cleaned;

[0036] (2) Diffusion junction formation. In a tube diffusion furnace, the N-type silicon substrate after texturing and cleaning is heated to 1080 °C in a nitrogen atmosphere, and then nitrogen, oxygen, and BBr3 are introduced. The nitrogen flow rate is 15 L / min, the oxygen flow rate is 0.8 L / min, and the BBr3 flow rate is 10 L / min. The duration is 65 min. Boron doping treatment is carried out on the front surface of the silicon substrate to obtain a boron diffusion layer P with a sheet resistance of 85 Ω / sq + ;

[0037] (3) Back tunneling layer formation. After boron doping is completed on the front surface of the silicon substrate, it is immersed in a mixed solution of hydrogen fluoride and hydrogen chloride with a molar concentration of 0.002 mol / L for 5 min to remove the BSG (boron silicate glass) on the surface and backside plating; then, by dry oxygen thermal oxidation method, at a temperature of 940 °C, dry pure oxygen is continuously introduced at a rate of 0.5 L / min for 20 min to grow a layer of silicon dioxide with a thickness of 1 nm on the back surface of the silicon substrate to obtain a silicon dioxide tunneling layer;

[0038] (4) Deposit a phosphorus-doped amorphous silicon layer on the back side. Using PECVD equipment, at a temperature of 400 °C, the volume ratio of PH3:SiH4:H2 gas is approximately 3:700:10000, the static pressure is 220 Pa, and the time is 3 min. Finally, a phosphorus-doped amorphous silicon thin film with a phosphorus doping concentration of 5×10 15 cm -3 and a thickness of 90 nm is prepared on the nano-silica thin film;

[0039] (5) Deposit a boron-doped amorphous silicon layer on the front side. Using PECVD equipment, at a temperature of about 400 °C, the volume ratio of TMB:SiH4:H2 gas is approximately 1:800:10000, the static pressure is 250 Pa, and the time is 2 min. Finally, deposit a boron-doped amorphous silicon thin film with a boron doping concentration of 7×10 + on the boron diffusion layer P 15 cm -3 and a thickness of 40 nm;

[0040] (6) Anneal and crystallize both sides to remove the BSG (boron silicate glass) on the front side and the PSG (phosphosilicate glass) layer on the back side. Place the silicon wafer in a tube furnace and heat it to 850 °C, with a nitrogen flow rate of 2.5 L / min and a time of 15 min;

[0041] (7) Plasma hydrogen passivation: Place the silicon substrate in PECVD, raise the chamber temperature to 300 °C, introduce hydrogen at a flow rate of 30 mL / min, the chamber pressure is 90 Pa, the power of the radio frequency power supply is 30 w, and the residence time is 10 min. The ionized hydrogen groups enter the silicon wafer and combine with the dangling bonds and defect states, thereby achieving the purpose of repairing the dangling bonds on the surface of the cell and internal defects and reducing the recombination centers; a polysilicon passivation layer P ++ and a polysilicon passivation layer N ++ are obtained on the front and back sides respectively;

[0042] (8) Deposit a fluorine-doped tin oxide layer TCO film on both sides: At 580 °C, according to the TFA flow rate of 60 mg / s, the MBTC flow rate of 300 mg / s, the MeOH flow rate of 30 mg / s, and the water vapor flow rate of 300 mg / s, introduce them into LPCVD, and deposit the TCO film on both sides of the silicon substrate at the same time. By adjusting the feeding time and the supply rate of water vapor, etc., a transparent conductive film with a thickness of 800 nm, a refractive index of 2.0, and a sheet resistance of 8.5 Ω / cm 2 is finally produced;

[0043] (9) Deposit an antireflection and antireflection-reducing film on both sides. At 500 °C, introduce C2H4 at a flow rate of 4 L / min, CO2 at a flow rate of 8 L / min, SiH4 at a flow rate of 2 L / min, and N2 at a flow rate of 20 L / min into LPCVD. By adjusting the gas flow rate and the reaction time, finally a SiC with a thickness of 75 nm and a refractive index of 1.71 is made.x O y Film layer;

[0044] (10) Screen printing and sintering, printing low-temperature silver paste on both sides of the battery, and then heating to 230 °C for sintering and curing.

[0045] The TCO film layers are deposited on the front and back of the battery structure of the present invention. The N-type crystalline silicon technology is integrated with the amorphous technology, significantly reducing the gate metal contact resistance. In this way, the number and width of the grid lines on the battery cell can be less and narrower than those of conventional TopCon batteries, and the overall grid line shading loss can be reduced by 15-25%; in addition, the double-sided battery structure and the recombination loss of photo-generated carriers on both sides of the battery, the open-circuit voltage and fill factor are improved. The excellent passivation performance of the battery interface defects of the battery structure of the present invention enables the open-circuit voltage of the battery to be 0.7% higher than that of the conventional TopCon battery, and the average short-circuit current is relatively 0.35% higher, and the average conversion efficiency is 0.3-0.45 percentage points higher than that of the ordinary manufacturing process; after testing, the average mass production photoelectric conversion efficiency of the front side of the battery structure of the present invention is 23.4%, and the photoelectric conversion efficiency of the back side is 21.9%.

[0046] Example 2

[0047] An N-type TopCon double-sided battery structure, as Figure 1 shown, from top to bottom in sequence are: front grid line 1, SiC x O y layer 2, TCO layer 3, polysilicon passivation layer P ++ 4, boron diffusion layer P + 5, N-type crystalline silicon substrate 6, silicon dioxide tunneling layer 7, polysilicon passivation layer N ++ 8, TCO layer 3, SiC x O y layer 2 and back grid line 1, and its preparation process steps are as Figure 2 shown, the specific process is as follows:

[0048] (1) Double-sided texturing and cleaning. In an etching and cleaning machine, an N-type monocrystalline silicon substrate with a length and width of 156 mm and a thickness of 190 μm is placed in a NaOH aqueous solution with a mass percentage of 13% and a temperature of 85 °C for rough etching for 50 s, and then placed in a NaOH aqueous solution with a mass percentage of 1.5% for fine etching for 9 min. After forming a "pyramid"-structured textured surface, the silicon wafer is cleaned;

[0049] (2) Diffusion junction formation: In a tube diffusion furnace, the N-type silicon substrate after texturing and cleaning is heated to 1080 °C in a nitrogen atmosphere, and then nitrogen, oxygen, and BBr3 are introduced. The nitrogen flow rate is 18 L / min, the oxygen flow rate is 1 L / min, and the BBr3 flow rate is 13 L / min. The duration is 65 min, and boron doping treatment is carried out on the front side of the silicon substrate to obtain a boron diffusion layer P with a sheet resistance of 90 Ω / sq. + ;

[0050] (3) Back tunneling layer formation: After boron doping is completed on the front side of the silicon substrate, it is immersed in a mixed solution of hydrogen fluoride and hydrogen chloride with a molar concentration of 0.003 mol / L for 4 min, and then the surface BSG (boron silicon glass) and backside plating are removed; then, by dry oxygen thermal oxidation method, dry pure oxygen is continuously introduced at a rate of 0.5 L / min at 950 °C for 25 min to grow a layer of silicon dioxide with a thickness of 1.4 nm on the back side of the silicon substrate to obtain a silicon dioxide tunneling layer;

[0051] (4) Back phosphorus-doped amorphous silicon layer formation: Using a PECVD device, at a temperature of 430 °C, the gas volume ratio of PH3:SiH4:H2 is about 3:700:10000, the static pressure is 220 Pa, and the time is 3.5 min. Finally, a phosphorus-doped amorphous silicon thin film with a phosphorus doping concentration of 5.5×10 15 cm -3 and a thickness of 100 nm is prepared on the nano-silicon dioxide thin film;

[0052] (5) Front boron-doped amorphous silicon layer formation: Using a PECVD device, at a temperature of about 430 °C, the gas volume ratio of PH3:SiH4:H2 is about 1:800:10000, the static pressure is 250 Pa, and the time is 2.5 min. Finally, a boron-doped amorphous silicon thin film with a boron doping concentration of 8×10 + is deposited on the boron diffusion layer P 15 cm -3 and a thickness of 55 nm;

[0053] (6) Double-sided annealing crystallization: Remove the front BSG (boron silicon glass) and the back PSG (phosphorus silicon glass) layer, place the silicon wafer in a tube furnace and heat it to 880 °C, with a nitrogen flow rate of 2.5 L / min and a time of 18 min;

[0054] (7) Plasma hydrogen passivation: Place the silicon substrate in a PECVD, raise the chamber temperature to 330 °C, introduce hydrogen at a flow rate of 35 mL / min, the chamber pressure is 100 Pa, the power of the radio frequency power supply is 35 w, and the residence time is 13 min. The ionized hydrogen groups enter the silicon wafer and combine with the dangling bonds and defect states, thereby achieving the purpose of repairing the dangling bonds on the surface of the cell and internal defects and reducing the recombination centers; polycrystalline silicon passivation layers P are obtained on the front and back sides respectively++ and polysilicon passivation layer N ++ ;

[0055] (8)Double-sided preparation of fluorine-doped tin oxide layer TCO film: At 600 °C, with a TFA flow rate of 80 mg / s, an MBTC flow rate of 360 mg / s, an MeOH flow rate of 35 mg / s, and a water vapor flow rate of 450 mg / s, introduce them into LPCVD to deposit the TCO film on both sides of the silicon substrate simultaneously. By adjusting the feeding time and the supply rate of water vapor, etc., finally produce a transparent conductive film with a thickness of 900 nm, a refractive index of 2.1, and a sheet resistance of 9 Ω / cm 2 ;

[0056] (9)Double-sided deposition of antireflection and antireflective film. At 530 °C, with a C2H4 flow rate of 5 L / min, a CO2 flow rate of 10 L / min, a SiH4 flow rate of 2.5 L / min, and an N2 flow rate of 35 L / min, introduce them into LPCVD. By adjusting the gas flow rate and the reaction time, finally produce a SiC x O y film layer with a thickness of 80 nm and a refractive index of 1.72;

[0057] (10)Screen printing and sintering. Print low-temperature silver paste on both sides of the battery, and then heat it to 230 °C for sintering and curing.

[0058] Example 3

[0059] An N-type TopCon double-sided battery structure, as Figure 1 shown, from top to bottom in sequence are: front grid line 1, SiC x O y layer 2, TCO layer 3, polysilicon passivation layer P ++ 4, boron diffusion layer P + 5, N-type crystalline silicon substrate 6, silicon dioxide tunneling layer 7, polysilicon passivation layer N ++ 8, TCO layer 3, SiC x O y layer 2 and back grid line 1, and its preparation process steps are as Figure 2 shown, and the specific process is as follows:

[0060] (1)Double-sided texturing and cleaning. In the etching and cleaning machine, place an N-type monocrystalline silicon substrate with a length and width of 156 mm and a thickness of 190 μm into a NaOH aqueous solution with a mass percentage of 13% and a temperature of 85 °C for rough etching for 55 s, and then place it into a NaOH aqueous solution with a mass percentage of 1.5% for fine etching for 12 min. After forming a "pyramid" - structured textured surface, clean the silicon wafer;

[0061] (2) Diffusion junction formation: In a tube diffusion furnace, the N-type silicon substrate after texturing and cleaning is heated to 1080 °C in a nitrogen atmosphere, and then nitrogen, oxygen, and BBr3 are introduced. The nitrogen flow rate is 20 L / min, the oxygen flow rate is 1.2 L / min, and the BBr3 flow rate is 15 L / min. The duration is 65 min, and boron doping treatment is carried out on the front side of the silicon substrate to obtain a boron diffusion layer P with a sheet resistance of 95 Ω / sq. + ;

[0062] (3) Back tunneling layer formation: After boron doping is completed on the front side of the silicon substrate, it is immersed in a mixed solution of hydrogen fluoride and hydrogen chloride with a molar concentration of 0.0035 mol / L. After etching for 6 min, the surface BSG (boron silicate glass) and backside overplating are removed; then, by dry oxygen thermal oxidation method, dry pure oxygen is continuously introduced at a rate of 0.5 L / min at 960 °C for 30 min, so that a layer of silicon dioxide with a thickness of 2 nm grows on the back side of the silicon substrate to obtain a silicon dioxide tunneling layer;

[0063] (4) Back phosphorus-doped amorphous silicon layer formation: Using PECVD equipment, at a temperature of 450 °C, the gas volume ratio of PH3:SiH4:H2 is about 3:700:10000, the static pressure is 220 Pa, and the time is 4 min. Finally, a phosphorus-doped amorphous silicon thin film with a phosphorus doping concentration of 6×10 15 cm -3 and a thickness of 120 nm is prepared on the nano-silicon dioxide thin film;

[0064] (5) Front boron-doped amorphous silicon layer formation: Using PECVD equipment, at a temperature of about 450 °C, the gas volume ratio of PH3:SiH4:H2 is about 1:800:10000, the static pressure is 250 Pa, and the time is 3 min. Finally, a boron-doped amorphous silicon thin film with a boron doping concentration of 9×10 + is deposited on the boron diffusion layer P 15 cm -3 and a thickness of 70 nm;

[0065] (6) Double-sided annealing crystallization: Remove the front BSG (boron silicate glass) and the back PSG (phosphorus silicate glass) layers, place the silicon wafer in a tube furnace and heat it to 900 °C, the nitrogen flow rate is 2.5 L / min, and the time is 20 min;

[0066] (7) Plasma hydrogen passivation: Place the silicon substrate in PECVD, raise the temperature in the cavity to 350 °C, introduce hydrogen at a flow rate of 40 mL / min, the chamber pressure is 110 Pa, the power of the radio frequency power supply is 40 w, and the residence time is 15 min. The ionized hydrogen groups enter the silicon wafer and combine with the dangling bonds and defect states, so as to achieve the purpose of repairing the dangling bonds on the surface of the cell and internal defects and reducing the recombination centers; polysilicon passivation layers P are obtained on the front and back sides respectively ++And polysilicon passivation layer N ++ ;

[0067] (8) Double-sided preparation of fluorine-doped tin oxide layer TCO film: At 610 °C, with a TFA flow rate of 90 mg / s, an MBTC flow rate of 400 mg / s, an MeOH flow rate of 50 mg / s, and a water vapor flow rate of 600 mg / s, introduce them into LPCVD to deposit the TCO film on both sides of the silicon substrate simultaneously. By adjusting the feeding time and the supply rate of water vapor, etc., finally produce a transparent conductive film with a thickness of 950 nm, a refractive index of 2.2, and a sheet resistance of 10 Ω / cm 2 ;

[0068] (9) Double-sided deposition of an antireflection and antireflective film. At 550 °C, with a C2H4 flow rate of 6 L / min, a CO2 flow rate of 12 L / min, a SiH4 flow rate of 3 L / min, and a N2 flow rate of 50 L / min, introduce them into LPCVD. By adjusting the gas flow rate and the reaction time, finally produce a SiC x O y film layer with a thickness of 85 nm and a refractive index of 1.74;

[0069] (10) Screen printing and sintering. Print low-temperature silver paste on both sides of the battery, and then heat it to 230 °C for sintering and curing.

Claims

1. A preparation method of an N-type TopCon double-sided battery structure, characterized in that, It includes the following steps: (1) Texturing and cleaning the surface. First, put the silicon wafer into a concentrated alkali solution for rough etching, and then transfer it to a dilute alkali solution for fine etching. After forming a textured surface, clean the silicon wafer; (2) Diffusion junction formation: Put the silicon wafer that has undergone step (1) into a tube diffusion furnace, heat it up in a nitrogen atmosphere, introduce nitrogen, oxygen, and BBr3, and perform boron doping diffusion propulsion on the front side of the silicon substrate to form a boron diffusion layer P + ; (3) Forming a tunneling layer on the back. First, etch the silicon wafer obtained in step (2) in a mixed solution of hydrogen fluoride and hydrogen chloride to remove BSG (borosilicate glass) and the side and back wrap-around coatings. Then, perform shallow oxidation on the back to obtain a nano-silicon dioxide film and generate a nano-silicon dioxide tunneling layer; (4) Forming a heavily phosphorus-doped amorphous silicon layer on the back. Prepare a heavily phosphorus-doped amorphous silicon layer on the nano-silicon dioxide tunneling layer; (5) Forming a heavily boron-doped amorphous silicon layer on the front. Remove the amorphous silicon film on the front, and then deposit a heavily boron-doped amorphous silicon layer on the front of the silicon substrate; (6) Annealing and crystallization. Place the silicon wafer in a tube furnace, heat it, and introduce nitrogen gas to convert the double-sided amorphous silicon layer into a polycrystalline silicon structure; (7) Place the silicon wafer in a hydrogen plasma atmosphere for passivation to repair the crystal defects existing in the silicon wafer; a polysilicon passivation layer P and a polysilicon passivation layer N are obtained on the front and back sides respectively. ++ and polysilicon passivation layer N ++ ; (8) Preparing a fluorine-doped tin oxide TCO layer on both sides; (9) An antireflection film is deposited on both sides of the silicon wafer to obtain the SiC x O y film layer; (10) Screen-printing and sintering to form grid line electrodes; In step (2), the temperature is raised to 1080 °C, the nitrogen flow rate is 15-20 L / min, the oxygen flow rate is 0.8-1.2 L / min, and the BBr3 flow rate is 10-15 L / min, obtaining a boron diffusion layer P + The sheet resistance is 85-95 Ω / sq; In step (3), the concentration of the mixed solution of hydrogen fluoride and hydrogen chloride is 0.002 mol / L to 0.0035 mol / L, and the etching time is 4 to 6 minutes. The specific process of shallow oxidation is to continuously introduce dry pure oxygen at a temperature of 940 to 960 °C for 20 to 30 minutes, and the oxygen flow rate is 0.5 L / min; The specific process of step (4) is as follows: Using a PECVD device, the temperature is 400 to 450 °C, the volume ratio of PH3:SiH4:H2 gas is 3:700:10000, the static pressure is 220 Pa, and the time is 3 to 4 minutes. The specific process of step (5) is as follows: Using a PECVD device, the temperature is 400 to 450 °C, the volume ratio of TMB:SiH4:H2 gas is 1:800:10000, the static pressure is 250 Pa, and the time is 2 to 3 minutes; In step (6), the annealing temperature is 850 to 900 °C, the nitrogen flow rate is 2.5 L / min, and the time is 15 to 20 minutes. In step (7), the specific passivation process is as follows: Place the silicon substrate in a PECVD, raise the temperature inside the chamber to 300 to 350 °C, introduce hydrogen gas at a flow rate of 30 to 40 mL / min, the chamber pressure is 90 to 110 Pa, the power of the radio frequency power supply is 30 to 40 w, and the residence time is 10 to 15 minutes; Step (8): The TCO film is made from TFA, MBTC, MeOH, oxygen, and water vapor as raw materials for the silicon wafer in an LPCVD device. The mass ratio of TFA, MBTC, MeOH, oxygen, and water vapor is 2:10:1:

10. Step (9): SiC x O y The film layer is made from C2H4, CO2, SiH4, and N2 as raw materials in an LPCVD device. The volume ratio of C2H4, CO2, SiH4, and N2 is 2:4:1:

10.

2. The preparation method according to claim 1, characterized in that, In step (1), the mass percentage of the concentrated alkali solution is 13%, and the mass percentage of the dilute alkali solution is 1.5%. Both the concentrated alkali solution and the dilute alkali solution are NaOH aqueous solutions.

3. The preparation method according to claim 1, characterized in that, Step (5) is specifically as follows: deposit a boron-doped amorphous silicon layer on the front side. Using a PECVD device, at a temperature of 400 °C, the volume ratio of TMB:SiH4:H2 gas is 1:800:10000, the static pressure is 250 Pa, and the time is 2 min. Finally, deposit a boron-doped amorphous silicon thin film with a boron doping concentration of 7×10 + on the boron diffusion layer P 15 cm -3 and a thickness of 40 nm.

4. The preparation method according to claim 1, characterized in that, Step (7) is specifically as follows: plasma hydrogen passivation. Place the silicon substrate in PECVD, raise the temperature inside the chamber to 300 °C, introduce hydrogen at a flow rate of 30 mL / min, the chamber pressure is 90 Pa, the power of the RF power supply is 30 W, and the residence time is 10 min. The ionized hydrogen groups enter the silicon wafer and combine with the dangling bonds and defect states, thereby achieving the purpose of repairing the dangling bonds on the surface of the cell and internal defects and reducing the recombination centers; a polysilicon passivation layer P is obtained on the front and back respectively ++ and a polysilicon passivation layer N ++ .

5. The preparation method according to claim 1, wherein, Step (9) is specifically as follows: Deposit an antireflection and antistatic film on both sides. At 500 °C, introduce C2H4 at a flow rate of 4 L / min, CO2 at a flow rate of 8 L / min, SiH4 at a flow rate of 2 L / min, and N2 at a flow rate of 20 L / min into LPCVD. By adjusting the gas flow rate and reaction time, finally produce a SiC film layer with a thickness of 75 nm and a refractive index of 1.

71. x O y film layer.

6. The N-type TopCon double-sided battery structure prepared by any of the methods of claims 1-5, characterized in that, The N-type TopCon double-sided battery structure, from top to bottom, is the front grid line, SiC x O y layer, TCO layer, polysilicon passivation layer P ++ , boron diffusion layer P + , N-type crystalline silicon substrate, silicon dioxide tunneling layer, polysilicon passivation layer N ++ , TCO layer, SiC x O y layer and the back grid line; The polysilicon passivation layer P ++ The boron doping concentration is 7×10 15 ~9×10 15 cm -3 , and the thickness is 40~70nm. The polysilicon passivation layer N ++ The phosphorus doping concentration is 5×10 15 ~6×10 15 cm -3 , and the thickness is 90~120nm; The thickness of the silicon dioxide tunneling layer is 1 to 2 nm; the thickness of the TCO layer is 800 to 950 nm; the SiC x O y layer has a thickness of 75 to 85 nm and a refractive index of 1.71 to 1.74; the TCO layer has a refractive index of 2.0 to 2.2 and a sheet resistance of 8.5 to 10 Ω / cm 2 .

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