TVS diode

Abstract

To improve electrical characteristics of a TVS diode.SOLUTION: A semiconductor chip 20 of a TVS diode 10 includes a first pin junction part 30 in a first polarity direction and a diode pair region 60. The diode pair region 60 includes: a first inverse pin junction part 60A in a second polarity direction which is provided while being separated from the first pin junction part 30 in a planar view; and a pn junction part 60E in the first polarity direction constituting a diode pair with the first inverse pin junction part 60A. The first pin junction part 30 includes: a p-type first terminal side high concentration region 31; an n-type first terminal side low concentration region 32 provided at a position overlapping the first terminal side high concentration region 31 in the planar view; an n-type first terminal side contact region 33; and a p-type first buffer region 35 in contact with the first terminal side high concentration region 31 between the first terminal side high concentration region 31 and the first terminal side low concentration region 32 in a thickness direction of the semiconductor chip 20.SELECTED DRAWING: Figure 29

Description

[Technical Field]

[0001] The present disclosure relates to TVS diodes. [Background technology]

[0002] Patent Document 1 discloses a diode chip including a TVS (Transient Voltage Suppressor) circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-57490

[0004] [overview] There is a demand for improved electrical characteristics of TVS diodes.

[0005] A TVS diode according to one aspect of the present disclosure includes a semiconductor chip having a first surface and a second surface opposite to the first surface, the semiconductor chip including a diode pair region including a first pin junction in a first polarity direction provided in a region of the semiconductor chip closer to the first surface, a first reverse pin junction in a second polarity direction provided at a distance from the first pin junction in a plan view seen in a thickness direction of the semiconductor chip, and a pn junction in the first polarity direction that forms a diode pair with the first reverse pin junction, and a second conductivity type first terminal side high concentration region provided at a distance from the first surface of the semiconductor chip closer to the second surface. a first terminal side low concentration region of a first conductivity type provided in a region closer to the first surface than the first terminal side high concentration region at a position overlapping the first terminal side high concentration region in the planar view; a first terminal side contact region of a first conductivity type provided in a surface layer portion of the first terminal side low concentration region; and a first buffer region of a second conductivity type that is in contact with the first terminal side high concentration region between the first terminal side high concentration region and the first terminal side low concentration region in the thickness direction of the semiconductor chip, and a pin diode is formed by the first terminal side contact region, the first terminal side low concentration region, and the first buffer region. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of an exemplary TVS diode according to a first embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view of the TVS diode taken along line F2-F2 in FIG. [Figure 3] FIG. 3 is a schematic cross-sectional view of the TVS diode taken along line F3-F3 in FIG. [Figure 4] FIG. 4 is a schematic plan view of a semiconductor chip. [Figure 5] FIG. 5 is a schematic cross-sectional view of the TVS diode taken along line F5-F5 in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view showing an enlarged portion of FIG. [Figure 7]FIG. 7 is a schematic plan view of first to third connection electrodes and wiring provided on a semiconductor chip. [Figure 8] FIG. 8 is a schematic circuit diagram of a TVS diode. [Figure 9] 9A to 9C are schematic cross-sectional views for explaining exemplary manufacturing processes for the TVS diode according to the first embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 21] FIG. 21 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 22] FIG. 22 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 23] FIG. 23 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 24]FIG. 24 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 25] FIG. 25 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 26] FIG. 26 is an enlarged schematic cross-sectional view of the diode pair region and its periphery in FIG. [Figure 27] FIG. 27 is a schematic cross-sectional view of the second pin junction, the third pin junction, and the surrounding area. [Figure 28] FIG. 28 is a schematic cross-sectional view of a TVS diode according to the second embodiment. [Figure 29] FIG. 29 is a schematic cross-sectional view of the TVS diode at a position different from that in FIG. [Figure 30] FIG. 30 is a schematic cross-sectional view showing an enlarged portion of FIG. [Figure 31] FIG. 31 is a graph showing the relationship between the position in the thickness direction of a semiconductor chip and the impurity concentration. [Figure 32] FIG. 32 is a schematic cross-sectional view for explaining an exemplary manufacturing process of the TVS diode according to the second embodiment. [Figure 33] FIG. 33 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 34] FIG. 34 is a schematic plan view of a semiconductor chip in the TVS diode of the third embodiment. [Figure 35] FIG. 35 is a schematic cross-sectional view of the TVS diode taken along line F35-F35 in FIG. [Figure 36] FIG. 36 is a schematic cross-sectional view of the TVS diode taken along line F36-F36 in FIG. [Figure 37] FIG. 37 is a schematic cross-sectional view for explaining an exemplary manufacturing process of the TVS diode according to the third embodiment. [Figure 38] FIG. 38 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 39] FIG. 39 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 40]FIG. 40 is a schematic plan view of a semiconductor chip in the TVS diode of the fourth embodiment. [Figure 41] FIG. 41 is a schematic plan view of first to third connection electrodes and wiring provided on a semiconductor chip. [Figure 42] FIG. 42 is a schematic cross-sectional view of the TVS diode taken along line F42-F42 in FIG. [Figure 43] FIG. 43 is a schematic plan view of a TVS diode. [Figure 44] FIG. 44 is a schematic plan view of a semiconductor chip in the TVS diode of the fifth embodiment. [Figure 45] FIG. 45 is a schematic plan view of first connection electrodes, second connection electrodes, and wiring provided on a semiconductor chip. [Figure 46] FIG. 46 is a schematic plan view of a TVS diode. [Figure 47] FIG. 47 is a schematic plan view of a semiconductor chip in the TVS diode of the sixth embodiment. [Figure 48] FIG. 48 is a schematic plan view of first connection electrodes, second connection electrodes, and wiring provided on a semiconductor chip. [Figure 49] FIG. 49 is a schematic plan view of a TVS diode. [Figure 50] FIG. 50 is a schematic plan view of a semiconductor chip in the TVS diode of the seventh embodiment. [Figure 51] FIG. 51 is a schematic cross-sectional view of the TVS diode taken along line F51-F51 in FIG. [Figure 52] FIG. 52 is a schematic plan view of first to fourth connection electrodes and wiring provided on a semiconductor chip. [Figure 53] FIG. 53 is a schematic plan view of a TVS diode. [Figure 54] FIG. 54 is a schematic plan view of a semiconductor chip in the TVS diode of the eighth embodiment. [Figure 55] FIG. 55 is a schematic plan view of first connection electrodes, second connection electrodes, and wiring provided on a semiconductor chip. [Figure 56] FIG. 56 is a schematic plan view of a TVS diode. [Figure 57] FIG. 57 is a schematic cross-sectional view of a modified TVS diode. [Figure 58] FIG. 58 is a schematic cross-sectional view of a modified TVS diode. [Figure 59] FIG. 59 is a schematic plan view of first to third connection electrodes and wiring provided on a semiconductor chip in a TVS diode of a modified example. [Figure 60] FIG. 60 is a schematic cross-sectional view of the TVS diode taken along line F60-F60 in FIG. [Figure 61] FIG. 61 is a schematic plan view of a modified TVS diode. [Figure 62] FIG. 62 is a schematic cross-sectional view of the TVS diode taken along line F62-F62 in FIG. [Figure 63] FIG. 63 is a schematic cross-sectional view of the TVS diode taken along line F63-F63 in FIG.

[0007] [Detailed explanation] Hereinafter, several embodiments of TVS diodes according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The phrase "at least one" used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] As used in this disclosure, the phrases "the dimensions (depth, width, length) of A are equal to the dimensions (depth, width, length) of B" or "the dimensions (depth, width, length) of A and the dimensions (depth, width, length) of B are equal to each other" also include a relationship in which the difference between the dimensions (depth, width, length) of A and the dimensions (depth, width, length) of B is within 10% of the dimensions (depth, width, length) of A, for example. Also, as used in this disclosure, the phrases "the concentration of A is equal to the concentration of B" or "the concentrations of A and B are equal to each other" also include a relationship in which the difference between the concentrations of A and B is within 10% of the concentration of A, for example.

[0011] First Embodiment [TVS diode configuration] The configuration of a TVS diode 10 according to a first embodiment will be described with reference to Figures 1 to 3. Figure 1 schematically shows the planar structure of the TVS diode 10. Figure 2 schematically shows the cross-sectional structure taken along line F2-F2 in Figure 1. Figure 3 schematically shows the cross-sectional structure taken along line F3-F3 in Figure 1.

[0012] As shown in Fig. 1, the TVS diode 10 is a diode chip that includes a TVS circuit 200 (see Fig. 8) that protects an electric circuit from ESD (Electro-Static Discharge). Details of the TVS circuit 200 will be described later with reference to Fig. 8. Such a TVS diode 10 is used to protect interfaces in electronic devices such as wearable devices and smartphones.

[0013] The TVS diode 10 includes a rectangular parallelepiped semiconductor chip 20. The semiconductor chip 20 is made of a material containing, for example, silicon (Si). The semiconductor chip 20 can also be said to be flat with the Z direction as its thickness direction. Hereinafter, the TVS diode 10 viewed from the Z direction will be referred to as a "planar view." Furthermore, directions perpendicular to the Z direction that are perpendicular to each other will be referred to as the "X direction" and the "Y direction." Here, the X direction is an example of a "second direction," and the Y direction is an example of a "first direction."

[0014] The semiconductor chip 20 includes a first surface 20S, a second surface 20R (see FIG. 2) opposite the first surface 20S, and first to fourth side surfaces 20A to 20D that connect the first surface 20S and the second surface 20R. In one example, the first surface 20S and the second surface 20R are formed by planes perpendicular to the Z direction. The first side surface 20A and the second side surface 20B form both end surfaces of the semiconductor chip 20 in the X direction. The third side surface 20C and the fourth side surface 20D form both end surfaces of the semiconductor chip 20 in the Y direction.

[0015] (Cross-sectional structure of a TVS diode) As shown in FIGS. 2 and 3, the semiconductor chip 20 includes a semiconductor substrate 21 and a semiconductor layer 22 provided on the semiconductor substrate 21.

[0016] The semiconductor substrate 21 is made of a material containing Si (silicon). In one example, a Si substrate is used as the semiconductor substrate 21. Alternatively, a SiC (silicon carbide) substrate may be used as the semiconductor substrate 21. The semiconductor substrate 21 has a flat plate shape with its thickness direction aligned in the Z direction. The thickness of the semiconductor substrate 21 can be set to 10 μm or more and 800 μm or less. In one example, the thickness of the semiconductor substrate 21 is 30 μm or more and 400 μm or less.

[0017] The semiconductor substrate 21 contains p-type impurities. In one example, the semiconductor substrate 21 has a generally constant p-type impurity concentration throughout the entire region. The p-type impurity concentration of the semiconductor substrate 21 is 1×10 19 cm -3 More than 1×10 21cm -3 In one example, the p-type impurity concentration of the semiconductor substrate 21 can be 1×10 19 cm -3 More than 1×10 20 cm -3 The following is the result.

[0018] The semiconductor layer 22 is composed of an epitaxial layer provided on the semiconductor substrate 21. In one example, the semiconductor layer 22 is composed of a stacked structure of a first semiconductor layer 23, a second semiconductor layer 24, and a third semiconductor layer 25. In Figures 2 and 3, the boundary between the first semiconductor layer 23 and the second semiconductor layer 24 and the boundary between the second semiconductor layer 24 and the third semiconductor layer 25 are indicated by dashed lines.

[0019] The first semiconductor layer 23 is composed of a p-type epitaxial layer provided on the upper surface of the semiconductor substrate 21. The thickness of the first semiconductor layer 23 can be set to 5 μm or more and 20 μm or less. For example, the thickness of the first semiconductor layer 23 is set to 10 μm or more and 18 μm or less. For example, the thickness of the first semiconductor layer 23 is about 15 μm.

[0020] The p-type impurity concentration of the first semiconductor layer 23 is lower than the p-type impurity concentration of the semiconductor substrate 21. The first semiconductor layer 23 has a concentration gradient in which the p-type impurity concentration gradually decreases from the semiconductor substrate 21 toward the crystal growth direction. In other words, the p-type impurity concentration of the first semiconductor layer 23 includes a portion where it decreases with increasing distance from the semiconductor substrate 21 in the Z direction. The degree of decrease in the p-type impurity concentration of the first semiconductor layer 23 increases with increasing distance from the semiconductor substrate 21. The minimum value of the p-type impurity concentration of the first semiconductor layer 23 is 1×10 15 cm -3 More than 1×10 17 cm -3 The minimum value of the p-type impurity concentration of the first semiconductor layer 23 is, for example, 1×10 16 cm -3 More than 1×10 17 cm -3 The range can be as follows:

[0021] The second semiconductor layer 24 is composed of an n-type epitaxial layer provided on the upper surface of the first semiconductor layer 23. The thickness of the second semiconductor layer 24 can be 1 μm or more and 10 μm or less. For example, the thickness of the second semiconductor layer 24 is 5 μm or more and 8 μm or less. For example, the thickness of the second semiconductor layer 24 is approximately 7 μm. Here, the n-type is an example of a "first conductivity type." The second semiconductor layer 24 may also be composed of a p-type epitaxial layer.

[0022] The peak value of the n-type impurity concentration of the second semiconductor layer 24 is 5×10 14 cm -3 More than 1×10 15 cm -3 In one example, the peak value of the n-type impurity concentration of the second semiconductor layer 24 can be 1×10 15 cm -3 In one example, the n-type impurity concentration of the second semiconductor layer 24 gradually increases from the first semiconductor layer 23 toward the center of the second semiconductor layer 24 in the Z direction. The n-type impurity concentration of the second semiconductor layer 24 gradually decreases from the center of the second semiconductor layer 24 in the Z direction toward the third semiconductor layer 25.

[0023] The third semiconductor layer 25 is composed of an n-type epitaxial layer provided on the upper surface of the second semiconductor layer 24. The third semiconductor layer 25 includes the first surface 20S of the semiconductor chip 20. The thickness of the third semiconductor layer 25 can be 5 μm or more and 20 μm or less. For example, the thickness of the third semiconductor layer 25 is 8 μm or more and 15 μm or less. For example, the thickness of the third semiconductor layer 25 is approximately 13 μm. Thus, the thickness of the third semiconductor layer 25 may be thicker than the thickness of the second semiconductor layer 24. The thickness of the third semiconductor layer 25 may be thinner than the thickness of the first semiconductor layer 23.

[0024] The n-type impurity concentration of the third semiconductor layer 25 is 1×10 13 cm -3 More than 1×10 15 cm -3 In one example, the n-type impurity concentration of the third semiconductor layer 25 can be 5×10 13 cm -35x10 or more 14 cm -3 In one example, the n-type impurity concentration of the third semiconductor layer 25 is 1×10 14 cm -3 More than 1×10 15 cm -3 The n-type impurity concentration of the third semiconductor layer 25 gradually decreases as it moves away from the second semiconductor layer 24 in the Z direction. That is, the n-type impurity concentration of the third semiconductor layer 25 reaches a peak in the region that contacts the second semiconductor layer 24 in the Z direction. The n-type impurity concentration reaches a minimum in the region of the third semiconductor layer 25 that is closer to the first surface 20S. In one example, the minimum value of the n-type impurity concentration of the third semiconductor layer 25 is 1×10 14 cm -3 In this way, the minimum value of the n-type impurity concentration of the third semiconductor layer 25 is less than the minimum value of the n-type impurity concentration of the second semiconductor layer 24. In one example, the n-type impurity concentration of the third semiconductor layer 25 is less than the n-type impurity concentration of the second semiconductor layer 24.

[0025] Both the second semiconductor layer 24 and the third semiconductor layer 25 are configured as high-resistivity n-type layers with a relatively low concentration of n-type impurities. Both the second semiconductor layer 24 and the third semiconductor layer 25 may have a resistivity of 50 Ω·cm or more and 150 Ω·cm or less. In one example, both the second semiconductor layer 24 and the third semiconductor layer 25 may have a resistivity of 80 Ω·cm or more and 120 Ω·cm or less.

[0026] (pin joint) 2 and 3, the semiconductor chip 20 includes a first pin (p-intrinsic-n) junction 30, a second pin junction 40, and a third pin junction 50. The first pin junction 30, the second pin junction 40, and the third pin junction 50 are each provided on a surface layer portion of the semiconductor chip 20 (a region including the first surface 20S of the semiconductor chip 20 and closer to the first surface 20S in the Z direction). The first pin junction 30, the second pin junction 40, and the third pin junction 50 are each a region of the semiconductor chip 20 where a pin diode of a first polarity direction is configured. Here, the first polarity direction is the direction in which a forward current flows from the second surface 20R to the first surface 20S of the semiconductor chip 20.

[0027] As shown in FIG. 2, the first pin junction 30 includes a first terminal side high concentration region 31, a first terminal side low concentration region 32, a first terminal side contact region 33, and a first partition region . The first terminal side highly doped region 31 is a p-type region provided across the first semiconductor layer 23, the second semiconductor layer 24, and the third semiconductor layer 25 in the Z direction. The first terminal side highly doped region 31 is provided in a portion of the first semiconductor layer 23 in the Z direction, the entire second semiconductor layer 24 in the Z direction, and a portion of the third semiconductor layer 25 in the Z direction. Therefore, the first terminal side highly doped region 31 is provided away from the first surface 20S of the semiconductor chip 20 toward the second surface 20R. The first terminal side highly doped region 31 is provided away from the semiconductor substrate 21 in the Z direction. The first terminal side highly doped region 31 can be divided into a first region 31A, a second region 31B, and a third region 31C in the Z direction. Here, the p-type is an example of a "second conductivity type."

[0028] The first region 31A is provided in a surface layer portion of the first semiconductor layer 23 (a region of the first semiconductor layer 23 that is closer to the second semiconductor layer 24 and includes the upper surface). The first region 31A is configured to suppress a decrease in the p-type impurity concentration of the first semiconductor layer 23. In other words, the first region 31A is configured to maintain a predetermined p-type impurity concentration. The p-type impurity concentration of the first region 31A is 1×10 17 cm -3 More than 1×1019 cm -3 In one example, the p-type impurity concentration of the first region 31A can be 1×10 18 cm -3 is.

[0029] The second region 31B is provided on the first region 31A across the entire second semiconductor layer 24 in the Z direction. In one example, the second region 31B includes a region configured such that the p-type impurity concentration gradually decreases with increasing distance from the first region 31A in the Z direction. Therefore, the p-type impurity concentration of the second region 31B is equal to or less than the minimum value of the p-type impurity concentration of the first region 31A.

[0030] The third region 31C is provided on the second region 31B in a region of the third semiconductor layer 25 closer to the second semiconductor layer 24. In one example, the p-type impurity concentration of the third region 31C gradually decreases with increasing distance from the second region 31B in the Z direction. Therefore, the p-type impurity concentration of the third region 31C is equal to or lower than the p-type impurity concentration of the second region 31B.

[0031] The first terminal side low concentration region 32 is provided in a region closer to the first surface 20S than the first terminal side high concentration region 31, at a position overlapping the first terminal side high concentration region 31 in a plan view. In one example, the first terminal side low concentration region 32 is provided on the third region 31C. The first terminal side low concentration region 32 is an n-type region formed by the third semiconductor layer 25. The first terminal side low concentration region 32 is exposed from the first surface 20S of the semiconductor chip 20. Therefore, the n-type impurity concentration of the first terminal side low concentration region 32 is equal to the n-type impurity concentration of the third semiconductor layer 25. Therefore, the n-type impurity concentration of the first terminal side low concentration region 32 is 1×10 14 cm -3 More than 1×10 15 cm -3 It can be as follows:

[0032] The first terminal side contact region 33 is an n-type region provided in a surface layer portion of the first terminal side low concentration region 32. The first terminal side contact region 33 is exposed from the first surface 20S of the semiconductor chip 20. The first terminal side contact region 33 is separated from the first terminal side high concentration region 31 in the Z direction.

[0033] The n-type impurity concentration of the first terminal side contact region 33 is higher than the n-type impurity concentration of the first terminal side low-concentration region 32. The peak value of the n-type impurity concentration of the first terminal side contact region 33 is 1×10 18 cm -3 More than 1×10 21 cm -3 In one example, the peak value of the n-type impurity concentration in the first terminal side contact region 33 can be 5×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0034] As described above, in the first pin junction 30, the p-type first terminal side high concentration region 31 constitutes the P layer of the pin diode, the n-type first terminal side low concentration region 32 constitutes the I layer of the pin diode, and the n-type first terminal side contact region 33 constitutes the N layer of the pin diode. That is, the first terminal side high concentration region 31, the first terminal side low concentration region 32, and the first terminal side contact region 33 constitute a pin junction in the Z direction. Therefore, in the first pin junction 30, the first terminal side high concentration region 31, the first terminal side low concentration region 32, and the first terminal side contact region 33 constitute a pin diode (diode 201) in the first polarity direction.

[0035] The first dividing region 34 is a p-type region provided so as to surround the first terminal side low-concentration region 32 in a plan view. The first dividing region 34 separates the first terminal side low-concentration region 32 from the third semiconductor layer 25 outside the first pin junction 30. The first dividing region 34 is provided in a region closer to the first surface 20S than the first terminal side high-concentration region 31, at a position overlapping with the first terminal side high-concentration region 31 in a plan view. The first dividing region 34 is provided spaced apart from the first terminal side contact region 33 in a plan view. The first dividing region 34 is provided so as to surround the first terminal side contact region 33 in a plan view.

[0036] The p-type impurity concentration of the first partition region 34 may be higher than the p-type impurity concentration of the third region 31C of the first-terminal-side high-concentration region 31. In one example, the p-type impurity concentration of the first partition region 34 is 1×10 17 cm -3 More than 1×10 18 cm -3 The p-type impurity concentration of the first partition region 34 can be changed arbitrarily within a range in which the first terminal side low concentration region 32 can be partitioned from the third semiconductor layer 25.

[0037] In the first pin junction 30, a pin diode is formed by the first dividing region 34, the first terminal side low concentration region 32, and the first terminal side contact region 33. In this manner, the first pin junction 30 is provided with a first current path in which a forward current flows through the first terminal side high concentration region 31, the first terminal side low concentration region 32, and the first terminal side contact region 33 in this order, and a second current path in which a forward current flows through the first dividing region 34, the first terminal side low concentration region 32, and the first terminal side contact region 33 in this order.

[0038] As shown in FIG. 3 , the second pin junction 40 includes a p-type second terminal side high-concentration region 41, an n-type second terminal side low-concentration region 42, an n-type second terminal side contact region 43, and a p-type second partition region 44. The second terminal side high-concentration region 41 is provided away from the first surface 20S of the semiconductor chip 20 toward the second surface 20R. The second terminal side high-concentration region 41 is provided away from the first terminal side high-concentration region 31 in a planar view. The second terminal side low-concentration region 42 is provided in a region of the first surface 20S closer to the second terminal side high-concentration region 41 so as to overlap with the second terminal side high-concentration region 41 in a planar view. The second terminal side contact region 43 is provided in a surface layer portion of the second terminal side low-concentration region 42. The second dividing region 44 is provided in a region closer to the first surface 20S than the second terminal side high-concentration region 41, at a position overlapping the second terminal side high-concentration region 41 in a plan view. The second dividing region 44 is provided to surround the second terminal side low-concentration region 42 in a plan view. In the second pin junction 40, the second terminal side high-concentration region 41, the second terminal side low-concentration region 42, and the second terminal side contact region 43 form a pin diode (diode 202). In the second pin junction 40, the second dividing region 44, the second terminal side low-concentration region 42, and the second terminal side contact region 43 form a pin diode.

[0039] Here, the configurations of the second terminal side high concentration region 41, the second terminal side low concentration region 42, the second terminal side contact region 43, and the second partition region 44 are the same as the first terminal side high concentration region 31, the first terminal side low concentration region 32, the first terminal side contact region 33, and the first partition region 34 of the first pin junction 30, so detailed explanations thereof will be omitted.

[0040] As shown in FIG. 2 , the third pin junction 50 includes a p-type third terminal side high-concentration region 51, an n-type third terminal side low-concentration region 52, an n-type third terminal side contact region 53, and a p-type third partition region 54. The third terminal side high-concentration region 51 is provided away from the first surface 20S of the semiconductor chip 20 toward the second surface 20R. The third terminal side high-concentration region 51 is provided away from both the first terminal side high-concentration region 31 and the second terminal side high-concentration region 41 in a planar view. The third terminal side low-concentration region 52 is provided in a region of the first surface 20S closer to the third terminal side high-concentration region 51 so as to overlap with the third terminal side high-concentration region 51 in a planar view. The third terminal side contact region 53 is provided in a surface layer portion of the third terminal side low-concentration region 52. The third dividing region 54 is provided in a region closer to the first surface 20S than the third terminal side high-concentration region 51, at a position overlapping the third terminal side high-concentration region 51 in a plan view. The third dividing region 54 is provided to surround the third terminal side low-concentration region 52 in a plan view. In the third pin junction 50, the third terminal side high-concentration region 51, the third terminal side low-concentration region 52, and the third terminal side contact region 53 form a pin diode (diode 203). In the third pin junction 50, the third dividing region 54, the third terminal side low-concentration region 52, and the third terminal side contact region 53 form a pin diode.

[0041] Here, the third terminal side high concentration region 51, the third terminal side low concentration region 52, the third terminal side contact region 53, and the third partition region 54 are the same as the first terminal side contact region 33 and the first partition region 34, so detailed explanations thereof will be omitted.

[0042] (Diode vs. Region) 2 and 3, the semiconductor chip 20 includes a diode pair region 60 provided at a distance from each of the first pin junction 30, the second pin junction 40, and the third pin junction 50 in a plan view. The diode pair region 60 is provided in a surface layer portion of the semiconductor chip 20.

[0043] The diode pair region 60 includes a first reverse pin junction 60A, a second reverse pin junction 60B, a third reverse pin junction 60C, and a pn junction 60E. Each of the first reverse pin junction 60A, the second reverse pin junction 60B, and the third reverse pin junction 60C is a region of the semiconductor chip 20 where a pin diode of a second polarity direction is configured. Here, the second polarity direction is the direction in which a forward current flows from the first surface 20S to the second surface 20R of the semiconductor chip 20. In other words, the second polarity direction is the opposite direction to the first polarity direction.

[0044] The diode pair region 60 includes a high-concentration region 61, a first low-concentration region 62A, a second low-concentration region 62B, a third low-concentration region 62C, a first contact region 63A, a second contact region 63B, a third contact region 63C, an internal region 64, and an isolation region 65. The high-concentration region 61, the first low-concentration region 62A, the second low-concentration region 62B, the third low-concentration region 62C, the first contact region 63A, the second contact region 63B, the third contact region 63C, the internal region 64, and the isolation region 65 form a first reverse pin junction 60A, a second reverse pin junction 60B, a third reverse pin junction 60C, and a pn junction 60E.

[0045] The high concentration region 61 is an n-type region provided at a position away from the first surface 20S and closer to the second surface 20R of the semiconductor chip 20 than the first surface 20S. The high concentration region 61 is provided at a position away from the first semiconductor layer 23 and closer to the first surface 20S in the Z direction. The high concentration region 61 is provided across the second semiconductor layer 24 and the third semiconductor layer 25 in the Z direction. The high concentration region 61 is provided in a part of the third semiconductor layer 25 in the Z direction.

[0046] The n-type impurity concentration of the high concentration region 61 is higher than the n-type impurity concentration of the second semiconductor layer 24. The n-type impurity concentration of the high concentration region 61 is higher than the n-type impurity concentration of the third semiconductor layer 25. The peak value of the n-type impurity concentration of the high concentration region 61 is 1×10 18 cm -3 More than 1×10 21 cm -3In one example, the peak value of the n-type impurity concentration of the high concentration region 61 can be 5×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0047] The first to third low-concentration regions 62A to 62C are n-type regions located closer to the first surface 20S than the high-concentration region 61. The first to third low-concentration regions 62A to 62C are located apart from one another in a plan view. Each of the first to third low-concentration regions 62A to 62C is located at a position overlapping the high-concentration region 61 in a plan view. Each of the first to third low-concentration regions 62A to 62C is exposed from the first surface 20S of the semiconductor chip 20. The first to third low-concentration regions 62A to 62C are formed by the third semiconductor layer 25. Therefore, the n-type impurity concentration of each of the first to third low-concentration regions 62A to 62C may be equal to the n-type impurity concentration of the third semiconductor layer 25. Therefore, the n-type impurity concentration of each of the first to third low-concentration regions 62A to 62C is 1×10 14 cm -3 More than 1×10 15 cm -3 In one example, the n-type impurity concentration of each of the first to third low concentration regions 62A to 62C can be set to 1×10 14 cm -3 is.

[0048] The first contact region 63A is a p-type region provided in a surface layer portion of the first low-concentration region 62A. The first contact region 63A is exposed from the first surface 20S of the semiconductor chip 20. The first contact region 63A is separated from the high-concentration region 61 in the Z direction. The p-type impurity concentration of the first contact region 63A is higher than the n-type impurity concentration of the first low-concentration region 62A.

[0049] The second contact region 63B is a p-type region provided in a surface layer portion of the second low-concentration region 62B. The second contact region 63B is exposed from the first surface 20S of the semiconductor chip 20. The second contact region 63B is separated from the high-concentration region 61 in the Z direction. The p-type impurity concentration of the second contact region 63B is higher than the n-type impurity concentration of the second low-concentration region 62B. The p-type impurity concentration of the second contact region 63B is equal to the p-type impurity concentration of the first contact region 63A.

[0050] The third contact region 63C is a p-type region provided in a surface layer portion of the third low-concentration region 62C. The third contact region 63C is exposed from the first surface 20S of the semiconductor chip 20. The third contact region 63C is separated from the high-concentration region 61 in the Z direction. The p-type impurity concentration of the third contact region 63C is higher than the n-type impurity concentration of the third low-concentration region 62C. The p-type impurity concentration of the third contact region 63C is equal to the p-type impurity concentration of the first contact region 63A.

[0051] The peak value of the p-type impurity concentration in each of the first to third contact regions 63A to 63C is 1×10 18 cm -3 More than 1×10 21 cm -3 In one example, the peak value of the p-type impurity concentration in each of the first to third contact regions 63A to 63C can be set to 5×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0052] Thus, in the first reverse pin junction 60A, the p-type first contact region 63A forms the P layer of the pin diode, the n-type first low-concentration region 62A forms the I layer of the pin diode, and the n-type high-concentration region 61 forms the N layer of the pin diode. That is, the first contact region 63A, the first low-concentration region 62A, and the high-concentration region 61 form a pin junction in the Z direction. Therefore, in the first reverse pin junction 60A, the high-concentration region 61, the first low-concentration region 62A, and the first contact region 63A form a pin diode (diode 204) in the second polarity direction.

[0053] In the second reverse pin junction 60B, the p-type second contact region 63B forms the P layer of the pin diode, the n-type second low-concentration region 62B forms the I layer of the pin diode, and the n-type high-concentration region 61 forms the N layer of the pin diode. That is, the second contact region 63B, the second low-concentration region 62B, and the high-concentration region 61 form a pin junction in the Z direction. Therefore, in the second reverse pin junction 60B, the high-concentration region 61, the second low-concentration region 62B, and the second contact region 63B form a pin diode (diode 205) in the second polarity direction.

[0054] In the third reverse pin junction 60C, the p-type third contact region 63C forms the P layer of the pin diode, the n-type third low-concentration region 62C forms the I layer of the pin diode, and the n-type high-concentration region 61 forms the N layer of the pin diode. That is, the third contact region 63C, the third low-concentration region 62C, and the high-concentration region 61 form a pin junction in the Z direction. Therefore, in the third reverse pin junction 60C, the high-concentration region 61, the third low-concentration region 62C, and the third contact region 63C form a pin diode (diode 206) in the second polarity direction.

[0055] The internal region 64 is a p-type region provided so as to be in contact with the high-concentration region 61 closer to the second surface 20R of the semiconductor chip 20 than the high-concentration region 61. The internal region 64 is provided at a position overlapping with the high-concentration region 61 in a planar view. The internal region 64 is provided across a surface portion of the first semiconductor layer 23 and a region of the second semiconductor layer 24 closer to the first semiconductor layer 23 in the Z direction. The internal region 64 is provided so as to overlap with each of the first low-concentration region 62A, the second low-concentration region 62B, and the third low-concentration region 62C in a planar view.

[0056] The internal region 64 is configured to suppress a decrease in the p-type impurity concentration of the first semiconductor layer 23. In other words, the internal region 64 is configured to maintain a predetermined p-type impurity concentration. The p-type impurity concentration of the internal region 64 is 1×10 16 cm -3 More than 1×10 19 cm -3 In one example, the p-type impurity concentration of the inner region 64 can be 1×10 18 cm -3 In this way, the p-type impurity concentration of the internal region 64 may be equal to the p-type impurity concentration of the first region 31A of the first terminal side high-concentration region 31 in the first pin junction 30.

[0057] The pn junction 60E is composed of a p-type internal region 64 and an n-type high-concentration region 61. That is, the internal region 64 and the high-concentration region 61 form a pn junction in the Z direction. Therefore, the internal region 64 and the high-concentration region 61 form a pn diode (diode 207) of the first polarity direction. The pn diode is reverse-connected to the pin diodes of the first reverse pin junction 60A, the second reverse pin junction 60B, and the third reverse pin junction 60C. Therefore, the pn junction 60E can be said to be reverse-connected to the first reverse pin junction 60A, the second reverse pin junction 60B, and the third reverse pin junction 60C. Here, the breakdown voltage of the pn junction 60E can be set by the p-type impurity concentration of the internal region 64. That is, the p-type impurity concentration of the internal region 64 is adjusted according to the desired breakdown voltage of the pn junction 60E.

[0058] The separation region 65 is an n-type region provided in a region closer to the first surface 20S than the high-concentration region 61. The separation region 65 is provided at a position overlapping the high-concentration region 61 in a plan view. The separation region 65 is a region that separates the first low-concentration region 62A, the second low-concentration region 62B, and the third low-concentration region 62C. Therefore, the separation region 65 is provided so as to surround each of the first low-concentration region 62A, the second low-concentration region 62B, and the third low-concentration region 62C in a plan view.

[0059] The peak value of the n-type impurity concentration of the isolation region 65 may be equal to the peak value of the n-type impurity concentration of the high concentration region 61. In one example, the peak value of the n-type impurity concentration of the isolation region 65 is 1×10 18 cm -3 More than 1×10 21 cm -3 In one example, the peak value of the n-type impurity concentration of the isolation region 65 can be 5×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0060] In the first reverse pin junction 60A, a pin diode is formed by the first contact region 63A, the first low-concentration region 62A, and a portion of the isolation region 65 that surrounds the first low-concentration region 62A. In this manner, the first reverse pin junction 60A is provided with a first current path in which a forward current flows through the first contact region 63A, the first low-concentration region 62A, and the high-concentration region 61 in this order, and a second current path in which a forward current flows through the first contact region 63A, the first low-concentration region 62A, and the isolation region 65 in this order.

[0061] In the second reverse pin junction 60B, a pin diode is formed by the second contact region 63B, the second low-concentration region 62B, and a portion of the isolation region 65 surrounding the second low-concentration region 62B. In this manner, the second reverse pin junction 60B is provided with a first current path in which a forward current flows through the second contact region 63B, the second low-concentration region 62B, and the high-concentration region 61 in this order, and a second current path in which a forward current flows through the second contact region 63B, the second low-concentration region 62B, and the isolation region 65 in this order.

[0062] In the third reverse pin junction 60C, a pin diode is formed by the third contact region 63C, the third low-concentration region 62C, and a portion of the isolation region 65 surrounding the third low-concentration region 62C. In this manner, the third reverse pin junction 60C is provided with a first current path in which a forward current flows through the third contact region 63C, the third low-concentration region 62C, and the high-concentration region 61 in this order, and a second current path in which a forward current flows through the third contact region 63C, the third low-concentration region 62C, and the isolation region 65 in this order.

[0063] The cathodes of the pin diodes of the first reverse pin junction 60A, the second reverse pin junction 60B, and the third reverse pin junction 60C are each electrically connected to the cathode of the pn diode of the pn junction 60E. Therefore, each of the first to third reverse pin junctions 60A to 60C forms a diode pair between itself and the pn junction 60E.

[0064] (Configuration on a semiconductor chip) The TVS diode 10 includes an insulating layer 70 covering the first surface 20S of the semiconductor chip 20. The insulating layer 70 may have a multilayer structure in which multiple insulating layers are stacked, or a single-layer structure consisting of a single insulating layer. The insulating layer 70 may include at least one of an SiO2 (silicon oxide) layer and an SiN (silicon nitride) layer. The insulating layer 70 may have a multilayer structure in which SiO2 layers and SiN layers are stacked in any order. The insulating layer 70 may have a single-layer structure composed of an SiO2 layer or an SiN layer. The thickness of the insulating layer 70 can be 1 μm or more and 10 μm or less. In one example, the thickness of the insulating layer 70 is 2 μm or more and 3 μm or less.

[0065] In one example, the insulating layer 70 includes a stacked structure of a first insulating layer 71 and a second insulating layer 72 . The first insulating layer 71 contacts the first surface 20S of the semiconductor chip 20. The first insulating layer 71 has a single-layer structure composed of a single SiO2 layer. The first insulating layer 71 is also called a field oxide film. The thickness of the first insulating layer 71 can be, for example, 14,000 Å.

[0066] The second insulating layer 72 is provided on the first insulating layer 71. The second insulating layer 72 may include at least one of an undoped silica glass (USG) layer, a phosphorus silicate glass (PSG) layer, and a boron phosphorus silicate glass (BPSG) layer. In one example, the second insulating layer 72 is configured with a stacked structure of a USG layer and a BPSG layer. The thickness of the second insulating layer 72 is thinner than the thickness of the first insulating layer 71, for example. The thickness of the second insulating layer 72 may be, for example, 6700 Å.

[0067] The insulating layer 70 includes first to sixth openings 73A to 73F and a wiring opening 73G that expose the first surface 20S of the semiconductor chip 20. Each of the first to sixth openings 73A to 73F and the wiring opening 73G penetrates the insulating layer 70 in the Z direction.

[0068] The first opening 73A exposes the first terminal side contact region 33 of the first pin junction 30. The second opening 73B exposes the second terminal side contact region 43 of the second pin junction 40. The third opening 73C exposes the third terminal side contact region 53 of the third pin junction 50. The fourth opening 73D exposes the first contact region 63A of the first reverse pin junction 60A. The fifth opening 73E exposes the second contact region 63B of the second reverse pin junction 60B. The sixth opening 73F exposes the third contact region 63C of the third reverse pin junction 60C.

[0069] The wiring opening 73G exposes the isolation region 65 of the diode pair region 60. Therefore, the isolation region 65 includes an exposed surface 65S that is exposed from the first surface 20S of the semiconductor chip 20. The TVS diode 10 includes a first connection electrode 81, a second connection electrode 82, and a third connection electrode 83 provided on an insulating layer 70. Each of the first to third connection electrodes 81 to 83 is made of a material containing at least one of Cu (copper) and Al (aluminum). In one example, each of the first to third connection electrodes 81 to 83 is made of AlCu. The thickness of each of the first to third connection electrodes 81 to 83 can be set to, for example, 42,000 Å.

[0070] The first connection electrode 81 electrically connects the first terminal side contact region 33 of the first pin junction 30 and the first contact region 63A of the first reverse pin junction 60A. The first connection electrode 81 contacts the first terminal side contact region 33 through a first opening 73A of the insulating layer 70. The first connection electrode 81 contacts the first contact region 63A through a fourth opening 73D of the insulating layer 70.

[0071] The second connection electrode 82 electrically connects the second terminal side contact region 43 of the second pin junction 40 and the second contact region 63B of the second reverse pin junction 60B. The second connection electrode 82 contacts the second terminal side contact region 43 through the second opening 73B of the insulating layer 70. The second connection electrode 82 contacts the second contact region 63B through the fifth opening 73E of the insulating layer 70.

[0072] The third connection electrode 83 electrically connects the third terminal side contact region 53 of the third pin junction 50 and the third contact region 63C of the third reverse pin junction 60B. The third connection electrode 83 is in contact with the third terminal side contact region 53 through the third opening 73C of the insulating layer 70. The third connection electrode 83 is in contact with the third contact region 63C through the sixth opening 73F of the insulating layer 70.

[0073] The TVS diode 10 includes a wiring 90 connected to the exposed surface 65S of the separation region 65 of the diode pair region 60. The wiring 90 is made of a material containing at least one of Cu and Al. In one example, the wiring 90 is made of AlCu. That is, the wiring 90 may be made of the same material as each of the first to third connection electrodes 81 to 83. The detailed configuration of the wiring 90 will be described later.

[0074] The TVS diode 10 includes a protective layer 74 that covers the insulating layer 70, the first to third connection electrodes 81 to 83, and the wiring 90. The protective layer 74 is an insulating layer that protects the semiconductor chip 20. The protective layer 74 may have a multilayer structure in which a plurality of insulating layers are stacked, or may have a single-layer structure made of a single insulating layer.

[0075] In one example, the protective layer 74 has a laminated structure of a first protective layer 75 and a second protective layer 76. In one example, the first protective layer 75 may be a passivation layer, and the second protective layer 76 may be a resin layer.

[0076] The first protective layer 75 may have a single layer structure including an SiO layer or an SiN layer, or may have a multilayer structure in which an SiO layer and an SiN layer are stacked in any order. In one example, the first protective layer 75 has a single layer structure composed of an SiN layer.

[0077] The second protective layer 76 may include a photosensitive resin. Examples of the photosensitive resin that the second protective layer 76 may include include at least one of PI (polyimide), PA (polyamide), and PBO (polybenzoxazole). In one example, the second protective layer 76 includes PI.

[0078] The protective layer 74 includes first to third terminal openings 77A to 77C. The first to third terminal openings 77A to 77C penetrate the protective layer 74 in the Z direction. The first terminal opening 77A partially exposes the first connection electrode 81. The first terminal opening 77A is provided at a position overlapping with the first opening 73A of the insulating layer 70 in a plan view. The second terminal opening 77B partially exposes the second connection electrode 82. The second terminal opening 77B is provided at a position overlapping with the second opening 73B of the insulating layer 70 in a plan view. The third terminal opening 77C partially exposes the third connection electrode 83. The third terminal opening 77C is provided at a position overlapping with the third opening 73C of the insulating layer 70 in a plan view.

[0079] [Planar structure of TVS diode] The planar structure of the TVS diode 10 will be described with reference to FIG. 1 and FIGS. 4 to 7. FIG. 4 schematically shows the planar structure of the first surface 20S of the semiconductor chip 20. FIG. 5 schematically shows the cross-sectional structure of the semiconductor chip 20 cut along line F5-F5 in FIG. 3. FIG. 6 schematically shows an enlarged cross-sectional structure of a portion of both the high-concentration region 61 and the internal region 64 in FIG. 5. Note that hatching lines are omitted in FIGS. 5 and 6 to facilitate understanding of the drawings. FIG. 7 schematically shows the planar structure of the first to third connection electrodes 81 to 83 and the wiring 90 of the TVS diode 10.

[0080] (Semiconductor chip) 4, the TVS diode 10 includes a peripheral region 110 provided on the periphery of the first surface 20S of the semiconductor chip 20. The peripheral region 110 is a region containing p-type impurities. The peripheral region 110 is provided to surround the first pin junction 30, the second pin junction 40, the third pin junction 50, and the diode pair region 60 in plan view.

[0081] The peripheral region 110 is integrated with the first terminal side high concentration region 31 (see FIG. 2) and the first partition region 34 of the first pin junction 30, the second terminal side high concentration region 41 (see FIG. 3) and the second partition region 44 of the second pin junction 40, and the third terminal side high concentration region 51 (see FIG. 2) and the third partition region 54 of the third pin junction 50. The concentration gradient of the p-type impurity concentration in the peripheral region 110 is similar to that of the first terminal side high concentration region 31 and the first partition region 34, for example.

[0082] In a plan view, the peripheral region 110 includes a first region 111 extending along the first side surface 20A, a second region 112 extending along the second side surface 20B, a third region 113 extending along the third side surface 20C, and a fourth region 114 extending along the fourth side surface 20D.

[0083] The first pin joint 30, the second pin joint 40, and the third pin joint 50 are spaced apart from one another. More specifically, the first pin joint 30 and the third pin joint 50 are located at the same position in the Y direction and spaced apart from one another in the X direction. The first pin joint 30 and the third pin joint 50 are located at ends of the first surface 20S of the semiconductor chip 20 in the Y direction that are closer to the fourth side surface 20D. The first pin joint 30 is located at ends of the first surface 20S in the X direction that are closer to the first side surface 20A. The third pin joint 50 is located at ends of the first surface 20S in the X direction that are closer to the second side surface 20B.

[0084] The second pin joint 40 is located at a different position in the X and Y directions relative to both the first pin joint 30 and the third pin joint 50. The second pin joint 40 is located at one of the two Y-direction ends of the first surface 20S of the semiconductor chip 20, the end closest to the third side surface 20C. The second pin joint 40 is located at the center of the first surface 20S in the X direction. Therefore, when viewed from the Y direction, the second pin joint 40 can be said to be located between the first pin joint 30 and the third pin joint 50 in the X direction.

[0085] The first partition region 34 of the first pin joint 30 is connected to the first region 111 and the fourth region 114 of the outer circumferential region 110. Therefore, the first terminal side low concentration region 32 of the first pin joint 30 is partitioned by the first region 111, the fourth region 114, and the first partition region 34 in a plan view. The first partition region 34 includes a first portion connected to the first region 111 and extending in the X direction, a second portion connected to the fourth region 114 and extending in the Y direction, and a connecting portion connecting the first portion and the second portion. The connecting portion is curved in a plan view.

[0086] The first terminal side low-concentration region 32 has a rectangular shape in a plan view. Each of the four corners of the rectangular first terminal side low-concentration region 32 is curved. The first terminal side contact region 33 has a rectangular shape in a plan view. Each of the four corners of the rectangular first terminal side contact region 33 is curved. The first terminal side contact region 33 is slightly smaller than the first terminal side low-concentration region 32 in a plan view.

[0087] The second partition region 44 of the second pin joint 40 is connected to the third region 113 of the outer peripheral region 110. The second partition region 44 is U-shaped and opens toward the third region 113 in a plan view. The second terminal side low-concentration region 42 of the second pin joint 40 is partitioned by the third region 113 and the second partition region 44 in a plan view. The second partition region 44 includes a first portion and a second portion connected to the third region 113 and extending in the Y direction, and a third portion spaced apart from the third region 113 toward the fourth side surface 20D and extending in the X direction. The first portion and the second portion are spaced apart from each other in the X direction. The second partition region 44 includes a first connection portion connecting the first portion and the third portion and a second connection portion connecting the second portion and the third portion. Each connection portion is curved in a plan view.

[0088] The second terminal side low-concentration region 42 has a rectangular shape in a plan view. Each of the four corners of the rectangular second terminal side low-concentration region 42 is curved. The second terminal side low-concentration region 42 may have the same size and shape as, for example, the first terminal side low-concentration region 32. The second terminal side contact region 43 has a rectangular shape in a plan view. Each of the four corners of the rectangular second terminal side contact region 43 is curved. The second terminal side contact region 43 is slightly smaller than the second terminal side low-concentration region 42 in a plan view. The second terminal side contact region 43 may have the same size and shape as, for example, the first terminal side contact region 33.

[0089] The third partition region 54 of the third pin joint 50 is connected to the second region 112 and the fourth region 114 of the outer circumferential region 110. Therefore, the third terminal side low concentration region 52 of the third pin joint 50 is partitioned by the second region 112, the fourth region 114, and the third partition region 54 in a plan view. The third partition region 54 includes a first portion connected to the second region 112 and extending in the X direction, a second portion connected to the fourth region 114 and extending in the Y direction, and a connecting portion connecting the first portion and the second portion. The connecting portion is curved in a plan view.

[0090] The third terminal side low-concentration region 52 has a rectangular shape in a plan view. Each of the four corners of the rectangular third terminal side low-concentration region 52 is curved. The third terminal side low-concentration region 52 may have the same size and shape as, for example, the first terminal side low-concentration region 32. The third terminal side contact region 53 has a rectangular shape in a plan view. Each of the four corners of the rectangular third terminal side contact region 53 is curved. The third terminal side contact region 53 is slightly smaller than the third terminal side low-concentration region 52 in a plan view. The third terminal side contact region 53 may have the same size and shape as, for example, the first terminal side contact region 33.

[0091] In one example, the shortest distance DA between the first defined area 34 and the second defined area 44 is equal to the shortest distance DB between the second defined area 44 and the third defined area 54. The shortest distance DC between the first defined area 34 and the third defined area 54 may be equal to or less than the shortest distances DA and DB.

[0092] The diode pair region 60 is provided in a region surrounded by the peripheral region 110, the first partition region 34, the second partition region 44, and the third partition region 54 in a plan view. Therefore, the diode pair region 60 is provided between the first pin junction 30 and the second pin junction 40, between the second pin junction 40 and the third pin junction 50, and between the first pin junction 30 and the third pin junction 50.

[0093] Diode pair region 60 includes a first region 66A, a second region 66B, and a third region 66C. The first region 66A is a region aligned with the first pin joint 30 in the Y direction. The first region 66A is disposed closer to the third side surface 20C than the first pin joint 30. The first reverse pin joint 60A is provided in the first region 66A. Therefore, it can be said that the first pin joint 30 and the first reverse pin joint 60A are aligned in the Y direction in a plan view. The first region 66A includes a region aligned with the second pin joint 40 in the X direction. The first region 66A is disposed closer to the first side surface 20A than the second pin joint 40 in the X direction. When viewed from the X direction, the first reverse pin joint 60A includes a portion overlapping with the second pin joint 40.

[0094] The first region 66A has a substantially rectangular shape in plan view. In one example, the first region 66A has a substantially rectangular shape with the Y direction as its longitudinal direction and the X direction as its lateral direction. The first region 66A includes first to fourth sides 66AA to 66AD. The first side 66AA is a side of the first region 66A closer to the first side surface 20A and extends in the Y direction in plan view. The second side 66AB is a side of the first region 66A closer to the second side surface 20B and extends in the Y direction in plan view. The length of the second side 66AB in the Y direction is shorter than the length of the first side 66AA in the Y direction. The third side 66AC is a side of the first region 66A closer to the third side surface 20C and extends in the X direction in plan view. The fourth side 66AD is a side of the first region 66A closer to the fourth side surface 20D and extends in the X direction in plan view. The length of the fourth side 66AD in the X direction is shorter than the length of the third side 66AC in the X direction.

[0095] The first region 66A includes a corner portion between the first side 66AA and the third side 66AC, a corner portion between the first side 66AA and the fourth side 66AD, and a corner portion between the second side 66AB and the third side 66AC. Each corner portion is curved in a plan view.

[0096] The second region 66B is aligned with the second pin junction 40 in the Y direction. The second region 66B is positioned closer to the fourth side surface 20D than the second pin junction 40. The second region 66B is provided with the second reverse pin junction 60B. Therefore, the second pin junction 40 and the second reverse pin junction 60B are aligned in the Y direction in a plan view. The second region 66B includes a region positioned between the first pin junction 30 and the third pin junction 50 in the X direction. Therefore, the second region 66B includes a region shifted in the Y direction relative to the first region 66A. The second region 66B is positioned closer to the second side surface 20B than the first region 66A in the X direction. When viewed from the X direction, the second reverse pin junction 60B includes portions overlapping both the first pin junction 30 and the third pin junction 50.

[0097] The second region 66B has a substantially rectangular shape in plan view. In one example, the second region 66B has a substantially rectangular shape with the Y direction as its longitudinal direction and the X direction as its lateral direction. The second region 66B includes first to fourth sides 66BA to 66BD. The first side 66BA is a side of the second region 66B closer to the first side surface 20A and extends in the Y direction in plan view. The length of the first side 66BA in the Y direction is equal to, for example, the length of the second side 66AB of the first region 66A in the Y direction. The second side 66BB is a side of the second region 66B closer to the second side surface 20B and extends in the Y direction in plan view. The length of the second side 66BB in the Y direction is equal to the length of the first side 66BA in the Y direction. The third side 66BC is a side of the second region 66B closer to the third side surface 20C and extends in the X direction in plan view. The fourth side 66BD is a side of the second region 66B closer to the fourth side surface 20D and extends in the X direction in a plan view. The first side 66BA, the second side 66BB, and the fourth side 66BD are each disposed closer to the fourth side surface 20D than the first region 66A in the Y direction. The length of the fourth side 66BD in the X direction is longer than the length of the third side 66BC in the X direction. The length of the third side 66BC in the X direction is shorter than the length of the third side 66AC of the first region 66A in the X direction.

[0098] The second region 66B includes a corner portion between the first side 66BA and the fourth side 66BD, and a corner portion between the second side 66BB and the fourth side 66BD. Each corner portion is curved in a plan view.

[0099] The third region 66C is a region aligned with the third pin joint 50 in the Y direction. The third region 66C is located closer to the third side surface 20C than the third pin joint 50. The third region 66C is located at the same position as the first region 66A in the Y direction. The third region 66C is located away from the first region 66A in the X direction. The third region 66C is provided with the third reverse pin joint 60C. Therefore, the third pin joint 50 and the third reverse pin joint 60C can be said to be aligned in the Y direction in a plan view. The third region 66C includes a region aligned with the second pin joint 40 in the X direction. The third region 66C is located closer to the second side surface 20B than the second pin joint 40 in the X direction. Therefore, the second pin joint 40 can be said to be located between the first region 66A and the third region 66C in the X direction. When viewed from the X direction, the third reverse pin junction 60C includes a portion that overlaps with the second pin junction 40.

[0100] The third region 66C has a substantially rectangular shape in plan view. In one example, the third region 66C has a substantially rectangular shape with the Y direction as its longitudinal direction and the X direction as its lateral direction. The third region 66C includes first to fourth sides 66CA to 66CD. The first side 66CA is a side of the third region 66C closer to the first side surface 20A and extends in the Y direction in plan view. The length in the Y direction of the first side 66CA is equal to, for example, the length in the Y direction of the second side 66AB of the first region 66A. The second side 66CB is a side of the third region 66C closer to the second side surface 20B and extends in the Y direction in plan view. The length in the Y direction of the second side 66CB is longer than the length in the Y direction of the first side 66CA. The length in the Y direction of the second side 66CB is equal to, for example, the length in the Y direction of the first side 66AA of the first region 66A. The third side 66CC is a side of the third region 66C closer to the third side surface 20C and extends in the X direction in plan view. The fourth side 66CD is a side of the third region 66C closer to the fourth side surface 20D and extends in the X direction in plan view. The length in the X direction of the third side 66CC is longer than the length in the X direction of the fourth side 66CD. The length in the X direction of the third side 66CC is equal to, for example, the length in the X direction of the third side 66AC of the first region 66A. The length in the X direction of the fourth side 66CD is equal to, for example, the length in the X direction of the fourth side 66AD of the first region 66A.

[0101] The third region 66C includes a corner portion between the first side 66CA and the third side 66CC, a corner portion between the second side 66CB and the fourth side 66CD, and a corner portion between the second side 66CB and the third side 66CC. Each corner portion is curved in a plan view.

[0102] In the example shown in FIG. 4 , the width dimension (X-direction dimension) WB of the second region 66B is larger than the width dimension (X-direction dimension) WA of the first region 66A and the width dimension (X-direction dimension) WC of the third region 66C. The width dimension WA of the first region 66A is equal to the width dimension WC of the third region 66C. Note that the width dimension WA of the first region 66A, the width dimension WB of the second region 66B, and the width dimension WC of the third region 66C can each be changed as desired. In one example, the width dimension WA of the first region 66A may be different from the width dimension WC of the third region 66C. In one example, the width dimension WB of the second region 66B may be equal to the width dimension WA of the first region 66A. In one example, the width dimension WB of the second region 66B may be equal to the width dimension WC of the third region 66C.

[0103] The diode pair region 60 includes a first connection region 67A connecting the first region 66A and the second region 66B and a second connection region 67B connecting the second region 66B and the third region 66C. The first connection region 67A is provided between the first region 66A and the second region 66B in the X direction, and the second connection region 67B is provided between the second region 66B and the third region 66C in the X direction. The first connection region 67A is disposed between the first pin junction 30 and the second pin junction 40 in a direction intersecting both the X direction and the Y direction in a plan view. The second connection region 67B is disposed between the second pin junction 40 and the third pin junction 50 in a direction intersecting both the X direction and the Y direction in a plan view.

[0104] The first connection region 67A connects a second side 66AB of the first region 66A to a third side 66BC of the second region 66B, and also connects a fourth side 66AD of the first region 66A to a first side 66BA of the second region 66B. Both ends of the first connection region 67A in the Y direction are curved in a plan view. The radii of curvature of both ends of the first connection region 67A in the Y direction are larger than the radii of curvature of each corner portion of the first region 66A.

[0105] The second connection region 67B connects the second side 66BB of the second region 66B to the fourth side 66CD of the third region 66C, and also connects the third side 66BC of the second region 66B to the first side 66CA of the third region 66C. Both ends of the second connection region 67B in the Y direction are curved in a plan view. The radii of curvature of both ends of the second connection region 67B in the Y direction are greater than the radii of curvature of each corner portion of the third region 66C.

[0106] The first low-concentration region 62A of the first reverse pin junction 60A has an elliptical shape with the Y direction as the longitudinal direction and the X direction as the lateral direction in a plan view. For example, the X-direction dimension (width dimension) of the first low-concentration region 62A is smaller than the X-direction dimension of the first-terminal-side low-concentration region 32 of the first pin junction 30. For example, the width dimension of the first low-concentration region 62A is smaller than the X-direction dimension of the first-terminal-side contact region 33 of the first pin junction 30. For example, the Y-direction dimension (length dimension) of the first low-concentration region 62A is larger than the Y-direction dimension of the first-terminal-side low-concentration region 32.

[0107] The first contact region 63A of the first reverse pin junction 60A has an elliptical shape with the Y direction as the longitudinal direction and the X direction as the lateral direction in a plan view. The first contact region 63A is slightly smaller than the first low-concentration region 62A in a plan view. The X-direction dimension (width dimension) of the first contact region 63A is smaller than the X-direction dimension of the first terminal-side contact region 33. The Y-direction dimension (length dimension) of the first contact region 63A is larger than the Y-direction dimension of the first terminal-side low-concentration region 32.

[0108] The second reverse pin junction 60B is disposed closer to the fourth side surface 20D than the first reverse pin junction 60A. The second reverse pin junction 60B includes a region overlapping with the first reverse pin junction 60A when viewed from the X direction. More specifically, both the second low-concentration region 62B and the second contact region 63B of the second reverse pin junction 60B include regions overlapping with both the first low-concentration region 62A and the first contact region 63A of the first reverse pin junction 60A.

[0109] The second low-concentration region 62B has an elliptical shape with the Y direction as the longitudinal direction and the X direction as the lateral direction in a plan view. In one example, the X-direction dimension (width dimension) of the second low-concentration region 62B is smaller than the X-direction dimension of the second-terminal-side low-concentration region 42 of the second pin joint 40. In one example, the width dimension of the second low-concentration region 62B is smaller than the X-direction dimension of the second-terminal-side contact region 43 of the second pin joint 40. In one example, the Y-direction dimension (length dimension) of the second low-concentration region 62B is larger than the Y-direction dimension of the second-terminal-side low-concentration region 42. In one example, the width and length dimensions of the second low-concentration region 62B are equal to the width and length dimensions of the first low-concentration region 62A.

[0110] The second contact region 63B has an oval shape with the Y direction as the longitudinal direction and the X direction as the lateral direction in a plan view. The second contact region 63B is slightly smaller than the second low-concentration region 62B in a plan view. The X-direction dimension (width dimension) of the second contact region 63B is smaller than the X-direction dimension of the second terminal-side contact region 43. The Y-direction dimension (length dimension) of the second contact region 63B is larger than the Y-direction dimension of the second terminal-side low-concentration region 42. In one example, the width and length dimensions of the second contact region 63B are equal to the width and length dimensions of the first contact region 63A.

[0111] The third reverse pin junction 60C is disposed closer to the third side surface 20C than the second reverse pin junction 60B. The third reverse pin junction 60C includes a region overlapping with the second reverse pin junction 60B when viewed from the X direction. More specifically, both the third low-concentration region 62C and the third contact region 63C of the third reverse pin junction 60C include regions overlapping with both the second low-concentration region 62B and the second contact region 63B. The third reverse pin junction 60C is disposed at the same position as the first reverse pin junction 60A in the Y direction.

[0112] The third low-concentration region 62C has an elliptical shape with the Y direction as the longitudinal direction and the X direction as the lateral direction in a plan view. For example, the X-direction dimension (width dimension) of the third low-concentration region 62C is smaller than the X-direction dimension of the third-terminal-side low-concentration region 52 of the third pin joint 50. For example, the width dimension of the third low-concentration region 62C is smaller than the X-direction dimension of the third-terminal-side contact region 53 of the third pin joint 50. For example, the Y-direction dimension (length dimension) of the third low-concentration region 62C is larger than the Y-direction dimension of the third-terminal-side low-concentration region 52. For example, the width and length dimensions of the third low-concentration region 62C are equal to the width and length dimensions of the first low-concentration region 62A.

[0113] The third contact region 63C has an elliptical shape with the Y direction as the longitudinal direction and the X direction as the lateral direction in a plan view. The third contact region 63C is slightly smaller than the third low-concentration region 62C in a plan view. The X-direction dimension (width dimension) of the third contact region 63C is smaller than the X-direction dimension of the third terminal side contact region 53. The Y-direction dimension (length dimension) of the third contact region 63C is larger than the Y-direction dimension of the third terminal side low-concentration region 52. In one example, the width dimension and length dimension of the third contact region 63C are equal to the width dimension and length dimension of the first contact region 63A.

[0114] The high concentration region 61 has the same area as the diode pair region 60 in plan view. The shape and size of the high concentration region 61 in plan view are the same as the shape and size of the diode pair region 60 in plan view.

[0115] The isolation region 65 is the region of the high-concentration region 61 excluding the first low-concentration region 62A, the second low-concentration region 62B, the third low-concentration region 62C, the first contact region 63A, the second contact region 63B, and the third contact region 63C in a planar view. Therefore, the isolation region 65 is provided in both the first connection region 67A and the second connection region 67B in a planar view. The isolation region 65 is provided around the entire periphery of the outer edge of the diode pair region 60 (high-concentration region 61). The isolation region 65 is provided in the first region 66A so as to surround the entire periphery of the first low-concentration region 62A. The isolation region 65 is provided in the second region 66B so as to surround the entire periphery of the second low-concentration region 62B. The isolation region 65 is provided in the third region 66C so as to surround the entire periphery of the third low-concentration region 62C.

[0116] The area of ​​the separation region 65 in a plan view is larger than the sum of the area of ​​the first low-concentration region 62A in a plan view, the area of ​​the second low-concentration region 62B in a plan view, and the area of ​​the third low-concentration region 62C in a plan view.

[0117] 5, the internal region 64 is provided so as to overlap all of the first region 66A, the second region 66B, and the third region 66C in a plan view. The internal region 64 is provided so as to overlap both the first connection region 67A and the second connection region 67B in a plan view. In one example, the internal region 64 is slightly smaller than the high-concentration region 61 in a plan view.

[0118] Similar to the diode pair region 60, the internal region 64 includes a first region 68A, a second region 68B, and a third region 68C, as well as a first connection region 69A and a second connection region 69B. The first region 68A is disposed at a position overlapping with the first region 66A in a plan view. The first region 68A is slightly smaller than the first region 66A in a plan view. The first region 68A includes first to fourth sides 68AA to 68AD. The first to fourth sides 68AA to 68AD correspond to the first to fourth sides 66AA to 66AD of the first region 66A in a plan view. The first to fourth sides 68AA to 68AD are disposed inside the first region 66A with respect to the first to fourth sides 66AA to 66AD of the first region 66A in a plan view. In other words, the first region 68A can be said to be disposed within the first region 66A in a plan view. The first region 68A is also disposed so as to overlap the entire first low-concentration region 62A (see FIG. 4) in a plan view.

[0119] The second region 68B is disposed at a position overlapping with the second region 66B in a plan view. The second region 68B is slightly smaller than the second region 66B in a plan view. The second region 68B includes first to fourth sides 68BA to 68BD. The first to fourth sides 68BA to 68BD correspond to the first to fourth sides 66BA to 66BD of the second region 66B in a plan view. The first to fourth sides 68BA to 68BD are disposed inside the second region 66B with respect to the first to fourth sides 66BA to 66BD of the second region 66B in a plan view. In other words, the second region 68B can be said to be disposed within the second region 66B in a plan view. The second region 68B is also disposed so as to overlap the entire second low-concentration region 62B (see FIG. 4) in a plan view.

[0120] The third region 68C is disposed at a position overlapping with the third region 66C in a plan view. The third region 68C is slightly smaller than the third region 66C in a plan view. The third region 68C includes first to fourth sides 68CA to 68CD. The first to fourth sides 68CA to 68CD correspond to the first to fourth sides 66CA to 66CD of the third region 66C in a plan view. The first to fourth sides 68CA to 68CD are disposed inside the third region 66C with respect to the first to fourth sides 66CA to 66CD of the third region 66C in a plan view. In other words, the third region 68C can be said to be disposed within the third region 66C in a plan view. The third region 68C is also disposed so as to overlap the entire third low-concentration region 62C (see FIG. 4) in a plan view.

[0121] The first connection region 69A is disposed at a position overlapping the first connection region 67A in a plan view. The first connection region 69A is slightly smaller than the first connection region 67A in a plan view. The first connection region 69A is disposed within the first connection region 67A in a plan view. The first connection region 69A connects a second side 68AB of the first region 68A to a third side 68BC of the second region 68B, and also connects a fourth side 68AD of the first region 68A to a first side 68BA of the second region 68B. Both ends of the first connection region 69A in the Y direction are curved in a plan view. The radii of curvature of both ends of the first connection region 69A in the Y direction are larger than the radii of curvature of the corners of the first region 68A.

[0122] The second connection region 69B is positioned so as to overlap the second connection region 67B in a plan view. The second connection region 69B is slightly smaller than the second connection region 67B in a plan view. The second connection region 69B is positioned within the second connection region 67B in a plan view. The second connection region 69B connects the second side 68BB of the second region 68B to the fourth side 68CD of the third region 68C, and also connects the third side 68BC of the second region 68B to the first side 68CA of the third region 68C. Both ends of the second connection region 69B in the Y direction are curved in a plan view. The radii of curvature of both ends of the second connection region 69B in the Y direction are greater than the radii of curvature of the corners of the third region 68C.

[0123] In this way, the internal region 64 is provided so as to overlap the entire first low-concentration region 62A, the entire second low-concentration region 62B, and the entire third low-concentration region 62C in a planar view. The internal region 64 has a shape similar to that of the high-concentration region 61 (diode pair region 60) in a planar view.

[0124] 6, the distance DD between the outer periphery of the internal region 64 and the outer periphery of the high-concentration region 61 is constant, for example, along the entire outer periphery of the internal region 64. The distance DD can be, for example, about 5 μm. Furthermore, the center of curvature C1 of the corner portion of the internal region 64 may be located at the same position as the center of curvature C2 of the corner portion of the high-concentration region 61 that corresponds to the corner portion of the internal region 64. Therefore, the radius of curvature of the corner portion of the internal region 64 is smaller than the radius of curvature of the corner portion of the high-concentration region 61.

[0125] (Connection electrodes and wiring) 7, the first connection electrode 81, the second connection electrode 82, and the third connection electrode 83 are each arranged within the outer circumferential region 110 (see FIG. 4) in a plan view. The first connection electrode 81, the second connection electrode 82, and the third connection electrode 83 are arranged spaced apart from one another.

[0126] The first connection electrode 81 is disposed closer to the first side surface 20A than the center of the semiconductor chip 20 in the X direction in a plan view. The first connection electrode 81 extends along the Y direction. The first connection electrode 81 includes a pin connection portion 81A and a wiring portion 81B extending in the Y direction from the pin connection portion 81A toward the third side surface 20C. In one example, the pin connection portion 81A and the wiring portion 81B are integrated.

[0127] The pin connection portion 81A is disposed at a position overlapping with the first pin joint 30 (see FIG. 4) in a plan view. The pin connection portion 81A is rectangular in a plan view. The pin connection portion 81A is disposed within the first terminal side low concentration region 32 (see FIG. 4) of the first pin joint 30 in a plan view. The pin connection portion 81A is slightly larger than the first terminal side contact region 33 of the first pin joint 30 in a plan view.

[0128] The wiring portion 81B is strip-shaped with a width in the X direction in a plan view. The width dimension of the wiring portion 81B is smaller than the dimension of the pin connection portion 81A in the X direction. The wiring portion 81B is arranged offset in the X direction with respect to the pin connection portion 81A. More specifically, a virtual line CL1 extending in the Y direction at the width center of the wiring portion 81B is positioned closer to the second side surface 20B than a virtual line CL2 extending in the Y direction at the center of the pin connection portion 81A in the X direction.

[0129] The wiring portion 81B is provided so as to cover the first contact region 63A of the first reverse pin junction 60A in a plan view. In one example, the wiring portion 81B covers the entire first contact region 63A in a plan view. Therefore, the width dimension of the wiring portion 81B is larger than the width dimension of the first contact region 63A. On the other hand, the width dimension of the wiring portion 81B is smaller than the width dimension of the first low-concentration region 62A. The tip portion of the wiring portion 81B is curved in a plan view.

[0130] A reverse pin connection portion 81C is provided in a position of the wiring portion 81B that overlaps with the first contact region 63A. The reverse pin connection portion 81C is connected to the first contact region 63A.

[0131] The second connection electrode 82 extends along the Y direction. The second connection electrode 82 is arranged in the X direction away from the first connection electrode 81 and closer to the second side surface 20B. The second connection electrode 82 includes a portion that overlaps with the first connection electrode 81 when viewed from the X direction. In one example, the second connection electrode 82 is arranged in the center of the semiconductor chip 20 in the X direction when viewed in a plan view.

[0132] The second connection electrode 82 includes a pin connection portion 82A and a wiring portion 82B extending in the Y direction from the pin connection portion 82A toward the fourth side surface 20D. In one example, the pin connection portion 82A and the wiring portion 82B are integrated.

[0133] The pin connection portion 82A is disposed at a position overlapping the second pin joint 40 (see FIG. 4) in a plan view. The pin connection portion 82A is rectangular in a plan view. The pin connection portion 82A is disposed within the second terminal side low concentration region 42 (see FIG. 4) of the second pin joint 40 in a plan view. The pin connection portion 82A is slightly larger than the second terminal side contact region 43 of the second pin joint 40 in a plan view. In one example, the size and shape of the pin connection portion 82A are the same as those of the pin connection portion 81A.

[0134] The wiring portion 82B has a strip shape with a width in the X direction in a plan view. The width dimension of the wiring portion 82B is smaller than the dimension of the pin connection portion 82A in the X direction. The wiring portion 82B is provided to cover the second contact region 63B of the second reverse pin junction 60B in a plan view. In one example, the wiring portion 82B covers the entire second contact region 63B in a plan view. Therefore, the width dimension of the wiring portion 82B is larger than the width dimension of the second contact region 63B. On the other hand, the width dimension of the wiring portion 82B is smaller than the width dimension of the second low-concentration region 62B. The tip of the wiring portion 82B is curved in a plan view. In one example, the size and shape of the wiring portion 82B are the same as those of the wiring portion 81B. The wiring portion 82B is connected to the center of the pin connection portion 82A in the X direction.

[0135] A reverse pin connection portion 82C is provided in a position of the wiring portion 82B that overlaps with the second contact region 63B. The reverse pin connection portion 82C is connected to the second contact region 63B.

[0136] The third connection electrode 83 extends along the Y direction. The third connection electrode 83 is disposed in the X direction away from the second connection electrode 82 and closer to the second side surface 20B. The third connection electrode 83 includes a portion that overlaps with the second connection electrode 82 when viewed from the X direction. In one example, the third connection electrode 83 is disposed in the same position as the first connection electrode 81 in the Y direction.

[0137] The third connection electrode 83 includes a pin connection portion 83A and a wiring portion 83B extending in the Y direction from the pin connection portion 83A toward the third side surface 20C. In one example, the pin connection portion 83A and the wiring portion 83B are integrated.

[0138] The pin connection portion 83A is disposed at a position overlapping with the third pin joint 50 (see FIG. 4) in a plan view. The pin connection portion 83A is rectangular in a plan view. The pin connection portion 83A is disposed within the third terminal side low concentration region 52 (see FIG. 4) of the third pin joint 50 in a plan view. The pin connection portion 83A is slightly larger than the third terminal side contact region 53 of the third pin joint 50 in a plan view. In one example, the size and shape of the pin connection portion 83A are the same as those of the pin connection portion 81A.

[0139] The wiring portion 83B is strip-shaped with a width in the X direction in a plan view. The width dimension of the wiring portion 83B is smaller than the dimension of the pin connection portion 83A in the X direction. The wiring portion 83B is arranged offset in the X direction with respect to the pin connection portion 83A. More specifically, a virtual line CL3 extending in the Y direction from the width center of the wiring portion 83B is positioned closer to the first side surface 20A than a virtual line CL4 extending in the Y direction from the X direction center of the pin connection portion 83A.

[0140] The wiring portion 83B is provided so as to cover the third contact region 63C of the third reverse pin junction 60C in a plan view. In one example, the wiring portion 83B covers the entire third contact region 63C in a plan view. Therefore, the width dimension of the wiring portion 83B is larger than the width dimension of the third contact region 63C. On the other hand, the width dimension of the wiring portion 83B is smaller than the width dimension of the third low-concentration region 62C. The tip portion of the wiring portion 83B is curved in a plan view. In one example, the size and shape of the wiring portion 83B are the same as those of the wiring portion 81B.

[0141] A reverse pin connection portion 83C is provided in a position of the wiring portion 83B that overlaps with the third contact region 63C. The reverse pin connection portion 83C is connected to the third contact region 63C. The reverse pin connection portion 83C has an elliptical shape with its longer side oriented in the Y direction and its shorter side oriented in the X direction in plan view.

[0142] The wiring 90 is disposed within the peripheral region 110 in a plan view. The wiring 90 is provided so as to overlap the diode pair region 60 (high concentration region 61) shown in FIG. 4 in a plan view. The peripheral edge of the wiring 90 includes a portion that is provided so as to overlap the peripheral edge of the diode pair region 60 (high concentration region 61) in a plan view. In one example, the wiring 90 is provided so that its entire area overlaps the isolation region 65 in a plan view. Therefore, the wiring 90 is provided so as to avoid the first pin junction 30, the second pin junction 40, and the third pin junction 50 in a plan view. The wiring 90 is provided so as to partially surround each of the first connection electrode 81, the second connection electrode 82, and the third connection electrode 83 in a plan view.

[0143] The wiring 90 includes a first region 91 , a second region 92 , a third region 93 , a first connection region 94 , and a second connection region 95 . The first region 91 is provided so as to overlap the first region 66A (see FIG. 4) of the diode pair region 60 in plan view. Portions of the outer periphery of the first region 91 that correspond to the first to third sides 66AA to 66AC (see FIG. 4) of the first region 66A are provided so as to overlap the first to third sides 66AA to 66AC in plan view.

[0144] The first region 91 includes a first recess 96A provided to avoid the first connection electrode 81 in plan view. The first recess 96A opens toward the first pin bond 30. The wiring portion 81B of the first connection electrode 81 is disposed within the first recess 96A. As a result, the first region 91 is provided to partially surround the first connection electrode 81 in plan view. Furthermore, the first recess 96A is provided to avoid the first low-concentration region 62A (see FIG. 4) of the first region 66A in plan view. Therefore, the first region 91 is provided to surround the first low-concentration region 62A in plan view.

[0145] By providing the first recess 96A, it can be said that the first region 91 is partially connected to the isolation region 65 (see FIG. 4) in the first region 66A. More specifically, as shown in FIG. 4, the isolation region 65 in the first region 66A includes a wiring connection region 65P to which the wiring 90 is connected and a first isolation region 65A that overlaps with the first connection electrode 81 (see FIG. 7) in a plan view. The first isolation region 65A is provided at one of both ends of the first region 66A in the Y direction, closer to the first pin junction 30. The first isolation region 65A is a region of the first region 66A between the first low-concentration region 62A and the fourth side 66AD in a plan view. The wiring connection region 65P is provided so as to partially surround the first low-concentration region 62A in a plan view. In other words, the wiring connection region 65P is provided so as to partially surround the first reverse pin junction 60A in a plan view. Therefore, the first region 91 (see FIG. 7) connected to the wiring connection region 65P is provided so as to partially surround the first reverse pin junction 60A in plan view.

[0146] The second region 92 (see FIG. 7) is provided so as to overlap with the second region 66B of the diode pair region 60 in plan view. Portions of the outer periphery of the second region 92 corresponding to the first side 66BA, the second side 66BB, and the fourth side 66BD of the second region 66B are provided so as to overlap with the first side 66BA, the second side 66BB, and the fourth side 66BD in plan view. Therefore, the second region 92 includes a region that is positioned offset in the Y direction with respect to the first region 91.

[0147] As shown in FIG. 7, the second region 92 includes a second recess 96B provided to avoid the second connection electrode 82 in a plan view. The second recess 96B opens toward the second pin joint 40 (see FIG. 4). The wiring portion 82B of the second connection electrode 82 is disposed within the second recess 96B. As a result, the second region 92 is provided to partially surround the second connection electrode 82 in a plan view. The second recess 96B is also provided to avoid the second low-concentration region 62B (see FIG. 4) of the second region 66B in a plan view. Therefore, the second region 92 is provided to surround the second low-concentration region 62B in a plan view.

[0148] By providing the second recess 96B, it can be said that the second region 92 is partially connected to the isolation region 65 in the second region 66B. More specifically, as shown in FIG. 4 , the isolation region 65 in the second region 66B includes a wiring connection region 65P to which the wiring 90 is connected and a second isolation region 65B that overlaps with the second connection electrode 82 in a plan view. The second isolation region 65B is provided at one of both ends of the second region 66B in the Y direction that is closer to the second pin junction 40. The second isolation region 65B is a region of the second region 66B between the second low-concentration region 62B and the third side 66BC in a plan view. The wiring connection region 65P is provided so as to partially surround the second low-concentration region 62B in a plan view. In other words, the wiring connection region 65P is provided so as to partially surround the second reverse pin junction 60B in a plan view. Therefore, the second region 92 (see FIG. 7) connected to the wiring connection region 65P is provided so as to partially surround the second reverse pin junction 60B in plan view.

[0149] The third region 93 (see FIG. 7) is provided so as to overlap the third region 66C of the diode pair region 60 in plan view. Portions of the outer periphery of the third region 93 corresponding to the first to third sides 66CA to 66CC of the third region 66C are provided so as to overlap the first to third sides 66CA to 66CC in plan view.

[0150] As shown in FIG. 7, the third region 93 includes a third recess 96C provided to avoid the third connection electrode 83 in a plan view. The third recess 96C opens toward the third pin joint 50. The wiring portion 83B of the third connection electrode 83 is disposed within the third recess 96C. As a result, the third region 93 is provided to partially surround the third connection electrode 83 in a plan view. Furthermore, the third recess 96C is provided to avoid the third low-concentration region 62C of the third region 66C in a plan view (see FIG. 4 for both). Therefore, the third region 93 is provided to surround the third low-concentration region 62C in a plan view.

[0151] By providing the third recess 96C, it can be said that the third region 93 is partially connected to the isolation region 65 in the third region 66C. More specifically, as shown in FIG. 4 , the isolation region 65 in the third region 66C includes a wiring connection region 65P to which the wiring 90 is connected and a third isolation region 65C that overlaps with the third connection electrode 83 in a plan view. The third isolation region 65C is provided at one of both ends of the third region 66C in the Y direction, closer to the third pin junction 50. The third isolation region 65C is a region of the third region 66C between the third low-concentration region 62C and the fourth side 66CD in a plan view. The wiring connection region 65P is provided so as to partially surround the third low-concentration region 62C in a plan view. In other words, the wiring connection region 65P is provided so as to partially surround the third reverse pin junction 60C in a plan view. Therefore, the third region 93 (see FIG. 7) connected to the wiring connection region 65P is provided so as to partially surround the third reverse pin junction 60C in plan view.

[0152] 7, the first connection region 94 is provided so as to overlap the first connection region 67A of the diode pair region 60 in a plan view (see FIG. 4 for both). The shape and size of the first connection region 94 are the same as those of the first connection region 67A. The first connection region 94 is connected to the entire first connection region 67A. In other words, the first connection region 67A is formed by the wiring connection region 65P.

[0153] The second connection region 95 is provided so as to overlap with the second connection region 67B of the diode pair region 60 in a plan view (see FIG. 4 for both). The shape and size of the second connection region 95 are the same as those of the second connection region 67B. The second connection region 95 is connected to the entire second connection region 67B. In other words, the second connection region 67B is formed by the wiring connection region 65P.

[0154] The area of ​​the wiring 90 in a plan view is larger than the area of ​​the first connection electrode 81 in a plan view. The area of ​​the wiring 90 in a plan view is larger than the area of ​​the second connection electrode 82 in a plan view. The area of ​​the wiring 90 in a plan view is larger than the area of ​​the third connection electrode 83 in a plan view. On the other hand, the area of ​​the wiring 90 in a plan view is smaller than the area of ​​the high concentration region 61 in a plan view. In one example, the wiring 90 is provided so as not to protrude from the outer edge of the high concentration region 61 in a plan view.

[0155] The area of ​​the wiring 90 in a plan view is smaller than the area of ​​the separation region 65 (see FIG. 4 ) in a plan view. In one example, the area of ​​the wiring 90 in a plan view can be 75% to 97% of the area of ​​the separation region 65 in a plan view. In one example, the area of ​​the wiring 90 in a plan view may be 80% to 95% of the area of ​​the separation region 65 in a plan view. In one example, the area of ​​the wiring 90 in a plan view may be 85% to 95% of the area of ​​the separation region 65 in a plan view. In one example, the area of ​​the wiring 90 in a plan view may be 90% to 95% of the area of ​​the separation region 65 in a plan view. In one example, the area of ​​the wiring 90 in a plan view may be 85% to 90% of the area of ​​the separation region 65 in a plan view.

[0156] (Terminal opening) 1, the first terminal opening 77A, the second terminal opening 77B, and the third terminal opening 77C are spaced apart from one another. More specifically, the first terminal opening 77A and the third terminal opening 77C are located at the same position in the Y direction and spaced apart from one another in the X direction. The first terminal opening 77A and the third terminal opening 77C are located closer to the fourth side surface 20D than the center in the Y direction of the first surface 20S of the semiconductor chip 20. The first terminal opening 77A is located closer to the first side surface 20A than the center in the X direction of the first surface 20S. The third terminal opening 77C is located closer to the second side surface 20B than the center in the X direction of the first surface 20S.

[0157] The second terminal opening 77B is disposed at a different position in the X direction and the Y direction from both the first terminal opening 77A and the third terminal opening 77C. The second terminal opening 77B is disposed closer to the third side surface 20C than the center in the Y direction of the first surface 20S of the semiconductor chip 20. The second terminal opening 77B is disposed at the center in the X direction of the first surface 20S. Therefore, when viewed from the Y direction, the second terminal opening 77B can be said to be disposed between the first terminal opening 77A and the third terminal opening 77C in the X direction.

[0158] 1 and 4, the first terminal opening 77A is provided at a position overlapping the first pin joint 30 in plan view. The second terminal opening 77B is provided at a position overlapping the second pin joint 40 in plan view. The third terminal opening 77C is provided at a position overlapping the third pin joint 50 in plan view.

[0159] In plan view, the first terminal opening 77A exposes the pin connection portion 81A of the first connection electrode 81. In plan view, the second terminal opening 77B exposes the pin connection portion 82A of the second connection electrode 82. In plan view, the third terminal 103 exposes the pin connection portion 83A of the third connection electrode 83.

[0160] [TVS diode circuit configuration] Next, a TVS circuit 200 of the TVS diode 10 will be described with reference to Fig. 8. Fig. 8 shows a schematic diagram of the circuit configuration of the TVS diode 10.

[0161] 8, the TVS circuit 200 includes first to sixth diodes 201 to 206, a Zener diode 207, and first to third terminals TM1 to TM3. Here, the first terminal TM1 may be formed, for example, by a portion of the first connection electrode 81 exposed from the first terminal opening 77A. The second terminal TM2 may be formed, for example, by a portion of the second connection electrode 82 exposed from the second terminal opening 77B. The third terminal TM3 may be formed, for example, by a portion of the third connection electrode 83 exposed from the third terminal opening 77C.

[0162] The first diode 201 constitutes the pin diode of the first pin junction 30. The second diode 202 constitutes the pin diode of the second pin junction 40. The third diode 203 constitutes the pin diode of the third pin junction 50. The fourth diode 204 constitutes the pin diode of the first reverse pin junction 60A. The fifth diode 205 constitutes the pin diode of the second reverse pin junction 60B. The sixth diode 206 constitutes the pin diode of the third reverse pin junction 60C.

[0163] The cathode of the first diode 201 is electrically connected to the anode of the fourth diode 204. The first terminal TM1 is electrically connected to a node N1 between the cathode of the first diode 201 and the anode of the fourth diode 204. The cathode of the second diode 202 is electrically connected to the anode of the fifth diode 205. The second terminal TM2 is electrically connected to a node N2 between the cathode of the second diode 202 and the anode of the fifth diode 205.

[0164] The cathode of the third diode 203 is electrically connected to the anode of the sixth diode 206. The third terminal TM3 is electrically connected to a node N3 between the cathode of the third diode 203 and the anode of the sixth diode 206.

[0165] The Zener diode 207 is connected in parallel with the series circuit of the first diode 201 and the fourth diode 204, the series circuit of the second diode 202 and the fifth diode 205, and the series circuit of the third diode 203 and the sixth diode 206. The anode of the Zener diode 207 is electrically connected to the anode of the first diode 201, the anode of the second diode 202, and the anode of the third diode 203. The cathode of the Zener diode 207 is electrically connected to the cathode of the fourth diode 204, the cathode of the fifth diode 205, and the cathode of the sixth diode 206. In this way, the Zener diode 207 forms a common reverse-connected diode for the fourth diode 204, the fifth diode 205, and the sixth diode 206.

[0166] In one example, the first terminal TM1 and the third terminal TM3 constitute input terminals, and the second terminal TM2 constitutes a ground terminal. Therefore, when a voltage is applied to the first terminal TM1, a current flows from the first terminal TM1 to the second terminal TM2 via the second diode 202, the Zener diode 207, and the third diode 203. When a voltage is applied to the third terminal TM3, a current flows from the third terminal TM3 to the second terminal TM2 via the fifth diode 205, the Zener diode 207, and the third diode 203. Alternatively, the first terminal TM1 and the second terminal TM2 may constitute input terminals, and the third terminal TM3 may constitute a ground terminal. Alternatively, the second terminal TM2 and the third terminal TM3 may constitute input terminals, and the first terminal TM1 may constitute a ground terminal.

[0167] [TVS diode manufacturing method] An example of a method for manufacturing the TVS diode 10 will be described with reference to Figures 9 to 25. Figures 9 to 25 show cross-sectional structures of the TVS diode 10 in the manufacturing process.

[0168] 9, the method for manufacturing the TVS diode 10 includes a step of preparing a semiconductor wafer 800. The semiconductor wafer 800 is, for example, a Si wafer. The semiconductor wafer 800 includes a p-type impurity. For example, B (boron) may be used as the p-type impurity.

[0169] 10, the method for manufacturing the TVS diode 10 includes a step of forming a first epitaxial layer 810. In this step, Si is crystal-grown from the upper surface of the semiconductor wafer 800 by epitaxial growth. A p-type impurity concentration is diffused into the Si during crystal growth of the semiconductor wafer 800. As a result, a p-type first epitaxial layer 810, which will become the first semiconductor layer 23, is formed on the semiconductor wafer 800.

[0170] 11 , the manufacturing method of the TVS diode 10 includes a step of selectively introducing a p-type impurity (e.g., B) into a surface portion of the first epitaxial layer 810. This step is a step of selectively introducing the p-type impurity into a region of the surface portion of the first epitaxial layer 810 where the first terminal side heavily doped region 31, the second terminal side heavily doped region 41 (see FIG. 3 ) and the third terminal side heavily doped region 51 are to be formed. In this step, the p-type impurity may be selectively implanted into the surface portion of the first epitaxial layer 810 by, for example, ion implantation using an ion implantation mask (not shown). As a result, a portion (first region 31A) of the first terminal side heavily doped region 31, a portion of the second terminal side heavily doped region 41 and a portion of the third terminal side heavily doped region 51 are formed.

[0171] 12, p-type impurities are introduced into a region of the surface layer portion of the first epitaxial layer 810 where the internal region 64 is to be formed. In this step, the p-type impurities may be selectively implanted into the surface layer portion of the first epitaxial layer 810 by the ion implantation method described above. As a result, part of the internal region 64 is formed.

[0172] 11 and 12, and subsequent drawings relating to the manufacturing method of the TVS diode 10 of the first embodiment show part of the first terminal side heavily doped region 31 (first region 31A), part of the third terminal side heavily doped region 51, and part of the internal region 64, but do not show part of the second terminal side heavily doped region 41. In addition, the step shown in FIG. 12 may be performed before the step shown in FIG.

[0173] 13, the method for manufacturing the TVS diode 10 includes a step of forming a second epitaxial layer 820. In this step, Si is crystal-grown from the first epitaxial layer 810 by epitaxial growth. As a result, an n-type second epitaxial layer 820, which will become the second semiconductor layer 24, is formed on the first epitaxial layer 810. Note that the second epitaxial layer 820 may also be p-type.

[0174] Next, the method for manufacturing the TVS diode 10 includes a step of selectively introducing p-type impurities into the second epitaxial layer 820. In this step, the p-type impurities are selectively implanted into regions of the second epitaxial layer 820 where the first terminal side high concentration region 31, the second terminal side high concentration region 41, the third terminal side high concentration region 51, and the internal region 64 are to be formed, for example, by ion implantation using an ion implantation mask (not shown). This step may also be divided into a step of selectively implanting p-type impurities into the regions where the first terminal side high concentration region 31, the second terminal side high concentration region 41, and the third terminal side high concentration region 51 are to be formed, and a step of selectively implanting p-type impurities into the region where the internal region 64 is to be formed, similar to the step shown in FIG.

[0175] Next, the method for manufacturing the TVS diode 10 includes a step of introducing an n-type impurity into a region in the surface portion of the second epitaxial layer 820 where the diode pair region 60 is to be formed. The n-type impurity may be, for example, at least one of As (arsenic) and P (phosphorus). The n-type impurity may be implanted into the surface portion of the second epitaxial layer 820 by ion implantation using an ion implantation mask (not shown). As a result, a part of the high-concentration region 61 is formed in the surface portion of the second epitaxial layer 820. The high-concentration region 61 is formed so as to cover the entire area of ​​the internal region 64 in a plan view. The high-concentration region 61 is formed so as to be in contact with the internal region 64. In other words, a pn junction 60E is formed.

[0176] Next, the method for manufacturing TVS diode 10 includes a step of diffusing the p-type impurities introduced into the surface portion of first epitaxial layer 810 and the p-type impurities and n-type impurities introduced into second epitaxial layer 820. In this step, the p-type impurities and n-type impurities are diffused by, for example, a drive-in process. As a result, the p-type impurities introduced into the surface portion of first epitaxial layer 810 diffuse into second epitaxial layer 820.

[0177] 14 , the manufacturing method of the TVS diode 10 includes a step of forming a third epitaxial layer 830. In this step, Si is crystal-grown from the second epitaxial layer 820 by epitaxial growth accompanied by the introduction of n-type impurities. In this step, p-type impurities and n-type impurities are diffused from the second epitaxial layer 820 into the Si during crystal growth. As a result, the third epitaxial layer 830 is formed on the second epitaxial layer 820. In addition, a portion of the first terminal side high concentration region 31, a portion of the second terminal side high concentration region 41, a portion of the third terminal side high concentration region 51, and a high concentration region 61 are formed at the boundary between the second epitaxial layer 820 and the third epitaxial layer 830.

[0178] Through the above steps, a semiconductor wafer structure 840 is formed, which includes a semiconductor wafer 800, a first epitaxial layer 810, a second epitaxial layer 820, and a third epitaxial layer 830. The semiconductor wafer structure 840 includes a first wafer surface 841 and a second wafer surface 842 opposite to the first wafer surface 841. The first wafer surface 841 corresponds to the first surface 20S of the semiconductor chip 20, and the second wafer surface 842 corresponds to the second surface 20R of the semiconductor chip 20. The first wafer surface 841 is formed by the third epitaxial layer 830. The second wafer surface 842 is formed by the semiconductor wafer 800.

[0179] As shown in FIG. 15 , the manufacturing method of the TVS diode 10 includes a step of forming the partition region and the peripheral region 110. In this step, p-type impurities are selectively implanted into a surface layer portion of the third epitaxial layer 830 by, for example, ion implantation using an ion implantation mask 910. The ion implantation mask 910 has openings 911 formed therein, which expose regions of the third epitaxial layer 830 where the first partition region 34, the second partition region 44 (see FIG. 3 ), the third partition region 54, and the peripheral region 110 are to be formed. The p-type impurities are implanted into the surface layer portion of the third epitaxial layer 830 through the openings 911. As a result, the p-type first partition region 34, the second partition region 44, the third partition region 54, and the peripheral region 110 are formed. By forming the first partition region 34 and the peripheral region 110, a first-terminal-side low-concentration region 32 surrounded by the first partition region 34 in a planar view is formed. The formation of the second partitioned region 44 and the outer periphery region 110 forms a second-terminal-side low-concentration region 42 that is surrounded by the second partitioned region 44 in a planar view. The formation of the third partitioned region 54 and the outer periphery region 110 forms a third-terminal-side low-concentration region 52 that is surrounded by the third partitioned region 54 in a planar view. Note that FIG. 15 shows the first partitioned region 34, the third partitioned region 54, and the outer periphery region 110, but does not show the second partitioned region 44.

[0180] 16, the manufacturing method of the TVS diode 10 includes a step of forming an isolation region 65. In this step, n-type impurities are selectively implanted into a surface portion of the third epitaxial layer 830 by, for example, ion implantation using an ion implantation mask 920. The ion implantation mask 920 has an opening 921 formed therein, which exposes a region of the surface portion of the third epitaxial layer 830 where the isolation region 65 is to be formed. The n-type impurities are implanted into the surface portion of the third epitaxial layer 830 through the opening 921. This forms the n-type isolation region 65. By forming the isolation region 65, a first low concentration region 62A, a second low concentration region 62B, and a third low concentration region 62C are formed, which are surrounded by the isolation region 65 in a planar view.

[0181] 17, the manufacturing method of the TVS diode 10 includes a step of forming a terminal-side contact region. In this step, n-type impurities are selectively implanted into a surface portion of the third epitaxial layer 830 by, for example, ion implantation using an ion implantation mask 930. The ion implantation mask 930 has openings 931 formed therein, which expose regions of the surface portion of the third epitaxial layer 830 where the first terminal-side contact region 33, the second terminal-side contact region 43, and the third terminal-side contact region 53 are to be formed. The openings 931 partially expose the surface portions of the first terminal-side low-concentration region 32, the second terminal-side low-concentration region 42 (see FIG. 3), and the third terminal-side low-concentration region 52 of the surface portion of the third epitaxial layer 830. The n-type impurities are implanted into the surface portions of the first terminal-side low-concentration region 32, the second terminal-side low-concentration region 42, and the third terminal-side low-concentration region 52 through the openings 931. As a result, an n-type first terminal side contact region 33 is formed in the surface layer portion of the first terminal side low concentration region 32. An n-type second terminal side contact region 43 (see FIG. 3) is formed in the surface layer portion of the second terminal side low concentration region 42. An n-type third terminal side contact region 53 is formed in the surface layer portion of the third terminal side low concentration region 52. Through the above steps, the first pin junction 30, the second pin junction 40, and the third pin junction 50 are formed. Note that FIG. 17 shows the first terminal side contact region 33 and the third terminal side contact region 53, but does not show the second terminal side contact region 43.

[0182] 18 , the manufacturing method of the TVS diode 10 includes a step of forming contact regions. In this step, p-type impurities are selectively implanted into a surface portion of the third epitaxial layer 830 by, for example, ion implantation using an ion implantation mask 940. The ion implantation mask 940 has openings 941 formed therein, which expose regions of the surface portion of the third epitaxial layer 830 where the first contact region 63A, the second contact region 63B, and the third contact region 63C are to be formed. The openings 941 partially expose the surface portions of the first low-concentration region 62A, the second low-concentration region 62B, and the third low-concentration region 62C of the surface portion of the third epitaxial layer 830. The p-type impurities are implanted into the surface portions of the first low-concentration region 62A, the second low-concentration region 62B, and the third low-concentration region 62C through the openings 941. As a result, a p-type first contact region 63A is formed in the surface layer portion of the first low-concentration region 62A. A p-type second contact region 63B is formed in the surface layer portion of the second low-concentration region 62B. A p-type third contact region 63C is formed in the surface layer portion of the third low-concentration region 62C. Through the above steps, the first reverse pin junction 60A, the second reverse pin junction 60B, and the third reverse pin junction 60C are formed.

[0183] As shown in FIGS. 19 to 21, the method for manufacturing the TVS diode 10 includes a step of forming an insulating layer 850. 19, the step of forming insulating layer 850 includes a step of forming first insulating layer 851. First insulating layer 851 is formed on first wafer surface 841 of semiconductor wafer structure 840. First insulating layer 851 is an insulating layer that constitutes first insulating layer 71 of insulating layer 70. First insulating layer 851 may be formed by a CVD (Chemical Vapor Deposition) method or an oxidation treatment method (e.g., a thermal oxidation treatment method).

[0184] 20, the step of forming the insulating layer 850 includes the step of forming a second insulating layer 852. The second insulating layer 852 is formed on the first insulating layer 851. The second insulating layer 852 is an insulating layer that constitutes the second insulating layer 72 of the insulating layer 70. The second insulating layer 852 may be formed by at least one of a CVD method and an oxidation treatment method.

[0185] 21, the step of forming insulating layer 850 includes the step of forming first to sixth openings 73A to 73F and wiring opening 73G, which partially expose first wafer surface 841. In this step, a resist mask 950 having a predetermined pattern is first formed on second insulating layer 852. Resist mask 950 exposes regions of insulating layer 850 where first to sixth openings 73A to 73F and wiring opening 73G of insulating layer 70 are to be formed, and covers the remaining regions. Next, the exposed portions of resist mask 950 are removed by etching using resist mask 950. As a result, first to sixth openings 73A to 73F and wiring opening 73G are formed.

[0186] 22, the method for manufacturing the TVS diode 10 includes a step of forming a connection electrode and a step of forming the wiring 90. In one example, the step of forming the connection electrode and the step of forming the wiring 90 are performed as a common step.

[0187] First, a metal layer is formed on insulating layer 850. The metal layer covers insulating layer 850 and fills first to sixth openings 73A to 73F. Therefore, the metal layer is in contact with first terminal side contact region 33, second terminal side contact region 43, third terminal side contact region 53, first to third contact regions 63A to 63C, and isolation region 65. The metal layer is a layer that constitutes first to third connection electrodes 81 to 83 and wiring 90.

[0188] Next, unnecessary portions of the metal layer are removed by etching using a resist mask (not shown) having a predetermined pattern. The resist mask covers the areas of the metal layer where the first to third connection electrodes 81 to 83 and the wiring 90 are to be formed, and leaves the other areas exposed. Then, the portions of the metal layer exposed by the resist mask are removed. This forms the first to third connection electrodes 81 to 83 and the wiring 90. Note that FIG. 22 shows the first connection electrode 81, the third connection electrode 83, and the wiring 90, but does not show the second connection electrode 82.

[0189] As shown in FIGS. 23 to 25, the method for manufacturing the TVS diode 10 includes a step of forming a protective layer 860. 23, the step of forming the protective layer 860 includes a step of forming a first protective layer 861. The first protective layer 861 is an insulating layer that constitutes the first protective layer 75 of the protective layer 74. The first protective layer 861 may be formed by a CVD method.

[0190] 24, the step of forming the protective layer 860 includes a step of forming a second protective layer 862. The second protective layer 862 is a resin layer that constitutes the second protective layer 76 of the protective layer 74. In one example, the second protective layer 862 is formed by applying a photosensitive resin (in one example, PI) onto the first protective layer 861.

[0191] As shown in FIG. 25, the step of forming protective layer 860 includes the step of forming first to third terminal openings 77A to 77C. The first to third terminal openings 77A to 77C are formed by exposing and developing first protective layer 861 and second protective layer 862. More specifically, photoresist is formed on second protective layer 862. Subsequently, openings are formed in the photoresist by, for example, exposure, exposing regions of second protective layer 862 where the first to third terminal openings 77A to 77C are to be formed. Subsequently, the second protective layer 862 and first protective layer 861 exposed from the openings in the photoresist are removed by development. This forms the first to third terminal openings 77A to 77C. Note that FIG. 25 shows first terminal opening 77A and third terminal opening 77C, but does not show second terminal opening 77B (see FIG. 3).

[0192] Although not shown, the manufacturing method of the TVS diode 10 includes a singulation step. In this step, the semiconductor wafer structure 840, the insulating layer 850, and the protective layer 860 are cut using, for example, a dicing blade. This results in the semiconductor chip 20, the insulating layer 70, and the protective layer 74 (see FIG. 2). Through these steps, the TVS diode 10 is manufactured.

[0193] [Effect] The operation of the TVS diode 10 of the first embodiment will be described with reference to Figures 26 and 27. Figure 26 schematically shows an enlarged cross-sectional structure of the diode pair region 60 of the TVS diode 10 and its surroundings. Figure 27 schematically shows the cross-sectional structures of the second pin junction 40, the second reverse pin junction 60B, the third reverse pin junction 60C, and the third pin junction 50.

[0194] 26, the diode pair region 60 includes first to third reverse pin junctions 60A to 60C. The high-concentration region 61 forms a common P layer for the first to third reverse pin junctions 60A to 60C. The internal region 64 is provided so as to overlap the first low-concentration region 62A, the second low-concentration region 62B, and the third low-concentration region 62C in plan view. In other words, the pn junction 60E formed by the high-concentration region 61 and the internal region 64 is provided as a common pn junction for the pn junction reversely connected to the first reverse pin junction 60A, the pn junction reversely connected to the second reverse pin junction 60B, and the pn junction reversely connected to the second reverse pin junction 60C. Therefore, compared to a configuration in which a pn junction reverse-connected to the first reverse pin junction 60A, a pn junction reverse-connected to the second reverse pin junction 60B, and a pn junction reverse-connected to the second reverse pin junction 60C are individually provided, the junction area between the high-concentration region 61 and the internal region 64 can be made larger for the same chip size. Furthermore, when the junction area between the high-concentration region 61 and the internal region 64 is maintained, the TVS diode 10 can be made smaller.

[0195] 26, in the first reverse pin junction 60A, a current flows through the first contact region 63A, the first low-concentration region 62A, and the isolation region 65 in that order. The current flowing through the isolation region 65 flows through the wiring 90 in contact with the isolation region 65. The wiring 90 is provided to surround the first to third reverse pin junctions 60A to 60C in plan view and to cover the outer edge of the high-concentration region 61. Therefore, the current flowing through the wiring 90 is likely to flow throughout the entire internal region 64 via the isolation region 65. The current also flows through the second reverse pin junction 60B and the third reverse pin junction 60C in a similar manner. Therefore, when a current flows through the second reverse pin junction 60B or the third reverse pin junction 60C, the current is likely to flow throughout the entire internal region 64.

[0196] 27 , by arranging a part of the diode pair region 60 between the second pin junction 40 and the third pin junction 50, the amplification factor of the parasitic NPN transistor provided between the second pin junction 40 and the third pin junction 50 can be reduced. This prevents current from flowing directly from the second pin junction 40 to the third pin junction 50 when the parasitic NPN transistor is turned on. Therefore, for example, when electrostatic discharge (ESD) is applied to the second terminal 102, the current flowing through the second terminal 102 passes through the second connection electrode 82, the second reverse pin junction 60B, and the pn junction 60E, and then flows into the first semiconductor layer 23. Then, the current flows from the first semiconductor layer 23 through the third pin junction 50 and the third connection electrode 83 to the third terminal 103. In this way, when the second pin junction 40 and the third pin junction 50 are arranged on either side of the diode pair region 60, the current passes through the diode pair region 60 and the first semiconductor layer 23.

[0197] [effect] According to the TVS diode 10 of the first embodiment, the following effects can be obtained. (1-1) The TVS diode 10 includes a semiconductor chip 20 having a first surface 20S and a second surface 20R opposite to the first surface 20S. The semiconductor chip 20 includes a first pin junction 30 in a first polarity direction that is provided closer to the first surface 20S of the semiconductor chip 20, a second pin junction 40 in the first polarity direction that is located at a position spaced apart from the first pin junction 30 in a plan view seen from the thickness direction of the semiconductor chip 20 in a region closer to the first surface 20S of the semiconductor chip 20, and a diode pair region 60 that is spaced apart from both the first pin junction 30 and the second pin junction 40 in a plan view. The diode pair region 60 includes an n-type high concentration region 61 provided at a distance from the first surface 20S of the semiconductor chip 20 closer to the second surface 20R, a first low concentration region 62A and a second low concentration region 62B of n-type that are provided at a distance from each other at a position overlapping the high concentration region 61 in a plan view in a region closer to the first surface 20S than the high concentration region 61 and have an impurity concentration lower than that of the high concentration region 61, and a second low concentration region 62B of n-type that is provided at a distance from each other at a position overlapping the high concentration region 61 in a plan view in a region closer to the first surface 20S than the high concentration region 61 The semiconductor device includes a separation region 65 provided at a position overlapping the high-concentration region 61 and separating the first low-concentration region 62A and the second low-concentration region 62B, a p-type first contact region 63A provided in a surface layer portion of the first low-concentration region 62A, a p-type second contact region 63B provided in a surface layer portion of the second low-concentration region 62B, and a p-type internal region 64 located at a position overlapping the high-concentration region 61 in a plan view and in contact with the high-concentration region 61 closer to the second surface 20R than the high-concentration region 61. The high-concentration region 61, the first low-concentration region 62A, and the first contact region 63A form a first reverse pin junction 60A in the second polarity direction. The high-concentration region 61, the second low-concentration region 62B, and the second contact region 63B form a second reverse pin junction 60B in the second polarity direction. The high concentration region 61 and the internal region 64 form a pn junction 60E of a first polarity direction so as to be reversely connected to the first reverse pin junction 60A and the second reverse pin junction 60B. The internal region 64 is provided so as to overlap both the first low concentration region 62A and the second low concentration region 62B in a plan view.

[0198] In this configuration, the high-concentration region 61 forms a common P layer for the first reverse pin junction 60A and the second reverse pin junction 60B. The pn junction 60E formed by the high-concentration region 61 and the internal region 64 serves as both a pn junction reversely connected to the first reverse pin junction 60A and a pn junction reversely connected to the second reverse pin junction 60B. This allows for a larger junction area between the high-concentration region 61 and the internal region 64 for the same chip size compared to a configuration in which a pn junction reversely connected to the first reverse pin junction 60A and a pn junction reversely connected to the second reverse pin junction 60B are provided separately. This allows for improved surge absorption capability due to the junction area. This, in turn, improves the electrical characteristics of the TVS diode 10.

[0199] (1-2) The isolation region 65 includes an exposed surface 65S exposed from the first surface 20S of the semiconductor chip 20. The TVS diode 10 includes a wiring 90 in contact with the exposed surface 65S. According to this configuration, the current flowing through the first pin junction 30 and the second pin junction 40 flows to the wiring 90 via the isolation region 65. The current flowing through the wiring 90 flows throughout the entire internal region 64 via the isolation region 65. In this way, compared to a configuration in which the current flows throughout the internal region 64 by passing through the high-concentration region 61 instead of the wiring 90, the current flows throughout the internal region 64 with low resistance. This improves the surge absorption capacity and reduces the clamp voltage.

[0200] (1-3) The isolation region 65 includes a first isolation region 65A overlapping with the first connection electrode 81 in a plan view, a second isolation region 65B overlapping with the second connection electrode 82 in a plan view, and a wiring connection region 65P to which the wiring 90 is connected. The wiring connection region 65P is provided so as to individually and partially surround both the first reverse pin junction 60A and the second reverse pin junction 60B in a plan view.

[0201] This configuration allows current to easily flow from each of the first and second reverse pin junctions 60A and 60B through the wiring connection region 65P to the wiring 90. This allows current to flow with low resistance throughout the entire internal region 64, improving surge absorption capability and reducing clamp voltage.

[0202] (1-4) The wiring 90 is provided so as to partially surround both the first connection electrode 81 and the second connection electrode 82 individually in plan view. According to this configuration, the wiring 90 is insulated from the first connection electrode 81 and the second connection electrode 82, and can increase the area of ​​contact with the separation region 65. Therefore, current flows from the high-concentration region 61 to the internal region 64 through the entire wiring 90, making it easier for current to flow throughout the entire internal region 64 with low resistance.

[0203] (1-5) The area of ​​the wiring 90 in plan view is larger than the area of ​​the first connection electrode 81 in plan view. This configuration can increase the area of ​​the wiring 90 in contact with the isolation region 65. Therefore, current flows from the high-concentration region 61 to the internal region 64 through the entire wiring 90, making it easier for current to flow throughout the entire internal region 64 with low resistance.

[0204] (1-6) The area of ​​the wiring 90 in plan view is smaller than the area of ​​the isolation region 65 in plan view. This configuration can reduce or eliminate the area of ​​the wiring 90 that protrudes from the isolation region 65 in a plan view. Therefore, the current path from the wiring 90 to the isolation region 65 is shortened, allowing current to flow throughout the entire internal region 64 with low resistance.

[0205] (1-7) The area of ​​the wiring 90 in plan view is 75% to 97% of the area of ​​the isolation region 65 in plan view. This configuration allows the area of ​​the wiring 90 in contact with the isolation region 65 to be increased. As a result, compared to when the area of ​​the wiring 90 in a plan view is less than 75% of the area of ​​the isolation region 65 in a plan view, the current flowing through the first pin junction 30 and the second pin junction 40 is more likely to flow from the isolation region 65 to the entire wiring 90. Therefore, the current flows from the high-concentration region 61 to the internal region 64 through the entire wiring 90, and thus the current is more likely to flow throughout the entire internal region 64 with low resistance.

[0206] (1-8) The outer edge of the internal region 64 is located inward from the outer edge of the high-concentration region 61 in plan view. This configuration can suppress electric field concentration at the outer edge of the internal region 64 compared to a configuration in which the outer edge of the internal region 64 is located at the same position as the outer edge of the high-concentration region 61 in plan view, thereby improving ESD resistance.

[0207] (1-9) In plan view, the outer edge of the internal region 64 includes a plurality of corner portions, each of which is curved in plan view. This configuration can suppress electric field concentration at each corner of the internal region 64. Therefore, the ESD resistance can be improved.

[0208] (1-10) The TVS diode 10 includes a semiconductor chip 20 having a first surface 20S and a second surface 20R opposite to the first surface 20S. The semiconductor chip 20 includes a first pin junction 30 and a second pin junction 40 in a first polarity direction provided in a region closer to the first surface 20S of the semiconductor chip 20, a first reverse pin junction 60A and a second reverse pin junction 60B in a second polarity direction provided in a region closer to the first surface 20S of the semiconductor chip 20, and a diode pair region 60 provided away from both the first pin junction 30 and the second pin junction 40 in a plan view. The diode pair region 60 includes a pn junction 60E in the first polarity direction that is located at a position overlapping the first reverse pin junction 60A and the second reverse pin junction 60B in a plan view seen from the thickness direction of the semiconductor chip 20 and that forms a diode pair with the first reverse pin junction 60A and the second reverse pin junction 60B. A diode pair region 60 is disposed between the first pin junction 30 and the second pin junction 40 in plan view.

[0209] According to this configuration, by arranging the diode pair region 60 between the first pin junction 30 and the second pin junction 40, it is possible to reduce the amplification factor of the parasitic NPN transistor provided between the first pin junction 30 and the second pin junction 40. This makes it possible to prevent a current from flowing directly from the first pin junction 30 to the second pin junction 40 when the parasitic NPN transistor is turned on, and to prevent a current from flowing directly from the second pin junction 40 to the first pin junction 30. This makes it possible to improve ESD resistance.

[0210] (1-11) The diode pair region 60 includes a first region 66A in which the first reverse pin junction 60A is provided and a second region 66B in which the second reverse pin junction 60B is provided. The second region 66B includes a region positioned offset in the Y direction with respect to the first region 66A. The first region 66A is adjacent to the second pin junction 40 in the X direction in a plan view. The second region 66B is adjacent to the first pin junction 30 in the X direction in a plan view.

[0211] This configuration allows for a large distance between the first pin junction 30 and the second pin junction 40, and also allows for a large area for the diode pair region 60. This improves surge absorption capability and ESD resistance.

[0212] (1-12) The first connection electrode 81 and the second connection electrode 82 are disposed spaced apart from each other in the X direction in a plan view. Each of the first connection electrode 81 and the second connection electrode 82 extends in the Y direction in a plan view.

[0213] This configuration simplifies the shapes of the first connection electrode 81 and the second connection electrode 82 in a planar view. In addition, it is possible to reduce the area of ​​the region where the first connection electrode 81 and the second connection electrode 82 overlap with the separation region 65 in a planar view. This allows the area of ​​the wiring 90 in contact with the separation region 65 to be increased.

[0214] (1-13) The semiconductor chip 20 includes a third pin junction 50 of a first polarity direction provided near the first surface 20S of the semiconductor chip 20, and a third reverse pin junction 60C of a second polarity direction provided near the first surface 20S of the semiconductor chip 20 and forming a diode pair with the pn junction 60E. In a plan view, the third pin junction 50 and the third reverse pin junction 60C are aligned in the Y direction and electrically connected to each other. In a plan view, the third pin junction 50 and the third reverse pin junction 60C are adjacent to each other on the opposite side of the first pin junction 30 and the first reverse pin junction 60A in the X direction relative to the second pin junction 40 and the second reverse pin junction 60B. In a plan view, the third pin junction 50 and the second reverse pin junction 60B are adjacent to each other in the X direction. In a plan view, the third reverse pin junction 60C and the second pin junction 40 are adjacent to each other in the X direction. The diode pair region 60 includes a region disposed between the second pin junction 40 and the third pin junction 50 in a direction intersecting both the X direction and the Y direction in a plan view.

[0215] According to this configuration, by arranging the diode pair region 60 between the second pin junction 40 and the third pin junction 50, it is possible to reduce the amplification factor of the parasitic NPN transistor provided between the second pin junction 40 and the third pin junction 50. This makes it possible to prevent current from flowing directly from the second pin junction 40 to the third pin junction 50 when the parasitic NPN transistor is turned on, and to prevent current from flowing directly from the third pin junction 50 to the second pin junction 40. This makes it possible to improve ESD resistance.

[0216] (1-14) The high-concentration region 61 includes a first region 66A in which the first reverse pin junction 60A is provided, a second region 66B in which the second reverse pin junction 60B is provided, and a third region 66C in which the third reverse pin junction 60C is provided. The second region 66B includes a region positioned offset in the Y direction with respect to both the first region 66A and the third region 66C. The second region 66B includes a portion disposed between the first pin junction 30 and the third pin junction 50 in the X direction. The first region 66A and the third region 66C include portions adjacent to the second pin junction 40 in the X direction.

[0217] This configuration allows for a large distance between the first pin junction 30 and the second pin junction 40, and a large distance between the second pin junction 40 and the third pin junction 50, and also allows for a large area for the diode pair region 60. This improves surge absorption capability and ESD resistance.

[0218] (1-15) The first connection electrode 81, the second connection electrode 82, and the third connection electrode 83 are arranged spaced apart from each other in the X direction in a plan view. Each of the first connection electrode 81, the second connection electrode 82, and the third connection electrode 83 extends in the Y direction in a plan view.

[0219] This configuration simplifies the shapes of the first connection electrode 81, the second connection electrode 82, and the third connection electrode 83 in a plan view. In addition, it is possible to reduce the area of ​​the region where the first connection electrode 81, the second connection electrode 82, and the third connection electrode 83 overlap with the separation region 65 in a plan view. This allows the area of ​​the wiring 90 in contact with the separation region 65 to be increased.

[0220] Second Embodiment A TVS diode 10 of the second embodiment will be described with reference to Figures 28 to 33. The TVS diode 10 of the second embodiment differs from the TVS diode 10 of the first embodiment mainly in the configurations of the first pin junction 30, the second pin junction 40, and the third pin junction 50. In the following, components common to the first embodiment are assigned the same reference numerals, and descriptions thereof will be omitted.

[0221] 28 and 29 schematically show the cross-sectional structure of the TVS diode 10 of the second embodiment. FIG. 28 mainly shows the first pin junction 30, the third pin junction 50, and the diode pair region 60. FIG. 29 mainly shows the first pin junction 30, the second pin junction 40, and the diode pair region 60. FIG. 30 schematically shows an enlarged structure of the first pin junction 30 and its surroundings in FIG. 28. FIG. 31 is a graph showing the relationship between the position in the Z direction of the first pin junction 30 and the impurity concentration. FIGS. 32 and 33 schematically show the cross-sectional structure of an example of a manufacturing process for the TVS diode 10 of the second embodiment.

[0222] 28 , the first pin junction 30 includes a p-type first buffer region 35. The first buffer region 35 is provided between the first terminal side high-concentration region 31 and the first terminal side low-concentration region 32 in the Z direction. The first buffer region 35 is in contact with the first terminal side high-concentration region 31. The first buffer region 35 is in contact with the first terminal side low-concentration region 32. The first partition region 34 is provided to surround the first buffer region 35 in a plan view. In the second embodiment, the first pin junction 30 is composed of a first terminal side contact region 33, a first terminal side low-concentration region 32, and the first buffer region 35. That is, the first terminal side contact region 33 constitutes an N layer, the first terminal side low-concentration region 32 constitutes an I layer, and the first buffer region 35 constitutes a P layer.

[0223] As shown in FIG. 29 , the second pin junction 40 includes a p-type second buffer region 45. The second buffer region 45 is provided between the second terminal side high-concentration region 41 and the second terminal side low-concentration region 42 in the Z direction. The second buffer region 45 is in contact with the second terminal side high-concentration region 41. The second buffer region 45 is in contact with the second terminal side low-concentration region 42. The second partition region 44 is provided to surround the second buffer region 45 in a plan view. In the second embodiment, the second pin junction 40 is composed of the second terminal side contact region 43, the second terminal side low-concentration region 42, and the second buffer region 45. That is, the second terminal side contact region 43 constitutes an N layer, the second terminal side low-concentration region 42 constitutes an I layer, and the second buffer region 45 constitutes a P layer.

[0224] As shown in FIG. 28 , the third pin junction 50 includes a p-type third buffer region 55. The third buffer region 55 is provided between the third terminal side high-concentration region 51 and the third terminal side low-concentration region 52 in the Z direction. The third buffer region 55 is in contact with the third terminal side high-concentration region 51. The third buffer region 55 is in contact with the third terminal side low-concentration region 52. The third partition region 54 is provided to surround the third buffer region 55 in a plan view. In the second embodiment, the third pin junction 50 is composed of a third terminal side contact region 53, a third terminal side low-concentration region 52, and the third buffer region 55. That is, the third terminal side contact region 53 constitutes an N layer, the third terminal side low-concentration region 52 constitutes an I layer, and the third buffer region 55 constitutes a P layer.

[0225] The first pin joint 30, the second pin joint 40, and the third pin joint 50 have the same configuration. Therefore, the following will describe the first pin joint 30 in detail, and will not describe the second pin joint 40 and the third pin joint 50 in detail.

[0226] 30, the first buffer region 35 is provided at the boundary between the second semiconductor layer 24 and the third semiconductor layer 25. That is, the boundary between the first buffer region 35 and the first terminal side highly doped region 31 is located in the second semiconductor layer 24 in the Z direction. Therefore, the thickness of the first terminal side highly doped region 31 is thinner than the thickness of the first terminal side highly doped region 31 in the first embodiment (see FIG. 2).

[0227] The boundary between the first buffer region 35 and the first terminal side low concentration region 32 is located closer to the first surface 20S of the semiconductor chip 20 than the boundary between the high concentration region 61 of the diode pair region 60 and the first low concentration region 62A. Therefore, the thickness of the first terminal side low concentration region 32 is thinner than the thickness of the first terminal side low concentration region 32 of the first embodiment (see FIG. 2). In one example, the thickness of the first terminal side low concentration region 32 is thinner than the thickness of the first low concentration region 62A. The thickness of the first terminal side low concentration region 32 is thinner than the thickness of the first buffer region 35.

[0228] As shown in FIG. 31, the p-type impurity concentration of the first buffer region 35 is 1×10 14 cm -3 5x10 or more 17 cm -3 The p-type impurity concentration of the first buffer region 35 has a concentration gradient that decreases in the Z direction from the first terminal side high-concentration region 31 to the first terminal side low-concentration region 32. Therefore, the p-type impurity concentration of the first buffer region 35 is maximum at the boundary between the first buffer region 35 and the first terminal side high-concentration region 31 and is minimum at the boundary between the first buffer region 35 and the first terminal side low-concentration region 32. Therefore, the first buffer region 35 has a p-type impurity concentration lower than the p-type impurity concentration of the first terminal side high-concentration region 31. Furthermore, the p-type impurity concentration of the first buffer region 35 may be equal to the n-type impurity concentration of the first terminal side low-concentration region 32 at the boundary between the first buffer region 35 and the first terminal side low-concentration region 32. In one example, the p-type impurity concentration at the boundary between the first buffer region 35 and the first terminal side low-concentration region 32 is 1×10 14 cm -3 31, the p-type impurity concentration of the first buffer region 35 is equal to or higher than the n-type impurity concentration of the first terminal side low concentration region 32.

[0229] The p-type impurity concentrations of the second buffer region 45 and the third buffer region 55 have the same concentration gradient as the p-type impurity concentration of the first buffer region 35. Therefore, the second buffer region 45 has a lower p-type impurity concentration than the second terminal side high-concentration region 41. The p-type impurity concentration of the second buffer region 45 has a concentration gradient that decreases in the Z direction from the second terminal side high-concentration region 41 to the second terminal side low-concentration region 42. The p-type impurity concentration of the second buffer region 45 is equal to or higher than the n-type impurity concentration of the second terminal side low-concentration region 42. The third buffer region 55 has a p-type impurity concentration lower than the p-type impurity concentration of the third terminal side high-concentration region 51. The p-type impurity concentration of the third buffer region 55 has a concentration gradient that decreases in the Z direction from the third terminal side high-concentration region 51 to the third terminal side low-concentration region 52. The p-type impurity concentration of the third buffer region 55 is equal to or higher than the n-type impurity concentration of the third terminal side low concentration region 52.

[0230] [TVS diode manufacturing method] An example of a method for manufacturing the TVS diode 10 of the second embodiment will be described. The second embodiment differs from the first embodiment in that a step of forming the first buffer region 35, the second buffer region 45, and the third buffer region 55 is added. This step will be described below.

[0231] The steps of forming the first buffer region 35, the second buffer region 45, and the third buffer region 55 are performed after forming the isolation region 65, the first terminal side contact region 33, the second terminal side contact region 43, and the third terminal side contact region 53. The step of forming the first buffer region 35 will be described below.

[0232] 32 and 33 show the cross-sectional structure in a process after the first terminal side contact region 33, the second terminal side contact region 43, and the third terminal side contact region 53 have been formed. Note that the second pin junction 40 is not shown in FIGS. 32 and 33. For the second pin junction 40, see FIG. 29.

[0233] 32, due to the n-type impurities forming the isolation region 65, the first terminal side contact region 33, the second terminal side contact region 43, and the third terminal side contact region 53, an autodoped layer 36 is formed at the end of the first terminal side low concentration region 32 closer to the first terminal side high concentration region 31. As shown in FIG. 31, the n-type impurity concentration of this autodoped layer 36 is higher than the n-type impurity concentration of the first terminal side low concentration region 32. In one example, the peak n-type impurity concentration of the autodoped layer 36 is 1×10 16 cm -3 That's about it.

[0234] 33, in the step of forming the first buffer region 35, p-type impurities are implanted into the first-terminal-side heavily doped region 31 by, for example, ion implantation using an ion implantation mask 970. Here, the p-type impurities are implanted into the auto-doped layer 36 by adjusting the implantation energy (ion acceleration voltage). As a result, the first buffer region 35 is formed in the auto-doped layer 36. Note that the steps of forming the second buffer region 45 and the third buffer region 55 are similar to the steps of forming the first buffer region 35, and therefore description thereof will be omitted.

[0235] [Effect] The operation of the TVS diode 10 of the second embodiment will be described with reference to Figures 31 and 32. Below, the first pin junction 30 will be described, but the same applies to the second pin junction 40 and the third pin junction 50.

[0236] 31 and 32 , the auto-doped layer 36 formed during the manufacturing process of the TVS diode 10 has a higher n-type impurity concentration than the n-type impurity concentration of the first terminal side low concentration region 32. Therefore, the junction capacitance between the auto-doped layer 36 and the first terminal side high concentration region 31 in the first pin junction 30 is larger than the junction capacitance between the first terminal side low concentration region 32 and the first terminal side high concentration region 31.

[0237] Therefore, in the TVS diode 10 of the second embodiment, a p-type first buffer region 35 is provided between the first terminal side heavily doped region 31 and the first terminal side lightly doped region 32. As a result, the n-type impurities in the auto-doped layer 36 are canceled out by the p-type impurities in the first buffer region 35. Therefore, in the first pin junction 30, instead of the junction between the auto-doped layer 36 and the first terminal side heavily doped region 31, a junction between the first buffer region 35 and the first terminal side lightly doped region 32 is formed. As a result, there is no region with a high concentration of n-type impurities in the first terminal side lightly doped region 32, and an increase in the junction capacitance of the first pin junction 30 can be suppressed.

[0238] [effect] According to the TVS diode 10 of the second embodiment, the following effects can be obtained. (2-1) The TVS diode 10 includes a semiconductor chip 20 having a first surface 20S and a second surface 20R opposite to the first surface 20S. The semiconductor chip 20 includes a diode pair region 60 including a first pin junction 30 of a first polarity direction provided in a region closer to the first surface 20S of the semiconductor chip 20, a first reverse pin junction 60A of a second polarity direction provided at a distance from the first pin junction 30 in a plan view seen from the thickness direction of the semiconductor chip 20, and a pn junction 60E of the first polarity direction that forms a diode pair with the first reverse pin junction 60A; the first terminal side contact region 33 is disposed in a surface layer portion of the first terminal side low concentration region 32; and the semiconductor chip 20 has a p-type first buffer region 35 in contact with the first terminal side high concentration region 31 between the first terminal side high concentration region 31 and the first terminal side low concentration region 32 in the thickness direction of the semiconductor chip 20. The first terminal side contact region 33, the first terminal side low concentration region 32, and the first buffer region 35 form a pin diode.

[0239] With this configuration, even if a region with a high n-type impurity concentration is formed closer to the first terminal side high concentration region 31 in the first terminal side low concentration region 32 during the manufacturing process of the TVS diode 10, the region with a high n-type impurity concentration is eliminated by the first buffer region 35. Therefore, an increase in the junction capacitance at the first pin junction 30 can be suppressed.

[0240] (2-2) The first buffer region 35 has a lower p-type impurity concentration than the first terminal side high-concentration region 31. According to this configuration, the junction capacitance between the first buffer region 35 and the first terminal side low concentration region 32 can be reduced, and therefore the junction capacitance of the first pin junction portion 30 can be reduced.

[0241] (2-3) The p-type impurity concentration of the first buffer region 35 decreases from the first terminal side high concentration region 31 toward the first terminal side low concentration region 32 in the thickness direction of the semiconductor chip 20.

[0242] According to this configuration, the p-type impurity concentration of the first buffer region 35 is minimum at the boundary between the first buffer region 35 and the first terminal side low concentration region 32. Therefore, the junction capacitance between the first buffer region 35 and the first terminal side low concentration region 32 can be reduced, and therefore the junction capacitance of the first pin junction 30 can be reduced.

[0243] (2-4) The semiconductor chip 20 includes: a second pin junction 40 of a first polarity direction provided in a region closer to the first surface 20S of the semiconductor chip 20, at a position spaced apart from the first pin junction 30 in a planar view; a p-type second terminal side high concentration region 41 provided in a position spaced apart from the first terminal side high concentration region 31 in a planar view, closer to the second surface 20R from the first surface 20S of the semiconductor chip 20; an n-type second terminal side low concentration region 42 provided in a region closer to the first surface 20S than the second terminal side high concentration region 41, at a position overlapping with the second terminal side high concentration region 41 in a planar view; an n-type second terminal side contact region 43 provided in a surface layer portion of the second terminal side low concentration region 42; and a p-type second buffer region 45 in contact with the second terminal side high concentration region 41 between the second terminal side high concentration region 41 and the second terminal side low concentration region 42 in the thickness direction of the semiconductor chip 20. The second buffer region 45, the second terminal side low concentration region 42, and the second terminal side contact region 43 form a second pin junction 40.

[0244] With this configuration, even if a region with a high n-type impurity concentration is formed closer to the second terminal side high concentration region 41 in the second terminal side low concentration region 42 during the manufacturing process of the TVS diode 10, the region with a high n-type impurity concentration is eliminated by the second buffer region 45. Therefore, an increase in the junction capacitance at the second pin junction 40 can be suppressed.

[0245] (2-5) The second buffer region 45 has a lower p-type impurity concentration than the second terminal side high-concentration region 41. According to this configuration, the junction capacitance between the second buffer region 45 and the second terminal side low concentration region 42 can be reduced, and therefore the junction capacitance of the second pin junction 40 can be reduced.

[0246] (2-6) The p-type impurity concentration of the second buffer region 45 decreases from the second terminal side high concentration region 41 toward the second terminal side low concentration region 42 in the thickness direction of the semiconductor chip 20.

[0247] According to this configuration, the p-type impurity concentration of the second buffer region 45 is minimum at the boundary between the second buffer region 45 and the second terminal side low concentration region 42. Therefore, the junction capacitance between the second buffer region 45 and the second terminal side low concentration region 42 can be reduced, and therefore the junction capacitance of the second pin junction 40 can be reduced.

[0248] (2-7) The semiconductor chip 20 includes a third pin junction 50 in a first polarity direction provided in a region close to the first surface 20S of the semiconductor chip 20 at a position spaced apart from both the first pin junction 30 and the second pin junction 40 in a plan view, and a p-type third terminal side highly doped region 51 provided in a position spaced apart from both the first terminal side highly doped region 31 and the second terminal side highly doped region 41 in a plan view from the first surface 20S of the semiconductor chip 20 toward the second surface 20R. an n-type third terminal side low concentration region 52 provided in a region closer to the first surface 20S than the third terminal side high concentration region 51 at a position overlapping the third terminal side high concentration region 51 in a plan view, an n-type third terminal side contact region 53 provided in a surface layer portion of the third terminal side low concentration region 52, and a p-type third buffer region 55 in contact with the third terminal side high concentration region 51 between the third terminal side high concentration region 51 and the third terminal side low concentration region 52 in the thickness direction of the semiconductor chip 20. The third buffer region 55, the third terminal side low concentration region 52, and the third terminal side contact region 53 form a third pin junction 50.

[0249] According to this configuration, even if a region with a high n-type impurity concentration is formed closer to the third terminal side high concentration region 51 in the third terminal side low concentration region 52 during the manufacturing process of the TVS diode 10, the region with a high n-type impurity concentration is eliminated by the third buffer region 55. Therefore, an increase in the junction capacitance at the third pin junction 50 can be suppressed.

[0250] (2-8) The third buffer region 55 has a lower p-type impurity concentration than the third terminal side high-concentration region 51. According to this configuration, the junction capacitance between the third buffer region 55 and the third-terminal side low-concentration region 52 can be reduced, and therefore the junction capacitance of the third pin junction 50 can be reduced.

[0251] (2-9) The p-type impurity concentration of the third buffer region 55 decreases from the third terminal side high concentration region 51 toward the third terminal side low concentration region 52 in the thickness direction of the semiconductor chip 20.

[0252] According to this configuration, the p-type impurity concentration of the third buffer region 55 is minimum at the boundary between the third buffer region 55 and the third terminal side low concentration region 52. Therefore, the junction capacitance between the third buffer region 55 and the third terminal side low concentration region 52 can be reduced, and therefore the junction capacitance of the third pin junction 50 can be reduced.

[0253] Third Embodiment A TVS diode 10 of the third embodiment will be described with reference to Figures 34 to 39. The TVS diode 10 of the third embodiment differs from the TVS diode 10 of the first embodiment mainly in the configurations of the first pin junction 30, the second pin junction 40, and the third pin junction 50. In the following, components common to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted.

[0254] Fig. 34 schematically shows the planar structure of the semiconductor chip 20 in the TVS diode 10 of the third embodiment. Fig. 35 schematically shows the cross-sectional structure of the TVS diode 10 taken along line F35-F35 in Fig. 34. Fig. 36 schematically shows the cross-sectional structure of the TVS diode 10 taken along line F36-F36 in Fig. 34. Figs. 37 to 39 schematically show cross-sectional structures of exemplary manufacturing processes for the TVS diode 10 of the third embodiment.

[0255] 34 and 35, the first pin junction 30 includes a first isolation trench structure 120A instead of the first partition region 34 (see FIG. 2). The first isolation trench structure 120A is configured to separate the first pin junction 30 from the diode pair region 60, for example.

[0256] The first isolation trench structure 120A includes a first isolation trench 121A, a first isolation insulating layer 122A, and a first isolation electrode 123A. The first isolation trench 121A has a ring shape surrounding the first terminal side high-concentration region 31 in a plan view. In one example, the first isolation trench 121A has a square ring shape in a plan view. The first isolation trench 121A is formed by digging down from the first surface 20S of the semiconductor chip 20 toward the second surface 20R. The first isolation trench 121A penetrates the third semiconductor layer 25 and the second semiconductor layer 24 and reaches the first semiconductor layer 23. In one example, the bottom wall of the first isolation trench 121A is located closer to the second surface 20R of the semiconductor chip 20 in the Z direction than the boundary between the first terminal side high-concentration region 31 and the first semiconductor layer 23. Therefore, the bottom wall of the first isolation trench 121A exposes the first semiconductor layer 23.

[0257] The first isolation trench 121A includes an inner peripheral wall and an outer peripheral wall. The inner peripheral wall of the first isolation trench 121A exposes the first terminal side low concentration region 32 and the first terminal side high concentration region 31. The outer peripheral wall of the first isolation trench 121A exposes the first to third semiconductor layers 23 to 25. As a result, the first isolation trench 121A separates the first terminal side low concentration region 32 and the first terminal side high concentration region 31 from the second semiconductor layer 24 and the third semiconductor layer 25.

[0258] Both the inner and outer peripheral walls of the first isolation trench 121A may be provided perpendicular to the first surface 20S of the semiconductor chip 20. Furthermore, both the inner and outer peripheral walls of the first isolation trench 121A may be tapered from the first surface 20S toward the bottom wall.

[0259] The width of the first isolation trench 121A can be 0.1 μm or more and 3 μm or less. For example, the width of the first isolation trench 121A is 1.5 μm or more and 2.5 μm or less. Here, the width of the first isolation trench 121A can be defined by the distance between the inner wall and the outer wall in a direction perpendicular to the extension direction of the first isolation trench 121A in a plan view.

[0260] The depth of the first isolation trench 121A can be 1 μm or more and 50 μm or less. In one example, the depth of the first isolation trench 121A is 15 μm or more and 35 μm or less. Here, the depth of the first isolation trench 121A can be defined as the distance in the Z direction between the first surface 20S of the semiconductor chip 20 and the bottom surface of the first isolation trench 121A.

[0261] The first isolation insulating layer 122A is provided in the first isolation trench 121A. More specifically, the first isolation insulating layer 122A is in the form of a film along the inner wall of the first isolation trench 121A. As a result, the first isolation insulating layer 122A defines a recess space in the first isolation trench 121A.

[0262] The first isolation and insulating layer 122A may include at least one of a SiO2 layer and a SiN layer. The first isolation and insulating layer 122A may have a layered structure in which SiO2 layers and SiN layers are stacked in any order. The first isolation and insulating layer 122A may have a single-layer structure composed of a SiO2 layer or a SiN layer. The first isolation and insulating layer 122A may be composed of the same insulating material as the first insulating layer 71. In one example, the first isolation and insulating layer 122A has a single-layer structure composed of a SiO2 layer.

[0263] The first isolated electrode 123A is embedded in the first isolated trench 121A with the first isolated insulating layer 122A sandwiched therebetween. The first isolated electrode 123A has an annular shape surrounding the first terminal side high-concentration region 31 in a plan view. In one example, the first isolated electrode 123A has a quadrangular annular shape in a plan view. The first isolated electrode 123A is made of, for example, polysilicon. The first isolated electrode 123A is in an electrically floating state.

[0264] As shown in FIGS. 34 and 36, the second pin junction 40 includes a second isolation trench structure 120B instead of the second partition region 44 (see FIG. 3). The second isolation trench structure 120B is configured to separate the second pin junction 40 from the diode pair region 60, for example. The second isolation trench structure 120B includes a second isolation trench 121B, a second isolation insulating layer 122B, and a second isolation electrode 123B. The second isolation trench 121B is provided on the first surface 20S of the semiconductor chip 20 so as to separate the second pin junction 40 from the diode pair region 60. The second isolation insulating layer 122B is provided within the second isolation trench 121B. The second isolation electrode 123B is embedded in the second isolation trench 121B with the second isolation insulating layer 122B sandwiched therebetween. The second isolation electrode 123B is in an electrically floating state. The configurations of second isolation trench 121B, second isolation insulating layer 122B, and second isolation electrode 123B are the same as those of first isolation trench 121A, first isolation insulating layer 122A, and first isolation electrode 123A, and therefore detailed description thereof will be omitted.

[0265] As shown in FIGS. 34 and 35 , the third pin junction 50 includes a third isolation trench structure 120C instead of the third partition region 54 (see FIG. 2 ). The third isolation trench structure 120C is configured to separate the third pin junction 50 from the diode pair region 60, for example. The third isolation trench structure 120C includes a third isolation trench 121C, a third isolation insulating layer 122C, and a third isolation electrode 123C. The third isolation trench 121C is provided on the first surface 20S of the semiconductor chip 20 so as to separate the third pin junction 50 from the diode pair region 60. The third isolation insulating layer 122C is provided within the third isolation trench 121C. The third isolation electrode 123C is embedded in the third isolation trench 121C with the third isolation insulating layer 122C sandwiched therebetween. The third isolation electrode 123C is in an electrically floating state. The configurations of third isolation trench 121C, third isolation insulating layer 122C, and third isolation electrode 123C are the same as those of first isolation trench 121A, first isolation insulating layer 122A, and first isolation electrode 123A, and therefore description thereof will be omitted.

[0266] [TVS diode manufacturing method] An example of a manufacturing method for the TVS diode 10 of the third embodiment will be described. The manufacturing method for the TVS diode 10 of the third embodiment is mainly different from the first embodiment in that it includes a step of forming a first isolation trench structure 120A, a second isolation trench structure 120B, and a third isolation trench structure 120C, instead of the step of forming the first partition region 34, the second partition region 44, and the third partition region 54. This step will be described below.

[0267] 37 to 39 show the steps of forming the first isolation trench structure 120A and the third isolation trench structure 120C. Although not shown, the second isolation trench structure 120B is formed in the same manner as the first isolation trench structure 120A and the third isolation trench structure 120C.

[0268] As shown in FIG. 37, this process includes forming the first isolation trench 121A and the third isolation trench 121C. More specifically, a hard mask (not shown) having a predetermined pattern is first formed on the first surface 20S of the semiconductor chip 20. The hard mask exposes regions of the first surface 20S where the isolation trenches 121A, 121B, and 121C are to be formed, and covers other regions. The hard mask may be formed by a CVD method or an oxidation treatment method. The hard mask may be patterned by an etching method using an etching mask. Subsequently, the regions of the first surface 20S of the semiconductor chip 20 exposed from the hard mask are removed by an etching method using the hard mask. The etching method may be a dry etching method. An example of the dry etching method may be a reactive ion etching (RIE) method. As a result, the first isolation trench 121A, the second isolation trench 121B, and the third isolation trench 121C are formed. The hard mask is then removed.

[0269] As shown in FIG. 38, the step of forming the first isolation trench structure 120A and the third isolation trench structure 120C includes the step of forming an insulating layer 870. The insulating layer 870 is formed in a film shape along the first surface 20S of the semiconductor chip 20 and the inner walls of each of the isolation trenches 121A, 121B, and 121C. The insulating layer 870 is an insulating layer that constitutes the first isolation insulating layer 122A and the third isolation insulating layer 122C. Although not shown, the insulating layer 870 is also an insulating layer that constitutes the second isolation insulating layer 122B. The insulating layer 870 may be formed by a CVD method or an oxidation treatment method (e.g., a thermal oxidation treatment method). In one example, the insulating layer 870 is formed by a thermal oxidation treatment method.

[0270] As shown in FIG. 39, the process of forming the first isolation trench structure 120A and the third isolation trench structure 120C includes the process of forming the first isolated electrode 123A and the third isolated electrode 123C. In this process, an electrode layer 880 is first formed on an insulating layer 870. The electrode layer 880 is a layer that constitutes the first isolated electrode 123A and the third isolated electrode 123C. Although not shown, the electrode layer 880 is also a layer that constitutes the second isolated electrode 123B. The electrode layer 880 is made of, for example, polysilicon. The electrode layer 880 is embedded in each of the isolation trenches 121A, 121B, and 121C with the insulating layer 870 sandwiched therebetween. The electrode layer 880 may be formed, for example, by a CVD method.

[0271] Next, although not shown, unnecessary portions of the electrode layer 880 are removed by etching. Portions of the electrode layer 880 other than those embedded in the isolation trenches 121A and 121C are removed. The electrode layer 880 is removed until the insulating layer 870 is exposed. As a result, the first isolation electrode 123A and the third isolation electrode 123C are formed. Through the above steps, the first isolation trench structure 120A and the third isolation trench structure 120C are formed. Note that the second isolation electrode 123B is formed by removing portions of the electrode layer 880 other than those embedded in the second isolation trench 121B. As a result, the second isolation trench structure 120B is formed.

[0272] Thereafter, although not shown, a step of forming an insulating layer 850 is performed. The first isolation trench structure 120A, the second isolation trench structure 120B, and the third isolation trench structure 120C are covered with a first insulating layer 851 of the insulating layer 850. Therefore, each of the isolation electrodes 123A, 123B, and 123C is covered with the insulating layer 870 and the first insulating layer 851.

[0273] [effect] According to the TVS diode 10 of the third embodiment, the following effects can be obtained. (3-1) The semiconductor chip 20 includes a first isolation trench 121A provided in the first surface 20S to separate the first pin junction 30 from the diode pair region 60, and a second isolation trench 121B provided in the first surface 20S to separate the second pin junction 40 from the diode pair region 60. The TVS diode 10 includes a first isolation insulating layer 122A provided in the first isolation trench 121A, and a second isolation insulating layer 122B provided in the second isolation trench 121B.

[0274] This configuration improves the insulation between the first pin junction 30 and the diode pair region 60, and the insulation between the second pin junction 40 and the diode pair region 60. This reduces the distance between the first pin junction 30 and the second pin junction 40 and the diode pair region 60. Therefore, for the same chip size, the area of ​​the diode pair region 60 can be increased in plan view, improving surge absorption performance. On the other hand, for the same area of ​​the diode pair region 60 in plan view, the TVS diode 10 can be made smaller by reducing the distance between the first pin junction 30 and the second pin junction 40 and the diode pair region 60.

[0275] <Fourth embodiment> 40 to 43, a TVS diode 10 according to a fourth embodiment will be described. The TVS diode 10 according to the fourth embodiment differs from the TVS diode 10 according to the first embodiment mainly in the planar structure of the TVS diode 10. In the following, components common to the first embodiment will be assigned the same reference numerals, and descriptions thereof will be omitted.

[0276] Fig. 40 schematically shows the planar structure of the semiconductor chip 20 in the TVS diode 10 of the fourth embodiment. Fig. 41 schematically shows the planar structure of the first to third connection electrodes 81 to 83 and wiring 90 of the TVS diode 10. Fig. 42 schematically shows the cross-sectional structure of the TVS diode 10 taken along line F42-F42 in Fig. 40. Fig. 43 schematically shows the planar structure of the TVS diode 10.

[0277] 40 , in the TVS diode 10 of the fourth embodiment, the first pin junction 30, the second pin junction 40, the third pin junction 50, and the diode pair region 60 are arranged side by side in the Y direction. The first pin junction 30, the second pin junction 40, and the third pin junction 50 are arranged closer to the fourth side surface 20D than the diode pair region 60 in a planar view. In other words, the diode pair region 60 is arranged closer to the third side surface 20C than the first pin junction 30, the second pin junction 40, and the third pin junction 50 in a planar view.

[0278] The first pin junction 30, the second pin junction 40, and the third pin junction 50 are arranged side by side in the X direction. More specifically, the first pin junction 30, the second pin junction 40, and the third pin junction 50 are arranged at the same positions in the Y direction and spaced apart from one another in the X direction. As shown in FIG. 42 , the cross-sectional structures of the first pin junction 30, the second pin junction 40, and the third pin junction 50 are the same as those in the first embodiment. The partitioned regions between the first terminal side low-concentration region 32 and the second terminal side low-concentration region 42 constitute a first partitioned region 34 and a second partitioned region 44. The partitioned regions between the second terminal side low-concentration region 42 and the third terminal side low-concentration region 52 constitute a second partitioned region 44 and a third partitioned region 54.

[0279] 40, the diode pair region 60 has a rectangular shape in a plan view. In one example, the diode pair region 60 has a rectangular shape with the X direction (the arrangement direction of the first pin junction 30, the second pin junction 40, and the third pin junction 50) as the longitudinal direction and the Y direction as the lateral direction. The diode pair region 60 is provided with a first reverse pin junction 60A, a second reverse pin junction 60B, and a third reverse pin junction 60C. Each of the reverse pin junctions 60A, 60B, and 60C is disposed at a position overlapping with a high concentration region 61 in a plan view.

[0280] The first reverse pin junction 60A, the second reverse pin junction 60B, and the third reverse pin junction 60C are arranged spaced apart from one another in the X direction. The first reverse pin junction 60A is positioned so as to overlap the first pin junction 30 when viewed from the Y direction. The second reverse pin junction 60B is positioned so as to overlap the second pin junction 40 when viewed from the Y direction. The third pin junction 50 is positioned so as to overlap the third pin junction 50 when viewed from the Y direction. As shown in FIG. 42 , the cross-sectional structures of the reverse pin junctions 60A, 60B, and 60C are the same as those of the first embodiment.

[0281] 40, the isolation region 65 is provided so as to surround each of the first low-concentration region 62A, the second low-concentration region 62B, and the third low-concentration region 62C. As in the first embodiment, the isolation region 65 includes first to third isolation regions 65A to 65C and a wiring connection region 65P. The first isolation region 65A is provided in the isolation region 65 between the first contact region 63A and the first terminal-side contact region 33 in the Y direction. The second isolation region 65B is provided in the isolation region 65 between the second contact region 63B and the second terminal-side contact region 43 in the Y direction. The third isolation region 65C is provided in the isolation region 65 between the third contact region 63C and the third terminal-side contact region 53 in the Y direction. The wiring connection region 65P is provided so as to partially surround each of the reverse pin junctions 60A, 60B, and 60C individually in a plan view.

[0282] As indicated by the dashed line in FIG. 40 , the outer edge of the internal region 64 is located inward of the outer edge of the high-concentration region 61 in plan view. In one example, the internal region 64 has a rectangular shape that is slightly smaller than the high-concentration region 61 (diode pair region 60) in plan view. Therefore, the internal region 64 is provided so as to overlap with each of the reverse pin junctions 60A, 60B, and 60C in plan view. More specifically, the internal region 64 is provided so as to overlap with each of the first low-concentration region 62A, the second low-concentration region 62B, and the third low-concentration region 62C in plan view. As shown in FIG. 42 , the cross-sectional structure of the pn junction 60E is similar to that of the first embodiment.

[0283] 41 , the first connection electrode 81 includes a pin connection portion 81A, a wiring portion 81B, and a reverse pin connection portion 81C, similar to the first embodiment. In one example, the pin connection portion 81A has a rectangular shape that covers the entire first terminal-side contact region 33 in a plan view. In a plan view, the wiring portion 81B extends in the Y direction from the pin connection portion 81A toward the third side surface 20C. In the X direction, the wiring portion 81B is connected to the pin connection portion 81A, biased toward the second side surface 20B with respect to the center of the pin connection portion 81A. In one example, the reverse pin connection portion 81C covers the entire first contact region 63A in a plan view.

[0284] Similar to the first embodiment, the second connection electrode 82 includes a pin connection portion 82A, a wiring portion 82B, and a reverse pin connection portion 82C. The wiring portion 82B extends in the Y direction from the pin connection portion 82A toward the third side surface 20C. In one example, the center of the wiring portion 82B in the X direction is located at the same position as the center of the pin connection portion 82A. In one example, the reverse pin connection portion 82C covers the entire second contact region 63B in a plan view.

[0285] Similar to the first embodiment, the third connection electrode 83 includes a pin connection portion 83A, a wiring portion 83B, and a reverse pin connection portion 83C. The wiring portion 83B extends in the Y direction from the pin connection portion 83A toward the third side surface 20C. In one example, the wiring portion 83B is connected to the pin connection portion 83A, biased toward the first side surface 20A with respect to the center of the pin connection portion 83A in the X direction. In one example, the reverse pin connection portion 83C covers the entire third contact region 63C in a plan view.

[0286] The wiring 90 has a comb-like shape in plan view. As in the first embodiment, the wiring 90 includes a first recess 96A, a second recess 96B, and a third recess 96C. Each of the recesses 96A to 96C opens toward the fourth side surface 20D in the Y direction. The wiring 90 also includes first to fourth tooth portions 97A to 97D and a connecting portion 97E. The first to fourth tooth portions 97A to 97D are arranged spaced apart from each other in the X direction in plan view. The connecting portion 97E is disposed closer to the third side surface 20C than the first to fourth tooth portions 97A to 97D. The connecting portion 97E connects the first to fourth tooth portions 97A to 97D. The first to fourth tooth portions 97A to 97D are arranged in this order from the first side surface 20A to the second side surface 20B. The first to fourth teeth 97A to 97D extend in the Y direction from the connecting portion 97E toward the fourth side surface 20D. The first recess 96A is formed by the first teeth 97A, the second teeth 97B, and the connecting portion 97E. The second recess 96B is formed by the second teeth 97B, the third teeth 97C, and the connecting portion 97E. The third recess 96C is formed by the third teeth 97C, the fourth teeth 97D, and the connecting portion 97E.

[0287] The wiring portion 81B of the first connection electrode 81 is disposed in the first recess 96A. The wiring portion 82B of the second connection electrode 82 is disposed in the second recess 96B. The wiring portion 83B of the third connection electrode 83 is disposed in the third recess 96C. In this way, the wiring 90 is provided so as to partially surround each of the first connection electrode 81, the second connection electrode 82, and the third connection electrode 83 in plan view.

[0288] As shown in FIG. 43, the first to third terminal openings 77A to 77C of the TVS diode 10 of the fourth embodiment are arranged at the same positions in the Y direction and spaced apart from each other in the X direction. The first to third terminal openings 77A to 77C are arranged closer to the fourth side surface 20D than to the third side surface 20C in a plan view. The first terminal opening 77A is arranged at a position overlapping with the first terminal side contact region 33 (see FIG. 40) in a plan view. The second terminal opening 77B is arranged at a position overlapping with the second terminal side contact region 43 (see FIG. 40) in a plan view. The third terminal opening 77C is arranged at a position overlapping with the third terminal side contact region 53 in a plan view. The TVS diode 10 of the fourth embodiment can achieve the same effects as those of the first embodiment.

[0289] Fifth Embodiment A TVS diode 10 according to a fifth embodiment will be described with reference to Figures 44 to 46. The TVS diode 10 according to the fifth embodiment differs from the TVS diode 10 according to the first embodiment mainly in the planar structure of the TVS diode 10. In the following, components common to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0290] Fig. 44 schematically shows the planar structure of the semiconductor chip 20 in the TVS diode 10 of the fifth embodiment. Fig. 45 schematically shows the planar structure of the first to third connection electrodes 81 to 83 and wiring 90 of the TVS diode 10. Fig. 46 schematically shows the planar structure of the TVS diode 10.

[0291] 44, the TVS diode 10 of the fifth embodiment includes a first pin junction 30, a second pin junction 40, a first reverse pin junction 60A, a second reverse pin junction 60B, and a pn junction 60E. In other words, the TVS diode 10 of the fifth embodiment has a configuration in which the third pin junction 50 and the third reverse pin junction 60C (both see FIG. 2) are omitted from the first embodiment. Although not shown, the cross-sectional structures of the first pin junction 30 and the second pin junction 40 are similar to those of the first embodiment.

[0292] The diode pair region 60 (high-concentration region 61) includes a first region 66A, a second region 66B, and a first connection region 67A. In other words, the diode pair region 60 (high-concentration region 61) of the fifth embodiment has a configuration in which the third region 66C and the second connection region 67B are omitted from the first embodiment. As indicated by the dashed line in FIG. 44 , the outer edge of the internal region 64 is located inward from the outer edge of the high-concentration region 61 in plan view. In one example, the internal region 64 is slightly smaller than the high-concentration region 61 (diode pair region 60) in plan view. Therefore, the internal region 64 is provided to overlap with each of the reverse pin junctions 60A and 60B in plan view. More specifically, the internal region 64 is provided to overlap with each of the first low-concentration region 62A and the second low-concentration region 62B in plan view. The cross-sectional structures of each of the reverse pin junctions 60A and 60B are similar to those of the first embodiment.

[0293] 45, the TVS diode 10 includes a first connection electrode 81, a second connection electrode 82, and a wiring 90. In other words, the TVS diode 10 of the fifth embodiment has a configuration in which the third connection electrode 83 is omitted from the first embodiment. Also, the planar structure of the wiring 90 differs from that of the first embodiment. The configurations of the first connection electrode 81 and the second connection electrode 82 are the same as those of the first embodiment.

[0294] The wiring 90 includes a first region 91, a second region 92, and a first connection region 94. The wiring 90 also includes a first recess 96A and a second recess 96B. In other words, the wiring 90 of the fifth embodiment has a configuration in which the third region 93, the second connection region 95, and the third recess 96C are omitted from the first embodiment.

[0295] As shown in FIG. 46, the TVS diode 10 of the fifth embodiment includes a first terminal opening 77A that exposes a portion of the first connection electrode 81 and a second terminal opening 77B that exposes a portion of the second connection electrode 82. The first terminal opening 77A is located in a corner of the semiconductor chip 20 that is closer to the first side surface 20A and the fourth side surface 20D in a plan view. The second terminal opening 77B is located in a corner of the semiconductor chip 20 that is closer to the second side surface 20B and the fourth side surface 20D in a plan view. The first terminal opening 77A is located at a position overlapping the first terminal contact region 33 (see FIG. 44) in a plan view. The second terminal opening 77B is located at a position overlapping the second terminal contact region 43 (see FIG. 44) in a plan view. The TVS diode 10 of the fifth embodiment provides the same effects as those of the first embodiment.

[0296] Sixth Embodiment A TVS diode 10 according to a sixth embodiment will be described with reference to Figures 47 to 49. The TVS diode 10 according to the sixth embodiment differs from the TVS diode 10 according to the first embodiment mainly in the planar structure of the TVS diode 10. In the following, components common to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0297] Fig. 47 schematically shows the planar structure of the semiconductor chip 20 in the TVS diode 10 of the sixth embodiment. Fig. 48 schematically shows the planar structure of the first to third connection electrodes 81 to 83 and wiring 90 of the TVS diode 10. Fig. 49 schematically shows the planar structure of the TVS diode 10.

[0298] 47, the TVS diode 10 of the sixth embodiment includes a first pin junction 30, a second pin junction 40, a first reverse pin junction 60A, a second reverse pin junction 60B, and a pn junction 60E. In other words, the TVS diode 10 of the third embodiment has a configuration in which the third pin junction 50 and the third reverse pin junction 60C (see FIG. 2) are omitted from the first embodiment.

[0299] The first pin junction 30 and the second pin junction 40 are spaced apart from each other in the Y direction. The diode pair region 60 is provided between the first pin junction 30 and the second pin junction 40 in the Y direction and spaced apart from both the first pin junction 30 and the second pin junction 40.

[0300] The first pin junction 30 and the second pin junction 40 are rectangular in shape, with the X direction as the longitudinal direction and the Y direction (the arrangement direction of the first pin junction 30 and the second pin junction 40) as the lateral direction. Therefore, both the first terminal side low-concentration region 32 and the second terminal side low-concentration region 42 are substantially rectangular in shape, with the X direction as the longitudinal direction and the Y direction as the lateral direction in plan view. Both the first terminal side contact region 33 and the second terminal side contact region 43 are substantially rectangular in shape, with the X direction as the longitudinal direction and the Y direction as the lateral direction in plan view. Each of the four corners of each of the terminal side low-concentration regions 32, 42 and each of the terminal side contact regions 33, 43 is curved. The cross-sectional structures of the first pin junction 30 and the second pin junction 40 are the same as those in the first embodiment.

[0301] The diode pair region 60 (high concentration region 61) has a rectangular shape in a plan view. In one example, the diode pair region 60 (high concentration region 61) has a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a plan view. The diode pair region 60 is provided with a first reverse pin junction 60A and a second reverse pin junction 60B. In one example, the first reverse pin junction 60A and the second reverse pin junction 60B are arranged at the same position in the Y direction and spaced apart from each other in the X direction. The first low concentration region 62A and the second low concentration region 62B are arranged at the same position in the Y direction and spaced apart from each other in the X direction. The first contact region 63A and the second contact region 63B are arranged at the same position in the Y direction and spaced apart from each other in the X direction. Each of the low-concentration regions 62A, 62B has a generally oval shape with its short side aligned in the X direction (the direction in which the first low-concentration regions 62A and the second low-concentration regions 62B are arranged) and its long side aligned in the Y direction. Each of the contact regions 63A, 63B has a generally oval shape with its short side aligned in the X direction (the direction in which the first contact region 63A and the second contact region 63B are arranged) and its long side aligned in the Y direction.

[0302] As shown by the dashed lines in FIG. 47, the outer edge of the internal region 64 is located inward of the outer edge of the high-concentration region 61 in plan view. In one example, the internal region 64 has a rectangular shape that is slightly smaller than the high-concentration region 61 (diode pair region 60) in plan view. Therefore, the internal region 64 is provided so as to overlap with each of the reverse pin junctions 60A, 60B in plan view. More specifically, the internal region 64 is provided so as to overlap with each of the first low-concentration region 62A and the second low-concentration region 62B in plan view. The cross-sectional structure of the pn junction 60E is the same as that of the first embodiment.

[0303] 48, the TVS diode 10 includes a first connection electrode 81, a second connection electrode 82, and a wiring 90. In other words, the TVS diode 10 of the third embodiment has a configuration in which the third connection electrode 83 is omitted from the first embodiment. In addition, the planar structure of the wiring 90 differs from that of the first embodiment.

[0304] The first connection electrode 81 includes a pin connection portion 81A, a wiring portion 81B, and a reverse pin connection portion 81C. The wiring portion 81B and the reverse pin connection portion 81C are similar to the first connection electrode 81 of the first embodiment. The pin connection portion 81A has a substantially rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a plan view. The pin connection portion 81A covers the entire first terminal side contact region 33 in a plan view.

[0305] The second connection electrode 82 includes a pin connection portion 82A, a wiring portion 82B, and a reverse pin connection portion 82C. The wiring portion 82B and the reverse pin connection portion 82C are similar to the second connection electrode 82 of the first embodiment. The pin connection portion 82A has a substantially rectangular shape with its longitudinal direction in the X direction and its lateral direction in the Y direction in plan view. The pin connection portion 82A covers the entire second terminal side contact region 43 in plan view.

[0306] The wiring 90 is provided so as to partially surround both the first connection electrode 81 and the second connection electrode 82 individually in a plan view. The wiring 90 includes a first recess 96A and a second recess 96B. The first recess 96A is provided so as to surround the first connection electrode 81 in a plan view. The second recess 96B is provided so as to surround the second connection electrode 82 in a plan view.

[0307] As shown in FIG. 49 , the first terminal opening 77A and the second terminal opening 77B of the TVS diode 10 of the sixth embodiment are located at the same position in the X direction and spaced apart from each other in the Y direction. The first terminal opening 77A is located at one of both Y-direction end portions of the semiconductor chip 20 closer to the fourth side surface 20D in a plan view. The second terminal opening 77B is located at one of both Y-direction end portions of the semiconductor chip 20 closer to the third side surface 20C in a plan view. Each of the first terminal opening 77A and the second terminal opening 77B has a substantially elliptical shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a plan view. The first terminal opening 77A is located at a position overlapping with the first terminal side contact region 33 (see FIG. 47 ). The second terminal opening 77B is located at a position overlapping with the second terminal side contact region 43 (see FIG. 47 ). The TVS diode 10 of the sixth embodiment can achieve the same effects as those of the first embodiment.

[0308] Seventh Embodiment A TVS diode 10 according to the seventh embodiment will be described with reference to Figures 50 to 53. The TVS diode 10 according to the seventh embodiment differs from the TVS diode 10 according to the first embodiment mainly in the planar structure of the TVS diode 10. In the following, components common to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0309] Fig. 50 schematically shows the planar structure of the semiconductor chip 20 in the TVS diode 10 of the seventh embodiment. Fig. 51 schematically shows the cross-sectional structure of the TVS diode 10 taken along line F51-F51 in Fig. 50. Fig. 52 schematically shows the planar structure of the first to third connection electrodes 81-83 and wiring 90 of the TVS diode 10. Fig. 53 schematically shows the planar structure of the TVS diode 10.

[0310] As shown in FIG. 50, the TVS diode 10 of the seventh embodiment has a configuration in which a fourth pin junction 130 and a fourth reverse pin junction 60D are added to the TVS diode 10 of the first embodiment.

[0311] In plan view, the fourth pin junction 130 is disposed closer to the second side surface 20B and the third side surface 20C than the third pin junction 50. The fourth pin junction 130 is disposed at the same position as the second pin junction 40 in the Y direction. In plan view, the third region 66C of the diode pair region 60 is disposed between the second pin junction 40 and the fourth pin junction 130. For this reason, it can be said that the second pin junction 40 and the fourth pin junction 130 are disposed opposite each other with the diode pair region 60 sandwiched between them in plan view.

[0312] As shown in FIG. 51 , the fourth pin junction 130 includes a fourth terminal side high-concentration region 131, a fourth terminal side low-concentration region 132, a fourth terminal side contact region 133, and a fourth partition region 134. The fourth terminal side high-concentration region 131, the fourth terminal side low-concentration region 132, and the fourth terminal side contact region 133 form the fourth pin junction 130. As shown in FIGS. 50 and 51 , the configuration of the fourth pin junction 130 is similar to that of the third pin junction 50. In the seventh embodiment, the configurations of the first pin junction 30, the second pin junction 40, and the third pin junction 50 are similar to those of the first embodiment. Therefore, the first pin junction 30, the second pin junction 40, the third pin junction 50, and the fourth pin junction 130 have the same configuration. Therefore, detailed description of the fourth terminal side high-concentration region 131, the fourth terminal side low-concentration region 132, the fourth terminal side contact region 133, and the fourth partition region 134 will be omitted. In the fourth pin junction 130, the p-type fourth terminal side high-concentration region 131 constitutes the P layer of the pin diode, the n-type fourth terminal side low-concentration region 132 constitutes the I layer of the pin diode, and the n-type fourth terminal side contact region 133 constitutes the N layer of the pin diode. In other words, the fourth terminal side high-concentration region 131, the fourth terminal side low-concentration region 132, and the fourth terminal side contact region 133 constitute a pin junction in the Z direction. Therefore, in the fourth pin junction 130, the fourth terminal side high-concentration region 131, the fourth terminal side low-concentration region 132, and the fourth terminal side contact region 133 constitute a pin diode (diode 208) in the first polarity direction.

[0313] In the example shown in FIG. 51 , the shortest distance DE between the fourth defined area 134 of the fourth pin connection 130 and the third defined area 54 of the third pin connection 50 is equal to the shortest distance DB between the second defined area 44 of the second pin connection 40 and the third defined area 54. The shortest distance DE is also equal to the shortest distance DA between the first defined area 34 of the first pin connection 30 and the second defined area 44. The shortest distance DF between the fourth defined area 134 and the second defined area 44 is also equal to the shortest distance DC between the first defined area 34 and the third defined area 54. Each of the shortest distances DE and DF can be changed as desired. In one example, the shortest distance DE may be different from at least one of the shortest distance DA and the shortest distance DB. The shortest distance DF may also be different from the shortest distance DC.

[0314] 50, the diode pair region 60 (high-concentration region 61) includes a fourth region 66D and a third connection region 67C. The fourth region 66D is provided so as to be shifted in the Y direction with respect to the third region 66C. More specifically, the fourth region 66D is provided closer to the second side surface 20B and the fourth side surface 20D with respect to the third region 66C. The fourth region 66D is provided at the same position as the second region 66B in the Y direction.

[0315] The fourth region 66D includes first to fourth sides 66DA to 66DD. The first side 66DA is a side of the fourth region 66D closer to the first side surface 20A and extends in the Y direction in a planar view. The second side 66DB is a side of the fourth region 66D closer to the second side surface 20B and extends in the Y direction in a planar view. The third side 66DC is a side of the fourth region 66D closer to the third side surface 20C and extends in the X direction in a planar view. The fourth side 66DD is a side of the fourth region 66D closer to the fourth side surface 20D and extends in the X direction in a planar view. The first side 66BA and the fourth side 66BD are disposed closer to the fourth side surface 20D than the third region 66C in the Y direction.

[0316] The fourth region 66D includes a corner portion between the first side 66DA and the fourth side 66DD, a corner portion between the second side 66DB and the fourth side 66DD, and a corner portion between the second side 66DB and the third side 66DC. Each corner portion is curved in plan view.

[0317] The third connection region 67C is provided between the third region 66C and the fourth region 66D. The third connection region 67C is a region that connects the third region 66C and the fourth region 66D. The third region 66C is disposed between the third pin joint 50 and the fourth pin joint 130 in a direction that intersects both the X direction and the Y direction in a plan view.

[0318] By providing the fourth region 66D and the third connection region 67C, the shape of the third region 66C in plan view differs from that of the first embodiment. Specifically, the corner portion between the second side 66CB and the fourth side 66CD is omitted from the third region 66C.

[0319] 50, the width dimension (dimension in the X direction) WD of the fourth region 66D is equal to the width dimension WA of the first region 66A. The width dimension WB of the second region 66B is greater than the width dimension WD of the fourth region 66D. The width dimension WC of the third region 66C is greater than the width dimension WD of the fourth region 66D. The width dimension WB of the second region 66B is equal to the width dimension WC of the third region 66C.

[0320] The width dimension WA of the first region 66A, the width dimension WB of the second region 66B, the width dimension WC of the third region 66C, and the width dimension WD of the fourth region 66D can each be changed as desired. For example, the width dimension WA of the first region 66A may be equal to the width dimension WC of the third region 66C. For example, the width dimension WD of the fourth region 66D may be equal to the width dimension WB of the second region 66B. The width dimension WD of the fourth region 66D may be different from the width dimension WA of the first region 66A.

[0321] The fourth region 66D is provided with a fourth reverse pin junction 60D. The fourth reverse pin junction 60D is aligned with the fourth pin junction 130 in the Y direction. The fourth reverse pin junction 60D is shifted in the Y direction relative to the third reverse pin junction 60C. The fourth reverse pin junction 60D includes a portion that overlaps with the third reverse pin junction 60C when viewed from the X direction.

[0322] As shown in FIG. 51 , the fourth reverse pin junction 60D includes a fourth low-concentration region 62D and a fourth contact region 63D. The configurations of the fourth low-concentration region 62D and the fourth contact region 63D are similar to, for example, the third low-concentration region 62C and the third contact region 63C. In the fourth reverse pin junction 60D, the p-type fourth contact region 63D constitutes the P layer of the pin diode, the n-type fourth low-concentration region 62D constitutes the I layer of the pin diode, and the n-type high-concentration region 61 constitutes the N layer of the pin diode. That is, the fourth contact region 63D, the fourth low-concentration region 62D, and the high-concentration region 61 constitute a pin junction in the Z direction. Therefore, in the fourth reverse pin junction 60D, the high-concentration region 61, the fourth low-concentration region 62D, and the fourth contact region 63D constitute a pin diode (diode 209) in the second polarity direction.

[0323] As indicated by the dashed lines in FIG. 50 , the outer edge of the internal region 64 is located inward of the outer edge of the high-concentration region 61 in plan view. In one example, the internal region 64 has a rectangular shape that is slightly smaller than the high-concentration region 61 (diode pair region 60) in plan view. Therefore, the internal region 64 is provided so as to overlap with each of the reverse pin junctions 60A, 60B, 60C, and 60D in plan view. More specifically, the internal region 64 is provided so as to overlap with each of the first low-concentration region 62A, the second low-concentration region 62B, the third low-concentration region 62C, and the fourth low-concentration region 62D in plan view. The cross-sectional structure of the pn junction 60E is similar to that of the first embodiment.

[0324] As shown in FIG. 52, the TVS diode 10 of the seventh embodiment has a configuration in which a fourth connection electrode 84 is added to the TVS diode 10 of the first embodiment. The fourth connection electrode 84 is disposed closer to the second side surface 20B than the center of the semiconductor chip 20 in the X direction in a plan view. The first connection electrode 81 extends along the Y direction. The fourth connection electrode 84 includes a pin connection portion 84A and a wiring portion 84B extending in the Y direction from the pin connection portion 84A toward the fourth side surface 20D. In one example, the pin connection portion 84A and the wiring portion 84B are integrated.

[0325] The pin connection portion 84A is disposed at a position overlapping with the fourth pin joint 130 (see FIG. 50) in a plan view. The pin connection portion 84A is rectangular in a plan view. The pin connection portion 84A is disposed within the fourth terminal side low concentration region 132 of the fourth pin joint 130 in a plan view. The pin connection portion 84A is slightly larger than the fourth terminal side contact region 133 of the fourth pin joint 130 in a plan view.

[0326] The wiring portion 84B is strip-shaped with a width in the X direction in a plan view. The width dimension of the wiring portion 84B is smaller than the dimension of the pin connection portion 84A in the X direction. The wiring portion 84B is arranged offset in the X direction with respect to the pin connection portion 84A. More specifically, a virtual line CL5 extending in the Y direction at the center of the width of the wiring portion 84B is positioned closer to the first side surface 20A than a virtual line CL6 extending in the Y direction at the center of the pin connection portion 84A in the X direction.

[0327] The wiring portion 84B is provided so as to cover the fourth contact region 63D of the fourth reverse pin junction 60D in a plan view. In one example, the wiring portion 84B covers the entire fourth contact region 63D in a plan view. Therefore, the width dimension of the wiring portion 84B is larger than the width dimension of the fourth contact region 63D. On the other hand, the width dimension of the wiring portion 84B is smaller than the width dimension of the fourth low-concentration region 62D. The tip portion of the wiring portion 84B is curved in a plan view.

[0328] A reverse pin connection portion 84C is provided in the wiring portion 84B at a position overlapping with the fourth contact region 63D. The reverse pin connection portion 84C is connected to the fourth contact region 63D. In one example, the fourth connection electrode 84 has the same configuration as the first connection electrode 81.

[0329] 51 , the fourth connection electrode 84 electrically connects the fourth terminal side contact region 133 of the fourth pin junction 130 and the fourth contact region 63D of the fourth reverse pin junction 60D. The fourth connection electrode 84 is in contact with the fourth terminal side contact region 133 through the seventh opening 73H of the insulating layer 70. The fourth connection electrode 84 is in contact with the fourth contact region 63D through the eighth opening 73J of the insulating layer 70.

[0330] 52, the shape of the third connection electrode 83 differs from that of the first embodiment due to the provision of the fourth connection electrode 84. In the seventh embodiment, the configuration of the third connection electrode 83 is similar to that of the second connection electrode 82. That is, the center in the X direction of the wiring portion 83B of the third connection electrode 83 is at the same position as the center in the X direction of the pin connection portion 83A.

[0331] The wiring 90 includes a fourth region 98, a third connection region 99, and a fourth recess 96D. The fourth region 98 is provided so as to overlap with the fourth region 66D (see FIG. 50) of the diode pair region 60 in plan view. Portions of the outer periphery of the fourth region 98 corresponding to the first side 66DA, the second side 66DB, and the fourth side 66DD (all see FIG. 50) of the fourth region 66D are provided so as to overlap with the first side 66DA, the second side 66DB, and the fourth side 66DD in plan view.

[0332] The fourth recess 96D is provided so as to avoid the fourth connection electrode 84 in plan view. The fourth recess 96D is open toward the third side surface 20C. As a result, the fourth region 98 is provided so as to partially surround the fourth connection electrode 84 in plan view. Furthermore, the fourth recess 96D is provided so as to avoid the fourth low-concentration region 62D of the fourth region 66D of the diode pair region 60 (high-concentration region 61) in plan view (see FIG. 50 for both). Therefore, the fourth region 98 is provided so as to surround the fourth low-concentration region 62D in plan view.

[0333] By providing the fourth recess 96D, it can be said that the fourth region 98 is partially connected to the isolation region 65 in the fourth region 66D. More specifically, as shown in FIG. 50 , the isolation region 65 in the fourth region 66D includes a wiring connection region 65P to which the wiring 90 is connected and a fourth isolation region 65D that overlaps with the fourth connection electrode 84 in a plan view. The fourth isolation region 65D is provided at one of both ends of the fourth region 66D in the Y direction, closer to the fourth pin junction 130. The fourth isolation region 65D is a region of the fourth region 66D between the fourth low-concentration region 62D and the third side 66DC in a plan view. The wiring connection region 65P is provided so as to partially surround the fourth low-concentration region 62D in a plan view. In other words, the wiring connection region 65P is provided so as to partially surround the fourth reverse pin junction 60D in a plan view. Therefore, the fourth region 98 (see FIG. 51) connected to the wiring connection region 65P is provided so as to partially surround the fourth reverse pin junction 60D in plan view.

[0334] 52, the third connection region 99 is provided so as to overlap the third connection region 67C (see FIG. 51) of the diode pair region 60 in a plan view. The shape and size of the third connection region 99 are the same as those of the first connection region 67A. The third connection region 99 is connected to the entire third connection region 67C. In other words, the third connection region 67C is formed by the wiring connection region 65P.

[0335] 53, the TVS diode 10 of the seventh embodiment has a configuration in which a fourth terminal opening 77D is added to the TVS diode 10 of the first embodiment. The arrangement and configuration of the first to third terminal openings 77A to 77C are the same as those of the first embodiment.

[0336] Fourth terminal opening 77D is arranged offset in both the X and Y directions with respect to third terminal 103 in plan view. Specifically, fourth terminal opening 77D is arranged closer to second side face 20B and third side face 20C than third terminal opening 77C in plan view. In one example, fourth terminal opening 77D is arranged at the same position as second terminal opening 77B in the Y direction.

[0337] 51, like the first to third terminal openings 77A to 77C, the fourth terminal opening 77D exposes the pin connection portion 84A of the fourth connection electrode 84. The fourth terminal opening 77D is arranged at a position overlapping the fourth terminal side contact region 133 in plan view. Note that the TVS diode 10 of the seventh embodiment can achieve the same effects as the first embodiment.

[0338] Eighth Embodiment A TVS diode 10 according to the eighth embodiment will be described with reference to Figures 54 to 56. The TVS diode 10 according to the eighth embodiment differs from the TVS diode 10 according to the seventh embodiment mainly in the planar structure of the TVS diode 10. In the following, components common to the seventh embodiment will be given the same reference numerals, and descriptions thereof will be omitted.

[0339] As shown in FIG. 54 , in the TVS diode 10 of the eighth embodiment, the first pin junction 30, the second pin junction 40, the third pin junction 50, and the fourth pin junction 130 are arranged at four corners of the first surface 20S of the semiconductor chip 20 in a plan view. The first pin junction 30 is arranged at a corner of the first surface 20S of the semiconductor chip 20 closer to the first side surface 20A and the fourth side surface 20D. The second pin junction 40 is arranged at a corner of the first surface 20S of the semiconductor chip 20 closer to the first side surface 20A and the third side surface 20C. The third pin junction 50 is arranged at a corner of the first surface 20S of the semiconductor chip 20 closer to the second side surface 20B and the fourth side surface 20D. The fourth pin junction 130 is arranged at a corner of the first surface 20S of the semiconductor chip 20 closer to the second side surface 20B and the third side surface 20C. The cross-sectional structures of the first pin joint 30, the second pin joint 40, the third pin joint 50, and the fourth pin joint 130 are the same as those in the seventh embodiment.

[0340] The diode pair region 60 (high concentration region 61) has a cross shape in a plan view. The diode pair region 60 includes first to fourth regions 66A to 66D and first to fourth reverse pin junctions 60A to 60D, similar to the seventh embodiment.

[0341] The first region 66A is a region where the first reverse pin junction 60A is provided. The first region 66A includes a portion located between the first pin junction 30 and the second pin junction 40 in the Y direction. In other words, the first pin junction 30 and the second pin junction 40 are arranged opposite each other with the first region 66A in between. The first reverse pin junction 60A also includes a portion located between the first pin junction 30 and the second pin junction 40 in the Y direction.

[0342] Both the first low-concentration region 62A and the first contact region 63A of the first reverse pin junction 60A have a generally rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a plan view. In one example, both the first low-concentration region 62A and the first contact region 63A include regions that extend beyond the first pin junction 30 and the second pin junction 40 when viewed from the Y direction.

[0343] The second region 66B is a region where the second reverse pin junction 60B is provided. The second region 66B includes a portion located between the second pin junction 40 and the fourth pin junction 130 in the X direction. In other words, the second pin junction 40 and the fourth pin junction 130 are arranged opposite each other with the second region 66B interposed therebetween. The second reverse pin junction 60B also includes a portion located between the second pin junction 40 and the fourth pin junction 130 in the X direction.

[0344] The second low-concentration region 62B and the second contact region 63B of the second reverse pin junction 60B are both substantially rectangular in shape, with the X direction as the short side and the Y direction as the long side in a plan view. In one example, when viewed from the X direction, both the second low-concentration region 62B and the second contact region 63B include regions that extend beyond the second pin junction 40 and the fourth pin junction 130.

[0345] The third region 66C is a region where the third reverse pin junction 60C is provided. The third region 66C includes a portion located between the first pin junction 30 and the third pin junction 50 in the X direction. In other words, the first pin junction 30 and the third pin junction 50 are arranged opposite each other with the third region 66C interposed therebetween. The third reverse pin junction 60C also includes a portion located between the first pin junction 30 and the third pin junction 50 in the X direction.

[0346] The third low-concentration region 62C and the third contact region 63C of the third reverse pin junction 60C are both substantially rectangular in shape, with the X direction as the short side and the Y direction as the long side in a plan view. In one example, the third low-concentration region 62C and the third contact region 63C include regions that extend beyond the first pin junction 30 and the third pin junction 50 when viewed from the X direction.

[0347] The fourth region 66D is a region where the fourth reverse pin junction 60D is provided. The fourth region 66D includes a portion located between the third pin junction 50 and the fourth pin junction 130 in the Y direction. In other words, the third pin junction 50 and the fourth pin junction 130 are arranged opposite each other with the fourth region 66D interposed therebetween. The fourth reverse pin junction 60D also includes a portion located between the third pin junction 50 and the fourth pin junction 130 in the Y direction.

[0348] Both the fourth low-concentration region 62D and the fourth contact region 63D of the fourth reverse pin junction 60D have a generally rectangular shape with the longitudinal direction in the X direction and the lateral direction in the Y direction in a plan view. In one example, both the fourth low-concentration region 62D and the fourth contact region 63D include regions that extend beyond the third pin junction 50 and the fourth pin junction 130 when viewed from the Y direction.

[0349] In the diode pair region 60 (high-concentration region 61), the region connecting the first region 66A and the second region 66B, the region connecting the first region 66A and the third region 66C, the region connecting the second region 66B and the fourth region 66D, and the region connecting the third region 66C and the fourth region 66D are each curved in a planar view. Furthermore, the corners of each of the first to fourth regions 66A to 66D are also curved in a planar view. The radius of curvature of each of the region connecting the first region 66A and the second region 66B, the region connecting the first region 66A and the third region 66C, the region connecting the second region 66B and the fourth region 66D, and the region connecting the third region 66C and the fourth region 66D is larger than the radius of curvature of the corners of each of the first to fourth regions 66A to 66D.

[0350] As indicated by the dashed lines in FIG. 54, the outer edge of the internal region 64 is located inward of the outer edge of the high-concentration region 61 in plan view. In one example, the internal region 64 has a rectangular shape that is slightly smaller than the high-concentration region 61 (diode pair region 60) in plan view. Therefore, the internal region 64 is provided so as to overlap with each of the reverse pin junctions 60A, 60B, 60C, and 60D in plan view. More specifically, the internal region 64 is provided so as to overlap with each of the first low-concentration region 62A, the second low-concentration region 62B, the third low-concentration region 62C, and the fourth low-concentration region 62D in plan view. The cross-sectional structure of the pn junction 60E (see FIG. 2) is similar to that of the first embodiment.

[0351] As shown in FIG. 55, the shapes of the first to fourth connection electrodes 81 to 84 in the eighth embodiment in plan view are different from those of the first to fourth connection electrodes 81 to 84 in the seventh embodiment. The first connection electrode 81 includes a pin connection portion 81A, a wiring portion 81B, and a reverse pin connection portion 81C. The pin connection portion 81A covers the entire first terminal side contact region 33 of the first pin junction 30 in a plan view. The pin connection portion 81A is in contact with the first terminal side contact region 33. The pin connection portion 81A is rectangular in a plan view. The wiring portion 81B extends in the Y direction from the pin connection portion 81A toward the third side surface 20C. The reverse pin connection portion 81C covers the entire first contact region 63A of the first reverse pin junction 60A in a plan view. The reverse pin connection portion 81C is in contact with the first contact region 63A. The reverse pin connection portion 81C is substantially rectangular in a plan view, with the X direction as the longitudinal direction and the Y direction as the lateral direction. In the eighth embodiment, the first to fourth connection electrodes 81 to 84 have the same shape in a plan view. Therefore, detailed description of the second to fourth connection electrodes 82 to 84 will be omitted.

[0352] The shape of the wiring 90 in the eighth embodiment in plan view is different from that of the wiring 90 in the seventh embodiment. The wiring 90 is provided so as to partially surround each of the first to fourth connection electrodes 81 to 84. More specifically, the wiring 90 includes first to fourth recesses 96A to 96D, as in the seventh embodiment. The first recess 96A of the wiring 90 is provided so as to avoid the reverse pin connection portion 81C of the first connection electrode 81 in plan view. The first recess 96A opens toward the pin connection portion 81A so that the wiring portion 81B passes through. Thus, the wiring 90 is provided so as to partially surround the reverse pin connection portion 81C and the wiring portion 81B of the first connection electrode 81. The second recess 96B is provided so as to avoid the reverse pin connection portion 82C of the second connection electrode 82 in plan view. The second recess 96B opens toward the pin connection portion 82A so that the wiring portion 82B passes through. As a result, the wiring 90 is provided so as to partially surround the reverse pin connection portion 82C and the wiring portion 82B of the second connection electrode 82. The third recess 96C is provided so as to avoid the reverse pin connection portion 83C of the third connection electrode 83 in plan view. The third recess 96C opens toward the pin connection portion 83A so that the wiring portion 83B passes through. As a result, the wiring 90 is provided so as to partially surround the reverse pin connection portion 83C and the wiring portion 83B of the third connection electrode 83. The fourth recess 96D is provided so as to avoid the reverse pin connection portion 84C of the fourth connection electrode 84 in plan view. The fourth recess 96D opens toward the pin connection portion 84A so that the wiring portion 84B passes through. As a result, the wiring 90 is provided so as to partially surround the reverse pin connection portion 84C and the wiring portion 84B of the fourth connection electrode 84.

[0353] The first recess 96A is provided to surround the first low-concentration region 62A (see FIG. 54) of the diode pair region 60 (high-concentration region 61) in plan view. The second recess 96B is provided to surround the second low-concentration region 62B (see FIG. 54) in plan view. The third recess 96C is provided to surround the third low-concentration region 62C (see FIG. 54) in plan view. The fourth recess 96D is provided to surround the fourth low-concentration region 62D (see FIG. 54) in plan view.

[0354] The wiring 90 is partially connected to the isolation region 65 of the diode pair region 60 (high-concentration region 61). More specifically, as shown in FIG. 54, the isolation region 65 includes first to fourth isolation regions 65A to 65D to which the wiring 90 is not connected, and an interconnect connection region 65P to which the wiring 90 is connected. The first isolation region 65A is a portion of the isolation region 65 that corresponds to the first region 66A and is covered by the wiring portion 81B (see FIG. 55). The second isolation region 65B is a portion of the isolation region 65 that corresponds to the second region 66B and is covered by the wiring portion 82B (see FIG. 55). The third isolation region 65C is a portion of the isolation region 65 that corresponds to the third region 66C and is covered by the wiring portion 83B (see FIG. 55). The fourth isolation region 65D is a portion of the isolation region 65 that corresponds to the fourth region 66D and is covered by the wiring portion 84B (see FIG. 55). In this way, the wiring connection region 65P is provided so as to partially surround each of the first to fourth low-concentration regions 62A to 62D in plan view. Therefore, the wiring 90 connected to the wiring connection region 65P is provided so as to partially surround each of the first to fourth low-concentration regions 62A to 62D in plan view.

[0355] 56, the first to fourth terminal openings 77A to 77D of the TVS diode 10 of the eighth embodiment are arranged at four corners of the first surface 20S of the semiconductor chip 20 in a plan view. The first terminal opening 77A is arranged at a corner of the first surface 20S of the semiconductor chip 20 closer to the first side surface 20A and the fourth side surface 20D. The second terminal opening 77B is arranged at a corner of the first surface 20S of the semiconductor chip 20 closer to the first side surface 20A and the third side surface 20C. The third terminal opening 77C is arranged at a corner of the first surface 20S of the semiconductor chip 20 closer to the second side surface 20B and the fourth side surface 20D. The fourth terminal opening 77D is arranged at a corner of the first surface 20S of the semiconductor chip 20 closer to the second side surface 20B and the third side surface 20C.

[0356] The first terminal opening 77A is arranged at a position overlapping with the first terminal side contact region 33 (see FIG. 54) in plan view. The second terminal opening 77B is arranged at a position overlapping with the second terminal side contact region 43 (see FIG. 54) in plan view. The third terminal opening 77C is arranged at a position overlapping with the third terminal side contact region 53 (see FIG. 54) in plan view. The fourth terminal opening 77D is arranged at a position overlapping with the fourth terminal side contact region 133 (see FIG. 54) in plan view. Note that the TVS diode 10 of the eighth embodiment can achieve the same effects as the first embodiment.

[0357] <Example of change> The above-described embodiments can be modified as follows: Furthermore, the above-described embodiments and the following modifications can be combined with each other within the scope of technical compatibility.

[0358] The second and third embodiments can be combined with each other. That is, the first pin junction 30 may include a first buffer region 35 and a first isolation trench structure 120A. The second pin junction 40 may include a second buffer region 45 and a second isolation trench structure 120B. The third pin junction 50 may include a third buffer region 55 and a third isolation trench structure 120C. In this case, the first partition region 34 may be omitted from the first pin junction 30. The second partition region 44 may be omitted from the second pin junction 40. The third partition region 54 may be omitted from the third pin junction 50.

[0359] At least one of the configurations of the second embodiment and the third embodiment can be applied to the fourth to eighth embodiments. In the third embodiment, at least one of the first separated electrode 123A, the second separated electrode 123B, and the third separated electrode 123C may be omitted.

[0360] In the third embodiment, at least one of the first isolation and insulation layer 122A, the second isolation and insulation layer 122B, and the third isolation and insulation layer 122C may be omitted. In the third embodiment, the size of the high-concentration region 61 can be changed arbitrarily. FIG. 57 shows a cross-sectional structure of a TVS diode 10 in which the size of the high-concentration region 61 is changed. As shown in FIG. 57, the high-concentration region 61 may expand to a position adjacent to the first isolation trench 121A and the second isolation trench 121B. Although not shown, the high-concentration region 61 may also expand to a position adjacent to the third isolation trench 121C. With such expansion of the high-concentration region 61, the internal region 64 may also expand. According to the TVS diode 10 of the modified example shown in FIG. 57, the junction area between the high-concentration region 61 and the internal region 64 increases, thereby improving the surge absorption performance of the TVS diode 10.

[0361] 57, the high-concentration region 61 may extend to a position adjacent to the first isolation trench 121A, while being provided at a position spaced apart from the second isolation trench 121B. In another example, the high-concentration region 61 may extend to a position adjacent to the second isolation trench 121B, while being provided at a position spaced apart from the first isolation trench 121A.

[0362] In the second embodiment, the TVS diode 10 may include the first pin junction 30 and a diode pair region 60 including the first reverse pin junction 60A and the p-n junction 60E. In other words, the second pin junction 40, the third pin junction 50, the second reverse pin junction 60B, and the third reverse pin junction 60C may be omitted from the TVS diode 10. Figure 58 schematically shows the cross-sectional structure of a modified TVS diode 10 including the first pin junction 30 and the diode pair region 60 including the first reverse pin junction 60A and the p-n junction 60E.

[0363] 58, the outer edge of the internal region 64 in the diode pair region 60 is located inward from the outer edge of the high concentration region 61 in a plan view. The outer edge of the internal region 64 is located at a position overlapping with the isolation region 65 in a plan view.

[0364] Although not shown, the high-concentration region 61 is rectangular in plan view. It includes four corner portions of the high-concentration region 61. Each corner portion of the high-concentration region 61 is curved in plan view. In one example, the internal region 64 is rectangular in plan view. The internal region 64 is slightly smaller than the high-concentration region 61 in plan view. Therefore, the inner edge of the internal region 64 is located more inward than the outer edge of the high-concentration region 61 in plan view. The internal region 64 is located at a position overlapping with the first low-concentration region 62A in plan view. The outer edge of the internal region 64 includes four corner portions. Each of the four corner portions is curved in plan view.

[0365] In the first and third embodiments, the TVS diode 10 may include the first pin junction 30 and a diode pair region 60 including the first reverse pin junction 60A and the pn junction 60E. In other words, the second pin junction 40 and the third pin junction 50, and the second reverse pin junction 60B and the third reverse pin junction 60C may be omitted from the TVS diode 10.

[0366] In the second embodiment, the p-type impurity concentration of the first buffer region 35 can be changed as desired. For example, the p-type impurity concentration of the first buffer region 35 may be equal to or greater than the p-type impurity concentration of the first terminal side high-concentration region 31. For example, the minimum value of the p-type impurity concentration of the first buffer region 35 may be less than the n-type impurity concentration of the first terminal side low-concentration region 32. The p-type impurity concentrations of the second buffer region 45 and the third buffer region 55 can also be changed in a similar manner.

[0367] In the second embodiment, the concentration gradient of the p-type impurity concentration in the first buffer region 35 can be changed as desired. For example, the p-type impurity concentration in the first buffer region 35 may be approximately constant in the Z direction. Note that the p-type impurity concentrations in the second buffer region 45 and the third buffer region 55 can also be changed in a similar manner.

[0368] In the first to third and seventh embodiments, the shape of the diode pair region 60 (high concentration region 61) in a planar view can be changed as desired. For example, the shape of the diode pair region 60 (high concentration region 61) in a planar view may be rectangular.

[0369] In the second embodiment, the diode pair region 60 (high-concentration region 61) may be composed of a first diode pair region, a second diode pair region, and a third diode pair region that are spaced apart from one another. The first diode pair region is provided with a first reverse pin junction 60A. The second diode pair region is provided with a second reverse pin junction 60B. The third diode pair region is provided with a third reverse pin junction 60C. In this case, the internal region 64 may be composed of a first internal region, a second internal region, and a third internal region that are spaced apart from one another. The first internal region is in contact with the high-concentration region of the first diode pair region. The second internal region is in contact with the high-concentration region of the second diode pair region. The third internal region is in contact with the high-concentration region of the third diode pair region.

[0370] In each embodiment, the internal region 64 may be provided so as to overlap only one of the first low-concentration region 62A, the second low-concentration region 62B, and the third low-concentration region 62C in a planar view. In one example, the internal region 64 may be provided so as to overlap both the first low-concentration region 62A and the third low-concentration region 62C in a planar view, but not overlap with the second low-concentration region 62B. In another example, the internal region 64 may be provided so as to overlap both the second low-concentration region 62B and the third low-concentration region 62C in a planar view, but not overlap with the first low-concentration region 62A.

[0371] In the first to third, fifth, and seventh embodiments, the arrangement of the first pin junction 30, the second pin junction 40, the third pin junction 50, and the first to third reverse pin junctions 60A to 60C can be arbitrarily changed. For example, the first pin junction 30 and the first reverse pin junction 60A do not have to be aligned in the Y direction in a plan view. For example, the first pin junction 30 and the first reverse pin junction 60A may be offset in the X direction in a plan view. For example, the second pin junction 40 and the second reverse pin junction 60B do not have to be aligned in the Y direction in a plan view. For example, the second pin junction 40 and the second reverse pin junction 60B may be offset in the X direction in a plan view. For example, the third pin junction 50 and the third reverse pin junction 60C do not have to be aligned in the Y direction in a plan view. In one example, the third pin joint 50 and the third reverse pin joint 60C may be arranged to be shifted in the X direction in a plan view.

[0372] In another example, the first pin junction 30 and the second reverse pin junction 60B do not have to be adjacent to each other in the X direction in a plan view. In another example, the first pin junction 30 may be offset in the Y direction from the second reverse pin junction 60B when viewed from the X direction so as not to overlap with it. In another example, the third pin junction 50 and the second reverse pin junction 60B do not have to be adjacent to each other in the X direction in a plan view. In another example, the third pin junction 50 may be offset in the Y direction from the second reverse pin junction 60B when viewed from the X direction so as not to overlap with it. In another example, the first reverse pin junction 60A and the second pin junction 40 do not have to be adjacent to each other in the X direction in a plan view. In another example, the second pin junction 40 may be offset in the Y direction from the first reverse pin junction 60A when viewed from the X direction so as not to overlap with it. In one example, the third reverse pin junction 60C and the second pin junction 40 do not have to be adjacent to each other in the X direction in a plan view. In one example, the second pin junction 40 may be shifted in the Y direction so as not to overlap with the third reverse pin junction 60C when viewed from the X direction.

[0373] In the seventh embodiment, the fourth pin joint 130 and the fourth reverse pin joint 60D do not have to be aligned in the Y direction in a plan view. In one example, the fourth pin joint 130 and the fourth reverse pin joint 60D may be offset in the X direction in a plan view.

[0374] In another example, the fourth pin junction 130 and the third reverse pin junction 60C do not have to be adjacent to each other in the X direction in a plan view. In another example, the fourth pin junction 130 may be shifted in the Y direction from the third reverse pin junction 60C when viewed from the X direction so as not to overlap with them. In another example, the fourth reverse pin junction 60D and the fourth pin junction 130 do not have to be adjacent to each other in the X direction when viewed from the X direction. In another example, the third pin junction 50 may be shifted in the Y direction from the fourth reverse pin junction 60D when viewed from the X direction so as not to overlap with them.

[0375] In each embodiment, the position of the outer edge of the internal region 64 in a planar view can be changed as desired. For example, the outer edge of the internal region 64 may be arranged to overlap the outer edge of the high-concentration region 61 in a planar view. For example, the outer edge of the internal region 64 may include a portion that extends beyond the high-concentration region 61 in a planar view. For example, at least a portion of the outer edge of the internal region 64 may be located at a position different from the separation region 65 in a planar view.

[0376] In each embodiment, at least one of the corners at the outer edge of the internal region 64 may be formed at a right angle instead of being curved in plan view. In each embodiment, the size and shape of the isolation region 65 in plan view can be changed as desired. The isolation region 65 may be provided along the entire periphery of the high-concentration region 61. In other words, the isolation region 65 may not include a portion surrounding the first reverse pin junction 60A in plan view. The isolation region 65 may not include a portion surrounding the second reverse pin junction 60B in plan view. The isolation region 65 may not include a portion surrounding the third reverse pin junction 60C in plan view. The isolation region 65 may not include a portion surrounding the fourth reverse pin junction 60D in plan view.

[0377] In each embodiment, the size of the wiring 90 can be changed arbitrarily. For example, the area of ​​the wiring 90 in a plan view may be less than 75% of the area of ​​the isolation region 65 in a plan view. For example, the area of ​​the wiring 90 in a plan view may be greater than 97% of the area of ​​the isolation region 65 in a plan view. For example, the area of ​​the wiring 90 in a plan view may be equal to or greater than the area of ​​the isolation region 65 in a plan view. For example, the area of ​​the wiring 90 in a plan view may be equal to or smaller than the area of ​​the first connection electrode 81 in a plan view. The area of ​​the wiring 90 in a plan view may be equal to or smaller than the area of ​​the second connection electrode 82 in a plan view.

[0378] In the first to third embodiments, the shape of the wiring 90 in plan view can be changed as desired. For example, the wiring 90 does not have to partially surround at least one of the first connection electrode 81 and the second connection electrode 82 in plan view.

[0379] In the fourth embodiment, the shape of the wiring 90 in plan view can be changed as desired. For example, the wiring 90 is provided in a region overlapping the outer periphery of the isolation region 65 in plan view, and may not be provided in at least one of the areas between the first reverse pin junction 60A and the second reverse pin junction 60B and the area between the second reverse pin junction 60B and the third reverse pin junction 60C. For another example, the wiring 90 may be provided only between the first reverse pin junction 60A and the second reverse pin junction 60B and the area between the second reverse pin junction 60B and the third reverse pin junction 60C.

[0380] In the fifth embodiment, the shape of the wiring 90 in a plan view can be changed as desired. For example, the wiring 90 may be provided in a region that overlaps with the outer periphery of the separation region 65 in a plan view, but may not be provided in a portion that overlaps with the first connection region 67A. For another example, the wiring 90 may be provided only in a portion that overlaps with the first connection region 67A.

[0381] In the sixth embodiment, the shape of the wiring 90 in plan view can be changed as desired. For example, the wiring 90 may be provided in a region that overlaps the outer periphery of the isolation region 65 in plan view, and may not be provided between the first reverse pin junction 60A and the second reverse pin junction 60B. For another example, the wiring 90 may be provided only between the first reverse pin junction 60A and the second reverse pin junction 60B.

[0382] In the seventh embodiment, the shape of the wiring 90 in plan view can be changed as desired. For example, the wiring 90 may be provided in a region overlapping the outer periphery of the separation region 65 in plan view, but may not be provided in at least one of the regions overlapping with the first to third connection regions 67A to 67C. For another example, the wiring 90 may be provided only in the region overlapping with the first to third connection regions 67A to 67C in plan view. For another example, the wiring 90 may be provided only in the region overlapping with the first connection region 67A and the region overlapping with the second connection region 67B in plan view. For another example, the wiring 90 may be provided only in the region overlapping with the second connection region 67B and the region overlapping with the third connection region 67C in plan view. For another example, the wiring 90 may be provided only in the region overlapping with the first connection region 67A and the region overlapping with the third connection region 67C in plan view. In another example, the wiring 90 may be provided only in one of the regions that overlap with the first to third connection regions 67A to 67C in a plan view.

[0383] In the eighth embodiment, the wiring 90 is provided in a region that overlaps the outer periphery of the isolation region 65 in a plan view, and does not have to be provided in the center of the isolation region 65. In one example, the wiring 90 may be provided only in the center of the isolation region 65.

[0384] In each embodiment, the wiring 90 may be omitted from the TVS diode 10. FIG. 59 schematically shows a planar structure in which the wiring 90 is omitted from the TVS diode 10 of the first embodiment. FIG. 60 schematically shows a cross-sectional structure of the TVS diode 10 taken along line F60-F60 in FIG. 59. As shown in FIG. 59, a protective layer 74 is provided between the first to third connection electrodes 81 to 83. Therefore, as shown in FIG. 60, the separation region 65 of the diode pair region 60 is covered with the insulating layer 70. The separation region 65 is in contact with the insulating layer 70.

[0385] In each embodiment, a structure in which the conductivity types of the semiconductor chip 20 are reversed may be adopted. That is, a p-type region may be an n-type region, and an n-type region may be a p-type region. In this case, the p-type is an example of the "first conductivity type," and the n-type is an example of the "second conductivity type."

[0386] As long as the outer edge of the internal region 64 is located inward from the outer edge of the high-concentration region 61 in plan view, the TVS diode 10 may have a configuration that includes, for example, the first pin junction 30 and the diode pair region 60 including the first reverse pin junction 60A and the pn junction 60E, but does not include the second pin junction 40, the third pin junction 50, the fourth pin junction 130, the second reverse pin junction 60B, the third reverse pin junction 60C, and the fourth reverse pin junction 60D.

[0387] In each embodiment, the TVS diode 10 may include terminals for mounting the TVS diode 10 on, for example, a circuit board. An example of a TVS diode 10 including terminals is shown in FIGS. 61 to 63. FIG. 61 schematically shows the planar structure of a modified TVS diode 10. FIG. 62 schematically shows the cross-sectional structure of the TVS diode 10 taken along line F62-F62 in FIG. 61. FIG. 63 schematically shows the cross-sectional structure of the TVS diode 10 taken along line F63-F63 in FIG. 61.

[0388] As shown in FIGS. 61 to 63, the TVS diode 10 includes a first terminal 101, a second terminal 102, and a third terminal 103 provided on the protective layer 74. 61, the first terminal 101, the second terminal 102, and the third terminal 103 are arranged spaced apart from each other. More specifically, the first terminal 101 and the third terminal 103 are arranged at the same position in the Y direction and spaced apart from each other in the X direction. The first terminal 101 and the third terminal 103 are arranged closer to the fourth side surface 20D than the center in the Y direction of the first surface 20S of the semiconductor chip 20. The first terminal 101 is arranged closer to the first side surface 20A than the center in the X direction of the first surface 20S. The third terminal 103 is arranged closer to the second side surface 20B than the center in the X direction of the first surface 20S.

[0389] The second terminal 102 is disposed at a different position in the X direction and the Y direction from both the first terminal 101 and the third terminal 103. The second terminal 102 is disposed closer to the third side surface 20C than the center in the Y direction of the first surface 20S of the semiconductor chip 20. The second terminal 102 is disposed at the center in the X direction of the first surface 20S. Therefore, when viewed from the Y direction, it can be said that the second terminal 102 is disposed between the first terminal 101 and the third terminal 103 in the X direction.

[0390] 62 and 63, the first terminal 101 is provided at a position overlapping the first pin joint 30 in a plan view. The second terminal 102 is provided at a position overlapping the second pin joint 40 in a plan view. The third terminal 103 is provided at a position overlapping the third pin joint 50 in a plan view.

[0391] The first terminal 101 is provided at a position overlapping the pin connection portion 81A of the first connection electrode 81 in a plan view. The second terminal 102 is provided at a position overlapping the pin connection portion 82A of the second connection electrode 82 in a plan view. The third terminal 103 is provided at a position overlapping the pin connection portion 83A of the third connection electrode 83 in a plan view.

[0392] The first terminal 101 is electrically connected to the first connection electrode 81 through the first terminal opening 77A. The first terminal 101 includes a first contact portion 101A that is provided within the first terminal opening 77A and that contacts the first connection electrode 81, and a first mounting portion 101B that is provided on the protective layer 74. In one example, the first contact portion 101A and the first mounting portion 101B are integrated.

[0393] The second terminal 102 is electrically connected to the second connection electrode 82 through the second terminal opening 77B. The second terminal 102 includes a second contact portion 102A that is provided in the second terminal opening 77B and that contacts the second connection electrode 82, and a second mounting portion 102B that is provided on the protective layer 74. In one example, the second contact portion 102A and the second mounting portion 102B are integrated.

[0394] The third terminal 103 is electrically connected to the third connection electrode 83 through the third terminal opening 77C. The third terminal 103 includes a third contact portion 103A that is provided within the third terminal opening 77C and that contacts the third connection electrode 83, and a third mounting portion 103B that is provided on the protective layer 74. In one example, the third contact portion 103A and the third mounting portion 103B are integrated.

[0395] Each of the first to third terminals 101 to 103 has a laminated structure including, for example, a Ni (nickel) layer, a Pd (palladium) layer, and an Au (gold) layer laminated in this order from the first surface 20S side of the semiconductor chip 20.

[0396] In the fifth and sixth embodiments, the TVS diode 10 may include a first terminal 101 and a second terminal 102, similar to the examples shown in Figures 61 to 63. In the seventh and eighth embodiments, the TVS diode 10 may include a first terminal 101, a second terminal 102, a third terminal 103, and a fourth terminal, similar to the examples shown in Figures 61 to 63.

[0397] One or more of the various examples described in the present disclosure may be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0398] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described in this disclosure being "up" and "down" of the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0399] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0400] [Appendix A1] A semiconductor chip (20) having a first surface (20S) and a second surface (20R) opposite to the first surface (20S), The semiconductor chip (20) a first pin joint portion (30) in a first polarity direction provided near the first surface (20S) of the semiconductor chip (20); a second pin joint (40) in a first polarity direction, which is arranged at a position spaced apart from the first pin joint (30) in a plan view seen from the thickness direction (Z) of the semiconductor chip (20) in a region of the semiconductor chip (20) close to the first surface (20S); a diode pair region (60) provided apart from both the first pin junction (30) and the second pin junction (40) in the plan view; Including, The diode pair region (60) a first conductivity type high concentration region (61) provided at a distance from the first surface (20S) of the semiconductor chip (20) toward the second surface (20R); a first low concentration region (62A) and a second low concentration region (62B) of a first conductivity type that are spaced apart from each other and have an impurity concentration lower than that of the high concentration region (61), in a region closer to the first surface (20S) than the high concentration region (61) and that overlap the high concentration region (61) in the plan view; a separation region (65) that is provided in a region closer to the first surface (20S) than the high-concentration region (61) and overlaps with the high-concentration region (61) in the planar view, and separates the first low-concentration region (62A) and the second low-concentration region (62B); a first contact region (63A) of a second conductivity type provided in a surface layer portion of the first low concentration region (62A); a second contact region (63B) of a second conductivity type provided in a surface layer portion of the second low concentration region (62B); an internal region (64) of a second conductivity type that is in contact with the high concentration region (61) at a position that overlaps the high concentration region (61) in the plan view and is closer to the second surface (20R) than the high concentration region (61); Including, a first reverse pin junction (60A) in a second polarity direction is formed by the high concentration region (61), the first low concentration region (62A), and the first contact region (63A); a second reverse pin junction (60B) in a second polarity direction is formed by the high concentration region (61), the second low concentration region (62B), and the second contact region (63B); a pn junction (60E) of a first polarity direction is configured by the high concentration region (61) and the internal region (64) so ​​as to be reversely connected to the first reverse pn junction (60A) and the second reverse pn junction (60B); The inner region (64) is provided so as to overlap both the first low-concentration region (62A) and the second low-concentration region (62B) in the plan view. TVS diode (10).

[0401] [Appendix A2] a first polarity direction is a direction in which a forward current flows from the second surface (20R) to the first surface (20S) in the thickness direction (Z) of the semiconductor chip (20); The second polarity direction is a direction in which a forward current flows in the thickness direction (Z) of the semiconductor chip (20), which is opposite to the first polarity direction. TVS diodes as described in Appendix A1.

[0402] [Appendix A3] the separation region (65) includes an exposed surface (65S) exposed from the first surface (20S), and wiring (90) in contact with the exposed surface (65S). TVS diodes as described in Appendix A1 or A2.

[0403] [Appendix A4] The semiconductor chip (20) a second conductivity type first terminal side high concentration region (31) provided at a distance from the first surface (20S) of the semiconductor chip (20) toward the second surface (20R); a first-terminal-side low-concentration region (32) of a first conductivity type provided at a position overlapping the first-terminal-side high-concentration region (31) in the plan view in a region closer to the first surface (20S) than the first-terminal-side high-concentration region (31); a first terminal side contact region (33) of a first conductivity type provided in a surface layer portion of the first terminal side low concentration region (32); a first partition region (34) that is provided in a region closer to the first surface (20S) than the first terminal side high concentration region (31) and that overlaps with the first terminal side high concentration region (31) in the plan view and that surrounds the first terminal side low concentration region (32); a second-terminal-side high-concentration region (41) of a second conductivity type provided at a position spaced from the first surface (20S) of the semiconductor chip (20) toward the second surface (20R) and spaced from the first-terminal-side high-concentration region (31) in the plan view; a second terminal side low concentration region (42) of a first conductivity type provided at a position overlapping the second terminal side high concentration region (41) in the plan view in a region closer to the first surface (20S) than the second terminal side high concentration region (41); a second terminal side contact region (43) of the first conductivity type provided in a surface layer portion of the second terminal side low concentration region (42); a second partition region (44) that is provided in a region closer to the first surface (20S) than the second terminal side high concentration region (41) and that overlaps with the second terminal side high concentration region (41) in the plan view and that surrounds the second terminal side low concentration region (42); Including, the first terminal side high concentration region (31), the first terminal side low concentration region (32), and the first terminal side contact region (33) form the first pin junction (30); The second terminal side high concentration region (41), the second terminal side low concentration region (42), and the second terminal side contact region (43) form the second pin junction (40). TVS diodes as described in Appendix A3.

[0404] [Appendix A5] an insulating layer (70) covering the first surface (20S); a first connection electrode (81) provided on the insulating layer (70) and connecting the first contact region (63A) and the first terminal side contact region (33); a second connection electrode (82) provided on the insulating layer (70) and connecting the second contact region (63B) and the second terminal side contact region (43); Contains TVS diodes as described in Appendix A4.

[0405] [Appendix A6] The separation region (65) a first separation region (65A) overlapping the first connection electrode (81) in the plan view; a second isolation region (65B) overlapping the second connection electrode (82) in the plan view; a wiring connection area (65P) to which the wiring (90) is connected; Including, The wiring connection region (65P) is provided so as to individually and partially surround both the first reverse pin junction (60A) and the second reverse pin junction (60B) in the plan view. TVS diodes as described in Appendix A5.

[0406] [Appendix A7] The wiring (90) is provided so as to partially surround both the first connection electrode (81) and the second connection electrode (82) individually in the plan view. TVS diodes as described in Appendix A6.

[0407] [Appendix A8] The area of ​​the wiring (90) in the plan view is larger than the area of ​​the first connection electrode (81) in the plan view. TVS diodes as described in Appendix A6 or A7.

[0408] [Appendix A9] The area of ​​the wiring (90) in the plan view is smaller than the area of ​​the isolation region (65) in the plan view. A TVS diode according to any one of appendices A5 to A8.

[0409] [Appendix A10] The area of ​​the wiring (90) in the plan view is 75% or more and 97% or less of the area of ​​the separation region (65) in the plan view. TVS diodes as described in Appendix A9.

[0410] [Appendix A11] a protective layer (74) covering the first connection electrode (81) and the second connection electrode (82); a first terminal (101) provided on the protective layer (74) and electrically connected to the first pin joint (30); a second terminal (102) provided on the protective layer (74) and electrically connected to the second pin joint (40); Including, The protective layer (74) a first terminal opening (77A) that partially exposes the first connection electrode (81); a second terminal opening (77B) that partially exposes the second connection electrode (82); Including, the first terminal (101) is electrically connected to the first connection electrode (81) through the first terminal opening (77A); The second terminal (102) is electrically connected to the second connection electrode (82) through the second terminal opening (77B). A TVS diode according to any one of appendices A5 to A10.

[0411] [Appendix A12] The outer edge of the inner region (64) is located inward from the outer edge of the high-concentration region (61) in the plan view. A TVS diode according to any one of appendices A1 to A11.

[0412] [Appendix A13] In the plan view, the outer edge of the internal region (64) includes a plurality of corner portions, Each of the plurality of corner portions is curved in the plan view. TVS diodes as described in Appendix A12.

[0413] [Appendix A14] In the plan view, the outer edge of the internal region (64) is disposed at a position overlapping with the separation region (65). TVS diodes as described in Appendix A12 or A13.

[0414] [Appendix A15] The semiconductor chip (20) a second conductivity type first terminal side high concentration region (31) provided at a distance from the first surface (20S) of the semiconductor chip (20) toward the second surface (20R); a first-terminal-side low-concentration region (32) of a first conductivity type provided at a position overlapping the first-terminal-side high-concentration region (31) in the plan view in a region closer to the first surface (20S) than the first-terminal-side high-concentration region (31); a first terminal side contact region (33) of a first conductivity type provided in a surface layer portion of the first terminal side low concentration region (32); a first isolation trench (121A) provided in the first surface (20S) so as to surround the first terminal side high concentration region (31), the first terminal side low concentration region (32), and the first terminal side contact region (33); a second-terminal-side high-concentration region (41) of a second conductivity type provided at a position spaced from the first surface (20S) of the semiconductor chip (20) toward the second surface (20R) and spaced from the first-terminal-side high-concentration region (31) in the plan view; a second terminal side low concentration region (42) of a first conductivity type provided at a position overlapping the second terminal side high concentration region (41) in the plan view in a region closer to the first surface (20S) than the second terminal side high concentration region (41); a second terminal side contact region (43) of the first conductivity type provided in a surface layer portion of the second terminal side low concentration region (42); a second isolation trench (121B) provided in the first surface (20S) so as to surround the second terminal side high concentration region (41), the second terminal side low concentration region (42), and the second terminal side contact region (43); Including, the first terminal side high concentration region (31), the first terminal side low concentration region (32), and the first terminal side contact region (33) form the first pin junction (30); The second terminal side high concentration region (41), the second terminal side low concentration region (42), and the second terminal side contact region (43) form the second pin junction (40). A TVS diode according to any one of appendices A1 to A3.

[0415] [Appendix A16] The semiconductor chip (20) a first isolation insulating layer (122A) provided in the first isolation trench (121A); a second isolation insulating layer (122B) provided in the second isolation trench (121B); Contains TVS diodes as described in Appendix A15.

[0416] [Appendix A17] a first isolation electrode (123A) embedded in the first isolation trench (121A) with the first isolation insulating layer (122A) interposed therebetween; a second isolation electrode (123B) embedded in the second isolation trench (121B) with the second isolation insulating layer (122B) interposed therebetween; Including, Both the first separated electrode (123A) and the second separated electrode (123B) are in an electrically floating state. TVS diodes as described in Appendix A16.

[0417] [Appendix A18] The high concentration region (61) includes a region adjacent to at least one of the first isolation trench (121A) and the second isolation trench (121B) in the plan view. A TVS diode according to any one of appendices A15 to A17.

[0418] [Appendix A19] a third pin joint (50) in a first polarity direction that is arranged at a position spaced apart from both the first pin joint (30) and the second pin joint (40) in the plan view in an area of ​​the semiconductor chip (20) close to the first surface (20S), The diode pair region (60) a third low concentration region (62C) of a first conductivity type, which has an impurity concentration lower than that of the high concentration region (61), and which is provided at a position overlapping with the high concentration region (61) in the plan view in a region closer to the first surface (20S) than the high concentration region (61), and which is spaced apart from both the first low concentration region (62A) and the second low concentration region (62B); a third contact region (63C) of the second conductivity type provided in a surface layer portion of the third low concentration region (62C); Including, the separation region (65) separates the first low-concentration region (62A) and the second low-concentration region (62B) from the third low-concentration region (62C); a third reverse pin junction (60C) in a second polarity direction is configured by the high concentration region (61), the third low concentration region (62C), and the third contact region (63C), the pn junction (60E) is configured to be reverse-connected to the third reverse pin junction (60C); The internal region (64) is provided so as to overlap the first low-concentration region (62A), the second low-concentration region (62B), and the third low-concentration region (62C) in the plan view. A TVS diode according to any one of appendices A1 to A3.

[0419] [Appendix A20] The semiconductor chip (20) a second conductivity type first terminal side high concentration region (31) provided at a distance from the first surface (20S) of the semiconductor chip (20) toward the second surface (20R); a first-terminal-side low-concentration region (32) of a first conductivity type provided at a position overlapping the first-terminal-side high-concentration region (31) in the plan view in a region closer to the first surface (20S) than the first-terminal-side high-concentration region (31); a first terminal side contact region (33) of a first conductivity type provided in a surface layer portion of the first terminal side low concentration region (32); a first partition region (34) that is provided in a region closer to the first surface (20S) than the first terminal side high concentration region (31) and that overlaps with the first terminal side high concentration region (31) in the plan view and that surrounds the first terminal side low concentration region (32); a second-terminal-side high-concentration region (41) of a second conductivity type provided at a position spaced from the first surface (20S) of the semiconductor chip (20) toward the second surface (20R) and spaced from the first-terminal-side high-concentration region (31) in the plan view; a second terminal side low concentration region (42) of a first conductivity type provided at a position overlapping the second terminal side high concentration region (41) in the plan view in a region closer to the first surface (20S) than the second terminal side high concentration region (41); a second terminal side contact region (43) of the first conductivity type provided in a surface layer portion of the second terminal side low concentration region (42); a second partition region (44) that is provided in a region closer to the first surface (20S) than the second terminal side high concentration region (41) and that overlaps with the second terminal side high concentration region (41) in the plan view and that surrounds the second terminal side low concentration region (42); a third-terminal-side high-concentration region (51) of a second conductivity type provided at a position spaced from the first surface (20S) of the semiconductor chip (20) toward the second surface (20R) and spaced from both the first-terminal-side high-concentration region (31) and the second-terminal-side high-concentration region (41) in the plan view; a third terminal side low concentration region (52) of the first conductivity type provided at a position overlapping the third terminal side high concentration region (51) in the plan view in a region closer to the first surface (20S) than the third terminal side high concentration region (51); a third terminal side contact region (53) of the first conductivity type provided in a surface layer portion of the third terminal side low concentration region (52); a third partition region (54) that is provided in a region closer to the first surface (20S) than the third terminal side high concentration region (51) and that overlaps with the third terminal side high concentration region (51) in the plan view and that surrounds the third terminal side low concentration region (52); Including, the first terminal side high concentration region (31), the first terminal side low concentration region (32), and the first terminal side contact region (33) form the first pin junction (30); the second terminal side high concentration region (41), the second terminal side low concentration region (42), and the second terminal side contact region (43) form the second pin junction (40); The third terminal side high concentration region (51), the third terminal side low concentration region (52), and the third terminal side contact region (53) form the third pin junction (50). TVS diodes as described in Appendix A19.

[0420] [Appendix A21] an insulating layer (70) covering the first surface (20S); a first connection electrode (81) provided on the insulating layer (70) and connecting the first contact region (63A) and the first terminal side contact region (33); a second connection electrode (82) provided on the insulating layer (70) and connecting the second contact region (63B) and the second terminal side contact region (43); a third connection electrode (83) provided on the insulating layer (70) and connecting the third contact region (63C) and the third terminal side contact region (53); Contains TVS diodes as described in Appendix A20.

[0421] [Appendix A22] the separation region (65) includes an exposed surface (65S) exposed from the first surface (20S), a wiring (90) in contact with the exposed surface (65S); The separation region (65) a first separation region (65A) overlapping the first connection electrode (81) in the plan view; a second isolation region (65B) overlapping the second connection electrode (82) in the plan view; a third isolation region (65C) overlapping the third connection electrode (83) in the plan view; a wiring connection area (65P) to which the wiring (90) is connected; Including, The wiring connection region (65P) is provided so as to partially surround each of the first reverse pin junction (60A), the second reverse pin junction (60B), and the third reverse pin junction (60C) individually in the plan view. TVS diodes as described in Appendix A21.

[0422] [Appendix A23] The wiring (90) is provided so as to partially surround each of the first connection electrode (81), the second connection electrode (82), and the third connection electrode (83) individually in the plan view. TVS diodes as described in Appendix A22.

[0423] [Appendix A24] The semiconductor chip (20) a second conductivity type first terminal side high concentration region (31) provided at a distance from the first surface (20S) of the semiconductor chip (20) toward the second surface (20R); a first-terminal-side low-concentration region (32) of a first conductivity type provided at a position overlapping the first-terminal-side high-concentration region (31) in the plan view in a region closer to the first surface (20S) than the first-terminal-side high-concentration region (31); a first terminal side contact region (33) of a first conductivity type provided in a surface layer portion of the first terminal side low concentration region (32); a first isolation trench (121A) provided in the first surface (20S) so as to surround the first terminal side high concentration region (31), the first terminal side low concentration region (32), and the first terminal side contact region (33); a second-terminal-side high-concentration region (41) of a second conductivity type provided at a position spaced from the first surface (20S) of the semiconductor chip (20) toward the second surface (20R) and spaced from the first-terminal-side high-concentration region (31) in the plan view; a second terminal side low concentration region (42) of a first conductivity type provided at a position overlapping the second terminal side high concentration region (41) in the plan view in a region closer to the first surface (20S) than the second terminal side high concentration region (41); a second terminal side contact region (43) of the first conductivity type provided in a surface layer portion of the second terminal side low concentration region (42); a second isolation trench (121B) provided in the first surface (20S) so as to surround the second terminal side high concentration region (41), the second terminal side low concentration region (42), and the second terminal side contact region (43); a third-terminal-side high-concentration region (51) of a second conductivity type provided at a position spaced from the first surface (20S) of the semiconductor chip (20) toward the second surface (20R) and spaced from both the first-terminal-side high-concentration region (31) and the second-terminal-side high-concentration region (41) in the plan view; a third terminal side low concentration region (52) of the first conductivity type provided at a position overlapping the third terminal side high concentration region (51) in the plan view in a region closer to the first surface (20S) than the third terminal side high concentration region (51); a third terminal side contact region (53) of the first conductivity type provided in a surface layer portion of the third terminal side low concentration region (52); a third isolation trench (121C) provided in the first surface (20S) so as to surround the third terminal side high concentration region (51), the third terminal side low concentration region (52), and the third terminal side contact region (53); Including, the first terminal side high concentration region (31), the first terminal side low concentration region (32), and the first terminal side contact region (33) form the first pin junction (30); the second terminal side high concentration region (41), the second terminal side low concentration region (42), and the second terminal side contact region (43) form the second pin junction (40); The third terminal side high concentration region (51), the third terminal side low concentration region (52), and the third terminal side contact region (53) constitute the second pin junction (50). TVS diodes as described in Appendix A19.

[0424] [Appendix A25] The semiconductor chip (20) a first isolation insulating layer (122A) provided in the first isolation trench (121A); a second isolation insulating layer (122B) provided in the second isolation trench (121B); a third isolation insulating layer (122C) provided in the third isolation trench (121C); Contains TVS diodes as described in Appendix A24.

[0425] [Appendix A26] a first isolation electrode (123A) embedded in the first isolation trench (121A) with the first isolation insulating layer (122A) interposed therebetween; a second isolation electrode (123B) embedded in the second isolation trench (121B) with the second isolation insulating layer (122B) interposed therebetween; a third isolation electrode (123C) embedded in the third isolation trench (121C) with the third isolation insulating layer (122C) interposed therebetween; Including, Each of the first separated electrode (123A), the second separated electrode (123B), and the third separated electrode (123C) is in an electrically floating state. TVS diodes as described in Appendix A25.

[0426] [Appendix A27] a fourth pin joint (130) in a first polarity direction that is arranged at a position spaced apart from each of the first pin joint (30), the second pin joint (40), and the third pin joint (50) in the plan view in an area of ​​the semiconductor chip (20) close to the first surface (20S), The diode pair region (60) a fourth low concentration region (62D) of a first conductivity type, which has an impurity concentration lower than that of the high concentration region (61), and which is provided at a position overlapping with the high concentration region (61) in the plan view in a region closer to the first surface (20S) than the high concentration region (61) and spaced apart from each of the first low concentration region (62A), the second low concentration region (62B), and the third low concentration region (62C); a fourth contact region (63D) of the second conductivity type provided in a surface layer portion of the fourth low concentration region (62D); Including, the separation region (65) separates the first low-concentration region (62A), the second low-concentration region (62B), the third low-concentration region (62C), and the fourth low-concentration region (62D), a fourth reverse pin junction (60D) in a second polarity direction is configured by the high concentration region (61), the fourth low concentration region (62D), and the fourth contact region (63D), the pn junction (60E) is configured to be reverse-connected to the fourth reverse pn junction (130); The internal region (64) is provided so as to overlap the first low-concentration region (62A), the second low-concentration region (62B), the third low-concentration region (62C), and the fourth low-concentration region (62D) in the plan view. TVS diodes as described in Appendix A19.

[0427] [Appendix A28] The semiconductor chip (20) a second conductivity type first terminal side high concentration region (31) provided at a distance from the first surface (20S) of the semiconductor chip (20) toward the second surface (20R); a first-terminal-side low-concentration region (32) of a first conductivity type provided at a position overlapping the first-terminal-side high-concentration region (31) in the plan view in a region closer to the first surface (20S) than the first-terminal-side high-concentration region (31); a first terminal side contact region (33) of a first conductivity type provided in a surface layer portion of the first terminal side low concentration region (32); a first partition region (34) that is provided in a region closer to the first surface (20S) than the first terminal side high concentration region (31) and that overlaps with the first terminal side high concentration region (31) in the plan view and that surrounds the first terminal side low concentration region (32); a second-terminal-side high-concentration region (41) of a second conductivity type provided at a position spaced from the first surface (20S) of the semiconductor chip (20) toward the second surface (20R) and spaced from the first-terminal-side high-concentration region (31) in the plan view; a second terminal side low concentration region (42) of a first conductivity type provided at a position overlapping the second terminal side high concentration region (41) in the plan view in a region closer to the first surface (20S) than the second terminal side high concentration region (41); a second terminal side contact region (43) of the first conductivity type provided in a surface layer portion of the second terminal side low concentration region (42); a second partition region (44) that is provided in a region closer to the first surface (20S) than the second terminal side high concentration region (41) and that overlaps with the second terminal side high concentration region (41) in the plan view and that surrounds the second terminal side low concentration region (42); a third-terminal-side high-concentration region (51) of a second conductivity type provided at a position spaced from the first surface (20S) of the semiconductor chip (20) toward the second surface (20R) and spaced from both the first-terminal-side hig...

Claims

1. a semiconductor chip having a first surface and a second surface opposite the first surface; The semiconductor chip comprises: a first pin junction portion in a first polarity direction provided in a region near the first surface of the semiconductor chip; a diode pair region including a first reverse pin junction in a second polarity direction provided apart from the first pin junction in a plan view seen from the thickness direction of the semiconductor chip, and a pn junction in a first polarity direction that forms a diode pair together with the first reverse pin junction; a first terminal side high concentration region of a second conductivity type provided at a distance from the first surface toward the second surface of the semiconductor chip; a first terminal side low concentration region of a first conductivity type provided in a region closer to the first surface than the first terminal side high concentration region and at a position overlapping the first terminal side high concentration region in the plan view; a first terminal side contact region of a first conductivity type provided in a surface layer portion of the first terminal side low concentration region; a first buffer region of a second conductivity type that is in contact with the first terminal side heavily doped region and is located between the first terminal side heavily doped region and the first terminal side lightly doped region in a thickness direction of the semiconductor chip; Including, The first terminal side contact region, the first terminal side low concentration region, and the first buffer region form a pin diode. TVS diode.

2. the semiconductor chip includes a first partitioned region that is located in a region closer to the first surface than the first terminal side high concentration region and that is positioned to overlap the first terminal side high concentration region in the plan view and surround the first terminal side low concentration region, The first partitioned region is provided so as to surround the first buffer region in the plan view. The TVS diode of claim 1 .

3. The first buffer region has a second conductivity type impurity concentration lower than that of the first terminal side high concentration region. The TVS diode of claim 1 .

4. The second conductivity type impurity concentration of the first buffer region decreases from the first terminal side high concentration region toward the first terminal side low concentration region in the thickness direction of the semiconductor chip. The TVS diode of claim 1 .

5. The second conductivity type impurity concentration of the first buffer region is equal to or higher than the first conductivity type impurity concentration of the first terminal side low concentration region. The TVS diode of claim 3 .

6. The diode pair region includes: a first conductivity type high concentration region provided at a distance from the first surface toward the second surface of the semiconductor chip; a first low concentration region of a first conductivity type that is located closer to the first surface than the high concentration region and that is spaced apart from the high concentration region in the plan view and has an impurity concentration lower than that of the high concentration region; a first contact region of a second conductivity type provided in a surface layer portion of the first low concentration region; an internal region of a second conductivity type that is in contact with the high concentration region at a position that overlaps the high concentration region in the plan view and is closer to the second surface than the high concentration region; Including, the first reverse pin junction is formed by the high concentration region, the first low concentration region, and the first contact region; The high concentration region and the internal region form the pn junction that is reversely connected to the first reverse pin junction. The TVS diode of claim 1 .

7. The semiconductor chip comprises: a second pin junction portion in a first polarity direction provided at a position spaced apart from the first pin junction portion in the plan view in a region close to the first surface of the semiconductor chip; a second terminal side heavily doped region of a second conductivity type provided at a position spaced from the first surface toward the second surface of the semiconductor chip and spaced from the first terminal side heavily doped region in the plan view; a second terminal side low concentration region of the first conductivity type provided in a region closer to the first surface than the second terminal side high concentration region and at a position overlapping the second terminal side high concentration region in the plan view; a second terminal side contact region of a first conductivity type provided in a surface layer portion of the second terminal side low concentration region; a second buffer region of a second conductivity type that is in contact with the second terminal side heavily doped region and is located between the second terminal side heavily doped region and the second terminal side lightly doped region in a thickness direction of the semiconductor chip; Including, The second pin junction is formed by the second buffer region, the second terminal side low concentration region, and the second terminal side contact region. The TVS diode of claim 1 .

8. the semiconductor chip includes a second partitioned region that is located in a region closer to the first surface than the second terminal side high concentration region and that is positioned to overlap the second terminal side high concentration region in the plan view and surround the second terminal side low concentration region, The second partitioned area is provided so as to surround the second buffer area in the plan view. The TVS diode of claim 7.

9. The second buffer region has a second conductivity type impurity concentration lower than that of the second terminal side high concentration region. The TVS diode of claim 7.

10. The second conductivity type impurity concentration of the second buffer region decreases from the second terminal side high concentration region toward the second terminal side low concentration region in the thickness direction of the semiconductor chip. The TVS diode of claim 7.

11. The second buffer region has a second conductivity type impurity concentration equal to or higher than the first conductivity type impurity concentration of the second terminal side low concentration region. The TVS diode of claim 9.

12. The diode pair region includes: a second reverse pin junction in a second polarity direction that configures the pn junction and the diode pair; a first conductivity type high concentration region provided at a distance from the first surface toward the second surface of the semiconductor chip; a first low concentration region and a second low concentration region of a first conductivity type that are spaced apart from each other and have an impurity concentration lower than that of the high concentration region, the first low concentration region and the second low concentration region being located in a region closer to the first surface than the high concentration region in the plan view and overlapping with the high concentration region; an isolation region that is provided in a region closer to the first surface than the high concentration region and overlaps the high concentration region in the plan view, and that electrically isolates the first low concentration region from the second low concentration region; a first contact region of a second conductivity type provided in a surface layer portion of the first low concentration region; a second contact region of a second conductivity type provided in a surface layer portion of the second low concentration region; an internal region of a second conductivity type that is in contact with the high concentration region at a position that overlaps the high concentration region in the plan view and is closer to the second surface than the high concentration region; Including, the first reverse pin junction is formed by the high concentration region, the first low concentration region, and the first contact region; the high concentration region, the second low concentration region, and the second contact region form the second reverse pin junction; The high concentration region and the internal region form the pn junction that is reversely connected to the first reverse pin junction and the second reverse pin junction. The TVS diode of claim 7.

13. In the plan view, the outer edge of the internal region is located inward from the outer edge of the high-concentration region. The TVS diode of claim 12.

14. In the plan view, an outer edge of the internal region is disposed at a position overlapping with the separation region.

14. The TVS diode of claim 13.

15. In the plan view, an outer edge of the internal region includes a plurality of corner portions, Each of the plurality of corner portions is curved in the plan view. The TVS diode of claim 12.

16. The semiconductor chip comprises: a first isolation trench in the first surface to separate the first pin junction from the diode pair region; a second isolation trench in the first surface to separate the second pin junction from the diode pair region; Contains The TVS diode of claim 7.

17. a first isolation insulating layer provided in the first isolation trench; a second isolation insulating layer provided in the second isolation trench; Contains 17. The TVS diode of claim 16.

18. a first isolation electrode embedded in the first isolation trench with the first isolation insulating layer interposed therebetween; a second isolation electrode embedded in the second isolation trench with the second isolation insulating layer interposed therebetween; Including, Both the first isolation electrode and the second isolation electrode are in an electrically floating state.

18. The TVS diode of claim 17.

19. a first polarity direction is a direction in which a forward current flows from the second surface to the first surface in a thickness direction of the semiconductor chip; The second polarity direction is a direction in which a forward current flows in the thickness direction of the semiconductor chip, the direction being opposite to the first polarity direction. The TVS diode of claim 1 .

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