Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method for forming the same, the semiconductor device comprising: a substrate, and a first reflective layer, a first contact layer, an active layer, a second contact layer and a second reflective layer located above the substrate; an insulating portion located between at least part of the first contact layer and at least part of the active layer, or between at least part of the second contact layer and at least part of the active layer, the insulating portion being in contact with the active layer; a first metal electrode located on a top surface of the first contact layer and outside the active layer; and a second metal electrode located on a top surface of the second contact layer and outside the second reflective layer, the insulating portion being located below the second metal electrode. The above scheme can shorten the current path between the metal electrodes during the operation of the semiconductor device, thereby reducing the heat generated by the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor device and a forming method thereof. BACKGROUND

[0002] The performance of a semiconductor device is often affected by temperature. In recent years, with the development of semiconductor technology, the heat requirement of semiconductor devices is becoming increasingly stringent. Taking a vertical-cavity surface-emitting laser (VCSEL) as an example, with the rise of 3D recognition, the VCSEL is increasingly widely used in the fields of face recognition, intelligent driving, augmented reality (AR) and the like, because the light spot emitted by the VCSEL can be circular and the emission is easier to be integrated into an array.

[0003] At present, a mainstream VCSEL chip mainly comprises an N-type distributed Bragg reflector (N-DBR) layer, a P-type distributed Bragg reflector (P-DBR) layer, a light-emitting hole (cavity) and an active layer (for example, a quantum well / barrier), a substrate and the like. The upper electrode (for example, a P electrode) of the VCSEL chip is usually located at the top surface of the chip, and the lower electrode (for example, an N electrode) is usually located at the back surface of the substrate of the chip.

[0004] When the VCSEL chip works, the P electrode is usually connected to a positive voltage, and the N electrode is usually connected to the ground. The current enters from the P electrode at the top surface of the VCSEL, passes through the P-DBR layer, the N-DBR layer and the substrate in sequence, and reaches the N electrode at the back surface of the substrate. In actual application, because the thicknesses of the N-DBR layer, the P-DBR layer and the substrate are all large, the current path is long, which often brings an unavoidable series resistance, thereby making the turn-on voltage of the VCSEL chip larger and causing a large device heat, which brings a reliability risk of the VCSEL chip. SUMMARY

[0005] The technical problem solved by the embodiments of the present application is how to make the current path between the metal electrodes shorter during the working process of the semiconductor device, so as to reduce the device heat.

[0006] To solve the above technical problems, the embodiment of the present application provides a semiconductor device, which specifically comprises: a substrate, and a first reflective layer, a first contact layer, an active layer, a second contact layer and a second reflective layer located above the substrate; an insulating part located between at least part of the first contact layer and at least part of the active layer, or located between at least part of the second contact layer and at least part of the active layer, the insulating part being in contact with the active layer; a first metal electrode located on the top surface of the first contact layer and on the outside of the active layer; and a second metal electrode located on the top surface of the second contact layer and on the outside of the second reflective layer, the insulating part being located below the second metal electrode.

[0007] Optionally, the semiconductor device further comprises: a conductive material layer located between the first contact layer and the active layer, or located between the second contact layer and the active layer, the insulating part being located on the outside of the conductive material layer.

[0008] Optionally, the material of the conductive material layer is Al x Ga (1-x) As, wherein x is the component of Al, and 0.8≤x<1.

[0009] Optionally, the insulating part is also located on the outside of part of the first contact layer and part of the active layer, or also located on the outside of part of the second contact layer and part of the active layer.

[0010] Optionally, the projection area of the second metal electrode on the substrate is located within the projection area of the insulating part on the substrate, and the projection area of the insulating part on the substrate is located within the projection area of the active layer on the substrate.

[0011] Optionally, the ratio between the distance between the top surface of the insulating part and the top surface of the second contact layer and the thickness of the second contact layer is within a second preset interval, and the ratio between the distance between the bottom surface of the insulating part and the bottom surface of the first contact layer and the thickness of the first contact layer is within a third preset interval.

[0012] Optionally, one or more of the following conditions is met: the second preset interval is 5% to 100%; and the third preset interval is 5% to 100%.

[0013] Optionally, the doping concentration of the first contact layer is greater than the doping concentration of the first reflective layer, and the doping concentration of the second contact layer is greater than the doping concentration of the second reflective layer.

[0014] Optionally, one or more of the following conditions is met: the doping concentration of the first contact layer is greater than or equal to 2e18 / cm 3The doping concentration of the second contact layer is greater than or equal to 2e18 / cm. 3 The doping concentration of the first reflective layer is less than or equal to 1e18 / cm. 3 The doping concentration of the second reflective layer is less than or equal to 1e18 / cm. 3 The doping concentration of the substrate is less than or equal to 1e18 / cm. 3 .

[0015] This invention also provides a method for forming a semiconductor device, specifically including: providing a substrate, forming a first reflective layer, a first contact layer, an active layer, a second contact layer, and a second reflective layer on the substrate; forming an insulating portion, the insulating portion being located between at least a portion of the first contact layer and at least a portion of the active layer, or between at least a portion of the second contact layer and at least a portion of the active layer, the insulating portion being in contact with the active layer; etching the second reflective layer to expose the top surface of the second contact layer; etching the second contact layer and the active layer to expose the top surface of the first contact layer; forming a second metal electrode on the top surface of the second contact layer, the insulating portion being located below the second metal electrode, the second metal electrode being located outside the second reflective layer; and forming a first metal electrode on the top surface of the first contact layer, the first metal electrode being located outside the active layer.

[0016] Optionally, the method further includes: forming a conductive material layer located between the first contact layer and the active layer, or between the second contact layer and the active layer; and forming the insulating portion based on a portion of the conductive material layer.

[0017] Optionally, the insulating portion is formed by oxidizing a portion of the conductive material layer after etching the second contact layer, the conductive material layer, and the active layer.

[0018] Optionally, the insulating portion is formed by ion implantation of the first contact layer and the active layer, or the second contact layer and the active layer.

[0019] Optionally, the method further includes: doping the first contact layer, the first reflective layer, the second contact layer, and the second reflective layer, wherein the doping concentration of the first contact layer is greater than the doping concentration of the first reflective layer, and the doping concentration of the second contact layer is greater than the doping concentration of the second reflective layer.

[0020] Optionally, one or more of the following conditions must be met: the doping concentration of the first contact layer is greater than or equal to 2e18 / cm3; the doping concentration of the second contact layer is greater than or equal to 2e18 / cm3; the doping concentration of the first reflective layer is less than or equal to 1e18 / cm3; the doping concentration of the second reflective layer is less than or equal to 1e18 / cm3; and the doping concentration of the substrate is less than or equal to 1e18 / cm3.

[0021] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0022] This invention provides a semiconductor device comprising: a substrate, and a first reflective layer, a first contact layer, an active layer, a second contact layer, and a second reflective layer located above the substrate; an insulating portion located between at least a portion of the first contact layer and at least a portion of the active layer, or between at least a portion of the second contact layer and at least a portion of the active layer, the insulating portion being in contact with the active layer; a first metal electrode located on the top surface of the first contact layer and outside the active layer; and a second metal electrode located on the top surface of the second contact layer and outside the second reflective layer, the insulating portion being located below the second metal electrode.

[0023] In this embodiment of the invention, when the semiconductor device is operating, the current between the first metal electrode and the second metal electrode does not flow through the relatively thick first reflective layer, the second reflective layer, and the substrate. The current path is significantly shortened, the resistance is reduced, and the turn-on voltage can be lowered, thereby effectively reducing device heat generation and improving device performance. Furthermore, by forming the insulating portion below the second metal electrode, the insulating portion region can block current, reducing light emission from the active region below the second metal electrode (because even if light is emitted, it will be blocked by the second metal electrode), thereby making the light emission from the active layer more concentrated.

[0024] Furthermore, in this embodiment of the invention, the projection area of ​​the second metal electrode on the substrate is located within the projection area of ​​the insulating portion on the substrate, and the projection area of ​​the insulating portion on the substrate is located within the projection area of ​​the active layer on the substrate. Thus, by utilizing the insulating effect of the insulating portion, the light emission from the active region below the second metal electrode can be further reduced, making the light emission of the active layer more concentrated. In practical applications, the projection areas of the second metal electrode and the insulating portion on the substrate can be designed to be located at the edge of the projection area of ​​the active layer on the substrate, thereby concentrating the light emission of the active layer in the central region.

[0025] Furthermore, in this embodiment of the invention, the ratio between the distance between the top surface of the insulating portion and the top surface of the second contact layer and the thickness of the second contact layer is within a second preset range; the ratio between the distance between the bottom surface of the insulating portion and the bottom surface of the first contact layer and the thickness of the first contact layer is within a third preset range. It can be understood that if the top surface of the insulating portion contacts the top surface of the second contact layer, it may directly block the current flow between the second metal electrode and the second contact layer. Correspondingly, if the bottom surface of the insulating portion contacts the bottom surface of the first contact layer, it may directly block the current flow between the first metal electrode and the first contact layer. Therefore, by setting the distance between the top surface of the insulating portion and the top surface of the second contact layer, and the distance between the bottom surface of the insulating portion and the bottom surface of the first contact layer, the adverse effects of the insulating portion on the conductivity of the semiconductor device can be avoided.

[0026] Furthermore, in this embodiment of the invention, the doping concentration of the first contact layer is greater than that of the first reflective layer, and the doping concentration of the second contact layer is greater than that of the second reflective layer. Since the first metal electrode and the second metal electrode are in contact with the first contact layer and the second contact layer, respectively, which have higher doping concentrations, a low-resistance ohmic contact can be formed between the metal electrode and the semiconductor material, improving conductivity. In addition, the first reflective layer, the second reflective layer, and the substrate can be configured with low doping concentrations. Because low doping concentrations result in higher thermal conductivity, the heat dissipation of the device can be improved. Attached Figure Description

[0027] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device in the prior art;

[0028] Figure 2 This is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention;

[0029] Figures 3 to 7 yes Figure 2 The diagram shows the cross-sectional views of the device corresponding to each step in the formation method. Detailed Implementation

[0030] As described in the background section, with the development of semiconductor technology, the requirements for the heat dissipation of semiconductor devices are becoming increasingly stringent.

[0031] Taking the current mainstream VCSEL chip as an example, the current flows through a long path between the metal electrodes during the operation of the VCSEL chip. The long current flow path will bring a series resistance that cannot be ignored, which will increase the turn-on voltage of the VCSEL chip and cause greater heat generation, thus posing a potential reliability risk to the VCSEL chip.

[0032] Reference Figure 1 , Figure 1 This is a cross-sectional schematic diagram of a semiconductor device in the prior art.

[0033] The semiconductor device may be a vertical-cavity surface-emitting laser (VCSEL), specifically including: a substrate 10 and an N-DBR layer 11, an active layer 12, a dielectric layer 13 and a P-DBR layer 14 formed layer by layer on the substrate 10, and may also include a first electrode layer 15 and a second electrode layer 16.

[0034] The first electrode layer 15 may include a P-type electrode, which may be located on the P-DBR layer 14. A gallium arsenide buffer layer (not shown) may also be present between the first electrode layer 15 and the P-DBR layer 14 to form a good ohmic contact with the first electrode layer 15. The second electrode layer 16 may include an N-type electrode, which may be located on the back side of the substrate 10. The dielectric layer 13 may be an oxide layer or an isolation layer formed by ion implantation. The dielectric layer 13 is typically used as an insulating layer. Oxide holes are formed in the dielectric layer 13.

[0035] like Figure 1 The semiconductor device shown has a first electrode layer 15 connected to a positive voltage and a second electrode layer 16 grounded. Current enters from the first electrode layer 15 and must pass through at least the P-DBR layer 14, the dielectric layer 13, the active layer 12, the N-DBR layer 11, and the substrate 10 before flowing to the first electrode layer 16 located on the back side of the substrate 10 (see current flow direction). Figure 1 (Indicated by the middle arrow). In practical applications, the thicknesses of the N-DBR layer 11, P-DBR layer 114, and substrate 10 are typically quite large, resulting in a longer current path between the first electrode layer 15 and the second electrode layer 16. This often leads to a significant series resistance, which in turn increases the turn-on voltage of the semiconductor device and causes substantial heat generation, posing a potential reliability risk.

[0036] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor device, specifically comprising: providing a substrate; forming a first reflective layer, a first contact layer, an active layer, a second contact layer, and a second reflective layer on the substrate; forming an insulating portion, the insulating portion being located between at least a portion of the first contact layer and at least a portion of the active layer, or between at least a portion of the second contact layer and at least a portion of the active layer, the insulating portion being in contact with the active layer; etching the second reflective layer to expose the top surface of the second contact layer; etching the second contact layer and the active layer to expose the top surface of the first contact layer; forming a second metal electrode on the top surface of the second contact layer, the insulating portion being located below the second metal electrode, the second metal electrode being located outside the second reflective layer; and forming a first metal electrode on the top surface of the first contact layer, the first metal electrode being located outside the active layer.

[0037] Therefore, in the semiconductor device described in this embodiment of the invention, when it is in operation, the current between the first metal electrode and the second metal electrode does not flow through the relatively thick first reflective layer, the second reflective layer, and the substrate. The current flow path is significantly shortened, the resistance is reduced, and the turn-on voltage can be lowered, thereby effectively reducing device heat generation and improving device performance. Furthermore, by forming the insulating portion below the second metal electrode, the insulating portion can act as a current blockage point, reducing light emission from the active region below the second metal electrode (because even if light is emitted, it will be blocked by the second metal electrode), thus making the light emission from the active layer more concentrated.

[0038] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Reference Figure 2 , Figure 2 This is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention. The method for forming the semiconductor device may include steps S21 to S26:

[0040] Step S21: Provide a substrate, and form a first reflective layer, a first contact layer, an active layer, a second contact layer, and a second reflective layer on the substrate;

[0041] Step S22: Form an insulating portion, the insulating portion being located between at least a portion of the first contact layer and at least a portion of the active layer, or between at least a portion of the second contact layer and at least a portion of the active layer, the insulating portion being in contact with the active layer;

[0042] Step S23: Etch the second reflective layer to expose the top surface of the second contact layer;

[0043] Step S24: Etch the second contact layer and the active layer to expose the top surface of the first contact layer;

[0044] Step S25: A second metal electrode is formed on the top surface of the second contact layer, the insulating portion is located below the second metal electrode, and the second metal electrode is located outside the second reflective layer;

[0045] Step S26: A first metal electrode is formed on the top surface of the first contact layer, the first metal electrode being located outside the active layer.

[0046] The following is combined Figures 3 to 7 The above steps are explained in detail.

[0047] Reference Figure 3 A substrate 20 is provided, on which a first reflective layer 30, a first contact layer 40, an active layer 50, a second contact layer 60, and a second reflective layer 70 are formed.

[0048] The semiconductor device described in this embodiment of the invention can be a vertical-cavity surface-emitting laser (VCSEL).

[0049] The substrate 20 can be a gallium arsenide (GaAs) substrate, and the active layer 50 can be a multiple quantum well (MQW) active layer, which serves as the light-emitting region of the VCSEL and also as the heat concentration region. The materials of the first contact layer 40 and the second contact layer 60 can be selected from GaAs or InGaA, etc.

[0050] The first reflective layer 30 can be an N-distributed Bragg reflector (N-DBR) layer; the second reflective layer 70 can be a P-distributed Bragg reflector (P-DBR) layer. The main function of the first reflective layer 30 and the second reflective layer 70 is to form a reflective area similar to a mirror, used to reflect laser light and reduce laser leakage.

[0051] Reference Figure 4 It can be formed Figure 3 In the process of the illustrated device, for example, after forming the active layer 50, a conductive material layer 80 is formed on the active layer 50; then, a conductive material layer 80 is formed on the conductive material layer 80. Figure 3 The second contact layer 60 and the second reflective layer 70 are shown.

[0052] Alternatively, it can also be formed Figure 3 In the process of the illustrated device, for example, after forming the first contact layer 40, the conductive material layer 80 is formed on the first contact layer 40; then, a... Figure 3 The active layer 50, the second contact layer 60, and the second reflective layer 70 are shown.

[0053] The conductive material layer 80 can be made of Al. x Ga (1-x) As, where x is the aluminum (Al) component, and 0.8 ≤ x < 1.

[0054] In specific implementations, the Al in the conductive material layer 80 can also be other suitable metal materials with similar electrical properties, such as copper (Cu). Correspondingly, GaAs can also be other suitable semiconductor materials with similar electrical properties, such as silicon germanide, silicon carbide, or indium gallium phosphate. This embodiment of the invention does not impose any particular limitation on the metal and semiconductor materials included in the conductive material layer 80.

[0055] Reference Figure 5 The second reflective layer 70 is etched to expose the top surface of the second contact layer 60; the second contact layer 60 and the active layer 50 are etched to expose the top surface of the first contact layer 40.

[0056] Furthermore, as a non-limiting embodiment, the forming process of the insulating portion 501 can be an oxidation process, specifically including: after etching the second contact layer 60, the active layer 50 and the conductive material layer 80, oxidizing a portion of the conductive material layer 80 to form the insulating portion 501.

[0057] In a specific implementation, a first preset area at the edge of the second reflective layer 70 can be etched to expose the top surface of the second contact layer 60; then, a second preset area at the edge of the second contact layer 60, the active layer 50, and the conductive material layer 80 can be etched to expose the top surface of the first contact layer 40. The first and second preset areas can be determined according to the actual scenario requirements.

[0058] Reference Figure 6 A second metal electrode B is formed on the top surface of the second contact layer 60, the insulating portion 501 is located below the second metal electrode B, and the second metal electrode B is located outside the second reflective layer 70; and a first metal electrode A is formed on the top surface of the first contact layer 40, the first metal electrode A being located outside the active layer 50.

[0059] In some embodiments, the first metal electrode A and the active layer 50 may be located in the same layer and have a non-zero gap between them; the second metal electrode B and the second reflective layer 70 may be located in the same layer and have a non-zero gap between them.

[0060] Reference Figure 7 As another non-limiting embodiment, the forming process of the insulating portion 501 can be an ion implantation process; specifically, it can be... Figure 3 Based on the device shown, ion implantation is performed on the first contact layer 40 and the active layer 50, or on the second contact layer 60 and the active layer 50, to form the insulating portion 501, wherein the insulating portion 501 is in contact with the active layer 50.

[0061] Then, you can refer to Figure 5 The etching process described herein involves etching the second reflective layer 70, as well as etching the second contact layer 60 and the active layer 50; then referring to... Figure 6 The process described herein involves forming the second metal electrode B on the top surface of the second contact layer 60 and forming the first metal electrode A on the top surface of the first contact layer 40. Thus, a process can be formed. Figure 7 The semiconductor device shown.

[0062] In other words, Figure 7 The semiconductor device shown can be considered as Figure 6 The diagram shows a modified structure of the semiconductor device, the main difference between the two being the formation process of the insulating portion 501. Furthermore, Figure 6 and Figure 7 The difference between the semiconductor devices shown also lies in the different positions of the insulating part 501.

[0063] In a specific implementation, ion implantation can be performed on the bottom region of the first contact layer 40 and the top region of the active layer 50, or on the top region of the second contact layer 60 and the bottom region of the active layer 50, in a direction perpendicular to the surface of the substrate 20, to form the insulating portion 501.

[0064] Furthermore, the implanted ions can be selected from one or more ions capable of providing suitable insulating properties, for example, they can be selected from hydrogen ions (H+). + It can also be selected from other ions that can play an insulating role, such as oxygen ions and inert gas ions (e.g., helium ions and argon ions).

[0065] As another non-limiting embodiment, in a specific implementation, if the insulating portion 501 is formed using an ion implantation process,Figure 7 The semiconductor device shown can also be used in Figure 3 Based on the device shown, it is formed using the following specific process steps:

[0066] (1) In Figure 3 Based on the device shown, first refer to Figure 5 The second reflective layer 70 is etched to expose the top surface of the second contact layer 60; the second contact layer 60 and the active layer 50 are etched to expose the top surface of the first contact layer 40.

[0067] (2) Then, ion implantation is performed on the bottom region of the first contact layer 40 and the top region of the active layer 50, or ion implantation is performed on the top region of the second contact layer 60 and the bottom region of the active layer 50 to form the insulating portion 501.

[0068] (3) Refer again Figure 6 The process described herein involves forming the second metal electrode B on the top surface of the second contact layer 60 and forming the first metal electrode A on the top surface of the first contact layer 40. It should be noted that in actual processes, the number of the insulating portion 501, the first metal electrode A, and the second metal electrode B can all be one, and their shapes can all be annular. Alternatively, the number and shape of the insulating portion 501, the first metal electrode A, and the second metal electrode B can be set to other values ​​and shapes according to the needs of specific application scenarios; this embodiment of the invention does not impose any limitations on this.

[0069] In specific implementations, when there are multiple insulating portions 501 and multiple second metal electrodes B, the insulating portions 501 and the second metal electrodes B can have a one-to-one correspondence.

[0070] Furthermore, the method for forming the semiconductor device may further include: doping the first contact layer 40, the first reflective layer 30, the second contact layer 60, and the second reflective layer 70, wherein the doping concentration of the first contact layer 40 is greater than the doping concentration of the first reflective layer 30, and the doping concentration of the second contact layer 60 is greater than the doping concentration of the second reflective layer 70.

[0071] In some non-limiting embodiments, the doping concentration of the first contact layer 40 is greater than or equal to 2e18 / cm. 3 The doping concentration of the second contact layer 60 is greater than or equal to 2e18 / cm. 3 The doping concentration of the first reflective layer 30 is less than or equal to 1e18 / cm. 3 The doping concentration of the second reflective layer 70 is less than or equal to 1e18 / cm.3 The doping concentration of the substrate 20 is less than or equal to 1e18 / cm. 3 .

[0072] In this embodiment of the invention, since the first metal electrode A and the second metal electrode B are in contact with the first contact layer 40 and the second contact layer 60 respectively with higher doping concentrations (for example, the doping concentrations of the first contact layer 40 and the second contact layer 60 can be greater than or equal to 2e18 / cm), 3 This allows for the formation of a low-resistance ohmic contact between the metal electrode and the semiconductor material, improving conductivity. Furthermore, the first reflective layer 30, the second reflective layer 70, and the substrate 20 can be configured with low-concentration doping (e.g., a doping concentration less than or equal to 1e18 / cm²). 3 Because low doping concentrations result in higher thermal conductivity, the heat dissipation of the semiconductor device can be improved.

[0073] This invention also discloses a semiconductor device, with reference to... Figure 6 or Figure 7 The semiconductor device may include: a substrate 20, and a first reflective layer 30, a first contact layer 40, an active layer 50, a second contact layer 60, and a second reflective layer 70 located above the substrate 20; an insulating portion 501 located between at least a portion of the first contact layer 40 and at least a portion of the active layer 50, or between at least a portion of the second contact layer 60 and at least a portion of the active layer 50, wherein the insulating portion 501 is in contact with the active layer 50; a first metal electrode A located on the top surface of the first contact layer 40 and outside the active layer 50; and a second metal electrode B located on the top surface of the second contact layer 60 and outside the second reflective layer 70, wherein the insulating portion 501 is located below the second metal electrode B.

[0074] In this embodiment of the invention, when the semiconductor device is operating, the second metal electrode B is connected to a positive voltage, and after the first metal electrode A is grounded, the current between the first metal electrode A and the second metal electrode B does not flow through the relatively thick first reflective layer 30, second reflective layer 70, and substrate 20. Compared to Figure 1 The existing semiconductor devices shown are Figure 6 and Figure 7 The current flow path in the semiconductor device shown is significantly shortened (the current flow path between the second metal electrode B and the first metal electrode A is as follows). Figure 6 and Figure 7As indicated by the middle arrow, the resistance is reduced and the turn-on voltage can be lowered, thereby effectively reducing the heat generation of the semiconductor device and improving device performance. Furthermore, by forming the insulating portion 501 below the second metal electrode B, the insulating portion 501 can block current at its location, reducing light emission from the active region below the second metal electrode B (even if light is emitted, it will be blocked by the second metal electrode B), thus making the light emission from the active layer 50 more concentrated.

[0075] Furthermore, such as Figure 6 As shown, the semiconductor device may further include: a conductive material layer 80 located between the first contact layer 40 and the active layer 50, or located between the second contact layer 60 and the active layer 50, and the insulating portion 501 located outside the conductive material layer 80.

[0076] Furthermore, the conductive material layer 80 can be made of Al. x Ga (1-x) As, where x is a component of Al, and 0.8 ≤ x < 1.

[0077] Furthermore, the insulating portion 501 may be located outside a portion of the first contact layer 40 and a portion of the active layer 50, or outside a portion of the second contact layer 60 and a portion of the active layer 50 (the term "outer side" here may also refer to the edge portion).

[0078] Furthermore, the projection area of ​​the second metal electrode B on the substrate 20 is located within the projection area of ​​the insulating portion 501 on the substrate 20, and the projection area of ​​the insulating portion 501 on the substrate 20 is located within the projection area of ​​the active layer 50 on the substrate 20.

[0079] In this embodiment of the invention, by controlling the projection area of ​​the insulating portion 501 on the front side of the substrate 20 to completely encompass the projection area of ​​the second metal electrode B on the front side of the substrate 20, the insulating effect of the insulating portion 501 can be utilized to minimize the light emission of the active region below the second metal electrode B, thereby making the light emission of the active layer 50 more concentrated. In practical applications, the projection areas of the second metal electrode B and the insulating portion 501 on the substrate 20 can be designed to be located at the edge of the projection area of ​​the active layer 50 on the substrate 20, thereby concentrating the light emission of the active layer 50 in the central region.

[0080] Furthermore, the ratio between the distance between the top surface of the insulating portion 501 and the top surface of the second contact layer 60 and the thickness of the second contact layer 60 is within a second preset range; the ratio between the distance between the bottom surface of the insulating portion 501 and the bottom surface of the first contact layer 40 and the thickness of the first contact layer 40 is within a third preset range.

[0081] In some non-limiting embodiments, the second preset interval can be set to [5%, 100%]. For example, the distance between the top surface of the insulating portion 501 and the top surface of the second contact layer 60 can be set to a ratio of 100% to the thickness of the second contact layer 60 (that is, equal to the thickness of the second contact layer 60).

[0082] In some non-limiting embodiments, the third preset interval can be set to [5%, 100%]. For example, the distance between the bottom surface of the insulating portion 501 and the bottom surface of the first contact layer 40 can be set to a ratio of 100% to the thickness of the first contact layer 40 (that is, equal to the thickness of the first contact layer 40).

[0083] It is understood that if the top surface of the insulating portion 501 contacts the top surface of the second contact layer 60, it may directly block the current flow between the second metal electrode B and the second contact layer 60. Correspondingly, if the bottom surface of the insulating portion 501 contacts the bottom surface of the first contact layer 40, it may directly block the current flow between the first metal electrode A and the first contact layer 40.

[0084] Therefore, in this embodiment of the invention, by appropriately setting the distance between the top surface of the insulating portion 501 and the top surface of the second contact layer 60, and the distance between the bottom surface of the insulating portion 501 and the bottom surface of the first contact layer 40, the adverse effects of the insulating portion 501 on the conductivity of the semiconductor device can be mitigated or even avoided.

[0085] Furthermore, the doping concentration of the first contact layer 40 is greater than that of the first reflective layer 30, and the doping concentration of the second contact layer 60 is greater than that of the second reflective layer 70.

[0086] For details on the principle, implementation, and beneficial effects of this semiconductor device, please refer to the previous text. Figures 3 to 7 The description of the semiconductor device formation method is omitted here.

[0087] It should be noted that, in the embodiments of the present invention, Figure 2 The sequence numbers of each step and the above appendix Figures 3 to 7The order of description and process methods presented here do not constitute a limitation on the formation process of the semiconductor device described in the embodiments of the present invention. In specific implementations, those skilled in the art can use other appropriate processes to form the epitaxial layers and insulating portions of the semiconductor device according to actual needs.

[0088] In the embodiments of this application, "multiple" refers to two or more.

[0089] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0090] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor device, characterized in that, include: A substrate, and a first reflective layer, a first contact layer, an active layer, a second contact layer, and a second reflective layer located above the substrate; An insulating portion is located between at least a portion of the first contact layer and at least a portion of the active layer, or between at least a portion of the second contact layer and at least a portion of the active layer, wherein the insulating portion is in contact with the active layer; The first metal electrode is located on the top surface of the first contact layer and outside the active layer; The second metal electrode is located on the top surface of the second contact layer and outside the second reflective layer, and the insulating portion is located below the second metal electrode; The first contact layer, the first reflective layer, the second contact layer, and the second reflective layer are doped, with the doping concentration of the first contact layer being greater than that of the first reflective layer, and the doping concentration of the second contact layer being greater than that of the second reflective layer.

2. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A conductive material layer is located between the first contact layer and the active layer, or between the second contact layer and the active layer, and the insulating portion is located outside the conductive material layer.

3. The semiconductor device as described in claim 2, characterized in that, The conductive material layer is made of AlxGa(1-x)As, where x is the composition of Al and 0.8 ≤ x < 1.

4. The semiconductor device as claimed in claim 1, characterized in that, The insulating portion is also located outside a portion of the first contact layer and a portion of the active layer, or it is also located outside a portion of the second contact layer and a portion of the active layer.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The projection area of ​​the second metal electrode on the substrate is located within the projection area of ​​the insulating portion on the substrate, and the projection area of ​​the insulating portion on the substrate is located within the projection area of ​​the active layer on the substrate.

6. The semiconductor device as claimed in claim 1, characterized in that, The ratio between the distance between the top surface of the insulating portion and the top surface of the second contact layer and the thickness of the second contact layer is within a second preset range; The ratio between the distance between the bottom surface of the insulating part and the bottom surface of the first contact layer and the thickness of the first contact layer is within a third preset range.

7. The semiconductor device as claimed in claim 6, characterized in that, Meet one or more of the following: The second preset range is 5% to 100%; The third preset range is 5% to 100%.

8. The semiconductor device as claimed in claim 1, characterized in that, Meet one or more of the following: The doping concentration of the first contact layer is greater than or equal to 2e18 / cm3; The doping concentration of the second contact layer is greater than or equal to 2e18 / cm3; The doping concentration of the first reflective layer is less than or equal to 1e18 / cm3; The doping concentration of the second reflective layer is less than or equal to 1e18 / cm3; The doping concentration of the substrate is less than or equal to 1e18 / cm3.

9. A method for forming a semiconductor device, characterized in that, include: A substrate is provided, on which a first reflective layer, a first contact layer, an active layer, a second contact layer, and a second reflective layer are formed; The first contact layer, the first reflective layer, the second contact layer, and the second reflective layer are doped, wherein the doping concentration of the first contact layer is greater than the doping concentration of the first reflective layer, and the doping concentration of the second contact layer is greater than the doping concentration of the second reflective layer. An insulating portion is formed, the insulating portion being located between at least a portion of the first contact layer and at least a portion of the active layer, or being located between at least a portion of the second contact layer and at least a portion of the active layer, the insulating portion being in contact with the active layer; The second reflective layer is etched to expose the top surface of the second contact layer; The second contact layer and the active layer are etched to expose the top surface of the first contact layer; A second metal electrode is formed on the top surface of the second contact layer, the insulating portion is located below the second metal electrode, and the second metal electrode is located outside the second reflective layer; A first metal electrode is formed on the top surface of the first contact layer, and the first metal electrode is located outside the active layer.

10. The method as described in claim 9, characterized in that, Also includes: A conductive material layer is formed, wherein the conductive material layer is located between the first contact layer and the active layer, or between the second contact layer and the active layer; The insulating portion is formed based on a portion of the conductive material layer.

11. The method as described in claim 10, characterized in that, The insulating portion is formed by oxidizing a portion of the conductive material layer after etching the second contact layer, the conductive material layer, and the active layer.

12. The method as described in claim 9, characterized in that, The insulating portion is formed by ion implantation of either the first contact layer and the active layer, or the second contact layer and the active layer.

13. The method as described in claim 9, characterized in that, Meet one or more of the following: The doping concentration of the first contact layer is greater than or equal to 2e18 / cm3; The doping concentration of the second contact layer is greater than or equal to 2e18 / cm3; The doping concentration of the first reflective layer is less than or equal to 1e18 / cm3; The doping concentration of the second reflective layer is less than or equal to 1e18 / cm3; The doping concentration of the substrate is less than or equal to 1e18 / cm3.

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