Peak Current Control Circuit, Method and DC-DC Converter with Adaptive Ramp Compensation

Abstract

The present invention discloses a peak current control circuit, method and DC-DC converter with adaptive slope compensation. The peak current control circuit includes an inductor current detection module, a control signal generation module, an adaptive slope compensation current generation module, a DC voltage adjustment module, a first current generation module and a second current generation module. Among them, the first and second input terminals of the inductor current detection module are respectively connected to both ends of the inductor in the DC-DC converter; the input terminal of the first current generation module is connected to the output voltage terminal of the DC-DC converter; the input terminal of the second current generation module is connected to the input voltage terminal of the DC-DC converter; the output terminal of the control signal generation module is connected to the inverting input terminal of the PWM comparator in the DC-DC converter to form a control current loop. The peak current control circuit can adaptively adjust the magnitude of the slope compensation current.

Description

Technical Field

[0001] The present invention relates to a peak current control circuit with adaptive ramp compensation, and also relates to a corresponding peak current control method, and a DC-DC converter including the peak current control circuit, belonging to the technical field of analog integrated circuits. Background Art

[0002] With the continuous development of integrated circuit technology, DC-DC converters are more and more widely used in integrated circuits, and the requirements for DC-DC switching power supplies are also getting higher and higher. When using PWM (Pulse Width Modulation) current mode control, the DC-DC converter has good dynamic characteristics such as fast transient response, large bandwidth, and easy implementation. However, in the case of introducing peak current control, when the duty cycle is greater than 50%, subharmonic oscillations will occur in the circuit. Therefore, it is necessary to introduce artificial ramp compensation to solve this problem.

[0003] In the prior art, the ramp compensation method of the DC-DC converter is to directly superimpose a sawtooth wave compensation current signal with a fixed slope on the sampled inductor current. This method is applicable to DC-DC converters with both input voltage and output voltage unchanged. When the output voltage of the DC-DC converter changes, for example, when the input voltage is 3.8V and the output voltage changes from 1V to 3.4V, the duty cycle of the control signal of the power switch tube will change from 26% to 89%. When the duty cycle of the control signal is less than 50%, no ramp compensation is required, while when the duty cycle of the control signal is greater than 50%, ramp compensation is required. On the other hand, when the ramp compensation amount is small, it will affect the stability of the system when operating at a large duty cycle; when the ramp compensation amount is large, it will affect the current feedback ability of the system when operating at a small duty cycle, thus affecting its transient response performance and load-carrying ability. Therefore, how to dynamically adjust the magnitude of the introduced artificial ramp compensation current, avoid over-compensation or under-compensation, and maintain the stability of the DC-DC converter operation is a very important technical research topic.

[0004] In the Chinese invention patent with the authorization announcement number CN114967829B, a voltage-current conversion circuit for ramp compensation is disclosed. This circuit is for the sawtooth wave voltage signal naturally generated by the oscillator circuit, which is input from the gate of the PMOS transistor and output from the source. Then, through a compact current-input type operational amplifier structure, the source potentials of the PMOS transistors on two branches are made the same. Then, through the PMOS transistor with the gate-drain shorted on another branch, the sawtooth wave voltage signal is transferred to the drains of the two PMOS transistors, and the sawtooth wave voltage signal is converted into a current signal through a resistor, and then through a current mirror mirroring circuit, it is superimposed with the sampled inductor current signal, having the advantages of low area and low cost in integrated circuit design. Summary of the Invention

[0005] The primary technical problem to be solved by the present invention is to provide a peak current control circuit with adaptive slope compensation for implementing a PWM current mode control loop in a DC-DC converter with a wide output voltage range.

[0006] Another technical problem to be solved by the present invention is to provide a peak current control method with adaptive slope compensation.

[0007] Another technical problem to be solved by the present invention is to provide a DC-DC converter including the peak current control circuit.

[0008] To achieve the above object, the present invention adopts the following technical solutions:

[0009] According to the first aspect of the embodiments of the present invention, there is provided a peak current control circuit with adaptive slope compensation for a control loop of a DC-DC converter. The peak current control circuit includes an inductor current detection module, a control signal generation module, an adaptive slope compensation current generation module, a DC voltage adjustment module, a first current generation module, and a second current generation module; wherein,

[0010] The inductor current detection module is configured to sample the current flowing through the inductor in the DC-DC converter and convert it into a corresponding voltage signal at a certain ratio, and output the voltage signal to the control signal generation module.

[0011] The first current generation module is configured to sample the output voltage of the DC-DC converter and convert it into a corresponding current signal, and output the current signal to the control signal generation module and the adaptive slope compensation current generation module respectively.

[0012] The second current generation module is configured to sample the input voltage of the DC-DC converter and convert it into a corresponding current signal, and output the current signal to the control signal generation module and the adaptive slope compensation current generation module respectively.

[0013] The adaptive slope compensation current generation module receives the current signals output by the second current generation module and the first current generation module, and generates a slope compensation current by subtraction or scaling and then subtraction, and outputs the slope compensation current to the control signal generation module.

[0014] The control signal generation module receives the current signals output by the inductor current detection module, the second current generation module, and the first current generation module, as well as the current signals output by the DC voltage adjustment module and the adaptive slope compensation current generation module, generates a control signal and outputs the control signal to the inverting input terminal of a PWM comparator in the DC-DC converter for adaptively adjusting the slope compensation intensity.

[0015] Preferably, the first input terminal and the second input terminal of the inductor current detection module are respectively connected to both ends of the inductor in the DC-DC converter. The input terminal of the first current generation module is connected to the output voltage terminal of the DC-DC converter. The input terminal of the second current generation module is connected to the input voltage terminal of the DC-DC converter. The output terminal of the control signal generation module is connected to the inverting input terminal of the PWM comparator in the DC-DC converter to form a control loop.

[0016] Preferably, the inductor current detection module is composed of a first resistor, a second resistor, a second capacitor, and a third capacitor. One end of the first resistor is connected to the first input terminal of the inductor current detection module. One end of the second capacitor is connected to the second input terminal of the inductor current detection module. The other end of the first resistor and the other end of the second capacitor are commonly connected to the third capacitor. The other end of the third capacitor is connected to the output terminal of the inductor current detection module and the second resistor. The other end of the second resistor is connected to the ground potential terminal. At the same time, the output terminal of the inductor current detection module is connected to the first input terminal of the control signal generation module.

[0017] Preferably, the DC voltage adjustment module is composed of a reference module, a fifth PMOS transistor, and a sixth PMOS transistor. The output terminal of the reference module is connected to the drain of the fifth PMOS transistor. The drain of the fifth PMOS transistor is short-circuited to the gate and then connected to the gate of the sixth PMOS transistor. The source of the fifth PMOS transistor and the source of the sixth PMOS transistor are both connected to the power supply terminal. The drain of the sixth PMOS transistor is connected to the output terminal of the DC voltage adjustment module. At the same time, this output terminal is connected to the first input terminal of the control signal generation module.

[0018] Preferably, the adaptive ramp compensation current generation module is composed of a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. Among them, the gate of the seventh PMOS transistor is connected to the first input terminal of the adaptive ramp compensation current generation module, the gate of the eighth PMOS transistor is connected to the second input terminal of the adaptive ramp compensation current generation module, the sources of the seventh PMOS transistor and the eighth PMOS transistor are both connected to the power supply terminal, the drain of the seventh PMOS transistor is connected to the drain of the third NMOS transistor, the drain of the third NMOS transistor is short-circuited to the gate and then connected to the gate of the fourth NMOS transistor, the sources of the third NMOS transistor and the fourth NMOS transistor are both connected to the ground potential terminal, the drain of the fourth NMOS transistor is connected to the drain of the eighth PMOS transistor and the drain of the fifth NMOS transistor, the drain of the fifth NMOS transistor is short-circuited to the gate and then connected to the gate of the sixth NMOS transistor, the sources of the fifth NMOS transistor and the sixth NMOS transistor are both connected to the ground potential terminal, the drain of the sixth NMOS transistor is connected to the drain of the ninth PMOS transistor, the drain of the ninth PMOS transistor is short-circuited to the gate and then connected to the gate of the tenth PMOS transistor, the sources of the ninth PMOS transistor and the tenth PMOS transistor are both connected to the power supply terminal, the drain of the tenth PMOS transistor is connected to the output terminal of the adaptive ramp compensation current generation module, and at the same time, this output terminal is connected to the second input terminal of the control signal generation module.

[0019] Preferably, the control signal generation module is composed of a first capacitor, a first control switch, and a second control switch. Among them, one end of the second control switch is connected to the second input terminal of the control signal generation module, the other end of the second control switch is connected to the first capacitor on the one hand and to the first control switch and the output terminal of the control signal generation module on the other hand, and the other ends of the first capacitor and the first control switch are both connected to the first input terminal of the control signal generation module.

[0020] The on / off states of the first control switch and the second control switch are controlled by a first control signal and a second control signal respectively.

[0021] Preferably, the adaptive ramp compensation current generation module may also be composed of an eleventh PMOS transistor, a twelfth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor. Among them, the gate of the eleventh PMOS transistor is connected to the first input terminal of the adaptive ramp compensation current generation module, the gate of the twelfth PMOS transistor is connected to the second input terminal of the adaptive ramp compensation current generation module, the sources of the eleventh PMOS transistor and the twelfth PMOS transistor are both connected to the power supply terminal, the drain of the eleventh PMOS transistor is connected to the drain of the seventh NMOS transistor, the drain of the seventh NMOS transistor is short-circuited to the gate and then connected to the gate of the eighth NMOS transistor, the sources of the seventh NMOS transistor and the eighth NMOS transistor are both connected to the ground potential terminal, the drains of the eighth NMOS transistor and the twelfth PMOS transistor are both connected to the output terminal of the adaptive ramp compensation current generation module; at the same time, this output terminal is connected to the second input terminal of the control signal generation module.

[0022] Preferably, when the duty cycle of the DC-DC converter is less than 50%, within each switching period T, the first control signal is a high-level signal, the first control switch is in a normally-on state, and the first voltage is directly output as the control signal; at the same time, the second control signal is a low-level signal, the second control switch is in a normally-off state, and the ramp compensation current is blocked; the control signal Vramp satisfies the following formula:

[0023]

[0024] Among them, V2 is the first voltage, I1 is the output current of the second current generation module, I2 is the output current of the first current generation module, I3 is the output current of the DC voltage adjustment module, Vout is the output terminal voltage of the DC-DC converter, F is the switching frequency in the DC-DC converter, L is the inductance value of the inductor in the DC-DC converter, I L is the current flowing through the inductor, R2 is the resistance value of the second resistor, and k is a coefficient related to the resistors and capacitors in the inductor current detection module.

[0025] Preferably, when the duty cycle of the DC-DC converter is greater than or equal to 50%, at the end of each switching period T, the first control signal generates a high-level pulse signal, the first control switch is instantaneously turned on, the charge on the first capacitor is cleared, and the control signal is pulled to the first voltage. At the same time, the second control signal generates a low-level pulse signal, the second control switch is instantaneously turned off, and the ramp compensation current is blocked at the moment when the charge on the first capacitor is cleared. Except at the end of each switching period T, the first control signal is a low-level signal, the first control switch is in the off state, the second control signal is a high-level signal, the second control switch is in the on state, and the first capacitor is charged by the ramp compensation current to form a compensation voltage. At this time, the compensation voltage is added to the first voltage and then output as the control signal. The control signal Vramp satisfies the following formula:

[0026]

[0027] Wherein, C1 is the capacitance value of the first capacitor, I4 is the current after scaling I1, I6 is the current after scaling I2, k1, k2, and k3 are all proportionality coefficients, and 0 ≤ t ≤ T.

[0028] According to the second aspect of the embodiments of the present invention, an adaptive ramp compensation peak current control method is provided, which is implemented based on the above peak current control circuit, and includes the following steps:

[0029] (1) Sample the input voltage, output voltage, and inductor current in the DC-DC converter, and convert them into a first current, a second current, and a third current respectively; the DC voltage adjustment module outputs a fourth current;

[0030] (2) A first voltage V2 is jointly formed by the first current, the second current, the third current, and the fourth current and provided to the first input end of the control signal generation module; the first current and the second current are input to the adaptive ramp compensation current generation module to generate a ramp compensation current and provided to the second input end of the control signal generation module;

[0031] (3) In the DC-DC converter, when the duty cycle is less than 50%, proceed to the next step; when the duty cycle is greater than or equal to 50%, input to step (6);

[0032] (4) In the control signal generation module, the first control switch is closed and the second control switch is opened, and the output control signal is equal to the first voltage and provided to the PWM comparator in the control loop;

[0033] (5) Return to step (1);

[0034] In the control signal generation module, except at the end of each period T, the first control switch is turned off and the second control switch is turned on. The ramp compensation current charges the first capacitor to form a compensation voltage, and the output control signal is equal to the sum of the first voltage and the compensation voltage, which is provided to the PWM comparator in the control loop.

[0035] (7)Return to step (1).

[0036] According to the third aspect of the embodiments of the present invention, a DC-DC converter is provided, and the DC-DC converter includes the above-mentioned peak current control circuit with adaptive ramp compensation.

[0037] Compared with the prior art, the peak current control circuit with adaptive ramp compensation provided by the present invention can, through the collaborative work of each module unit, provide a compensation current that varies with the output voltage and the input voltage when the duty cycle of the DC-DC converter is greater than or equal to 50%, so that the generated ramp compensation amount is always maintained within a suitable range (i.e., between 0.75 and 1 times the slope of the inductor current falling section), so that the overall loop will neither have sub-ramp oscillations due to under-compensation nor affect the transient characteristics of the peak current mode due to over-compensation in a system where the input voltage and the output voltage are variable. At the same time, the present invention can also adjust the voltage range of the control signal Vramp and keep the control signal within a suitable range all the time, so as to ensure the normal operation of the error amplifier. Therefore, the peak current control circuit with adaptive ramp compensation provided by the present invention has the beneficial effects of ingenious and reasonable structural design, low design cost, high working efficiency of the converter, and excellent circuit performance. Description of the Drawings

[0038] Figure 1 It is a circuit schematic diagram of a Buck-type DC-DC converter provided by the embodiments of the present invention;

[0039] Figure 2 It is a circuit block diagram of a peak current control circuit with adaptive ramp compensation provided by the embodiments of the present invention;

[0040] Figure 3 It is a circuit schematic diagram of the peak current control circuit with adaptive ramp compensation in the first embodiment of the present invention;

[0041] Figure 4 (a) is a schematic diagram of the voltage-current conversion circuit of the first solution in the embodiments of the present invention;

[0042] Figure 4 (b) is a schematic diagram of the voltage-current conversion circuit of the second solution in the embodiments of the present invention;

[0043] Figure 5 (a) is a waveform diagram of the control signal VT1 and the control signal VT2 when the duty cycle is less than 50% in the embodiments of the present invention;

[0044] Figure 5(b) is a waveform diagram of control signal VT1 and control signal VT2 when the duty cycle is greater than or equal to 50% in the embodiment of the present invention;

[0045] Figure 6 is a circuit schematic diagram of a peak current control circuit with adaptive slope compensation in the second embodiment of the present invention;

[0046] Figure 7 is a method flow chart for a peak current control circuit to achieve adaptive slope compensation in the embodiment of the present invention;

[0047] Figure 8 is a simulation test diagram of the waveform of control signal Vramp in a Buck-type DC-DC converter in the embodiment of the present invention. Detailed implementation manners

[0048] The technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0049] Figure 1 Shown is a circuit schematic diagram of a Buck-type DC-DC converter provided by an embodiment of the present invention. The DC-DC converter at least includes a switching transistor PM0, a switching transistor NM0, an inductor L, a capacitor C0, and a load R L , as well as an input voltage terminal Vin and an output voltage terminal Vout. Its control circuit uses PWM current mode to control the output voltage. To accelerate the circuit response speed, a peak current control loop is introduced. The control loop includes a voltage-dividing resistor feedback circuit, an error amplifier circuit, a slope compensation control circuit, a PWM comparator, a control logic unit, and a buffer circuit. Among them, the slope compensation control circuit is the peak current control circuit provided by the embodiment of the present invention. As shown by the dashed box in Figure 1 , the two input terminals of the peak current control circuit are respectively connected to both ends of the inductor L, and the output terminal of the peak current control circuit is connected to the inverting input terminal of the PWM comparator. In addition, the input voltage terminal Vin and the output voltage terminal Vout of the DC-DC converter are also respectively connected to the other two input terminals of the peak current control circuit.

[0050] On the one hand, when the output voltage of the DC-DC converter changes to make the duty cycle greater than or equal to 50%, in order to avoid sub-harmonic oscillation in the current loop, dynamic slope compensation is required. The peak current control circuit provided by the embodiment of the present invention can adaptively adjust the slope compensation intensity according to the changes in the input voltage Vin and the output voltage Vout.

[0051] On the other hand, when the DC-DC converter is operating stably, the intersection point of the output signal Vea of the error amplifier and the control signal Vramp output by the peak current control circuit must meet the duty cycle requirement. Since the variation range of the duty cycle is relatively large, it is required that this intersection point should not be too low when the duty cycle is small and should not be too high when the duty cycle is large. Otherwise, the output signal Vea of the error amplifier will be too small or too large, which will cause the error amplifier to be in an abnormal working state, thereby affecting its gain and the output accuracy of the circuit. The peak current control circuit provided by the embodiment of the present invention can adjust the peak voltage range of the control signal Vramp as a whole through the DC voltage adjustment module, thus avoiding the occurrence of this phenomenon.

[0052] Figure 2 The circuit block diagram of the peak current control circuit provided by the embodiment of the present invention is shown. The peak current control circuit includes an inductor current detection module 1, a control signal generation module 2, an adaptive ramp compensation current generation module 3, a DC voltage adjustment module 4, a first current generation module 5, and a second current generation module 6. Among them, the first input terminal and the second input terminal of the inductor current detection module 1 are respectively connected to both ends of the inductor L in the DC-DC converter, and the output terminal of the inductor current detection module 1 is connected to the first input terminal of the control signal generation module 2; the input terminal of the first current generation module 5 is connected to the output voltage terminal Vout in the DC-DC converter, the first output terminal of the first current generation module 5 is connected to the first input terminal of the control signal generation module 2, and the second output terminal of the first current generation module 5 is connected to the second input terminal of the adaptive ramp compensation current generation module 3; the input terminal of the second current generation module 6 is connected to the input voltage terminal Vin in the DC-DC converter, the first output terminal of the second current generation module 6 is connected to the first input terminal of the control signal generation module 2, and the second output terminal of the second current generation module 6 is connected to the first input terminal of the adaptive ramp compensation current generation module 3; the output terminal of the DC voltage adjustment module 4 is connected to the first input terminal of the control signal generation module 2; the output terminal of the adaptive ramp compensation current generation module 3 is connected to the second input terminal of the control signal generation module 2, and the output terminal of the control signal generation module 2 is connected to the inverting input terminal of the PWM comparator in the DC-DC converter to form a control current loop.

[0053] The inductor current detection module 1 is used to sample the current flowing through the inductor L in the DC-DC converter and convert it into a corresponding voltage signal at a certain ratio, and output it to the control signal generation module 2.

[0054] The first current generation module 5 is used to sample the output voltage Vout of the DC-DC converter and convert it into a corresponding current signal, and output it to the control signal generation module 2 and the adaptive ramp compensation current generation module 3 respectively.

[0055] The second current generation module 6 is configured to sample the input voltage Vin of the DC-DC converter and convert it into a corresponding current signal, which are respectively output to the control signal generation module 2 and the adaptive ramp compensation current generation module 3.

[0056] The DC voltage adjustment module 4 outputs a DC current signal to the control signal generation module 2, which is used to adjust the maximum value of the control signal Vramp so that the variation range of the maximum value of the control signal Vramp is within the appropriate operating range of the error amplifier in the DC-DC converter.

[0057] The adaptive ramp compensation current generation module 3 receives the current signals output by the second current generation module 6 and the first current generation module 5, and generates a ramp compensation current Iramp through subtraction or scaling and subtraction, and outputs it to the control signal generation module 2. Among them, the adaptive ramp compensation current generation module 3 is composed of four circuit units: two current scaling units, a current subtraction unit, and a ramp compensation current unit according to the function setting.

[0058] After receiving the current signals output by the sense current detection module 1, the second current generation module 6, and the first current generation module 5, as well as the current signals output by the DC voltage adjustment module 4 and the adaptive ramp compensation current generation module 3, the control signal generation module 2 generates a control signal Vramp and outputs it to the inverting input terminal of the PWM comparator in the DC-DC converter, which is used to adaptively adjust the ramp compensation intensity.

[0059] As Figure 3 shown, in the first embodiment provided by the present invention, the peak current control circuit with adaptive ramp compensation includes an inductor current detection module 1, a control signal generation module 2, an adaptive ramp compensation current generation module 3, a DC voltage adjustment module 4, a first current generation module 5, and a second current generation module 6. Next, the circuit compositions of each module unit will be described in detail.

[0060] The inductor current detection module 1 is composed of a first resistor R1, a second resistor R2, a second capacitor C2, and a third capacitor C3. The first input terminal of this unit circuit is the L1 terminal, the second input terminal is the L2 terminal, and the output terminal is the V2 terminal. Among them, the first input terminal L1 and the second input terminal L2 are respectively connected to both ends of the inductor L in the DC-DC converter. One end of the first resistor R1 is connected to the first input terminal L1, one end of the second capacitor C2 is connected to the second input terminal L2, the other ends of the first resistor R1 and the second capacitor C2 are commonly connected to the third capacitor C3, the other end of the third capacitor C3 is connected to the output terminal V2 and the second resistor R2, and the other end of the second resistor R2 is connected to the ground potential terminal. At the same time, the output terminal V2 is connected to the first input terminal of the control signal generation module 2.

[0061] Both the first current generation module 5 and the second current generation module 6 are implemented using a voltage-to-current (V to I) circuit. In the embodiments of the present invention, two voltage-to-current circuit solutions are provided. Among them, the input terminal of the voltage-to-current circuit for the first current generation module 5 is connected to the output voltage terminal Vout in the DC-DC converter, and the output current of the voltage-to-current circuit is the second current Iout2; the input terminal of the voltage-to-current circuit for the second current generation module 6 is connected to the input voltage terminal Vin in the DC-DC converter, and the output current of the voltage-to-current circuit is the first current Iout1.

[0062] As shown in FIG. 4(a), the voltage-to-current circuit of the first solution is composed of a third resistor R41, a fourth resistor R42, a fifth resistor R43, a first PMOS transistor PM41, a second PMOS transistor PM42, a first NMOS transistor NM41, and a first operational amplifier A. Among them, the third resistor R41 is connected to the input terminal of this unit circuit, the other end of the third resistor R41 is connected to the non-inverting input terminal of the first operational amplifier A and the fourth resistor R42, the other end of the fourth resistor R42 is connected to the fifth resistor R43 and the ground potential terminal, the other end of the fifth resistor R43 is connected to the inverting input terminal of the first operational amplifier A and the source of the first NMOS transistor NM41, the output terminal of the first operational amplifier A is connected to the gate of the first NMOS transistor NM41, the drain of the first NMOS transistor NM41 is connected to the drain of the second PMOS transistor PM42, the drain of the second PMOS transistor PM42 is short-circuited to the gate and then connected to the gate of the first PMOS transistor PM41, the sources of the second PMOS transistor PM42 and the first PMOS transistor PM41 are both connected to the power supply terminal VDD, and the drain of the first PMOS transistor PM41 is connected to the output terminal of this unit circuit.

[0063] As shown in FIG. 4(b), the voltage-to-current circuit of the second solution is composed of a sixth resistor R44, a seventh resistor R45, an eighth resistor R46, a third PMOS transistor PM43, a fourth PMOS transistor PM44, and a second NMOS transistor NM42. Among them, the sixth resistor R44 is connected to the input terminal of this unit circuit, the other end of the sixth resistor R44 is connected to the gate of the second NMOS transistor NM42 and the seventh resistor R45, the other end of the seventh resistor R45 is connected to the eighth resistor R46 and the ground potential terminal, the other end of the eighth resistor R46 is connected to the source of the second NMOS transistor NM42, the drain of the second NMOS transistor NM42 is connected to the drain of the fourth PMOS transistor PM44, the drain of the fourth PMOS transistor PM44 is short-circuited to the gate and then connected to the gate of the third PMOS transistor PM43, the sources of the fourth PMOS transistor PM44 and the third PMOS transistor PM43 are both connected to the power supply terminal VDD, and the drain of the third PMOS transistor PM43 is connected to the output terminal of this unit circuit.

[0064] The DC voltage adjustment module 4 is composed of a reference module, a fifth PMOS transistor PM21, and a sixth PMOS transistor PM22. Among them, the output terminal of the reference module is connected to the drain of the fifth PMOS transistor PM21. The drain of the fifth PMOS transistor PM21 is short-circuited to the gate and then connected to the gate of the sixth PMOS transistor PM22. The source of the fifth PMOS transistor PM21 and the source of the sixth PMOS transistor PM22 are both connected to the power supply terminal VDD. The drain of the sixth PMOS transistor PM22 is connected to the output terminal of this unit circuit. Among them, the reference module can be implemented by an existing bandgap (bandgap reference) circuit.

[0065] The adaptive ramp compensation current generation module 3 is composed of a seventh PMOS transistor PM24, an eighth PMOS transistor PM23, a ninth PMOS transistor PM25, a tenth PMOS transistor PM26, a third NMOS transistor NM21, a fourth NMOS transistor NM22, a fifth NMOS transistor NM23, and a sixth NMOS transistor NM24. Among them, the gate of the seventh PMOS transistor PM24 is connected to the first input terminal of this unit circuit. The gate of the eighth PMOS transistor PM23 is connected to the second input terminal of this unit circuit. The source of the seventh PMOS transistor PM24 and the source of the eighth PMOS transistor PM23 are both connected to the power supply terminal VDD. The drain of the seventh PMOS transistor PM24 is connected to the drain of the third NMOS transistor NM21. The drain of the third NMOS transistor NM21 is short-circuited to the gate and then connected to the gate of the fourth NMOS transistor NM22. The source of the third NMOS transistor NM21 and the source of the fourth NMOS transistor NM22 are both connected to the ground potential terminal. The drain of the fourth NMOS transistor NM22 is connected to the drain of the eighth PMOS transistor PM23 and the drain of the fifth NMOS transistor NM23. The drain of the fifth NMOS transistor NM23 is short-circuited to the gate and then connected to the gate of the sixth NMOS transistor NM24. The source of the fifth NMOS transistor NM23 and the source of the sixth NMOS transistor NM24 are both connected to the ground potential terminal. The drain of the sixth NMOS transistor NM24 is connected to the drain of the ninth PMOS transistor PM25. The drain of the ninth PMOS transistor PM25 is short-circuited to the gate and then connected to the gate of the tenth PMOS transistor PM26. The source of the ninth PMOS transistor PM25 and the source of the tenth PMOS transistor PM26 are both connected to the power supply terminal VDD. The drain of the tenth PMOS transistor PM26 is connected to the output terminal of this unit circuit.

[0066] In the adaptive ramp compensation current generation module 3, the eighth PMOS transistor PM23 and the seventh PMOS transistor PM24 respectively form two current scaling units; the third NMOS transistor NM21, the fourth NMOS transistor NM22, and the fifth NMOS transistor NM23 form a current difference unit; the sixth NMOS transistor NM24 and the ninth PMOS transistor PM25, the tenth PMOS transistor PM26 form a ramp compensation current unit.

[0067] The control signal generation module 2 is composed of a first capacitor C1, a first control switch S1, and a second control switch S2. Among them, one end of the second control switch S2 is connected to the second input terminal of the unit circuit, and the other end of the second control switch S2 is connected to the first capacitor C1 on the one hand, and to the first control switch S1 and the output terminal of the unit circuit on the other hand. The other end of the first capacitor C1 and the other end of the first control switch S1 are both connected to the first input terminal of the unit circuit.

[0068] In the control signal generation module 2, the on / off states of the first control switch S1 and the second control switch S2 are respectively controlled by a control signal VT1 and a control signal VT2. The waveforms of the control signal VT1 and the control signal VT2 are shown in Fig. 5(a) and Fig. 5(b). Among them, Fig. 5(a) shows the waveform of the control signal when the duty cycle is less than 50%; Fig. 5(b) shows the waveform of the control signal when the duty cycle is greater than or equal to 50%. The control signal D in the figure P is the control signal of the switching transistor PM0 in the DC-DC converter.

[0069] In the above first embodiment provided by the present invention, the circuit composition structures of the various module units in the peak current control circuit with adaptive ramp compensation have been described in detail. Next, in combination with Figure 3 the working principle of this peak current control circuit will be analyzed and described.

[0070] The inductor current detection module 1 detects the current flowing through the inductor L in the DC-DC converter and converts it into an output terminal voltage signal V2 according to a certain ratio. Taking Figure 1 the Buck-type DC-DC converter shown as an example, the first input terminal L1 and the second input terminal L2 of the unit circuit are respectively connected to both ends of the inductor L in the DC-DC converter. Among them, the second input terminal L2 is connected to the output voltage (i.e., Vout) side of the DC-DC converter. The frequency F of the switching transistor PM0 in the DC-DC converter is usually a constant value. The resistance value of the first resistor R1 of the unit circuit is taken as 1 / (2π*F*C2), and let R1 = 1 / (2π*F*C2) = Zrc, where C2 is the capacitance value of the second capacitor C2, and Zrc is a substitution symbol introduced for convenient expression. Then the output terminal voltage V2 of the unit circuit is:

[0071] (1)

[0072] Wherein, L is the inductance value of the inductor L in the DC-DC converter; I L is the current flowing through the inductor L; Vout is the voltage at the output terminal of the DC-DC converter; R 2 is the resistance value of the second resistor R2 in this unit circuit; C 3 is the capacitance value of the third capacitor C3 in this unit circuit.

[0073] As can be seen from Equation 1, when the frequency F is constant, the output voltage V2 and the inductor current I L are linearly related, and the magnitude of the output voltage V2 can be changed by adjusting the magnitudes of the third capacitor C3 and the second resistor R2. At the same time, since the current ripple of the inductor current I L is relatively large compared with the voltage ripple of the output voltage Vout, therefore, the influence of the voltage ripple of the output voltage Vout on the current ripple of the inductor current I L can be ignored, and it can be considered that only the magnitude of the output voltage V2 of this unit circuit is changed as a whole.

[0074] Based on the voltage V2 in the above Equation 1, the control signal generation module 2 superimposes a ramp compensation voltage component on the voltage V2 and generates a control signal Vramp at the output terminal of this unit circuit, and outputs it to the inverting input terminal of the PWM comparator in the DC-DC converter. At this time, the voltage V2 not only includes the voltage signal converted from the inductor current sampled by the inductor current detection module 1, but also includes the voltage signals generated by the output currents I3, I2, and I1 provided by the DC voltage adjustment module 4, the first current generation module 5, and the second current generation module 6 on the second resistor R2. Therefore, the complete expression of the voltage V2 (the first voltage) is:

[0075] (2)

[0076] Let: (3)

[0077] Equation 2 can be rearranged as:

[0078] (4)

[0079] Among them, I1 is the output current of the second current generation module 6 and is a function of the input voltage Vin of the DC-DC converter; I2 is the output current of the first current generation module 5 and is a function of the output voltage Vout of the DC-DC converter; I3 is the output current of the DC voltage adjustment module 4.

[0080] As can be seen from Equation 2, Equation 3, and Equation 4, the magnitude of the voltage V2 (the first voltage) can change with the changes in the input voltage Vin and the output voltage Vout of the DC-DC converter. At the same time, by setting an appropriate DC voltage, the fluctuation of the voltage V2 can be ensured within a certain range, that is, by controlling the control signal Vramp to change within an appropriate range, so as to ensure that the error amplifier in the DC-DC converter always operates in a normal state.

[0081] The on and off of the first control switch S1 and the second control switch S2 in the control signal generation module 2 are controlled by the control signal VT1 and the control signal VT2 respectively. As shown in Figure 5(a), when the output voltage Vout is less than half of the input voltage Vin, that is, when the duty cycle is less than 50%, no slope compensation is required. Therefore, the first control switch S1 controlled by the control signal VT1 is in a normally on state, and the voltage V2 (the first voltage) is directly output as the control signal Vramp. At this time, the second control switch S2 controlled by the control signal VT2 is in a normally off state, blocking the slope compensation current Iramp. Therefore, when the duty cycle is less than 50%, the control signal Vramp is:

[0082] (5)

[0083] As shown in Figure 5(b), when the duty cycle is greater than or equal to 50%, at the end of each switching period T, the control signal VT1 generates a high-level pulse signal, and the first control switch S1 conducts instantaneously, clearing the charge on the first capacitor C1, that is, pulling the control signal Vramp to the voltage V2. At the same time, the control signal VT2 generates a low-level pulse signal, and the second control switch S2 disconnects instantaneously, blocking the slope compensation current Iramp at the moment when the charge on the first capacitor C1 is cleared. During one period T, except at the end of the period T, the first control switch S1 is in an off state, and the second control switch S2 is in an on state. The first capacitor C1 is charged by the slope compensation current Iramp generated by the adaptive slope compensation circuit to form a compensation voltage. This compensation voltage ΔV C1 is:

[0084] (6)

[0085] Where, Iramp is the ramp compensation current output by the adaptive ramp compensation current generation module 3; C1 is the capacitance value of the first capacitor C1 in this unit circuit; t is the charging time of the first capacitor C1 within a period T.

[0086] This compensation voltage ΔV C1 After being added to the voltage V2 (shown in Formula 4), it is output as the control signal Vramp. Therefore, when the duty cycle is greater than or equal to 50%, within one period, the control signal Vramp is:

[0087] (7)

[0088] The second input terminal of the adaptive ramp compensation current generation module 3 receives the output current signal provided by the first current generation module 5, and scales it to the current I6 through the eighth PMOS transistor PM23. At the same time, the first input terminal of the adaptive ramp compensation current generation module 3 receives the output current signal provided by the second current generation module 6, and scales it to the current I4 through the seventh PMOS transistor PM24. The current I4 passes through the current mirror composed of the third NMOS transistor NM21 and the fourth NMOS transistor NM22, and mirrors the current I4 to the current I5 in a ratio of 1:k1. The difference between the current I6 and the current I5, I6 - I5 = I7. The current I7 passes through the current mirror composed of the fifth NMOS transistor NM23 and the sixth NMOS transistor NM24, and mirrors the current I7 to the current I8 in a ratio of 1:k2. The current 8 passes through the current mirror composed of the ninth PMOS transistor PM25 and the tenth PMOS transistor PM26, and mirrors the current I8 to generate the ramp compensation current Iramp in a ratio of 1:k3, and outputs it to the second input terminal of the control signal generation module 2.

[0089] Based on the above analysis, the relationship between the ramp compensation current Iramp and the current I4 and the current I6 can be obtained as:

[0090] Iramp = k2 * k3(I6 - k1 * I4) (8)

[0091] Among them, the current I6 is a component related to the output voltage Vout of the DC-DC converter, and the current I4 is a component related to the input voltage Vin of the DC-DC converter. Taking the Buck-type DC-DC converter as an example, when the input voltage Vin is constant and the output voltage Vout increases, that is, the duty cycle increases. At this time, the current I4 remains unchanged and the current I6 increases. It can be seen from Equation 8 that the ramp compensation current Iramp will increase. When the output voltage Vout is constant and the input voltage Vin increases, that is, the duty cycle decreases. At this time, the current I6 remains unchanged and the current I4 increases. It can be seen from Equation 8 that the ramp compensation current Iramp will decrease. Therefore, this peak current control circuit can adaptively adjust the magnitude of the ramp compensation current Iramp according to the changes in the input voltage Vin and the output voltage Vout.

[0092] In the above analysis, the currents I4 and I6 are respectively currents that linearly change with the input voltage Vin and the output voltage Vout. These two currents are respectively provided by the second current generation module 6 and the first current generation module 5. The second current generation module 6 and the first current generation module 5 can be implemented by a voltage-current conversion circuit.

[0093] The reference module in the DC voltage adjustment module 4 provides a DC current, which is appropriately scaled through a current mirror composed of the fifth PMOS transistor PM21 and the sixth PMOS transistor PM22 and then outputs the current I3, which is used to change the voltage peak range of the control signal Vramp, so that the error amplifier in the DC-DC converter can work within an appropriate range. Substituting Equation 4 and Equation 8 into Equation 7, the control signal Vramp can be obtained as:

[0094] (9)

[0095] Among them, the first term is the ramp compensation term, the second term is the inductor current I L related term, the third term is the term related to the input voltage Vin, the fourth term is the term related to the output voltage Vout, and the fifth term is the DC voltage adjustment term; and 0 ≤ t ≤ T.

[0096] It can be seen from Equation 9 that by changing the magnitude of the output current I3 of this unit circuit, the range of the control signal Vramp can be adjusted as a whole, so that the control signal Vramp can change within an appropriate working range of the error amplifier in the DC-DC converter.

[0097] The first current generation module 5 and the second current generation module 6 are both voltage-current conversion circuits, which can convert voltage signals into current signals. As shown in Fig. 4(a), the working principle of the voltage-current conversion circuit in the first solution is that a voltage division circuit composed of the third resistor R41 and the fourth resistor R42 forms a divided voltage V41 at its node for the input terminal voltage (Vin or Vout). The node voltage V41 and the node voltage V42 are clamped by the first operational amplifier A to make the voltages at the two points equal. Therefore, the current I flowing through the fifth resistor R43 is I = V41 / R43, and this current is copied (assuming a copying ratio of 1:1) by the current mirror composed of the first PMOS transistor PM41 and the second PMOS transistor PM42 to generate the output current (Iout1 or Iout2), and its output current is represented by Iout as follows:

[0098] (10)

[0099] where Iout is the output current of the voltage-current conversion circuit, and V IN is the input voltage of the voltage-current conversion circuit. When the voltage-current conversion circuit is used in the first current generation module 5, Iout is the second current Iout2, and V IN is the output voltage Vout in the DC-DC converter; when the voltage-current conversion circuit is used in the second current generation module 6, Iout is the first current Iout1, and V IN is the input voltage Vin in the DC-DC converter.

[0100] It can be seen from Equation (10) that the output current Iout of the voltage-current conversion circuit and the input voltage V IN are in a linear relationship. When the first PMOS transistor PM41 in the voltage-current conversion circuit replaces the seventh PMOS transistor PM24 or the eighth PMOS transistor PM23 in the adaptive ramp compensation current generation module 3 circuit (as Figure 3 shown), the output current Iout of the voltage-current conversion circuit can be used as the current I6 or the current I4 in Equation (8).

[0101] As shown in Fig. 4(b), the working principle of the voltage-current conversion circuit in the second solution is similar to that of the first solution. Among them, the sixth resistor R44 and the seventh resistor R45 form a voltage division circuit, the third PMOS transistor PM43 and the fourth PMOS transistor PM44 form a current mirror circuit, and the second NMOS transistor NM42 works as a source follower, that is, the node voltage V44 changes following the change of the node voltage V43. Assuming that the body bias effect and the change of the gate-source voltage of the second NMOS transistor NM42 are ignored, its output terminal current Iout is as follows:

[0102] (11)

[0103] Among them, VgsNM42 is the gate-source voltage of the second NMOS transistor NM42; Iout and V IN represent the same meaning as in Formula 10.

[0104] Similarly, from Formula 11, it can be known that the output current Iout of the voltage-current conversion circuit and the input voltage V IN are in a linear relationship. When the third PMOS transistor PM43 in the voltage-current conversion circuit replaces the seventh PMOS transistor PM24 or the eighth PMOS transistor PM23 in the adaptive ramp compensation current generation module 3 circuit (as Figure 3 shown), the output current Iout of the voltage-current conversion circuit can be used as the current I6 or the current I4 in Formula 8.

[0105] Such as Figure 6 shown, it is the second embodiment provided by the present invention. The peak current control circuit with adaptive ramp compensation includes an inductor current detection module 1, a control signal generation module 2, an adaptive ramp compensation current generation module 3, a DC voltage adjustment module 4, a first current generation module 5, and a second current generation module 6. Among them, except for the adaptive ramp compensation current generation module 3, other module units are the same as the corresponding units in the above first embodiment. The circuit structure and working principle of the adaptive ramp compensation current generation module 3 in this embodiment will be described in detail below, and other module units will not be elaborated.

[0106] In the second embodiment of the present invention, the adaptive ramp compensation current generation module 3 is composed of an eleventh PMOS transistor PM51, a twelfth PMOS transistor PM52, a seventh NMOS transistor NM51, and an eighth NMOS transistor NM52. Among them, the gate of the eleventh PMOS transistor PM51 is connected to the first input terminal of this unit circuit, the gate of the twelfth PMOS transistor PM52 is connected to the second input terminal of this unit circuit, the sources of the eleventh PMOS transistor PM51 and the twelfth PMOS transistor PM52 are both connected to the power supply terminal VDD, the drain of the eleventh PMOS transistor PM51 is connected to the drain of the seventh NMOS transistor NM51, the drain of the seventh NMOS transistor NM51 is short-circuited to the gate and then connected to the gate of the eighth NMOS transistor NM52, the sources of the seventh NMOS transistor NM51 and the eighth NMOS transistor NM52 are both connected to the ground potential terminal, and the drains of the eighth NMOS transistor NM52 and the twelfth PMOS transistor PM52 are both connected to the output terminal of this unit circuit.

[0107] In the adaptive slope compensation current generating module 3, the eleventh PMOS transistor PM51 and the twelfth PMOS transistor PM52 respectively constitute two current scaling units, and the seventh NMOS transistor NM51 and the eighth NMOS transistor NM52 constitute a current difference unit. In the second embodiment of the present invention, no slope compensation current unit is provided, and the output of the current difference unit is directly output to the output end of the unit circuit.

[0108] The working principle of the adaptive slope compensation current generating module 3 is as follows: the second input terminal of the adaptive slope compensation current generating module 3 receives the output current signal provided by the first current generating module 5, and scales it to the current I6 through the twelfth PMOS transistor PM52. At the same time, the first input terminal of the adaptive slope compensation current generating module 3 receives the output current signal provided by the second current generating module 6, and scales it to the current I4 through the eleventh PMOS transistor PM51. The current I4 passes through the current mirror formed by the seventh NMOS transistor NM51 and the eighth NMOS transistor NM52, and the current I4 is mirrored to the current I5 at a ratio of 1:k51. The current signal after the difference between the current I6 and the current I5 is directly used as the slope compensation current Iramp, and is output to the second input terminal of the control signal generating module 2.

[0109] According to the above analysis, it can be concluded that the relationship between the slope compensation current Iramp and the current I4 and the current I6 in the second embodiment of the present invention is:

[0110] Iramp = I6 - k51 * I4 (12)

[0111] Through the above analysis, it can be known that the slope compensation current Iramp shown in formula 12 in this embodiment has the same functional characteristics as the slope compensation current Iramp shown in formula 8 in the first embodiment. Taking the Buck-type DC-DC converter as an example, when the input voltage Vin is constant and the output voltage Vout increases, that is, the duty cycle increases, at this time, the current I4 remains unchanged and the current I6 increases. It can be seen from formula 12 that the slope compensation current Iramp will increase. When the output voltage Vout is constant and the input voltage Vin increases, that is, the duty cycle decreases, at this time, the current I6 remains unchanged and the current I4 increases. It can be seen from formula 12 that the slope compensation current Iramp will decrease. Therefore, the peak current control circuit can adaptively adjust the size of the slope compensation current Iramp according to the changes in the input voltage Vin and the output voltage Vout.

[0112] Compared with the first embodiment, the peak current control circuit provided in the second embodiment of the present invention simplifies the structure of the adaptive slope compensation current generating module 3 and omits the slope compensation current module therein. Therefore, the peak current control circuit provided in the first embodiment has a higher regulation accuracy for the slope compensation current Iramp than the second embodiment.

[0113] Based on the peak current control circuit provided in each of the above embodiments, the present invention further provides a control method for the peak current control circuit to achieve adaptive ramp compensation. As shown in FIG. 7, the control method includes the following steps:

[0114] S1: The inductor current detection module samples the current flowing through the inductor L in the DC-DC converter and converts it into a corresponding output current I0; the first current generation module samples the input voltage Vin of the DC-DC converter and converts it into a corresponding output current I1; the second current generation module samples the output voltage Vout of the DC-DC converter and converts it into a corresponding output current I2; the DC voltage adjustment module outputs a current I3.

[0115] S2: The currents I0, I1, I2, and I3 jointly form a voltage V2 (the first voltage) at the node V2 and provide it to the first input terminal of the control signal generation module; after the currents I1 and I2 are input to the adaptive ramp compensation current generation module, a ramp compensation current Iramp is generated and provided to the second input terminal of the control signal generation module.

[0116] S3: In the DC-DC converter, when the duty cycle is less than 50%, proceed to the next step; when the duty cycle is greater than or equal to 50%, input step S6.

[0117] S4: In the control signal generation module, the switch S1 is in the closed state and the switch S2 is in the open state, and the output control signal Vramp = V2 is provided to the PWM comparator in the control loop.

[0118] S5: Return to step S1.

[0119] S6: Except at the end of each cycle T in the control signal generation module, the switch S1 is in the open state and the switch S2 is in the closed state, and the ramp compensation current Iramp charges the first capacitor C1 to form a compensation voltage ΔV C1 , and the output control signal Vramp = V2 + ΔV C1 , and is provided to the PWM comparator in the control loop.

[0120] S7: Return to step S1.

[0121] The peak current control circuit provided by the present invention realizes real-time adaptive ramp compensation control of the DC-DC converter by cyclically executing sampling of relevant current / voltage signals, generating the control signal Vramp, and providing it to the control loop.

[0122] In order to verify the excellent performance of the peak current control circuit provided by the embodiments of the present invention, the inventor applied this technical solution to a Buck-type DC-DC converter and conducted a simulation test on the control signal Vramp waveform when the duty cycle is greater than or equal to 50%. The test results are shown in Figure 8.

[0123] In Figure 8, the abscissa is time, and the ordinates from top to bottom are the inductor current I L , the node voltage V2, and the control signal Vramp. It can be seen from Figure 8 that the signal waveform of the node voltage V2 can well follow the change of the signal waveform of the inductor current I L . The signal waveform of the control signal Vramp after adaptive ramp compensation can meet the requirements of the stable operation of the loop and avoid the occurrence of sub-harmonic oscillation.

[0124] The embodiments of the present invention further provide a DC-DC converter. This DC-DC converter includes the peak current control circuit with adaptive ramp compensation provided by the present invention as described above. Its function is to adaptively adjust the ramp compensation intensity by sampling the changes in the output voltage and the input voltage, so as to ensure the stable operation of the DC-DC converter. This DC-DC converter can be a Buck-type, Boost-type, Buck-Boost-type, Cuk-type, etc. DC-DC converter with a wide output voltage range. Its circuit also at least includes components such as the switching tube, inductor, and capacitor shown in Figure 1. The specific structure of the peak current control circuit in this DC-DC converter will not be elaborated here.

[0125] In summary, compared with the prior art, the peak current control circuit with adaptive ramp compensation provided by the present invention can, through the collaborative work of each module unit, provide a compensation current that changes with the output voltage and the input voltage when the duty cycle of the DC-DC converter is greater than or equal to 50%, so that the generated ramp compensation amount is always maintained within a suitable range (i.e., between 0.75 and 1 times the slope of the inductor current falling section), so that the overall loop will neither have sub-ramp oscillation due to under-compensation nor affect the transient characteristics of the peak current mode due to over-compensation in a system where the input voltage and the output voltage are variable. At the same time, the present invention can also adjust the voltage range of the control signal Vramp and keep the Vramp signal within a suitable range all the time, so as to ensure the normal operation of the error amplifier. Therefore, the peak current control circuit provided by the present invention has the beneficial effects of ingenious and reasonable circuit design, low design cost, high converter working efficiency, and excellent circuit performance.

[0126] The above has described in detail the peak current control circuit, method and DC-DC converter with adaptive slope compensation provided by the present invention. For those of ordinary skill in the art, any obvious changes made to it without departing from the essence of the present invention will fall within the protection scope of the patent right of the present invention.

Claims

1. An adaptive slope compensation peak current control circuit for the control loop of a DC-DC converter, characterized in that It includes an inductor current detection module, a control signal generation module, an adaptive ramp compensation current generation module, a DC voltage adjustment module, a first current generation module, and a second current generation module; wherein, The inductor current detection module is used to sample the current flowing through the inductor in the DC-DC converter and convert it into a corresponding voltage signal, and output it to the control signal generation module; The first current generation module is used to sample the output voltage of the DC-DC converter and convert it into a corresponding current signal, and output it to the control signal generation module and the adaptive ramp compensation current generation module respectively; The second current generation module is used to sample the input voltage of the DC-DC converter and convert it into a corresponding current signal, and output it to the control signal generation module and the adaptive ramp compensation current generation module respectively; The adaptive ramp compensation current generation module receives the current signals output by the second current generation module and the first current generation module, and generates a ramp compensation current through subtraction or scaling and subtraction, and outputs it to the control signal generation module; The control signal generation module receives the current signals output by the inductor current detection module, the second current generation module, and the first current generation module, as well as the current signals output by the DC voltage adjustment module and the adaptive ramp compensation current generation module, generates a control signal and outputs it to the inverting input terminal of the PWM comparator in the DC-DC converter, for adaptively adjusting the ramp compensation intensity.

2. The peak current control circuit according to claim 1, wherein: The first input terminal and the second input terminal of the inductor current detection module are respectively connected to both ends of the inductor in the DC-DC converter, the input terminal of the first current generation module is connected to the output voltage terminal in the DC-DC converter, the input terminal of the second current generation module is connected to the input voltage terminal in the DC-DC converter, and the output terminal of the control signal generation module is connected to the inverting input terminal of the PWM comparator in the DC-DC converter, forming a control loop.

3. The peak current control circuit according to claim 2, wherein: The inductor current detection module is composed of a first resistor, a second resistor, a second capacitor, and a third capacitor; wherein, one end of the first resistor is connected to the first input terminal of the inductor current detection module, one end of the second capacitor is connected to the second input terminal of the inductor current detection module, the other end of the first resistor and the other end of the second capacitor are commonly connected to the third capacitor, the other end of the third capacitor is connected to the output terminal of the inductor current detection module and the second resistor, the other end of the second resistor is connected to the ground potential terminal, and at the same time, the output terminal of the inductor current detection module is connected to the first input terminal of the control signal generation module.

4. The peak current control circuit according to claim 1, wherein: The DC voltage adjustment module is composed of a reference module, a fifth PMOS transistor, and a sixth PMOS transistor. Among them, the output terminal of the reference module is connected to the drain of the fifth PMOS transistor. The drain of the fifth PMOS transistor is short-circuited to its gate and then connected to the gate of the sixth PMOS transistor. The sources of the fifth PMOS transistor and the sixth PMOS transistor are both connected to the power supply terminal. The drain of the sixth PMOS transistor is connected to the output terminal of the DC voltage adjustment module. At the same time, the output terminal is connected to the first input terminal of the control signal generation module.

5. The peak current control circuit according to claim 1, wherein: The adaptive ramp compensation current generation module is composed of a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. Among them, The gate of the seventh PMOS transistor is connected to the first input terminal of the adaptive ramp compensation current generation module. The gate of the eighth PMOS transistor is connected to the second input terminal of the adaptive ramp compensation current generation module. The sources of the seventh PMOS transistor and the eighth PMOS transistor are both connected to the power supply terminal. The drain of the seventh PMOS transistor is connected to the drain of the third NMOS transistor. The drain of the third NMOS transistor is short-circuited to its gate and then connected to the gate of the fourth NMOS transistor. The sources of the third NMOS transistor and the fourth NMOS transistor are both connected to the ground potential terminal. The drain of the fourth NMOS transistor is connected to the drain of the eighth PMOS transistor and the drain of the fifth NMOS transistor. The drain of the fifth NMOS transistor is short-circuited to its gate and then connected to the gate of the sixth NMOS transistor. The sources of the fifth NMOS transistor and the sixth NMOS transistor are both connected to the ground potential terminal. The drain of the sixth NMOS transistor is connected to the drain of the ninth PMOS transistor. The drain of the ninth PMOS transistor is short-circuited to its gate and then connected to the gate of the tenth PMOS transistor. The sources of the ninth PMOS transistor and the tenth PMOS transistor are both connected to the power supply terminal. The drain of the tenth PMOS transistor is connected to the output terminal of the adaptive ramp compensation current generation module. At the same time, the output terminal is connected to the second input terminal of the control signal generation module.

6. The peak current control circuit according to claim 1, wherein: The control signal generation module is composed of a first capacitor, a first control switch, and a second control switch. Among them, One end of the second control switch is connected to the second input terminal of the control signal generation module. The other end of the second control switch is connected to the first capacitor on the one hand and to the first control switch and the output terminal of the control signal generation module on the other hand. The other end of the first capacitor and the other end of the first control switch are both connected to the first input terminal of the control signal generation module; The on-off states of the first control switch and the second control switch are controlled by a first control signal and a second control signal respectively.

7. The peak current control circuit according to claim 1, wherein: The adaptive ramp compensation current generation module is composed of an eleventh PMOS transistor, a twelfth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; among them, the gate of the eleventh PMOS transistor is connected to the first input terminal of the adaptive ramp compensation current generation module, the gate of the twelfth PMOS transistor is connected to the second input terminal of the adaptive ramp compensation current generation module, the sources of the eleventh PMOS transistor and the twelfth PMOS transistor are both connected to the power supply terminal, the drain of the eleventh PMOS transistor is connected to the drain of the seventh NMOS transistor, the drain of the seventh NMOS transistor is short-circuited to the gate and then connected to the gate of the eighth NMOS transistor, the sources of the seventh NMOS transistor and the eighth NMOS transistor are both connected to the ground potential terminal, and the drains of the eighth NMOS transistor and the twelfth PMOS transistor are both connected to the output terminal of the adaptive ramp compensation current generation module; meanwhile, the output terminal is connected to the second input terminal of the control signal generation module.

8. The peak current control circuit according to any one of claims 1 to 7, characterized in that: When the duty cycle of the DC-DC converter is less than 50%, within each switching period T, the first control signal is a high-level signal, the first control switch is in a normally-conducting state, and the first voltage is directly output as the control signal; meanwhile, the second control signal is a low-level signal, the second control switch is in a normally-off state, and the ramp compensation current is blocked; the control signal Vramp satisfies the following formula: Among them, V2 is the first voltage, I1 is the output current of the second current generation module, I2 is the output current of the first current generation module, I3 is the output current of the DC voltage adjustment module, Vout is the output terminal voltage of the DC-DC converter, F is the switching frequency in the DC-DC converter, L is the inductance value of the inductor in the DC-DC converter, I L is the current flowing through the inductor, R2 is the resistance value of the second resistor, and k is a coefficient related to the resistors and capacitors in the inductor current detection module.

9. The peak current control circuit according to any one of claims 1 to 7, characterized in that: When the duty cycle of the DC-DC converter is greater than or equal to 50%, at the end of each switching period T, the first control signal generates a high-level pulse signal, the first control switch conducts instantaneously, the charge on the first capacitor is cleared, and the control signal is pulled to the first voltage. At the same time, the second control signal generates a low-level pulse signal, the second control switch disconnects instantaneously, and the ramp compensation current is blocked at the moment when the charge on the first capacitor is cleared. During each switching period T, except at the end moment, the first control signal is a low-level signal, the first control switch is in the off state, the second control signal is a high-level signal, the second control switch is in the on state, and the first capacitor is charged by the ramp compensation current to form a compensation voltage. At this time, the sum of the compensation voltage and the first voltage is output as the control signal; the control signal Vramp satisfies the following formula: Wherein, Vout is the output voltage of the DC-DC converter, F is the switching frequency in the DC-DC converter, L is the inductance value of the inductor in the DC-DC converter, I L is the current flowing through the inductor, R2 is the resistance value of the second resistor, k is a coefficient related to the resistors and capacitors in the inductor current detection module, C1 is the capacitance value of the first capacitor, I1 is the output current of the second current generation module, I2 is the output current of the first current generation module, I3 is the output current of the DC voltage adjustment module, I4 is the current after scaling I1, I6 is the current after scaling I2, k1, k2, and k3 are all proportionality coefficients, and 0 ≤ t ≤ T.

10. An adaptive slope compensation peak current control method, implemented based on the peak current control circuit described in any one of claims 1 to 9, characterized in that It includes the following steps: (1) Sample the input voltage, output voltage, and inductor current in the DC-DC converter, and convert them into a first current, a second current, and a third current respectively; the DC voltage adjustment module outputs a fourth current; (2) A first voltage is jointly formed by the first current, the second current, the third current, and the fourth current and provided to the first input terminal of the control signal generation module; the first current and the second current are input to the adaptive ramp compensation current generation module to generate a ramp compensation current and provided to the second input terminal of the control signal generation module; (3) In the DC-DC converter, when the duty cycle is less than 50%, proceed to the next step; When the duty cycle is greater than or equal to 50%, input to step (6); (4) In the control signal generation module, the first control switch is closed and the second control switch is opened, and the output control signal is equal to the first voltage and provided to the PWM comparator in the control loop; (5) Return to step (1); (6) In the control signal generation module, except at the end of each period T, the first control switch is opened and the second control switch is closed, the ramp compensation current charges the first capacitor to form a compensation voltage, and the output control signal is equal to the sum of the first voltage and the compensation voltage and provided to the PWM comparator in the control loop; (7) Return to step (1).

11. A DC-DC converter, characterized in that It includes the peak current control circuit according to any one of claims 1 to 9.

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