A mode switching circuit for peak current mode Buck converter

Abstract

The present invention belongs to the field of integrated circuit technology and power electronics, and specifically relates to a mode switching circuit for a peak current mode Buck converter, including an error amplifier, an oscillator control current generation circuit, a current control oscillator, a peak current limit generation circuit, and a peak current detection circuit. When overloaded, the peak current limit generation circuit plays a major role in generating a peak current limit I that varies with the load. PEAK , the oscillator controls the current generating circuit and the current controlled oscillator generates a fixed frequency pulse signal V osc , realizing PWM mode control of Buck converter; when light load is applied, the oscillator controls the current generation circuit and the current control oscillator to play a major role, generating a pulse signal V with a frequency that varies with the load. osc , the peak current limit generation circuit generates a fixed peak current limit I PEAK , realize the PFM mode control of the Buck converter; the peak current detection circuit is used to detect whether the inductor current reaches the peak current limit I PEAK And generate logic signal PCD.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit technology and power electronics, and specifically relates to a pulse width modulation (PWM) and pulse frequency modulation (PWM) mode switching circuit for a peak current mode Buck converter. Background Art

[0002] Buck DC-DC converters are essential chips in many electronic products today, with advantages such as high efficiency, high power density and wide application range. As the working state of the load circuit changes, the output current of the Buck converter will change greatly. How to ensure the high efficiency of the Buck converter in a wide load range is a current research hotspot.

[0003] The main modulation modes of the Buck converter include PWM mode and PFM mode. The Buck operating frequency in PWM mode is fixed, and the output voltage is modulated by changing the on-time of the power upper tube through feedback. The specific control methods include voltage mode, peak current mode, valley current mode, etc. The PWM mode has the advantages of small ripple, fixed switching noise and electromagnetic interference (EMI) frequency, and easy processing, but has the disadvantage of low efficiency under light load. The Buck in PFM mode modulates the output voltage by changing the switching frequency through feedback. Its light load efficiency is significantly improved compared to PWM, but its output voltage ripple is generally large, and the switching noise and EMI with non-fixed frequency are difficult to handle. Summary of the invention

[0004] In view of the respective advantages and disadvantages of the above-mentioned PWM and PFM modes, the present invention proposes a PWM / PFM mode switching circuit suitable for a peak current mode Buck converter, so that it works in PWM mode under heavy load, with smaller output voltage ripple and EMI characteristics, and works in PFM mode under light load, with higher efficiency, combining the advantages of both modulation modes.

[0005] To achieve the above object, the present invention adopts the following technical solution:

[0006] A PWM / PFM mode switching circuit of a peak current mode Buck converter comprises an error amplifier (EA), an oscillator control current generating circuit, a current control oscillator, a peak current limit generating circuit, and a peak current detection circuit.

[0007] The error amplifier is used to amplify the error between the output voltage and the expected voltage to reduce the steady-state output voltage of the Buck converter. Its in-phase input terminal is connected to the internal reference voltage V REF , the inverting input terminal is connected to the feedback voltage V FB The output is connected to the input end of the oscillator control current generating circuit and the peak current limit generating circuit.

[0008] The oscillator control current generating circuit is used to generate a current according to the output voltage V of EA. EA The corresponding oscillator control current is generated, and its input is connected to the output voltage V generated by EA EA , output oscillator control current I OSC Connect to a fluidically controlled oscillator.

[0009] Specifically, the oscillator controls the current generating circuit, including a first current source I 1 , the second current source I 2 , the first NMOS tube M N1 , the second NMOS tube M N2 , the third NMOS tube M N3 , the first PMOS tube M P1 , the second PMOS tube M P2 ; The first current source I 1 The current input end is connected to the internal power supply VDD, and the current outflow end is connected to the second NMOS tube M N2 The drain and gate of the third NMOS tube M N3 The gate of the second current source I 2 The current input terminal is connected to the second PMOS tube M P2 The drain and oscillator control current generation circuit current output port I OSC , its current outflow end is grounded; the first NMOS tube M N1 The gate connection EA output voltage V EA And the third NMOS tube M N3 The source of the second NMOS tube M N2 The source of the third NMOS tube M N3 The drain of the first PMOS tube M P1 The drain and gate of the second PMOS tube M P2 The gate of the node is marked as the first node, and the voltage is V 1 ; The first PMOS tube M P1 The source of the second PMOS tube M P2 The sources are connected to the power supply VDD.

[0010] The current controlled oscillator is used to control the current I according to the oscillator OSC, generating a periodic pulse signal V with a frequency inversely proportional to it OSC , to achieve PFM mode control for the Buck converter. Its input is the oscillator control current I generated by the oscillator control current generation circuit. OSC , output periodic pulse signal V OSC Connect to logic and driver modules.

[0011] The peak current limit generating circuit is used to generate a peak current according to the output voltage V EA The corresponding peak current limit is generated, and its input is connected to the output voltage V generated by EA EA , output peak current limit I PEAK Connect to peak current sensing circuit.

[0012] Specifically, the peak current limit generating circuit includes a third current source I 3 , the fourth current source I 4 , the fourth NMOS tube M N4 , the fifth NMOS tube M N5 , the sixth NMOS tube M N6 , the third PMOS tube M P3 , the fourth PMOS tube M P4 , the fifth PMOS tube M P5 , the first resistor R 1 ; The third current source I 3 The current input end is connected to the internal power supply VDD, and the current outflow end is connected to the fourth NMOS tube M N4 The drain of the third PMOS tube M P3 The drain of the fourth PMOS tube M P4 And the fifth PMOS tube M P5 The gate of the fourth current source I 4 The current input end is connected to the internal power supply VDD, and the current outflow end is connected to the fifth NMOS tube M N5 The drain and gate of the sixth NMOS tube M N6 The gate of the fifth PMOS tube M P5 The drain of the fourth NMOS tube M N4 The gate connection EA output voltage V EA , whose source is connected to the fourth PMOS tube M P4 The drain node is connected to the first resistor R 1 Ground; fifth NMOS tube M N5 , the sixth NMOS tube M N6 The sources of the sixth NMOS tube M are grounded; N6 The drain of the peak current limit generating circuit is connected to the current output port I PEAK ; The third PMOS tube M P3The gate of the oscillator is connected to the first node V of the oscillator control current generating circuit 1 , whose source is connected to the power supply VDD; the fourth PMOS tube M P4 , the fifth PMOS tube M P5 The sources are connected to the power supply VDD.

[0013] The peak current detection circuit is used to detect the inductor current I of the Buck converter. L , and when it exceeds the peak current limit I PEAK The power upper tube NH is turned off when the current is on. Its input is connected to the peak current limit I generated by the peak current limit generation circuit. PEAK , the output logic signal PCD is connected to the logic and driver module.

[0014] Common error amplifiers, current-controlled oscillators, and peak current detection circuit structures are all applicable to the corresponding modules in the present invention, and any embodiments that can achieve the functions described fall within the scope of protection of the present invention.

[0015] In the above scheme, under heavy load conditions, the EA output voltage is high, and the peak current limit generation circuit plays a major role, generating a peak current limit I that changes with the EA output voltage. PEAK , the oscillator controls the current generating circuit and the current controlled oscillator generates a fixed frequency pulse signal V osc Realize PWM mode control of Buck converter; Under light load conditions, EA output voltage is low, oscillator control current generation circuit and current control oscillator play a major role, generating a pulse signal V with a frequency that changes with EA output voltage osc , the peak current limit generation circuit generates a fixed peak current limit I PEAK The PFM mode of the Buck converter is realized; the peak current detection circuit is used to detect whether the inductor current reaches the peak current limit I PEAK And generate logic signal PCD.

[0016] The beneficial effects of the present invention are as follows: the present invention proposes a PWM / PFM mode switching circuit suitable for a peak current mode Buck converter, which can automatically switch its modulation mode according to the load current of the Buck converter, so that the Buck converter works in PWM mode when it is heavily loaded and in PFM mode when it is lightly loaded, thereby combining the advantages of both modulation modes and effectively improving the efficiency of the Buck converter under light load. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of the PWM / PFM mode switching circuit proposed by the present invention;

[0018] Figure 2 A schematic diagram of an application circuit of the present invention in a peak current mode Buck converter;

[0019] Figure 3 This is a schematic diagram of the oscillator control current generation circuit proposed by the present invention;

[0020] Figure 4 This is a schematic diagram of a peak current limit generating circuit proposed by the present invention;

[0021] Figure 5 This is a schematic diagram of the output of the PWM / PFM mode switching circuit proposed in the present invention. DETAILED DESCRIPTION

[0022] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and embodiments:

[0023] The PWM / PFM mode switching circuit proposed by the present invention is suitable for a peak current mode Buck converter, and its architecture is as follows: Figure 1 As shown, it includes EA, peak current limit generation circuit, peak current detection circuit, oscillator control current generation circuit and current control oscillator, and its input signal is Buck internal reference voltage V REF and feedback voltage V FB , the output is a periodic pulse signal V OSC and logic signal PCD.

[0024] The application circuit of the present invention in the peak current mode Buck converter is as follows: Figure 2 As shown, it includes the present invention, inductor current zero-crossing detection, logic and drive, power upper tube NH, power lower tube NL, first inductor L 1 , the first capacitor C 1 , the second resistor R 2 , the third resistor R 3 Among them, the output signals PCD and V of the inductor current zero-crossing detection of the present invention are OSC , ZCD are connected to the logic and drive module, and are converted by the logic and drive module into drive signals for the power upper tube NH and the power lower tube NL.

[0025] Under heavy load conditions, the Buck converter operates in continuous conduction mode (CCM). At this time, the inductor current is always greater than 0. OSC When the pulse arrives, the upper power tube NH is turned on and the lower power tube NL is turned off; when the inductor current rises to the peak current limit I PEAK When the logic signal PCD changes to a high level, the upper power tube NH is turned off, and the lower power tube NL is turned on. At this time, the frequency generated by the present invention is fixed to f OSC_PWM The pulse signal V OSC And follow V FB Varying peak current limit IPEAK , by the peak current limit I PEAK By adjusting the duty cycle, the Buck converter works in PWM mode.

[0026] When the load decreases, the Buck converter first enters the discontinuous conduction mode (DCM). At this time, the inductor current will decrease to 0 during the opening of the power lower tube NL. The logic signal ZCD output by the inductor current zero-crossing detection becomes high, so that the power upper tube NH and the power lower tube NL are turned off at the same time until the next cycle pulse signal V OSC The pulse arrives, at this time the switching period is still fixed, and the duty cycle is still determined by the peak current limit I PEAK control, still in PWM mode.

[0027] If the load continues to decrease, the peak current limit I PEAK Reduced to the peak current lower limit I PEAK_PFM The Buck converter enters a light load state. At this time, the peak current limit I PEAK No longer changes with the load, but the periodic pulse signal V OSC The frequency f OSC As the load decreases, the duty cycle is controlled by the pulse signal frequency, and the Buck converter operates in PFM mode.

[0028] Figure 3 The oscillator control current generation circuit schematic diagram of the present invention includes a first current source I 1 , the second current source I 2 , the first NMOS tube M N1 , the second NMOS tube M N2 , the third NMOS tube M N3 , the first PMOS tube M P1 , the second PMOS tube M P2 The third NMOS tube M N3 The gate-source voltage V GSN3 for:

[0029] V GSN3 =V DSN1 +V GSN2 -V EA

[0030] Under heavy load conditions, the feedback voltage V FB is too low, the EA output voltage V EA Higher, the first NMOS tube M N1 The gate-source voltage is large, but its drain-source current is fixed at I 1 , then its drain-source voltage V DSN1Very low, while the second NMOS tube M N2 The gate-source voltage V GSN2 Relatively fixed, at this time the third NMOS tube M N3 The gate-source voltage V GSN3 is less than the threshold voltage, no current flows, and the voltage V 1 Close to the power supply VDD, so the oscillator controls the current generation circuit to output current I OSC is a fixed current I 2 , the pulse signal V generated by the current-controlled oscillator OSC The frequency is fixed at f OSC_PWM .

[0031] When the load current decreases to light load, the feedback voltage V FB Increases, the EA output voltage V EA When the first NMOS tube M N1 The drain-source voltage V DSN1 Gradually increase until the third NMOS tube M N3 The gate-source voltage V GSN3 When the threshold voltage is exceeded, current flows, causing the voltage V 1 Reduce, output current I OSC Reduce the pulse signal V generated by the current-controlled oscillator OSC The frequency f OSC Reduced and affected by EA output voltage V EA Control, the circuit enters PFM mode.

[0032] Figure 4 The peak current limit generating circuit schematic diagram of the present invention includes a third current source I 3 , the fourth current source I 4 , the fourth NMOS tube M N4 , the fifth NMOS tube M N5 , the sixth NMOS tube M N6 , the third PMOS tube M P3 , the fourth PMOS tube M P4 , the fifth PMOS tube M P5 , the first resistor R 1 ; The fourth NMOS tube M N4 The gate-source voltage V GSN4 for:

[0033] V GSN4 =V EA -(I 3 +I P4 )R 1

[0034] Among them, I P4 is the current flowing through the fourth PMOS tube MP4 Under light load conditions, the feedback voltage V FB is too high, the EA output voltage V EA Lower, the fourth NMOS tube M N4 The gate-source voltage is small, and the current flowing through it is smaller than the third current source I 3 Therefore, its drain voltage is pulled up to close to the power supply VDD, so that the fourth PMOS tube M P4 And the fifth PMOS tube M P5 The gate-source voltage is also very small and no current will flow through it. Therefore, the output of the peak current limit generating circuit is proportional to the fourth current source I 4 Fixed value I PEAK_PFM .

[0035] When the load current increases to heavy load, the feedback voltage V FB decreases, the EA output voltage V EA When the fourth NMOS tube M N4 The gate-source voltage V GSN4 The drain voltage gradually increases, and the drain voltage gradually decreases until the fifth PMOS tube M P5 The gate-source voltage increases to near the threshold voltage. At this time, the peak current limit of the Buck converter I PEAK The output voltage V EA Controlled current, enters peak current mode PWM control state.

[0036] Among them, the third PMOS tube M P3 and the first resistor R 1 It plays a role in ensuring that the PWM and PFM modulation modes will not be effective at the same time. When working in PWM mode, the third current source I 3 And the fourth PMOS tube M P4 The current flows through the first resistor R 1 The fourth NMOS tube M N4 The source voltage is raised, which requires a higher EA output voltage V EA To work in PWM mode, ensure that the pulse signal V OSC The frequency f OSC is a fixed value; while in PFM mode, the first node voltage V 1 The third PMOS tube M P3 The gate-source voltage of the fourth NMOS tube M is greater than the threshold voltage, and its current N4 The drain node of the transistor is charged and raised, turning off the fifth PMOS transistor M P5 , to ensure the peak current limit I in PFM mode PEAK Will not change with EA output voltage V EA change.

[0037] Figure 5 This is a schematic diagram of the output of the PWM / PFM mode switching circuit proposed in the present invention, where the horizontal axis is the feedback voltage V FB In fact, due to the high gain of EA, the range of the coordinate axis in the figure is generally a few millivolts, corresponding to the static error of the Buck converter output voltage, and the vertical axis is the peak current limit I PEAK And the pulse signal V OSC The frequency f OSC When the load is heavy, the Buck converter output voltage is low and the feedback voltage V FB Also low, pulse signal V OSC The frequency is fixed at f OSC_PWM , the frequency is related to the second current source I 2 The ratio depends on the specific implementation of the current controlled oscillator. The peak current limit I PEAK As the load current increases and the feedback voltage V FB The decrease in the voltage V increases the peak current mode to achieve PWM mode control; when the load is light, the Buck converter output voltage is high, and the feedback voltage V FB The peak current limit is fixed at I PEAK PFM , this current is connected to the fourth current source I 4 The ratio depends on the specific implementation of the peak current detection module. The pulse signal V OSC The frequency f OSC As the load current decreases and the feedback voltage V FB The increase of decreases realizes the PFM mode control of the Buck converter.

Claims

1. A mode switching circuit for a peak current mode Buck converter, characterized in that: It includes an error amplifier, an oscillator control current generating circuit, a current controlled oscillator, a peak current limit generating circuit, and a peak current detecting circuit; The non-inverting input terminal of the error amplifier EA is connected to the internal reference voltage V of the Buck converter. REF , the inverting input terminal is connected to the feedback voltage V FB , the output is connected to the input end of the oscillator control current generating circuit and the peak current limit generating circuit; the output end of the oscillator control current generating circuit is connected to the input end of the current controlled oscillator; The output end of the peak current limit generating circuit is connected to the input end of the peak current detection circuit; the output ends of the current control oscillator and the peak current detection circuit are connected to the logic and driving module; The oscillator control current generating circuit includes a first current source I1, a second current source I2, a first NMOS transistor M N1 , the second NMOS tube M N2 , the third NMOS tube M N3 , the first PMOS tube M P1 , the second PMOS tube M P2 The current input terminal of the first current source I1 is connected to the internal power supply VDD, and the current outflow terminal thereof is connected to the second NMOS tube M N2 The drain and gate of the third NMOS tube M N3 The current input terminal of the second current source I2 is connected to the second PMOS tube M P2 The drain and oscillator control current generation circuit current output port I OSC , its current outflow end is grounded; the first NMOS tube M N1 The gate connection EA output voltage V EA And the third NMOS tube M N3 The source of the second NMOS tube M N2 The source of the third NMOS tube M N3 The drain of the first PMOS tube M P1 The drain and gate of the second PMOS tube M P2 The gate of the first PMOS tube M is marked as the first node, and the voltage is V1; P1 The source of the second PMOS tube M P2 The source electrodes are connected to the power supply VDD; The current controlled oscillator is used to control the current I according to the oscillator OSC , generating a periodic pulse signal V with a frequency inversely proportional to it OSC , realize PFM mode control for Buck converter; The peak current limit generating circuit includes a third current source I3, a fourth current source I4, a fourth NMOS transistor M N4 , the fifth NMOS tube M N5 , the sixth NMOS tube M N6 , the third PMOS tube M P3 , the fourth PMOS tube M P4 , the fifth PMOS tube M P5 , the first resistor R1; the current input terminal of the third current source I3 is connected to the internal power supply VDD, and the current outflow terminal thereof is connected to the fourth NMOS tube M N4 The drain of the third PMOS tube M P3 The drain of the fourth PMOS tube M P4 And the fifth PMOS tube M P5 The current input terminal of the fourth current source I4 is connected to the internal power supply VDD, and the current outflow terminal thereof is connected to the fifth NMOS tube M N5 The drain and gate of the sixth NMOS tube M N6 The gate of the fifth PMOS tube M P5 The drain of the fourth NMOS tube M N4 The gate connection EA output voltage V EA , whose source is connected to the fourth PMOS tube M P4 The drain of the fifth NMOS tube M is connected to the ground through the first resistor R1; N5 , the sixth NMOS tube M N6 The sources of the sixth NMOS tube M are grounded; N6 The drain of the peak current limit generating circuit is connected to the current output port I PEAK ; The third PMOS tube M P3 The gate of the fourth PMOS transistor M is connected to the first node V1 of the oscillator control current generating circuit, and the source thereof is connected to the power supply VDD; P4 , the fifth PMOS tube M P5 The source electrodes are connected to the power supply VDD; The peak current detection circuit is used to detect the inductor current I of the Buck converter. L , and when it exceeds the peak current limit I PEAK The power upper tube is turned off when the peak current limit circuit generates the peak current limit I PEAK , the output logic signal is connected to the logic and driver module.

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