A boost diode clamped five-level inverter and its working method

Abstract

This invention discloses a boost diode-clamped five-level inverter and its operating method, including a DC power supply U in The inverter consists of one capacitor C, one inductor L, eight switching transistors S1-S8, and four clamping diodes D1-D4. Compared to traditional diode-clamped five-level inverters, the proposed inverter replaces the capacitor on the low-side of the DC input with a DC power supply U. in A boost inductor L is connected between the midpoint o and the output terminal a of the right bridge arm. Thus, the DC power supply U... in The inductor L, capacitor C, and switching transistors S5-S8 on the right side of the inverter's bridge arm form a boost circuit. Without altering the switching logic of a traditional five-level inverter, the inductor L can be connected to the DC power supply U through switching transistors S5-S8 with the same duty cycle. in The capacitor C is connected alternately in parallel, so that the voltage across capacitor C is the same as that across the DC power supply U. in Equal and self-balancing are maintained to achieve boost function, producing a voltage gain of 2 times and an amplitude of ±2U. in ±U in The five-level output voltage u of 0 and 0 o .

Description

Technical Field

[0001] This invention relates to the technical field of multilevel inverters, and in particular to a boost diode-clamped five-level inverter and its operating method. Background Technology

[0002] Compared to traditional two-level inverters, multi-level inverters have an output waveform that is closer to a sine wave. They have advantages such as low total harmonic distortion, low loss, and low electromagnetic interference. They are now widely used in fields such as motor drives, new energy power generation, high-voltage transmission systems, and power quality control.

[0003] Traditional multilevel inverter topologies mainly include: diode-clamped, flying capacitor, cascaded H-bridge, and switched capacitor. Among these, diode-clamped and flying capacitor multilevel inverters contain a large number of switching devices and energy storage components, and their capacitor voltage self-balancing capability is poor, requiring auxiliary circuitry to achieve capacitor voltage balancing. Furthermore, neither of these two types of multilevel inverters has boost capability and cannot generate AC output with an amplitude higher than the input DC voltage, thus limiting their application in low-voltage input situations.

[0004] To address the aforementioned problems of traditional multilevel inverters, researching novel multilevel inverter topologies has become an important research issue in multilevel inverter technology. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to address the shortcomings of the prior art by providing a boost diode-clamped five-level inverter and its operating method, so as to solve the problems of poor capacitor voltage self-balancing capability and lack of boost capability of traditional diode-clamped five-level inverters.

[0006] To achieve the above objectives, the specific technical solution of the boost diode-clamped five-level inverter and its operating method of the present invention is as follows:

[0007] A boost diode-clamped five-level inverter includes a DC power supply U in Inductor L, capacitor C, clamping diodes D1, D2, D3, and D4, and the switching transistors S1, S2, S3, and S4 of the left bridge arm and S5, S6, S7, and S8 of the right bridge arm.

[0008] The first terminal of switching transistor S1, the first terminal of capacitor C, and the first terminal of switching transistor S5 are connected. The positive terminal of clamping diode D1, the first terminal of inductor L, and the negative terminal of clamping diode D2 are connected to the third node o. The third node o is connected to the second terminal of capacitor C and the DC power supply U. inThe positive terminal is connected, and the second terminal of both switching transistor S4 and switching transistor S8 is connected to the DC power supply U. in The negative terminal of clamping diode D1 is connected to the second terminal of switching transistor S1 and the first terminal of switching transistor S2. The second terminal of switching transistor S2 and the first terminal of switching transistor S3 are connected to the second node b. The positive terminal of clamping diode D2 is connected to the second terminal of switching transistor S3 and the first terminal of switching transistor S4.

[0009] The negative terminal of clamping diode D3 is connected to the second terminal of switching transistor S5 and the first terminal of switching transistor S6. The positive terminal of clamping diode D3 is connected to the first terminal of inductor L and the negative terminal of clamping diode D4. The second terminal of switching transistor S6, the second terminal of inductor L, and the first terminal of switching transistor S7 are connected to the first node a. The positive terminal of clamping diode D4 is connected to the second terminal of switching transistor S7 and the first terminal of switching transistor S8.

[0010] Furthermore, the first node a is the positive voltage output terminal of the five-level inverter, and the second node b is the negative voltage output terminal of the five-level inverter.

[0011] Furthermore, the third pole of switching transistors S1, S2, S3, S4, S5, S6, S7, and S8 is connected to the control signal.

[0012] A method for operating a boost diode-clamped five-level inverter is disclosed. This method, applied to a boost diode-clamped five-level inverter, controls the five-level inverter to have the following seven operating modes:

[0013] Working Mode 1:

[0014] In the left bridge arm, switches S2 and S3 are turned on, while switches S1 and S4 are turned off. The second node b and the third node o are shorted to switch S2 via clamping diode D1 or to switch S3 via clamping diode D2. The voltage u... bo =0;

[0015] In the right bridge arm, switches S6 and S7 are turned on, while switches S5 and S8 are turned off. The first node a and the third node o are shorted to switch S6 via clamping diode D3 or to switch S7 via clamping diode D4. The voltage u... ao =0;

[0016] When the two ends of inductor L are shorted, the current i L With the voltage remaining constant, capacitor C is open-circuited, and the inverter output voltage u... o =u ao -u bo =0;

[0017] Working Mode 2:

[0018] In the left bridge arm, switches S2 and S3 are turned on, while switches S1 and S4 are turned off. The second node b and the third node o are shorted to switch S2 via clamping diode D1 or to switch S3 via clamping diode D2. The voltage u... bo =0;

[0019] In the right bridge arm, switches S5 and S6 are turned on, while switches S7 and S8 are turned off. The first node a is connected to the positive terminal of capacitor C, and the voltage u ao =U in ;

[0020] An inductor L is connected in parallel across a capacitor C to release energy, with a current i L The inverter output voltage u decreases linearly. o =u ao -u bo =U in ;

[0021] Working Mode 3:

[0022] In the left bridge arm, switches S3 and S4 are turned on, while switches S1 and S2 are turned off. The second node b is connected to the DC power supply U. in The negative terminal, voltage u bo =-U in ;

[0023] In the right bridge arm, switches S5 and S6 are turned on, while switches S7 and S8 are turned off. The first node a is connected to the positive terminal of capacitor C, and the voltage u ao =U in ;

[0024] An inductor L is connected in parallel across a capacitor C to release energy, with a current i L The inverter output voltage u decreases linearly. o =u ao -u bo =2U in ;

[0025] Working Mode 4:

[0026] In the left bridge arm, switches S3 and S4 are turned on, while switches S1 and S2 are turned off. The second node b is connected to the DC power supply U. in The negative terminal, voltage u bo =-U in ;

[0027] In the right bridge arm, switches S6 and S7 are turned on, while switches S5 and S8 are turned off. The first node a and the third node o are shorted to switch S6 via clamping diode D3 or to switch S7 via clamping diode D4. The voltage u... ao =0;

[0028] When the two ends of inductor L are shorted, the current i L With the voltage remaining constant, capacitor C is open-circuited, and the inverter output voltage u... o =u ao -u bo =U in ;

[0029] Working Mode 5:

[0030] In the left bridge arm, switches S2 and S3 are turned on, while switches S1 and S4 are turned off. The second node b and the third node o are shorted to switch S2 via clamping diode D1 or to switch S3 via clamping diode D2. The voltage u... bo =0;

[0031] In the right bridge arm, switches S7 and S8 are turned on, while switches S5 and S6 are turned off. The first node a is connected to the DC power supply U. in The negative terminal, voltage u ao =-U in ;

[0032] Inductor L is connected in parallel with DC power supply U in Energy is stored at both ends, with current i L Linear rise, capacitor C open circuit, inverter output voltage u o =u ao -u bo =-U in ;

[0033] Working Mode Six:

[0034] In the left bridge arm, switches S1 and S2 are turned on, while switches S3 and S4 are turned off. The second node b is connected to the positive terminal of capacitor C, and the voltage u bo =U in ;

[0035] In the right bridge arm, switches S7 and S8 are turned on, while switches S5 and S6 are turned off. The first node a is connected to the DC power supply U. in The negative terminal, voltage u ao =-U in ;

[0036] Inductor L is connected in parallel with DC power supply U in Energy is stored at both ends, with current i LThe inverter output voltage u rises linearly. o =u ao -u bo =-2U in ;

[0037] Working Mode 7:

[0038] In the left bridge arm, switches S1 and S2 are turned on, while switches S3 and S4 are turned off. The second node b is connected to the positive terminal of capacitor C, and the voltage u bo =U in ;

[0039] In the right bridge arm, switches S6 and S7 are turned on, while switches S5 and S8 are turned off. The first node a and the third node o are shorted to switch S6 via clamping diode D3 or to switch S7 via clamping diode D4. The voltage u... ao =0;

[0040] When the two ends of inductor L are shorted, the current i L The inverter output voltage u remains unchanged. o =u ao -u bo =-U in .

[0041] Compared with the prior art, the beneficial effects of the present invention are:

[0042] The inverter of this invention consists of a DC power supply U in It consists of a capacitor C, an inductor L, eight switching transistors S1-S8, and four clamping diodes D1-D4. Compared to traditional diode-clamped five-level inverters, the proposed inverter replaces the capacitor on the low-side of the DC input with a DC power supply U. in A boost inductor L is connected between the midpoint o and the output terminal a of the right bridge arm. Thus, the DC power supply U... in The inductor L, capacitor C, and switching transistors S5-S8 on the right side of the inverter's bridge arm form a boost circuit. Without altering the switching logic of a traditional five-level inverter, the inductor L can be connected to the DC power supply U through switching transistors S5-S8 with the same duty cycle. in The capacitor C is connected alternately in parallel, so that the voltage across capacitor C is the same as that across the DC power supply U. in Equal and self-balancing are maintained to achieve boost function, producing a voltage gain of 2 times and an amplitude of ±2U. in ±U in The five-level output voltage u of 0 and 0 o Therefore, compared to traditional diode-clamped five-level inverters, the proposed inverter has boost capability and capacitor voltage self-balancing capability, making control simpler and the output voltage range wider, thus making it applicable to a wider range of scenarios. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the boost diode-clamped five-level inverter topology of the present invention;

[0045] Figure 2 This is a schematic diagram of the equivalent circuit of the boost diode clamped five-level inverter operating mode one of the present invention;

[0046] Figure 3 This is a schematic diagram of the equivalent circuit of the boost diode clamped five-level inverter operating mode two of the present invention;

[0047] Figure 4 This is a schematic diagram of the equivalent circuit of the boost diode clamped five-level inverter operating mode three of the present invention;

[0048] Figure 5 This is a schematic diagram of the equivalent circuit of the boost diode clamped five-level inverter operating mode four of the present invention;

[0049] Figure 6 This is a schematic diagram of the equivalent circuit of the boost diode clamped five-level inverter operating mode five of the present invention;

[0050] Figure 7 This is a schematic diagram of the equivalent circuit of the boost diode clamped five-level inverter operating mode six of the present invention;

[0051] Figure 8 This is a schematic diagram of the equivalent circuit of the boost diode clamped five-level inverter operating mode seven of the present invention. Detailed Implementation

[0052] To better understand the purpose, structure, and function of this invention, the following detailed description of a boost diode-clamped five-level inverter and its operating method is provided in conjunction with the accompanying drawings and specific preferred embodiments.

[0053] Example 1:

[0054] Please see Figure 1 This invention provides a technical solution: a boost diode-clamped five-level inverter, including a DC power supply U inInductor L, capacitor C, clamping diodes D1, D2, D3, and D4, and the switching transistors S1, S2, S3, and S4 of the left bridge arm and S5, S6, S7, and S8 of the right bridge arm.

[0055] The first terminal of switching transistor S1, the first terminal of capacitor C, and the first terminal of switching transistor S5 are connected. The positive terminal of clamping diode D1, the first terminal of inductor L, and the negative terminal of clamping diode D2 are connected to the third node o. The third node o is connected to the second terminal of capacitor C and the DC power supply U. in The positive terminal is connected, and the second terminal of both switching transistor S4 and switching transistor S8 is connected to the DC power supply U. in The negative terminal of clamping diode D1 is connected to the second terminal of switching transistor S1 and the first terminal of switching transistor S2. The second terminal of switching transistor S2 and the first terminal of switching transistor S3 are connected to the second node b. The positive terminal of clamping diode D2 is connected to the second terminal of switching transistor S3 and the first terminal of switching transistor S4.

[0056] The negative terminal of clamping diode D3 is connected to the second terminal of switching transistor S5 and the first terminal of switching transistor S6. The positive terminal of clamping diode D3 is connected to the first terminal of inductor L and the negative terminal of clamping diode D4. The second terminal of switching transistor S6, the second terminal of inductor L, and the first terminal of switching transistor S7 are connected to the first node a. The positive terminal of clamping diode D4 is connected to the second terminal of switching transistor S7 and the first terminal of switching transistor S8.

[0057] Furthermore, the first node a is the positive voltage output terminal of the five-level inverter, and the second node b is the negative voltage output terminal of the five-level inverter.

[0058] Furthermore, the third pole of switching transistors S1, S2, S3, S4, S5, S6, S7, and S8 is connected to the control signal.

[0059] Example 2:

[0060] Please see Figure 1-8 Based on Example 1, the solution will be described in conjunction with specific embodiments to further demonstrate its technical effectiveness. In the figure, U... C Let i be the voltage across capacitor C. L Let be the current flowing through inductor L.

[0061] like Figure 1 As shown, the inverter of the present invention consists of a DC power supply U inIt consists of a capacitor C, an inductor L, eight switching transistors S1-S8, and four clamping diodes D1-D4. Compared to traditional diode-clamped five-level inverters, the proposed inverter replaces the capacitor on the low-side of the DC input with a DC power supply U. in A boost inductor L is connected between the midpoint o and the output terminal a of the right bridge arm. Thus, the DC power supply U... in The inductor L, capacitor C, and switching transistors S5-S8 on the right side of the inverter's bridge arm form a boost circuit. Without altering the switching logic of a traditional five-level inverter, the inductor L can be connected to the DC power supply U through switching transistors S5-S8 with the same duty cycle. in The capacitor C is connected alternately in parallel, so that the voltage across capacitor C is the same as that across the DC power supply U. in Equal and self-balancing are maintained to achieve boost function, producing a voltage gain of 2 times and an amplitude of ±2U. in ±U in The five-level output voltage u of 0 and 0 o Therefore, compared to traditional diode-clamped five-level inverters, the proposed inverter has boost capability and capacitor voltage self-balancing capability.

[0062] The switching logic of the switching transistors corresponding to each output level of the inverter is shown in Table 1:

[0063] Table 1. Switching states corresponding to each operating mode of the inverter

[0064]

[0065] A method for operating a boost-type diode-clamped five-level inverter, wherein "1" and "0" of each switch transistor represent its on and off states, respectively, and "↑", "↓", and "—" of the inductor L represent its energy storage, energy release, and short-circuit states, respectively; the working principle of each operating mode is analyzed as follows:

[0066] Working Mode 1: such as Figure 2 As shown;

[0067] In the left bridge arm, switches S2 and S3 are turned on, while switches S1 and S4 are turned off. The second node b and the third node o are shorted to switch S2 via clamping diode D1 or to switch S3 via clamping diode D2. The voltage u... bo =0;

[0068] In the right bridge arm, switches S6 and S7 are turned on, while switches S5 and S8 are turned off. The first node a and the third node o are shorted to switch S6 via clamping diode D3 or to switch S7 via clamping diode D4. The voltage u... ao =0;

[0069] When the two ends of inductor L are shorted, the current i L With the voltage remaining constant, capacitor C is open-circuited, and the inverter output voltage u... o =u ao -u bo =0;

[0070] Working Mode 2: such as Figure 3 As shown;

[0071] In the left bridge arm, switches S2 and S3 are turned on, while switches S1 and S4 are turned off. The second node b and the third node o are shorted to switch S2 via clamping diode D1 or to switch S3 via clamping diode D2. The voltage u... bo =0;

[0072] In the right bridge arm, switches S5 and S6 are turned on, while switches S7 and S8 are turned off. The first node a is connected to the positive terminal of capacitor C, and the voltage u ao =U in ;

[0073] An inductor L is connected in parallel across a capacitor C to release energy, with a current i L The inverter output voltage u decreases linearly. o =u ao -u bo =U in ;

[0074] Working Mode 3: such as Figure 4 As shown;

[0075] In the left bridge arm, switches S3 and S4 are turned on, while switches S1 and S2 are turned off. The second node b is connected to the DC power supply U. in The negative terminal, voltage u bo =-U in ;

[0076] In the right bridge arm, switches S5 and S6 are turned on, while switches S7 and S8 are turned off. The first node a is connected to the positive terminal of capacitor C, and the voltage u ao =U in ;

[0077] An inductor L is connected in parallel across a capacitor C to release energy, with a current i L The inverter output voltage u decreases linearly. o =u ao -u bo =2U in ;

[0078] Working Mode 4: such as Figure 5 As shown;

[0079] In the left bridge arm, switches S3 and S4 are turned on, while switches S1 and S2 are turned off. The second node b is connected to the DC power supply U. in The negative terminal, voltage u bo =-U in ;

[0080] In the right bridge arm, switches S6 and S7 are turned on, while switches S5 and S8 are turned off. The first node a and the third node o are shorted to switch S6 via clamping diode D3 or to switch S7 via clamping diode D4. The voltage u... ao =0;

[0081] When the two ends of inductor L are shorted, the current i L With the voltage remaining constant, capacitor C is open-circuited, and the inverter output voltage u... o =u ao -u bo =U in ;

[0082] Working Mode 5: such as Figure 6 As shown;

[0083] In the left bridge arm, switches S2 and S3 are turned on, while switches S1 and S4 are turned off. The second node b and the third node o are shorted to switch S2 via clamping diode D1 or to switch S3 via clamping diode D2. The voltage u... bo =0;

[0084] In the right bridge arm, switches S7 and S8 are turned on, while switches S5 and S6 are turned off. The first node a is connected to the DC power supply U. in The negative terminal, voltage u ao =-U in ;

[0085] Inductor L is connected in parallel with DC power supply U in Energy is stored at both ends, with current i L Linear rise, capacitor C open circuit, inverter output voltage u o =u ao -u bo =-U in ;

[0086] Working Mode Six: such as Figure 7 As shown;

[0087] In the left bridge arm, switches S1 and S2 are turned on, while switches S3 and S4 are turned off. The second node b is connected to the positive terminal of capacitor C, and the voltage u bo =U in ;

[0088] In the right bridge arm, switches S7 and S8 are turned on, while switches S5 and S6 are turned off. The first node a is connected to the DC power supply U. in The negative terminal, voltage u ao =-U in ;

[0089] Inductor L is connected in parallel with DC power supply U in Energy is stored at both ends, with current i L The inverter output voltage u rises linearly. o =u ao -u bo =-2U in ;

[0090] Working Mode 7: such as Figure 8 As shown;

[0091] In the left bridge arm, switches S1 and S2 are turned on, while switches S3 and S4 are turned off. The second node b is connected to the positive terminal of capacitor C, and the voltage u bo =U in ;

[0092] In the right bridge arm, switches S6 and S7 are turned on, while switches S5 and S8 are turned off. The first node a and the third node o are shorted to switch S6 via clamping diode D3 or to switch S7 via clamping diode D4. The voltage u... ao =0;

[0093] When the two ends of inductor L are shorted, the current i L The inverter output voltage u remains unchanged. o =u ao -u bo =-U in .

[0094] Capacitor voltage analysis:

[0095] according to Figure 2-8 From the equivalent circuits of the inverter's various operating modes, we can see that the voltage u across the inductor L is [value missing] in operating modes two and three. L =-U C Under operating modes five and six, the voltage u across the inductor L L =U in Assume the combined duration of inverter operating modes two and three is t. p The combined duration of working modes five and six is ​​t. n .

[0096] Based on the symmetry of the positive and negative output levels of the inverter, we know that: t p =t n (Equation 1)

[0097] Under steady state, according to the volt-second balance principle of inductors, we can obtain: -U C t p +U in t n =0; (Equation 2)

[0098] Substituting equation 1 into equation 2, we can obtain: U C =U in (Equation 3)

[0099] Equation 3 illustrates the average capacitor voltage U C With DC power supply voltage U in The values ​​are equal and balanced, verifying the correctness of the above content. It also shows that the proposed inverter has boost capability and capacitor voltage self-balancing capability compared with the traditional diode-clamped five-level inverter.

[0100] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A boost diode-clamped five-level inverter, characterized in that: Including DC power supply U in Inductor L, capacitor C, clamping diodes D1, D2, D3, and D4, and the switching transistors S1, S2, S3, and S4 of the left bridge arm and S5, S6, S7, and S8 of the right bridge arm. The first terminal of switching transistor S1, the first terminal of capacitor C, and the first terminal of switching transistor S5 are connected. The positive terminal of clamping diode D1, the first terminal of inductor L, and the negative terminal of clamping diode D2 are connected to the third node o. The third node o is connected to the second terminal of capacitor C and the DC power supply U. in The positive terminal is connected, and the second terminal of both switching transistor S4 and switching transistor S8 is connected to the DC power supply U. in The negative terminal of clamping diode D1 is connected to the second terminal of switching transistor S1 and the first terminal of switching transistor S2. The second terminal of switching transistor S2 and the first terminal of switching transistor S3 are connected to the second node b. The positive terminal of clamping diode D2 is connected to the second terminal of switching transistor S3 and the first terminal of switching transistor S4. The negative terminal of clamping diode D3 is connected to the second terminal of switching transistor S5 and the first terminal of switching transistor S6. The positive terminal of clamping diode D3 is connected to the first terminal of inductor L and the negative terminal of clamping diode D4. The second terminal of switching transistor S6, the second terminal of inductor L, and the first terminal of switching transistor S7 are connected to the first node a. The positive terminal of clamping diode D4 is connected to the second terminal of switching transistor S7 and the first terminal of switching transistor S8. The first node a is the positive voltage output terminal of the five-level inverter, and the second node b is the negative voltage output terminal of the five-level inverter.

2. The boost diode-clamped five-level inverter according to claim 1, characterized in that, The third pole of switching transistors S1, S2, S3, S4, S5, S6, S7, and S8 is connected to the control signal.

3. The operating method of the boost diode-clamped five-level inverter according to any one of claims 1-2, characterized in that, The five-level inverter has the following seven operating modes, specifically: Working Mode 1: In the left bridge arm, switches S2 and S3 are turned on, while switches S1 and S4 are turned off. The second node b and the third node o are shorted to switch S2 via clamping diode D1 or to switch S3 via clamping diode D2. The voltage u... bo =0; In the right bridge arm, switches S6 and S7 are turned on, while switches S5 and S8 are turned off. The first node a and the third node o are shorted to switch S6 via clamping diode D3 or to switch S7 via clamping diode D4. The voltage u... ao =0; When the two ends of inductor L are shorted, the current i L With the voltage remaining constant, capacitor C is open-circuited, and the inverter output voltage u... o =u ao -u bo =0; Working Mode 2: In the left bridge arm, switches S2 and S3 are turned on, while switches S1 and S4 are turned off. The second node b and the third node o are shorted to switch S2 via clamping diode D1 or to switch S3 via clamping diode D2. The voltage u... bo =0; In the right bridge arm, switches S5 and S6 are turned on, while switches S7 and S8 are turned off. The first node a is connected to the positive terminal of capacitor C, and the voltage u ao =U in ; An inductor L is connected in parallel across a capacitor C to release energy, with a current i L The inverter output voltage u decreases linearly. o =u ao -u bo =U in ; Working Mode 3: In the left bridge arm, switches S3 and S4 are turned on, while switches S1 and S2 are turned off. The second node b is connected to the DC power supply U. in The negative terminal, voltage u bo =-U in ; In the right bridge arm, switches S5 and S6 are turned on, while switches S7 and S8 are turned off. The first node a is connected to the positive terminal of capacitor C, and the voltage u ao =U in ; An inductor L is connected in parallel across a capacitor C to release energy, with a current i L The inverter output voltage u decreases linearly. o =u ao -u bo =2U in ; Working Mode 4: In the left bridge arm, switches S3 and S4 are turned on, while switches S1 and S2 are turned off. The second node b is connected to the DC power supply U. in The negative terminal, voltage u bo =-U in ; In the right bridge arm, switches S6 and S7 are turned on, while switches S5 and S8 are turned off. The first node a and the third node o are shorted to switch S6 via clamping diode D3 or to switch S7 via clamping diode D4. The voltage u... ao =0; When the two ends of inductor L are shorted, the current i L With the voltage remaining constant, capacitor C is open-circuited, and the inverter output voltage u... o = u ao -u bo =U in ; Working Mode 5: In the left bridge arm, switches S2 and S3 are turned on, while switches S1 and S4 are turned off. The second node b and the third node o are shorted to switch S2 via clamping diode D1 or to switch S3 via clamping diode D2. The voltage u... bo =0; In the right bridge arm, switches S7 and S8 are turned on, while switches S5 and S6 are turned off. The first node a is connected to the DC power supply U. in The negative terminal, voltage u ao =-U in ; Inductor L is connected in parallel with DC power supply U in Energy is stored at both ends, with current i L Linear rise, capacitor C open circuit, inverter output voltage u o =u ao -u bo =-U in ; Working Mode Six: In the left bridge arm, switches S1 and S2 are turned on, while switches S3 and S4 are turned off. The second node b is connected to the positive terminal of capacitor C, and the voltage u bo =U in ; In the right bridge arm, switches S7 and S8 are turned on, while switches S5 and S6 are turned off. The first node a is connected to the DC power supply U. in The negative terminal, voltage u ao =-U in ; Inductor L is connected in parallel with DC power supply U in Energy is stored at both ends, with current i L The inverter output voltage u rises linearly. o =u ao -u bo =-2U in ; Working Mode 7: In the left bridge arm, switches S1 and S2 are turned on, while switches S3 and S4 are turned off. The second node b is connected to the positive terminal of capacitor C, and the voltage u bo =U in ; In the right bridge arm, switches S6 and S7 are turned on, while switches S5 and S8 are turned off. The first node a and the third node o are shorted to switch S6 via clamping diode D3 or to switch S7 via clamping diode D4. The voltage u... ao =0; When the two ends of inductor L are shorted, the current i L The inverter output voltage u remains unchanged. o =u ao -u bo =-U in .

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