3db out-of-band amplified low power programmable gain amplifier

Abstract

A low-power programmable gain amplifier (PGA) with 3dB out-of-band amplification is based on a second-generation current conveyor structure of foldable source follower, which comprises a common-mode feedback loop, a DC offset self-calibration loop, a fast start circuit and a dynamic bias circuit. The programmable gain amplifier amplifies narrow-band signals with 3dB out-of-band, changes the bandwidth by adjusting the tail current with digital signals, and then changes the gain size, thereby building a bridge between power consumption and gain. The gain and power consumption are positively correlated, and the effect of dynamic low power consumption is achieved. The common-mode feedback loop controls the PGA output DC point at V DD / 2, so that the PGA output has the maximum swing. The DC offset self-calibration loop suppresses the output DC offset of the PGA through voltage-current negative feedback. The fast start circuit is used to ensure smooth and fast start of the PGA. The dynamic bias circuit is used to provide current bias to control the gain of the PGA.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication technology, specifically relating to a low-power programmable gain amplifier with 3dB out-of-band amplification. Background Technology

[0002] In wireless communication systems, the signal strength received by the receiver can vary significantly due to changes in the surrounding environment or transmission power. If the receiver's signal receiving link gain is fixed, a strong signal can easily cause nonlinear distortion of the signal waveform, leading to amplifier output saturation, large signal blocking, or even damage to the receiver. Conversely, a weak signal can easily be overwhelmed by noise, preventing subsequent circuits from demodulating it. Therefore, an automatic gain control circuit needs to be added to the receiving link to appropriately control the gain. When the input signal is weak, the receiver gain should be increased; when the input signal is strong, the receiver gain should be appropriately decreased to keep the received signal level within a reasonable range.

[0003] Traditional programmable gain amplifiers (PGAs) typically use digital signals to control a resistor array, changing the feedback coefficient to alter the gain and amplify the received signal within its band, without changing power consumption. When the received signal is strong, the PGA still operates at high power consumption, wasting receiver power.

[0004] Currently, commonly used technologies include PGA gain adjustment methods such as: (1) Resistive PGA: The maximum gain of the amplifier is determined by the resistance ratio of the negative feedback resistor divider in the fully balanced differential amplifier. The gain of the amplifier is programmable by attenuating the input signal through the resistor switch array module. (2) Capacitive PGA: A single-stage amplification structure is adopted, and the gain is variable by changing the ratio of the feedback capacitor and the output capacitor. (3) Regenerative PGA: In the sampling stage, the input signal is sampled and primary amplification is achieved through the sampling capacitor and the first-stage amplifier. In the regenerative amplification stage, the cross-coupling pair causes the sampling capacitor and the negative resistor to form a shunt, generating a negative time constant, which causes the output voltage to increase exponentially. The dB linear gain control is achieved by controlling the regeneration time. All three types of PGA amplification achieve signal amplification within the 3dB band. For high-frequency signals, a high bandwidth design is required, which is not conducive to reducing power consumption. Moreover, the gain change of the PGA is not significantly related to the power consumption of the PGA. Summary of the Invention

[0005] The PGA of this invention achieves signal amplification outside the 3dB band, thus greatly reducing the bandwidth requirement of the PGA and making it suitable for amplifying narrowband signals. By changing the tail current source of the amplification, the bandwidth of the PGA is changed, thereby changing the gain. Power consumption and gain are linked. When the required gain decreases, the tail current source is reduced, power consumption is reduced, and the purpose of dynamic power saving is achieved.

[0006] The problem solved by this invention is:

[0007] Traditional programmable gain amplifiers (PGAs) change the gain by altering the feedback coefficient, but power consumption and gain are not clearly correlated. Even when achieving low-gain amplification, power consumption remains high, resulting in wasted power and negatively impacting system endurance. Low-power PGAs with 3dB out-of-band amplification amplify narrowband signals at 3dB out-of-band. By controlling the bias current with a digital signal, the bandwidth is changed, thereby altering the signal gain. This links amplifier power consumption to gain: increasing the bias current increases power consumption and voltage gain; decreasing the bias current decreases power consumption and voltage gain. For signals of different strengths, gain adjustment is achieved by changing the power consumption, giving the PGA its low-power characteristics.

[0008] The low-power programmable gain amplifier with 3dB out-of-band amplification proposed in this invention amplifies the received signal at 3dB out-of-band. The amplifier bandwidth is changed by controlling the tail current through digital signals, which changes the out-of-band voltage gain of the PGA. The gain of the PGA is linked to the power consumption, and the gain is dynamically changed according to the received signal magnitude to save power consumption, thus achieving low-power operation.

[0009] The technical solution of this invention is:

[0010] A low-power programmable gain amplifier with 3dB out-of-band amplification is disclosed. The programmable gain amplifier is designed based on a second-generation current transmitter structure with a foldable source follower, exhibiting high bandwidth and low power consumption characteristics. It also includes a common-mode feedback loop, a DC offset self-calibration loop, a fast startup circuit, and a dynamic bias circuit. The programmable gain amplifier amplifies narrowband signals at 3dB out-of-band. By adjusting the tail current with a digital signal, the bandwidth is changed, thereby altering the gain. This bridges the gap between power consumption and gain, showing a positive correlation between them and achieving dynamic low power consumption. The common-mode feedback loop controls the PGA output DC point at V... DD / 2, allowing the PGA output to have maximum swing. The DC offset self-calibration loop suppresses the PGA output DC offset through voltage-current negative feedback. The fast start-up circuit ensures a smooth and rapid start-up of the PGA. The dynamic bias circuit provides current bias to control the PGA gain.

[0011] The second-generation current transmitter of the foldable source follower is based on the PGA structure. M3 and M4 are source followers, and M5 and M6 provide negative feedback for the source followers, giving them extremely low output impedance. The source follower transmits the input signal V... in Copying to the sources of M3 and M4 generates V on R1. inThe current from R1 flows through M5 and M6 to form a loop, which is then replicated to the drain terminals of M9 and M13 via a current mirror. Due to the high output impedance of its sleeve-type output stage, it can be assumed that all the output current flows to the load of the PGA, including two paths: R4, R5 and R2, C1, R3. R4 and R5 have lower impedance, so it can be assumed that all the PGA output current flows into this path, forming V... out This achieves voltage amplification.

[0012] The common-mode feedback loop includes: DC sampling resistors R4 and R5, used to sample V. out The common-mode voltage; a five-transistor operational amplifier whose inputs are the sampled common-mode voltage and the reference level V. DD / 2, the output is the gate of M7 and M11, used to form a common-mode feedback loop with the branch containing M7 and M11, setting the output DC operating point at V. DD / 2 places, making V out It has the largest swing; Miller capacitor C2 is needed because the loop consists of two single-pole amplifiers of the same stage, so C2 is required to adjust the phase margin of the loop and ensure the stability of the loop.

[0013] The DC offset self-calibration loop includes C1, R2, and R3, which form a low-pass filter to reduce V. out The DC signal is sampled across C1 and applied to the gates of M1 and M2. M1 and M2 convert the output DC offset voltage into a small DC signal current, which cancels out the small signal current generated by the DC input offset voltage. This achieves voltage-current negative feedback for the DC signal, reduces the gain of the DC offset voltage, and avoids the saturation problem of the subsequent circuit.

[0014] The fast-start circuit includes C3, which, together with R4 and R5, forms an RC charging network to slow down V after power-on. out The voltages at the two nodes make V out In more than V cm Afterwards, M1 and M2 do not enter the off state, but M7 and M11 are turned off. Therefore, current mirrors M10 and M14 can control V. out Scroll down to V cm This ensures the smooth and rapid launch of the PGA.

[0015] The aforementioned dynamic bias circuit provides dynamic bias current to the PGA to achieve dynamic gain. It is a 5-bit current-to-analog converter. Its input is a 5-bit digital signal, and its output is a 32-level bias current, with an output current I... out The load is a current mirror that provides bias to the PGA. This module employs a low-dropout linear regulator structure; due to feedback, the voltage across the resistor array is a constant V. DD / 2, which realizes an adjustable tail current source.

[0016] Compared with the prior art, the beneficial technical effects of the present invention are as follows:

[0017] 1) By amplifying narrowband signals outside the 3dB band and adjusting the tail current through digital signals to change the bandwidth, thereby changing the gain, a bridge is built between power consumption and gain. Increasing the tail current increases the power consumption and the gain increases the gain, while decreasing the tail current decreases the gain. The gain and power consumption are positively correlated, achieving a dynamic low power consumption effect.

[0018] 2) In order to suppress DC offset output and avoid saturation of subsequent circuits, the DC offset self-calibration loop converts the output DC offset voltage into a small DC signal current, which cancels out the small signal current generated by the DC input offset voltage, thereby realizing voltage-current negative feedback for DC signals. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the low-power programmable gain amplifier with 3dB out-of-band amplification of the present invention;

[0020] Figure 2 This is a schematic diagram of the common-mode feedback loop of the present invention;

[0021] Figure 3 This is a schematic diagram of the DC offset self-calibration loop of the present invention;

[0022] Figure 4 (a) and (b) are the gain amplitude-frequency response curves of the present invention;

[0023] Figure 5 This is the gain variation curve of the present invention at the carrier wave;

[0024] Figure 6 This is an adaptive control model diagram;

[0025] Figure 7 Here are the system timing diagrams, where (a) is the system timing diagram when the PGA gain is too large, and (b) is the system timing diagram when the PGA gain is too small. Detailed Implementation

[0026] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments, but this should not be construed as limiting the scope of protection of the present invention.

[0027] like Figure 1As shown, this invention provides a low-power programmable gain amplifier with 3dB out-of-band amplification. It amplifies the input signal at 3dB out-of-band and changes the bandwidth, and thus the signal gain, by controlling the bias current with a digital signal. When the input signal is small, increasing the circuit bias current increases power consumption, bandwidth, and the 3dB out-of-band gain; when the input signal is large, decreasing the circuit bias current decreases power consumption, bandwidth, and the 3dB out-of-band gain. Figure 4 As shown in (b). This invention can dynamically save power consumption by adjusting the circuit bias current according to the input signal magnitude to achieve signal amplification and meet the operating requirements of the downstream circuit. The PGA operates in an open-loop state and achieves closed-loop control under the system-level adaptive control algorithm, thus exhibiting extremely low and adaptive power consumption.

[0028] A low-power programmable gain amplifier with 3dB out-of-band amplification is disclosed. The programmable gain amplifier is designed based on a second-generation current transmitter structure with a foldable source follower, exhibiting high bandwidth and low power consumption characteristics. It also includes a common-mode feedback loop, a DC offset self-calibration loop, a fast startup circuit, and a dynamic bias circuit. The programmable gain amplifier amplifies narrowband signals at 3dB out-of-band. By adjusting the tail current with a digital signal, the bandwidth is changed, thereby altering the gain. This bridges the gap between power consumption and gain, showing a positive correlation between them and achieving dynamic low power consumption. The common-mode feedback loop controls the PGA output DC point at V... DD / 2, allowing the PGA output to have maximum swing. The DC offset self-calibration loop suppresses the PGA output DC offset through voltage-current negative feedback. The fast start-up circuit ensures a smooth and rapid start-up of the PGA. The dynamic bias circuit provides current bias to control the PGA gain.

[0029] The second-generation current transmitter 1 with foldable source followers includes source follower input transistors M3 and M4, source follower output transistors M5 and M6, NMOS transistors M9, M10, M13, and M14, and PMOS transistors M7, M8, M11, and M12. Source follower output transistors M5 and M6 provide negative feedback to source follower input transistors M3 and M4, respectively, resulting in extremely low output impedance. NMOS transistors M9, M10, M13, and M14, together with source followers M3, M4, M5, and M6, form a current mirror. PMOS transistors M7, M8, M11, and M12 form a sleeve-type output stage for the current mirror. Input signal V in The signal is copied to the sources of the source follower input transistors M3 and M4, generating V across the source follower load R1. inThe current from R1 flows through the source follower output transistors M5 and M6, forming a circulating current. This current is then replicated through the current mirror to the drains of NMOS transistors M9 and M13. Due to the high output impedance of its sleeve-type output stage, all the output current flows to the PGA load, including two paths: R4, R5 and R2, C1, R3. R4 and R5 have lower impedance, so it can be assumed that all the PGA output current flows into this path, forming V. out This achieves voltage amplification.

[0030] like Figure 4 As shown in (a), M3 and M4 are source followers, and M5 and M6 provide negative feedback for the source followers, giving them extremely low output impedance. The source followers convert the input signal V... in Copying to the sources of M3 and M4 generates V on R1. in The current from R1 flows through M5 and M6 to form a loop, which is then replicated to the drain terminals of M9 and M13 via a current mirror. Due to the high output impedance of its sleeve-type output stage, it can be assumed that all the output current flows to the load of the PGA, including two paths: R4, R5 and R2, C1, R3. R4 and R5 have lower impedance, so it can be assumed that all the PGA output current flows into this path, forming V... out This achieves voltage amplification.

[0031] Common-mode feedback loop 2 includes: DC sampling resistors R4 and R5, used to sample V. out The common-mode voltage, R4 and R5 are connected in series in the differential output V OUT+ and V OUT- Between R4 and R5, a sampled common-mode voltage is generated at the intermediate node.

[0032] A simple five-transistor operational amplifier whose inputs are the sampled common-mode voltage and the reference level V. DD / 2, the output is the gate of PMOS transistors M7 and M11 in the PGA output stage, used to form a common-mode feedback loop with the branch containing M7 and M11, setting the output DC operating point at V. DD / 2 places, making V out It has the largest swing amplitude.

[0033] Miller capacitor C2 is located between the intermediate sampling node of R4 and R5 and the output point of the five-transistor operational amplifier. It is used to adjust the phase margin of the common-mode feedback loop to ensure loop stability.

[0034] To maximize the output swing of the PGA, the common-mode voltage output of common-mode feedback loop 2 should be half the supply voltage. Figure 2 The common-mode feedback loop shown uses a five-transistor op-amp to sample V at the midpoint between R4 and R5. out The common-mode voltage, and Vcm (i.e. V) DD / 2) In comparison, the output of the five-transistor op-amp drives M7 and M11 to form a common-mode feedback loop with the branches containing M7 and M11, making the common-mode output voltage V. cm To lower the dominant pole of the five-transistor op-amp output, a smaller power consumption can be designed to reduce its bandwidth and save power, at the cost of reduced common-mode feedback response speed.

[0035] The DC offset self-calibration loop 3 includes: a low-pass filter composed of capacitor C1, resistors R2 and R3, feedback input POMS transistors M1 and M2, and a programmable gain amplifier (PGA). Figure 3 The impedance of paths C1, R2, and R3 is much greater than that of paths R4 and R5 with a defined gain, and they can be considered as ideal voltage detectors. The low-pass filter will then... out The DC signal is sampled across C1, which can then be used to sample V. out The DC signal (low-frequency signal) acts on the gates of M1 and M2, without responding to relatively high-frequency signals. M1 and M2 convert the output DC offset voltage into a small DC current, which cancels out the small current generated by the DC input offset voltage. This achieves voltage-current negative feedback for the DC (low-frequency) signal, reducing the gain of the DC offset voltage and thus avoiding saturation problems in subsequent circuits. The low-frequency gain of the PGA is suppressed by this loop, so its DC input offset voltage and flicker noise are not amplified to the output stage, ensuring that the PGA DC offset is kept at a sufficiently small level and ensuring system stability. At low frequencies, the PGA is similar to a unity-gain buffer with a feedback coefficient of g. m1 / g m3 It has a large loop gain. The large loop gain suppresses the effects of process, voltage, and temperature, as well as the impact of layout mismatch on PGA performance, giving the PGA good robustness.

[0036] The fast-start circuit 4 includes a starting capacitor C3. C3, R4, and R5 form an RC charging network, which slows down the voltage drop after power-on. out The voltages at the two nodes make V out In more than V cm Afterwards, M1 and M2 do not enter the off state, but M7 and M11 are turned off. Therefore, current mirrors M10 and M14 can control V. out Scroll down to V cm This ensures a smooth and rapid startup of the PGA. Without C3, startup problems may occur during the PGA power-on process: V out With both ports at low voltage, the output port of the five-transistor op-amp is also at low voltage, causing M7 and M11 to turn on. V outBoth nodes have sufficient pull-up current, but their pull-down current is limited by the bias current provided by the DAC, therefore V out The voltage at both ports will rise sharply when V out Greater than V cm When the output of the five-transistor op-amp is pulled up, M7 and M11 tend to turn off from fully open. However, this process takes some time, during which V... out It is still rising. At the same time, the gate voltages of M1 and M2 will also increase with V. out An increase causes M1 and M2 to tend to turn off, and the turning off of M1 and M2 will cause V to... out Without the pull-down current, the pull-up of the five-transistor op amp will also cause V to... out Losing pull-up current may eventually lead to V out When the voltage is close to the supply voltage, it becomes a floating node, causing the PGA to fail to start normally. Therefore, C3 was added to prevent the PGA from having startup problems. Due to the presence of C3, V... out The rate of voltage rise at both nodes is slowed down by the RC charging network formed by R4, R5, and C3, V out More than V cm Afterwards, M1 and M2 will not enter the off state, but M7 and M11 will be turned off, so current mirrors M10 and M14 can control V. out Scroll down to V cm This ensured the smooth and rapid launch of the PGA.

[0037] Dynamic bias circuit 5 provides dynamic bias current to the PGA to achieve dynamic gain. It is a 5-bit current-to-analog converter. Its input is a 5-bit digital signal, and its output is a 32-level bias current, with an output current I. out The load is a current mirror that provides bias to the PGA. This module employs a low-dropout linear regulator structure; due to feedback, the voltage across the resistor array is a constant V. DD / 2, which realizes an adjustable tail current source.

[0038] Since this PGA amplifies the signal out of band by 3dB, the dynamic gain adjustment range at the carrier frequency is the most important parameter in the design. Figure 5 The results show that the gain at the carrier frequency is positively correlated with its power consumption, but not linearly. Therefore, system-level negative feedback is needed to control the PGA gain.

[0039] Here is an example of an adaptive control model for PGA application, such as... Figure 6As shown, the input signal is an OOK modulated signal. The PGA module processes narrowband signals beyond the 3dB bandwidth. The amplified signal's amplitude is detected by an envelope detector and converted into a single-ended voltage signal. The decision demodulation module compares this signal with a reference voltage Vref2 to obtain output Vo2, which is the demodulated data output. The decision feedback module compares this signal with a reference voltage Vref1 to obtain output Vo1, which is used in the system-level control loop. The control logic determines the PGA state by identifying the timing of the decision feedback module's output and adjusts the PGA gain in a closed loop using a 5-bit PGA gain word. The 5-bit current bias DAC acts as a converter from the digital domain to the analog domain in this process. When the PGA output is too high, a rising edge appears in the decision feedback output, indicating that the PGA gain is too high. The PGA bias current should be reduced to decrease the PGA gain. Figure 7 As shown in (a). When the PGA output is too small, there is no rising edge in the decision feedback output, indicating that the PGA gain is too small. The PGA bias current should be increased to increase the PGA gain, such as... Figure 7 As shown in (b).

[0040] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these are merely illustrative examples. Various changes or modifications can be made to these embodiments without departing from the principles and essence of the present invention. Therefore, the scope of protection of the present invention is defined by the appended claims.

Claims

1. A 3 dB out-of-band amplified low-power programmable gain amplifier characterized by, The application relates to a second-generation current transfer device of a foldable source follower, which is differential in input and output and is used for amplifying differential signals. A common-mode feedback loop is connected to the output end of the second-generation current transfer device of the foldable source follower, and is used for controlling the DC point of the programmable gain amplifier output at VDD / 2 and ensuring that the output has the maximum swing. A DC offset self-calibration loop is connected to the output end and the input end of the second-generation current transfer device of the foldable source follower, and is used for suppressing the output DC offset of the programmable gain amplifier through voltage-current negative feedback. A fast start circuit is connected to the common-mode feedback loop and an output node, and is used for ensuring the smooth and fast start of the programmable gain amplifier. A dynamic biasing circuit is connected to the biasing node of the second-generation current transfer device of the foldable source follower, and is used for providing a current biasing for controlling the gain of the programmable gain amplifier. The programmable gain amplifier amplifies a narrow-band signal out of the 3dB band, adjusts the tail current through the dynamic biasing circuit to change the bandwidth, and then changes the gain, so that the gain and the power consumption are positively correlated. ​ 2. The 3 dB out-of-band amplified low-power programmable gain amplifier of claim 1, wherein, The second generation current transmitter of the foldable source follower, wherein the NMOS tubes M9, M10, M13 and M14 and the source followers M3, M4, M5 and M6 constitute a current mirror, and the PMOS tubes M7, M8, M11 and M12 constitute a sleeve type output stage; the source follower copies the input signal V in to the sources of M3 and M4, to generate a current of V in / R1 on R1, the current flows through M5 and M6 to form a circulating current, and is copied to the drain ends of M9 and M13 through the current mirror; The sleeve type output stage has high output impedance, output current flows through load path R4, R5, forms output voltage V out , realizes voltage amplification effect.

3. The 3 dB out-of-band amplified low-power programmable gain amplifier of claim 1, wherein, The common-mode feedback loop comprises: DC sampling resistors R4 and R5 for sampling the common-mode voltage V out ; a five-tube operational amplifier, a first input end of which is connected to the center of R4 and R5, a second input end of which is connected to a reference voltage V DD / 2, and an output of which is the gate of PMOS tubes M7 and M11, for forming a common-mode feedback loop with the branch in which M7 and M11 are located, setting the output DC working point at V DD / 2, so that V out has the maximum swing; and a Miller capacitor C2 connected between the output end of the five-tube operational amplifier and the center, for adjusting the phase margin of the common-mode feedback loop and ensuring the stability of the loop.

4. The 3 dB out-of-band amplified low-power programmable gain amplifier of claim 1, wherein, The direct current self-calibration loop comprises: C1, R2 and R3 constitute a low-pass filter, sampling the direct current signal to both ends of C1, acting on the gate of M1 and M2; M1 and M2 convert the output direct current offset voltage into a direct current small signal current, which offsets the small signal current generated by the direct current input offset voltage, thereby realizing the voltage-current negative feedback for the direct current signal. out The direct current self-calibration loop comprises: C1, R2 and R3 constitute a low-pass filter, sampling the direct current signal to both ends of C1, acting on the gate of M1 and M2; M1 and M2 convert the output direct current offset voltage into a direct current small signal current, which offsets the small signal current generated by the direct current input offset voltage, thereby realizing the voltage-current negative feedback for the direct current signal.

5. The 3 dB out-of-band amplified low-power programmable gain amplifier of claim 1, wherein, The fast start-up circuit includes C3, which forms an RC charging network with R4 and R5 to slow down the two node voltages of V out after power up, so that V out does not exceed V cm , and M1 and M2 do not enter the off state, and the current mirror M10 and M14 pull V out down to V cm , ensuring smooth and fast start-up of the programmable gain amplifier.

6. The 3 dB out-of-band amplified low-power programmable gain amplifier of claim 1, wherein, The dynamic bias circuit is used for providing dynamic bias current, realizing dynamic gain, input is 5-bit digital signal, output is 32-gear bias current, and the output current I out The load of the current mirror is used for providing bias for the programmable gain amplifier.

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