Amplification circuits, low-noise amplifiers, apparatus and methods for amplification.

Abstract

This disclosure relates to amplifier circuits, low-noise amplifiers, apparatuses, and methods for performing amplification. Embodiments provide amplifier circuits, apparatuses for performing amplification, low-noise amplifiers, radio receivers, mobile terminals, base stations, and methods for performing amplification. An amplifier circuit 10 for amplifying radio signals includes components configured to amplify an input signal V. in (t) A first amplification stage 12 is used to amplify the intermediate signal to obtain an intermediate signal. Circuit 10 also includes a first output signal V configured to amplify the intermediate signal to obtain a first output signal V. outn The cascaded circuit 14 of (t) is also included. Circuit 10 further includes amplification of the intermediate signal to obtain a second output signal V. outp The second amplification stage of (t) is 16.

Description

[0001] Case Analysis

[0002] This application is a divisional application of Chinese Patent Application No. 201710342302.0, filed on May 12, 2017, entitled "Amplifier Circuit, Low Noise Amplifier, Apparatus and Method for Amplification". Technical Field

[0003] This disclosure relates to signal amplification, and more specifically, but not exclusively, to low-noise amplification of a single-ended low-noise current signal to obtain an amplified differential output signal. Background Technology

[0004] Many receivers use low-noise amplifiers (LNAs) to enhance the received signal level before further signal processing. For example, an LNA may be coupled to a receiving antenna, with a filter circuit likely between the LNA and the antenna. An LNA located at the input of a radio frequency (RF) receiver is often considered essential for any modern transceiver with challenging sensitivity requirements. Fully differential LNAs (which output differential signals, essentially two signals with opposite polarities) can be used because they can be connected to a double-balanced mixer, which inherently has lower second-order nonlinearity than a single-balanced mixer, and they can also effectively suppress any kind of common-mode noise originating from power or ground.

[0005] As the number of RF input ports in transceivers continues to increase, most multimode and multiband transceivers use single-ended LNAs with single-ended outputs, potentially saving input balls and chip area. Consequently, single-balanced mixers are used, which increase the mixer's second-order nonlinearity and, at least in some cases, lead to complex mixer calibration and further use of bulky and large blocking capacitors that introduce noise. Attached Figure Description

[0006] The following will describe some examples of apparatus and / or methods by way of example only, and with reference to the accompanying drawings, wherein:

[0007] Figure 1 Examples of amplifier circuits or amplifier devices and examples of low-noise amplifiers are shown;

[0008] Figure 2 Another example of an amplifier circuit or amplifier device is shown;

[0009] Figure 3 Examples of radio transceivers, mobile transceivers, and base station transceivers are shown;

[0010] Figure 4A block diagram illustrating an example of a method for magnification is shown; and

[0011] Figure 5 A schematic diagram of an example mobile transceiver is shown. Detailed Implementation

[0012] Various examples will now be described more fully with reference to the accompanying drawings, some of which are shown in the drawings. In the drawings, the thickness of areas, layers, and / or lines may be exaggerated for clarity.

[0013] Therefore, although other examples can have various modifications and alternatives, some examples are shown by way of example in the accompanying drawings and will be described in detail herein. However, it should be understood that the examples are not intended to limit the specific forms disclosed; rather, the examples will cover all modifications, equivalents, and alternatives falling within the scope of this disclosure. The same reference numerals are used throughout the description of the accompanying drawings to refer to the same or similar elements.

[0014] What will be understood is that when an element is referred to as being "connected" or "coupled" to another element, that element can be directly connected or coupled to the other element, or there may be intermediate elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements. Other terms used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0015] The terminology used herein is for the purpose of describing particular examples only and is not intended to limit other examples. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to also include the plural forms. It will also be understood that when the terms “comprising,” “including,” “having,” and / or “containing” are used herein, these terms indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0016] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the examples pertain. It will also be understood that, unless explicitly defined herein, terms defined, for example, in a general dictionary, should be interpreted as having a meaning consistent with that meaning in the context of the relevant field.

[0017] Some examples will be described below. Some examples introduce single-ended low-noise amplifiers with built-in source balun functionality to generate differential outputs, allowing the application of double-balanced mixers. Therefore, these examples can further allow for reduced second-order nonlinearity compared to single-balanced mixers.

[0018] Figure 1 Examples of amplifier circuits or amplifier devices are shown, as well as examples of low-noise amplifiers. Figure 1 An amplifier circuit 10 is shown for amplifying radio signals or input signals. Figure 1 The LNA100, which includes amplifier circuitry 10, is also shown (shown in dashed lines because it may include other components besides the example amplifier circuitry).

[0019] In the example, an LNA can be used at the RF front end of the receiver, for example, coupled to one or more receiving antennas via its input, with optional filter circuitry, a diplexer, and a duplexer between the LNA and the receiving antennas. It can be assumed that the signal level at the LNA input has very low power and noise. Therefore, one design goal for the LNA is to add as little additional noise power as possible to the input signal in order to maintain the highest possible signal-to-noise ratio (SNR) of the output signal.

[0020] like Figure 1 As shown, the amplifier circuit 10 includes a first amplification stage 12, which is configured to amplify the input signal V. in (t) Amplification is performed to obtain an intermediate signal. The amplifier circuit also includes a cascaded circuit 14, which is configured to amplify the intermediate signal to obtain a first output signal V. outn (t). The amplifier circuit 10 also includes a second amplification stage 16, which is configured to amplify the intermediate signal to obtain a second output signal V. outp (t).

[0021] exist Figure 1 In the illustrated example, a single-ended LNA with differential-well-equalized output signals but minimal additional current consumption can be implemented without sacrificing the LNA's linearity or noise figure. Then, the first and second output signals V... outn (t), V outp (t) can form the differential output of amplifier circuit 10. The differential output can correspond to two signals with different phases, for example, although the differential signal can be defined only as the 180-degree out-of-phase signal portion (V). outp (t)-V outn(t)) / 2, but the phase difference can be 90, 120, 150, 160, 170, or 180 degrees. Therefore, although theoretically the signal components of the differential signal can have a 180-degree phase shift, in this example, it may only be approximately so. In another example, one of the first amplification stage 12 and the second amplification stage 16 is an inverting amplification stage, while the other is a non-inverting amplification stage. Since one amplification stage is inverting and the other is not, an approximately 180-degree phase shift, or a phase shift within the aforementioned boundaries, can be achieved between the two output signals.

[0022] Figure 1 Also shown is a device 10 for amplifying radio signals. This device includes amplification of the input signal V. in (t) A first device 12 for amplifying the intermediate signal to obtain an intermediate signal. The device 10 also includes a method for amplifying the intermediate signal to obtain a first output signal V. outn The cascaded device 14 of (t) is further included. The device 10 also includes amplification of the intermediate signal from the cascaded device 14 to obtain a second output signal V. outp The second device 16 of (t). An amplification device, cascade device, amplifier stage, or cascade circuit can correspond to any one or more amplifier devices, units, or modules of various conceivable variations. For example, a transistor circuit can be used. First and second output signals V outn (t), V outp (t) can form the differential output of amplifier device 10, as described above. In another example, one of the first device 12 for amplification and the second device 16 for amplification is an inverting amplification stage, while the other is a non-inverting amplification stage.

[0023] In the example, circuit 10 or device 10 generates a differential output without using a passive transformer, which can be very bulky and area-intensive. Furthermore, compared to a conventional active balun with two branches, the example may utilize only two common source stages in the case of common-source and common-gate amplification stages in a field-effect transistor (FET) circuit. Thus, the noise figure of the example LNA may remain unaffected and be as good as a common-source LNA. Another example can construct out-of-phase signals using only one additional amplification branch, compared to a conventional active balun using two additional branches. The example can save on additional current consumption.

[0024] Figure 2 Another example of amplifier circuit 10 or amplifier device 10 is shown. In this example, transistors are used to implement the amplification stage or amplification device, which will be explained in detail later. Figure 2 The circuit shown. Figure 2 Examples include with Figure 1The functional components depicted in the example are similar to the first amplification stage 12, the second amplification stage 16, and the cascaded circuit 14. Figure 2 The example shown uses a metal-oxide-semiconductor field-effect transistor (MOSFET). Other types of transistors can be used in other examples. These include FETs, bipolar transistors, bipolar junction transistors (BJTs), etc.

[0025] like Figure 2 As shown, the first amplification stage 12 includes a push-pull stage cascaded with the cascaded circuit 14. For example... Figure 2 As shown, the two transistors are configured to alternately provide current using complementary transistor sets, a concept known as push-pull. The first amplification stage 12 includes a first push-pull stage cascaded with the cascaded circuit 14, and the second amplification stage 16 includes a second push-pull stage configured to amplify the intermediate signal.

[0026] However, cascaded circuit 14 can correspond to another amplification stage with a different configuration compared to the first amplification stage 12, such as Figure 2 As shown. The transistors in cascaded circuit 14 are in a common-gate configuration, while the transistors in the first amplification stage 12 are in a common-source configuration. Cascaded circuit 14 can also be referred to as a transconductance amplifier followed by a current buffer. Cascaded circuit 14, together with the first amplification stage 12, can be configured to provide higher input-output isolation (transconductance), higher input impedance, higher output impedance, higher gain, and / or higher bandwidth. Figure 2 In the example shown, the current generated by the first amplification stage 12 is converted into a voltage signal by the cascaded circuit 14. This cascading corresponds to the cascading of the cathodes and can achieve high input impedance (input signal V). in (t) is coupled to Figure 2 The gate connector of the transistor in the cascade is biased with a reference voltage. Cascading also allows for very low coupling between the input and output. Furthermore, because the cascaded circuit is a common-gate configuration, the source voltage (and therefore the drain of the input transistor) remains almost constant during operation because the gate is effectively grounded at the operating frequency. In other words, the cascaded transistors experience low input resistance to the transistors in the first amplification stage 12, resulting in a smaller voltage gain for the amplification transistors, which may reduce the Miller feedback capacitance from the drain to the gate of the amplification stage transistors. This loss of voltage gain can be recovered by the cascaded transistors. Therefore, cascaded transistors can allow the transistors in the amplification stage to operate with reduced Miller feedback, which can improve their bandwidth.

[0027] exist Figure 2 In the depicted example, the first amplification stage 12 includes at least two transistors M coupled in a push-pull arrangement. 1N M 1P The cascaded circuit 14 includes Figure 2 At least two transistors M in the example 2N M 2P It is arranged in a push-pull configuration and coupled to at least two transistors M of the first amplification stage 12. 1N M 1P Between. Furthermore, at least two transistors M of the first amplification stage 12. 1N M 1P These are two MOSFETs with different channel types. Therefore, M 1N M 1P In the presented example, they are complementary. At least two transistors M of the cascaded circuit 14. 2N M 2P They are also two (complementary) MOSFETs with different channel types.

[0028] As further shown in the example, the first transistor M of the first amplification stage 12 1N It is coupled to a reference potential or a negative supply voltage. In some examples, the reference potential may correspond to ground; in other examples, the negative supply voltage may be a symmetrical voltage compared to the positive supply voltage, differing only in its negative polarization. The second transistor M of the first amplification stage 12 1P It is coupled to the positive power supply voltage. The first transistor M of the cascaded circuit 14 2N The first transistor M is coupled to the first amplification stage 12 1N The first transistor M of the cascaded circuit 14 2N The second transistor M is coupled to the cascade circuit 14 2P And the second transistor M of cascade stage 14 2P The second transistor M is coupled to the first amplification stage 12 1P .

[0029] Furthermore, the second amplification stage 16 includes a push-pull stage, which comprises at least two transistors M. 3N M 3P ,like Figure 2 As shown in the example. The second amplification stage 16 has at least two transistors M. 3N M 3P These are two (complementary) MOSFETs with different channel types. The second amplification stage 16 has at least two transistors M. 3N M 3P They are coupled to each other in a push-pull arrangement and can be considered as being in parallel with respect to the output, wherein the first transistor M of the second amplification stage 16 3N It is coupled to the negative power supply voltage or reference potential as described above. The second transistor M of the second amplification stage 16 3P It is coupled to the positive power supply voltage.

[0030] exist Figure 2 In the circuit depicted in the example, the second amplification stage 16 includes a push-pull stage comprising two transistors M. 3N M 3P The two transistors M in the second amplification stage 16 3N M 3P The transistors are coupled to each other in a push-pull arrangement. The first transistor M of the second amplification stage 16 3N Coupled to a negative supply voltage or reference potential, and the second transistor M of the second amplification stage 16 3P It is coupled to the positive power supply voltage. The first transistor M of the second amplification stage 16... 3N The first transistor M is coupled to the first amplification stage 12 1N The first transistor M of the cascaded circuit 14 2N The second transistor M of the second amplification stage 16 3P The second transistor M is coupled to the first amplification stage 12 1P and the second transistor M of the cascaded circuit 2P .

[0031] More specifically, in the example, the first amplification stage 12 includes at least two MOSFETs, with the first MOSFET M being an n-channel type. 1N and the second MOSFET M of the p-channel type 1P The cascaded circuit 14 also includes at least two MOSFETs, with the first MOSFET M being an n-channel type. 2N and the second MOSFET M of the p-channel type 2P MOSFET M 1N M 1P M 2N and M 2P Each of these includes at least a gate, source, and drain connector. These connectors are in... Figure 2 The corresponding letters "G", "D", and "S" indicate this. Figure 2 In the example, the first MOSFET M of the first amplification stage 12 1N The source connector is coupled to the negative supply voltage or reference potential as described above. The first MOSFET M of the first amplification stage 12... 1N The drain connector is coupled to the first MOSFET M of the cascaded circuit 14. 2N The source connector. The first MOSFET M of the cascaded circuit 14. 2N The drain connector is coupled to the second MOSFET M of the cascaded circuit 14. 2P The drain connector. The second MOSFET M of the cascaded circuit 14. 2P The source connector is coupled to the second MOSFET M of the first amplification stage 12. 1PThe drain connector. The second MOSFET M of the first amplification stage 12. 1P The source connector is coupled to the positive power supply voltage.

[0032] like Figure 2 As further shown, the first MOSFET M of the first amplification stage 12 1N The source connector is connected through at least one resistor R S1N Coupled to a negative supply voltage or reference potential, R S1N Allows tuning or biasing M 1N The source potential. The second MOSFET M of the first amplification stage 12. 1P The source connector is connected through at least one other resistor R. S1P Coupled to the positive power supply voltage, R S1P This allows the resistance source of amplifier circuit 10 to be reduced to increase linearity, and R S1P It can be programmed as needed. Input signal V in(t) The first and second MOSFETs M are coupled to the first amplification stage 12 1N and M 1P The gate connector. The first and second MOSFETs M of the cascaded circuit 14. 2N and M 2P The gate connector is coupled to a reference potential, which can be ground in the example or the supply voltage in the case of an NMOS (n-type MOS). It is important to note that the biasing of the amplifier stage and the cascaded circuit can be applied separately. In other words, for example... Figure 2 For all the gates shown, depending on the transistor type and implementation, certain potentials can be applied to tune the circuit to the desired requirements. These potentials can be the same or different; in some examples, each gate can be biased to a different potential.

[0033] exist Figure 2 In the example, the input signal passes through at least one capacitor C. 1N The first MOSFET M is coupled to the first amplification stage 12 1N The gate connector can also be selected according to actual needs (e.g., the desired bandwidth or frequency of the received signal). 1N The input signal also passes through at least one other capacitor C. 1P The second MOSFET M is coupled to the first amplification stage 12 1P The gate connector. In the example, capacitor C... 1N and C 1P They can have the same or different capacities.

[0034] The first MOSFET M of the cascaded circuit 14 2NThe gate connector is connected through at least one capacitor C 2N Coupled to the reference potential. The second MOSFET M of cascaded circuit 14. 2P The gate connector is connected through at least one other capacitor C. 2P They are coupled to a reference potential. These capacitors can filter any modulation to the reference potential, just like the RF shortening of the gate. The reference potential for gate bias is directly connected to the gate. In the example, capacitor C 2N and C 2P They can have the same or different capacitances, and in some examples they can even be equal to the capacitor C. 1N and C 1P .

[0035] exist Figure 2 In the example, the second amplifier circuit 16 may include at least two MOSFETs, with the first MOSFET M being an n-channel type. 3N and the second MOSFET M of the p-channel type 3P MOSFET M in the second amplification stage 16 3N M 3P Each of these includes at least a gate, source, and drain connector. The first MOSFET M of the second amplification stage 16... 3N The source connector is coupled to the negative power supply voltage or reference potential as described above. The first MOSFET M of the second amplification stage... 3N The drain connector is coupled to the second MOSFET M of the second amplification stage 16. 3P The drain connector. The second MOSFET M of the second amplification stage 16. 3P The source connector is coupled to the positive power supply. The first MOSFET M of the second amplification stage 16... 3N The source connector is connected through at least one resistor R S2N Coupled to a negative supply voltage or reference potential, R S2N Allow the resistive source of the MOS to degrade.

[0036] The second MOSFET M of the second amplification stage 16 3P The source connector is connected through at least one other resistor R. S2P Coupled to the positive power supply voltage, R S2P This allows the resistive source of the MOS to degrade. The first MOSFET M in the second amplification stage 16... 3N The gate connector is coupled to the first MOSFET M of the first amplification stage 12. 1N The drain connector. The first MOSFET M of the second amplification stage 16. 3N The gate connector is coupled to the first MOSFET M of the cascaded circuit 14. 2NThe source connector. In this example, the intermediate signal corresponds to the current signal output by the first amplifier stage 12. The current signal is the input to the cascade circuit 14, and the voltage signal caused by the current signal applied to the cascade circuit 14 is input to the second amplifier stage 16. The second amplifier stage 16 has a high input impedance (two gate connectors), which is why the current output from the first amplifier stage 12 flows through the cascade circuit 14. Similarly, the second MOSFET M of the second amplifier stage 16... 3P The gate connector is coupled to the second MOSFET M of the first amplification stage 12. 1P The drain connector, and the second MOSFET M of the second amplification stage 16. 3P The gate connector is coupled to the second MOSFET M of the cascaded circuit 14. 2P The source connector.

[0037] like Figure 2 As further shown, the first and second MOSFETs M of the second amplification stage 16 3N and M 3P The gate connector is connected through at least one capacitor C AC Coupling. This capacitor can be used to shorten or attenuate certain high frequencies at the input of the second amplification stage 16. The capacitor can also be used to balance the output signal V. outn (t) and V outp The gain of (t), V outn (t) and V outp (t) A differential output pair is formed. The gain of the first output is affected by the first amplifier stage 12 (a common-source amplifier with higher gain) and the cascaded circuit 14 (a common-gate amplifier with lower gain). The second output signal V outp The gain of (t) is affected by the gain of the second amplification stage 16 (with a high-gain common source) and the capacitor C. AC The effect of tuning capacitor C. AC It can tune the gain or symmetry of the differential output signals (first and second output signals).

[0038] In addition, the first MOSFET M of the second amplification stage 16 3N The gate connector is connected through at least one capacitor C 3N The first MOSFET M is coupled to the first amplification stage 12 1N The drain connector. The first MOSFET M of the second amplification stage 16. 3N The gate connector is connected to capacitor C. 3N The first MOSFET M is coupled to the cascade circuit 14 2N The source connector. Therefore, the second amplifier stage 16 is decoupled from the first amplifier stage 12 and the cascaded circuit 14 relative to DC. It should be noted that capacitor C3N And the capacitor C, which will be introduced later. 3P It can also be used with capacitor C AC The relationship affects the second output signal V outp The gain of (t). As shown in the example, the second MOSFET M of the second amplifier stage 16. 3P The gate connector is connected through at least one other capacitor C. 3P The second MOSFET M is coupled to the first amplification stage 12 1P The drain connector. The second MOSFET of the second amplification stage 16. 3P The gate connector also connects to another capacitor C. 3P The second MOSFET M is coupled to the cascade circuit 14 2P The source connector. For example, capacitor C. 3N and C 3P They can have the same capacity. In some examples, they may also have different capacities.

[0039] The first output signal is generated by the first MOSFET M of the cascaded circuit 14. 2N The drain connector and the second MOSFET M of the cascade circuit 14 2P The drain connector is provided. The second output signal is provided by the first MOSFET M of the second amplification stage 16. 3N The drain connector and the second MOSFET M of the second amplification stage 16 3P The drain connector is provided. The input signal is coupled to the first MOSFET M of the cascaded circuit 14. 2N The drain connector and the second MOSFET M of the cascade circuit 14 2P The drain connector. The input signal passes through at least one resistor R. FB and capacitor C FB The first MOSFET M is coupled to the cascade circuit 14 2N The drain connector and the second MOSFET M of the cascade circuit 14 2P The drain connector. In Figure 2 In the example, resistor R FB and capacitor C FB The input impedance or transconductance of amplifier circuit 10 can be set. In the example, the amplifier circuit can be part of LNA 100, see reference. Figure 1 .

[0040] Figure 2The example LNA topology in the example omits the bias circuitry. As noted above, in applications or implementations, the transistor gates can be biased using a specific DC potential to fine-tune amplifier stages 12, 16, and the cascaded circuitry for the appropriate application. Figure 2 In the example, the first stage 12 includes a push-pull stage M. 1N M 1P Metal-oxide-semiconductor (MOS) transistors, and cascaded circuits including M 2N M 2P MOS transistor. Resistor and capacitor feedback R FB and C FB Provides the required input impedance matching. The output of this branch is directly fed to the LNA output V. outn (t).

[0041] Out-of-phase signals are generated by including MOS transistor M 3P M 3N The second push-pull stage 16 is generated. The input signals for the second stage are created in a specific manner. They originate from the first push-pull stage 12M. 1N and M 1P The output of the gm (transconductance) stage. Both signals are generated using capacitor C. AC Shortened to 16M for Level 2 3N M 3P The single input signal is AC (alternating current). This can essentially improve the phase balance behavior of the LNA. The output of the second push-pull stage 16 is ultimately fed to the LNA's V... outp (t). First stage 12M 2N M 2P The cascaded stage 14 in the middle results in low or even minimal isolation between the two stages 12 and 14 in a current-consumption neutral manner. Furthermore, they can be used to... outn The gain of (t) and V outp (t) Branch matching is used to ensure good amplitude balance between the two branches. This can be achieved by adjusting the source degradation resistor R in the first and second amplification stages. S1N R S1P R S2N and R S2P This is to achieve further gain matching.

[0042] Due to the input push-pull stage M 1N and M 1P The output differential signal is then created, so the noise figure of this structure may be as good as that of a traditional single-ended LNA, but it outperforms traditional active balancing-to-unbalanced converters in terms of noise figure and current consumption.

[0043] Another example is... Figure 3 As shown in the image. Figure 3 Examples of radio receivers 200 and 300 (mobile transceiver 200 and base transceiver 300) are shown in general. Figure 3 An example of a mobile transceiver 200, including an example of an LNA 100a, is shown. Figure 3 An example of a base transceiver 300, including an LNA 100b, is also shown. The mobile transceiver 200 and base transceiver 300 originate from a mobile communication system, as another example. The mobile communication system may, for example, correspond to one of the standardized mobile communication networks of the 3rd Generation Partnership Project (3GPP), where the term mobile communication system is used synonymously with mobile communication network. The mobile or wireless communication system may correspond to a fifth-generation (5G) mobile communication system and may use millimeter-wave technology. Mobile communication systems can correspond to or include, for example, Long Term Evolution (LTE), Advanced LTE (LTE-A), High Speed ​​Packet Access (HSPA), Universal Mobile Telecommunications System (UMTS) or UMTS Terrestrial Radio Access Network (UTRAN), Evolved UTRAN (e-UTRAN), Global System for Mobile Communications (GSM) or Enhanced Data Rate GSM Evolution (EDGE) network, GSM / EDGE Radio Access Network (GERAN), or mobile communication networks with different standards (e.g., Global Microwave Access Interoperability (WIMAX) network IEEE 802.16 or Wireless Local Area Network (WLAN) IEEE 802.11), which are typically Orthogonal Frequency Division Multiple Access (OFDMA) networks, Time Division Multiple Access (TDMA) networks, Code Division Multiple Access (CDMA) networks, Wideband CDMA (WCDMA) networks, Frequency Division Multiple Access (FDMA) networks, Space Division Multiple Access (SDMA) networks, etc.

[0044] The base station or base transceiver 300 is operable to communicate with one or more active mobile transceivers 200, and the base transceiver 300 may be located within or near the coverage area of ​​another base transceiver (e.g., a macrocell base transceiver or a small cell base transceiver). Therefore, examples may provide a mobile communication system including one or more mobile transceivers 200 and one or more base transceivers 300, wherein the base transceiver 300 can establish macrocells or small cells, such as pico, metro, or femtocells. The mobile transceiver 200 may correspond to a smartphone, cellular phone, user equipment, laptop computer, notebook computer, personal computer, personal digital assistant (PDA), universal serial bus (USB) stick, automobile, etc. The mobile transceiver 200 may also be referred to as a user equipment (UE) or mobile device in 3GPP terminology.

[0045] The base transceiver 300 can be located in a fixed or stationary part of a network or system. The base transceiver 300 can correspond to a remote radio head unit, transmission point, access point, macro cell, small cell, micro cell, femtocell, metropolitan area cell, etc. The base transceiver 300 can be a wireless interface of a wired network, allowing the transmission of radio signals to a UE or mobile transceiver 200. Such radio signals can conform to, for example, radio signals standardized by 3GPP, or generally, conform to one or more of the systems listed above. Therefore, the base transceiver 300 can correspond to a Node B, eNodeB, base transceiver station (BTS), access point, remote radio head unit, transmission point, etc., which can be further subdivided into remote units and central units.

[0046] Figure 4 A block diagram illustrating an example of a method for amplification is shown. The method for amplifying a radio signal obtained at the input to provide an amplified signal at the output includes amplifying the input signal V... in (t) Amplification 22 is performed to obtain an intermediate signal. The method also includes cascading the intermediate signal 24 to obtain a first output signal V. outn (t), and amplify the intermediate signal by 26 to obtain the second output signal V. outp (t). First and second output signals V outn (t), V outp (t) Forms the differential output of amplifier circuit 10. Amplification of the input signal 22 or amplification of the intermediate signal may further include inverting the input signal. In the example, amplification stage 12 includes a push-pull stage, and cascading includes cascaded push-pull stages. Amplification of the input signal 22 may use a first push-pull stage, cascading 24 may refer to the first push-pull stage, and amplification of the intermediate signal 26 may use a second push-pull stage.

[0047] In another example, the amplification 22 of the input signal uses a first amplification stage 12, which includes at least two transistors M coupled in a push-pull arrangement. 1N M 1P And cascaded 24 uses at least two transistors M 2N M 2P M 2N M 2P The transistor M is coupled to the first amplification stage 12 in a push-pull arrangement. 1N M 1P Between. In some examples, at least two transistors M of the first amplification stage 12. 1N M 1P These are two MOSFETs with different channel types. At least two transistors M are used in the cascading. 2N M 2PThis can be two MOSFETs with different channel types. In another example, the method may also include the first transistor M of the first amplification stage 12. 1N Coupled to a negative power supply voltage or reference potential, and the second transistor M of the first amplification stage 12 is... 1P Coupled to the positive power supply voltage.

[0048] The method may also include using a first transistor M for cascading. 2N The first transistor M is coupled to the first amplification stage 12. 1N And the first transistor M used for cascading 2N Coupled to the second transistor M for cascading 2P The method may also include using a second transistor M for cascading. 2P The second transistor M is coupled to the first amplification stage 12 1P The amplification of the intermediate signal 26 can be achieved using at least two transistors M. 3N M 3P A push-pull stage. At least two transistors M. 3N M 3P It can be two MOSFETs with different channel types included in the second amplification stage 16. The method for amplification may also include at least two transistors M in the second amplification stage 16. 3N M 3P Coupled to each other in a push-pull arrangement, it also includes the first transistor M of the second amplification stage 16. 3N Coupled to a negative power supply voltage or reference potential, and to the second transistor M of the second amplification stage 16. 3P Coupled to the positive power supply voltage.

[0049] According to Figure 2 The example explained further illustrates that the method may also include the two transistors M of the second amplification stage 16. 3N M 3P They are coupled to each other in a push-pull arrangement, and the first transistor M of the second amplification stage 16 is coupled to each other. 3N Coupled to a negative power supply voltage or reference potential. The method may also include coupling the second transistor M of the second amplification stage 16. 3P Coupled to the positive power supply voltage, and the first transistor M of the second amplification stage 16 3N The first transistor M is coupled to the first amplification stage 12. 1N and the first transistor M used for cascading 2N The method may further include using the second transistor M of the second amplification stage 16. 3P The second transistor M is coupled to the first amplification stage 12 1P and the second transistor M used for cascading 2P .

[0050] Figure 5 A schematic diagram of an example mobile transceiver 200 is shown, which includes an RF processing section 200a, a baseband processor module 170, and a power supply module 180. (See diagram below.) Figure 5 As illustrated, the antenna is coupled to an RF processing section 200a, which includes an example of an LNA 100a. The LNA 100a includes an example of the aforementioned amplifier circuit. It should be noted that the RF processing section 200a may include additional filters or RF components, such as input filters, RF band filters, intermediate filters, output filters, duplexers, duplexers, etc. The output of the LNA 100a is then down-converted by converter 110 and filtered by filter 120, which may again involve additional components. The output of filter 120 is then provided to baseband processor module 170. Baseband processor module 170 is configured to further process the baseband received signal. Furthermore, the mobile transceiver includes a power supply unit 180 that supplies power to at least the RF processing section and the baseband processor module 170.

[0051] The embodiments described herein can be summarized as follows:

[0052] The first example is an amplifier circuit 10 for amplifying radio signals, which includes an amplifier circuit configured to amplify an input signal V. in (t) A first amplification stage 12 is used to amplify the intermediate signal to obtain an intermediate signal. Circuit 10 also includes a first output signal V configured to amplify the intermediate signal to obtain a first output signal V. outn The cascaded circuit 14 of (t), and configured to amplify the intermediate signal to obtain the second output signal V. outp The second amplification stage of (t) is 16.

[0053] In Example 2, the first and second output signals V outn (t), V outp (t) forms the differential output of amplifier circuit 10.

[0054] In Example 3, one of the first amplification stage 12 and the second amplification stage 16 is an inverting amplification stage, while the other is a non-inverting amplification stage.

[0055] In Example 4, the first amplification stage 12 includes a push-pull stage cascaded with the cascaded circuit 14.

[0056] In Example 5, the first amplification stage 12 includes a first push-pull stage cascaded with the cascaded circuit 14, and the second amplification stage 16 includes a second push-pull stage configured to amplify the intermediate signal.

[0057] In Example 6, the first amplification stage 12 includes at least two transistors M coupled in a push-pull arrangement. 1NM 1P The cascaded circuit 14 includes at least two transistors M. 2N M 2P M 2N M 2P At least two transistors M are coupled to the first amplification stage 12 in a push-pull arrangement. 1N M 1P between.

[0058] In Example 7, at least two transistors M of the first amplification stage 12 1N M 1P These are two metal-oxide-semiconductor field-effect transistors (MOSFETs) with different channel types.

[0059] In Example 8, at least two transistors M of the cascaded circuit 14 2N M 2P These are two MOSFETs with different channel types.

[0060] In Example 9, the first transistor M of the first amplification stage 12 1N Coupled to a reference potential or a negative supply voltage, and wherein the second transistor M of the first amplification stage 12 is... 1P It is coupled to the positive power supply voltage.

[0061] In Example 10, the first transistor M of the cascaded circuit 14 2N The first transistor M is coupled to the first amplification stage 12 1N The first transistor M of the cascaded circuit 14 2N The second transistor M is coupled to the cascade circuit 14 2P And the second transistor M of cascade stage 14 2P The second transistor M is coupled to the first amplification stage 12 1P .

[0062] In Example 11, the second amplification stage 16 includes a transistor M with at least two transistors. 3N M 3P The push-pull stage.

[0063] In Example 12, at least two transistors M of the second amplification stage 16 3N M 3P They are two MOSFETs with different channel types.

[0064] In Example 13, at least two transistors M of the second amplification stage 16 3N M 3P The transistors are coupled to each other in a push-pull arrangement, wherein the first transistor M of the second amplification stage 16 3NIt is coupled to a negative supply voltage or reference potential, and the second transistor M of the second amplification stage 16 is... 3P It is coupled to the positive power supply voltage.

[0065] In Example 14, the second amplification stage 16 includes two transistors M. 3N M 3P The push-pull stage, the second amplification stage has two transistors M16. 3N M 3P The first transistor M of the second amplification stage 16 is coupled to each other in a push-pull arrangement. 3N Coupled to a negative supply voltage or reference potential, the second transistor M of the second amplification stage 16 3P Coupled to the positive power supply voltage, the first transistor M of the second amplification stage 16 3N The first transistor M is coupled to the first amplification stage 12 1N The first transistor M of the cascaded circuit 14 2N The second transistor M of the second amplification stage 16 3P The second transistor M is coupled to the first amplification stage 12 1P The second transistor M of the cascaded circuit 14 2P .

[0066] In Example 15, the first amplification stage 12 includes at least two MOSFETs, with the first MOSFET M being an n-channel type. 1N and the second MOSFET M of the p-channel type 1P The cascaded circuit 14 includes at least two MOSFETs, with the first MOSFET M being an n-channel type. 2N and the second MOSFET M of the p-channel type 2P MOSFET M 1N M 1P M 2N M 2P Each of these includes at least a gate, a source, and a drain connector. The first MOSFET M of the first amplification stage 12... 1N The source connector is coupled to a negative supply voltage or reference potential, and the first MOSFET M of the first amplification stage 12 1N The drain connector is coupled to the first MOSFET M of the cascaded circuit 14. 2N The source connector. The first MOSFET M of the cascaded circuit 14. 2N The drain connector is coupled to the second MOSFET M of the cascaded circuit 14. 2P The drain connector. The second MOSFET M of the cascaded circuit 14. 2P The source connector is coupled to the second MOSFET M of the first amplification stage 12. 1PThe drain connector, and the second MOSFET M of the first amplification stage 12. 1P The source connector is coupled to the positive power supply voltage.

[0067] In Example 16, the first MOSFET M of the first amplification stage 12 1N The source connector is connected through at least one resistor R S1N It is coupled to a negative supply voltage or reference potential. The second MOSFET M of the first amplification stage 12... 1P The source connector is connected through at least one other resistor R. S1P It is coupled to the positive power supply voltage.

[0068] In Example 17, the input signal V in (t) The first and second MOSFETs M are coupled to the first amplification stage 12. 1N and M 1P The gate connector, and the first and second MOSFETs M of the cascaded circuit 14 2N and M 2P The gate connector is coupled to the reference potential.

[0069] In Example 18, the input signal passes through at least one capacitor C. 1N The first MOSFET M is coupled to the first amplification stage 12 1N The gate connector, and the input signal passes through at least one other capacitor C. 1P The second MOSFET M is coupled to the first amplification stage 12 1P Gate connector.

[0070] In Example 19, the first MOSFET M of the cascaded circuit 14 2N The gate connector is connected through at least one capacitor C 2N Coupled to the reference potential. The second MOSFET M of cascaded circuit 14. 2P The gate connector is connected through at least one other capacitor C. 2P It is coupled to the reference potential.

[0071] In Example 20, the second amplifier circuit 10 includes at least two MOSFETs, with the first MOSFET M being an n-channel type. 3N and the second MOSFET M of the p-channel type 3P The second amplification stage uses a 16-MOSFET M. 3N M 3P Each of these includes at least a gate, source, and drain connector. The first MOSFET M of the second amplification stage 16... 3NThe source connector is coupled to a negative supply voltage or a reference potential. The first MOSFET M of the second amplification stage 16... 3N The drain connector is coupled to the second MOSFET M of the second amplification stage 16. 3P The drain connector. The second MOSFET M of the second amplification stage 16. 3P The source connector stage 16 is coupled to the positive power supply.

[0072] In Example 21, the first MOSFET M of the second amplification stage 16 3N The source connector is connected through at least one resistor R S2N It is coupled to a negative supply voltage or a reference potential. The second MOSFET M of the second amplification stage 16. 3P The source connector is connected through at least one other resistor R. S2P It is coupled to the positive power supply voltage.

[0073] In Example 22, the first MOSFET M of the second amplification stage 16 3N The gate connector is coupled to the first MOSFET M of the first amplification stage 12. 1N The drain connector. The first MOSFET M of the second amplification stage 16. 3N The gate connector is coupled to the first MOSFET M of the cascaded circuit 14. 2N The source connector. The second MOSFET M of the second amplification stage 16. 3P The gate connector is coupled to the second MOSFET M of the first amplification stage 12. 1P The drain connector. The second MOSFET of the second amplification stage 16. 3P The gate connector is coupled to the second MOSFET M of the cascaded circuit 14. 2P The source connector.

[0074] In Example 23, the first and second MOSFETs M of the second amplification stage 16 3N and M 3P The gate connector is connected through at least one capacitor C AC coupling.

[0075] In Example 24, the first MOSFET M of the second amplification stage 16 3N The gate connector is connected through at least one capacitor C 3N The first MOSFET M is coupled to the first amplification stage 12 1N The drain connector. The first MOSFET of the second amplification stage 16. 3N The gate connector is connected to capacitor C. 3N The first MOSFET M is coupled to the cascade circuit 142N The source connector. The second MOSFET M of the second amplification stage 16. 3P The gate connector is connected through at least one other capacitor C. 3P The second MOSFET M is coupled to the first amplification stage 12 1P The drain connector. The second MOSFET M of the second amplification stage 16. 3P The gate connector is connected to another capacitor C. 3P The second MOSFET M is coupled to the cascade circuit 14 2P The source connector.

[0076] In Example 25, the first output signal V outn (t) The first MOSFET M of the cascaded circuit 14 2N The drain connector and the second MOSFET M of the cascade circuit 14 2P Drain connectors are provided.

[0077] In Example 26, the second output signal V outp (t) is generated by the first MOSFET M of the second amplification stage 16. 3N The drain connector and the second MOSFET M of the second amplification stage 16 3P Drain connectors are provided.

[0078] In Example 27, the input signal V in (t) The first MOSFET M coupled to cascade circuit 14 2N The drain connector and the second MOSFET M of the cascade circuit 14 2P Drain connector.

[0079] In Example 28, the input signal V in (t) at least through resistor R FB and capacitor C FB The first MOSFET M is coupled to the cascade circuit 14 2N The drain connector and the second MOSFET M of the cascade circuit 14 2P Drain connector.

[0080] In Example 29, the apparatus 10 for amplifying radio signals includes a means for amplifying the input signal V. in (t) A first device 12 for amplifying the intermediate signal to obtain an intermediate signal. The device 10 also includes a method for amplifying the intermediate signal to obtain a first output signal V. outn The cascaded device 14 of (t) is further included. The device 10 also includes amplification of the intermediate signal from the cascaded device 14 to obtain a second output signal V. outp The second device 16 of (t).

[0081] In Example 30, the first and second output signals V outn (t), V outp (t) forms the differential output of the amplifier 10.

[0082] In Example 31, one of the first device 12 for amplification and the second device 16 for amplification is an inverting amplification stage, while the other is a non-inverting amplification stage.

[0083] In Example 32, the low-noise amplifiers 100, 100a, 100b include an amplifier circuit 10 or device 10 according to one of the above examples.

[0084] In Example 33, radio receivers 200 and 300 include the low-noise amplifier 100 of the aforementioned examples.

[0085] In Example 34, the mobile terminal 200 includes the example low-noise amplifier 100a.

[0086] In Example 35, base station 300 includes example low-noise amplifier 100b.

[0087] In Example 36, a method for amplifying a radio signal obtained at an input to provide an amplified signal at an output includes: amplifying the input signal V... in (t) Amplification 22 is performed to obtain an intermediate signal. The method also includes cascading the intermediate signal 24 to obtain a first output signal V. outn (t). The method also includes amplifying the intermediate signal 26 to obtain a second output signal V. outp (t).

[0088] In Example 37, the first and second output signals V outn (t), V outp (t) forms the differential output of amplifier circuit 10.

[0089] In Example 38, amplifying the input signal 22 or the intermediate signal also includes inverting the phase.

[0090] In Example 39, the amplification stage 12 includes a push-pull stage, and the cascade includes a cascaded push-pull stage.

[0091] In Example 40, for the input signal V in (t) Amplification 22 uses the first push-pull stage, cascade 24 refers to the first push-pull stage, and amplification of the intermediate signal 26 uses the second push-pull stage.

[0092] In Example 41, for the input signal V in(t) Amplification 22 is performed using a first amplification stage 12, which includes at least two transistors M coupled in a push-pull arrangement. 1N M 1P And the cascaded 24 uses at least two transistors M 2N M 2P M 2N M 2P At least two transistors M are coupled to the first amplification stage 12 in a push-pull arrangement. 1N M 1P between.

[0093] In Example 42, at least two transistors M of the first amplification stage 12 1N M 1P These are two MOSFETs with different channel types, namely metal-oxide-semiconductor field-effect transistors.

[0094] In Example 43, at least two transistors M are used in the cascading. 2N M 2P These are two MOSFETs with different channel types.

[0095] In Example 44, the method further includes the first transistor M of the first amplification stage 12. 1N Coupled to a negative power supply voltage or reference potential, and the second transistor M of the first amplification stage 12 is... 1P Coupled to the positive power supply voltage.

[0096] In Example 45, the method also includes a first transistor M for cascading. 2N The first transistor M is coupled to the first amplification stage 12. 1N The first transistor M to be used for cascading 2N Coupled to the second transistor M for cascading 2P and the second transistor M to be used for cascading 2P The second transistor M is coupled to the first amplification stage 12 1P .

[0097] In Example 46, the intermediate signal is amplified 26 using a transistor M comprising at least two transistors. 3N M 3P The push-pull stage.

[0098] In Example 47, at least two transistors M 3N M 3P These are two MOSFETs with different channel types included in the second amplification stage 16.

[0099] In Example 48, the method includes at least two transistors M of the second amplification stage 16. 3N M3P Coupled to each other in a push-pull arrangement, it also includes the first transistor M of the second amplification stage 16. 3N Coupled to a negative power supply voltage or reference potential, and the second transistor M of the second amplification stage 16 3P Coupled to the positive power supply voltage.

[0100] In Example 49, the method also includes two transistors M of the second amplification stage 16. 3N M 3P The first transistor M of the second amplification stage 16 is coupled to each other in a push-pull arrangement. 3N Coupled to a negative power supply voltage or reference potential. The method also includes coupling the second transistor M of the second amplification stage 16. 3P Coupled to the positive power supply voltage, and the first transistor M of the second amplification stage 16 3N The first transistor M is coupled to the first amplification stage 12. 1N and the first transistor M used for cascading 2N The method also includes the second transistor M of the second amplification stage 16. 3P The second transistor M is coupled to the first amplification stage 12 1P And coupled to the second transistor M for cascading. 2P .

[0101] The specification and accompanying drawings illustrate only the principles of this disclosure. It will therefore be understood that those skilled in the art will be able to conceive of various arrangements exemplifying the principles of this disclosure and included within the spirit and scope of this disclosure (although not explicitly described or shown herein). Furthermore, all examples recorded herein are primarily and explicitly intended for illustrative purposes only to aid the reader in understanding the principles of this disclosure and the concepts contributed by (one or more) the inventors to advance the technology, and are to be understood not to limit the scope of such specific examples and conditions. Moreover, all statements and specific examples of the principles, aspects, and examples of this disclosure herein are intended to cover their equivalents.

[0102] A function block denoted as "a device for..." (performing a certain function) should be understood as a function block that includes circuitry configured to perform that function accordingly. Therefore, "a device for doing something" can also be understood as "a device configured or adapted to do something". A device configured to perform a function does not imply that the device must be performing that function (at a given moment).

[0103] The functionality of the various elements shown in the accompanying drawings (including any functional blocks labeled "device," "device for amplification," "device for cascading," etc.) can be provided using dedicated hardware (e.g., "amplifier," "cascader," etc.) and hardware capable of running software in conjunction with appropriate software. Furthermore, any entity described herein, such as "device," can correspond to or be implemented as "one or more modules," "one or more devices," "one or more units," etc. When functionality is provided by a processor, it can be provided by a single dedicated processor, a single shared processor, or multiple independent processors (some of which may be shared). Moreover, the explicit use of the terms "processor" or "controller" should not be construed as exclusively referring to hardware capable of running software, but may implicitly include, but is not limited to, digital signal processor (DSP) hardware, network processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), read-only memory (ROM) for storing software, random access memory (RAM), and non-transitory storage devices. Other conventional and / or custom hardware may also be included.

[0104] Those skilled in the art will understand that any block diagrams herein illustrate conceptual views of illustrative circuits representing the principles of this disclosure. Similarly, it will be understood that any flowchart, schematic diagram, state transition diagram, pseudocode, etc., represents various processes that can be substantially represented in a computer-readable medium and therefore executed by a computer or processor (whether or not such computer or processor is explicitly shown).

[0105] Furthermore, the appended claims are incorporated into the specific embodiments, wherein each claim may exist as a separate example on its own. While each claim may exist as a separate example on its own, it should be noted that although dependent claims may refer to a particular combination with one or more other claims in the claims statement, other examples may also include combinations of dependent claims with the subject matter of each of the other dependent or independent claims. Such combinations are suggested herein unless stated otherwise. Additionally, it is intended that the features of a claim be included in any other independent claim, even if that claim is not directly dependent on that independent claim.

[0106] It should also be noted that the methods disclosed in the specification or claims can be implemented by a device having means for performing each corresponding action of these methods.

[0107] Furthermore, it should be understood that the disclosure of multiple actions or functions as disclosed in the specification or claims is not to be construed as taking on a particular order. Therefore, the disclosure of multiple actions or functions does not limit these actions or functions to a particular order unless such actions or functions are not interchangeable for technical reasons. Additionally, in some examples, a single action may include multiple sub-actions or may be divided into multiple sub-actions. Unless expressly excluded, such sub-actions may be included and such sub-actions may be part of the disclosure of that single action.

Claims

1. An amplifier circuit for amplifying radio signals, the amplifier circuit comprising: The first amplification stage is configured to amplify the input signal to generate an intermediate signal; A cascaded circuit is configured to amplify the intermediate signal to generate a first output signal; as well as The second amplification stage is configured to amplify the intermediate signal to generate a second output signal; Each of the first amplification stage, the cascaded circuit, and the second amplification stage includes at least two transistors of different channel types; The first transistor of the first amplification stage is coupled to the negative power supply voltage or reference potential through a first resistor, and is also coupled to the first transistor of the cascaded circuit. The second transistor of the first amplification stage is coupled to the positive power supply voltage through a second resistor, and is also coupled to the second transistor of the cascaded circuit; and The first transistor of the cascaded circuit is coupled to the second transistor of the cascaded circuit.

2. The amplifier circuit of claim 1, wherein the first amplification stage includes a push-pull stage cascaded with the cascaded circuit.

3. The amplifier circuit of claim 1, wherein the input signal is coupled to the input terminal of the first transistor and the input terminal of the second transistor of the first amplifier stage, and the input terminals of the first transistor and the second transistor of the cascaded circuit are coupled to a reference potential.

4. The amplifier circuit as claimed in claim 1, wherein the first output signal and the second output signal form the differential output of the amplifier circuit.

5. The amplifier circuit of claim 1, wherein the input signal is coupled to the input terminal of the first transistor of the first amplifier stage via at least one capacitor, and the input signal is coupled to the input terminal of the second transistor of the first amplifier stage via at least one other capacitor.

6. The amplifier circuit of claim 1, wherein the input terminal of the first transistor of the cascaded circuit is coupled to the reference potential through at least one capacitor, and the input terminal of the second transistor of the cascaded circuit is coupled to the reference potential through at least one other capacitor.

7. The amplifier circuit of claim 1, wherein the second amplification stage includes a second push-pull stage configured to amplify the intermediate signal.

8. The amplifier circuit as described in claim 7, wherein The first transistor of the second amplification stage is coupled to a negative power supply voltage or a reference potential; The second transistor of the second amplification stage is coupled to the positive power supply voltage; The first transistor of the second amplification stage is coupled to the first transistor of the first amplification stage and the first transistor of the cascaded circuit; The second transistor of the second amplification stage is coupled to the second transistor of the first amplification stage and the second transistor of the cascaded circuit.

9. The amplifier circuit of claim 8, wherein the input terminal of the first transistor and the input terminal of the second transistor in the second amplifier stage are coupled by at least one capacitor.

10. The amplifier circuit of claim 8, wherein the input terminal of the first transistor of the second amplifier stage is coupled to the intermediate signal through at least one capacitor, and the input terminal of the second transistor of the second amplifier stage is coupled to the intermediate signal through at least one other capacitor.

11. The amplifier circuit as claimed in claim 8, wherein The first transistor of the second amplification stage is coupled to the negative power supply voltage or the reference potential through at least one resistor, and the second transistor of the second amplification stage is coupled to the positive power supply voltage through at least one other resistor.

12. The amplifier circuit of claim 1, wherein one of the first amplification stage and the second amplification stage is an inverting amplification stage, and the other is a non-inverting amplification stage.

13. The amplifier circuit of claim 1, wherein the at least two transistors in the first amplification stage, the cascaded circuit, and the second amplification stage are two metal-oxide-semiconductor field-effect transistors (MOSFETs) with different channel types.

14. The amplifier circuit of claim 1, wherein the input signal is coupled to the drain terminal of the first transistor of the cascaded circuit and the drain terminal of the second transistor of the cascaded circuit via resistors and capacitors.

15. The amplifier circuit of claim 1, wherein the input signal is a single-ended signal.

16. A method for amplifying radio signals, comprising: The input signal is amplified using the first amplification stage to generate an intermediate signal; The intermediate signal is amplified using a cascaded circuit to generate a first output signal; and The intermediate signal is amplified using a second amplification stage to generate a second output signal. Each of the first amplification stage, the cascaded circuit, and the second amplification stage includes at least two transistors of different channel types; The first transistor of the first amplification stage is coupled to the negative power supply voltage or reference potential through a first resistor, and is also coupled to the first transistor of the cascaded circuit. The second transistor of the first amplification stage is coupled to the positive power supply voltage through a second resistor, and is also coupled to the second transistor of the cascaded circuit; and The first transistor of the cascaded circuit is coupled to the second transistor of the cascaded circuit.

17. The method of claim 16, wherein the first amplification stage includes a push-pull stage cascaded with the cascaded circuit.

18. The method of claim 16, wherein the input signal is coupled to the drain terminal of the first transistor of the cascaded circuit and the drain terminal of the second transistor of the cascaded circuit via a resistor and a capacitor.

19. The method of claim 16, wherein the first output signal and the second output signal form a differential output.

20. A mobile terminal, comprising the amplifier circuit as described in claim 1.

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