An on-chip clock generator

Abstract

The application provides an on-chip clock generator applied to the technical field of integrated circuits, which comprises a capacitor, a P-type field effect transistor, an N-type field effect transistor, a temperature coefficient adjustable bias current circuit, a comparator, a logic shaping circuit, a D flip-flop, a logic delay circuit, a narrow pulse width generator, a first inverter, a second inverter and a third inverter. The bias current circuit outputs current to control the charging speed of the capacitor, the current temperature and the current size, eliminate the output frequency deviation of the on-chip clock generator and improve the output precision of the clock frequency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and particularly relates to an on-chip clock generator. BACKGROUND

[0002] The on-chip clock generator has the advantages of small size and low power consumption because it does not need a separate inductance and capacitance to generate a clock oscillation period like an off-chip crystal oscillator, and is therefore widely used in chip systems that require a clock in an on-chip SOC.

[0003] The existing on-chip clock generator generates a charging current through an adjustable current source, and the generated charging current charges a capacitor. When the charging voltage reaches the reference voltage set by the comparator, the capacitor is discharged through a logic gate, a sawtooth wave is generated on the capacitor, and the clock frequency is finally determined by adjusting the reference voltage of the comparator, the RC time constant of the capacitor charging, and the charging slope. However, the clock frequency generated by the existing on-chip clock generator has a large deviation, which cannot meet the high-precision requirement. SUMMARY

[0004] Therefore, the embodiments of the present application provide an on-chip clock generator, which aims to eliminate the output frequency deviation of the on-chip clock generator and improve the output precision of the clock frequency.

[0005] The embodiments of the present application provide an on-chip clock generator, which comprises a capacitor, a P-type field effect transistor, an N-type field effect transistor, a temperature coefficient adjustable bias current circuit, a comparator, a logic shaping circuit, a D flip-flop, a logic delay circuit, a narrow pulse width generator, a first inverter, a second inverter and a third inverter.

[0006] The temperature coefficient adjustable bias current circuit is connected with the P-type field effect transistor and the comparator respectively.

[0007] The P-type field effect transistor is connected with the temperature coefficient adjustable bias current circuit, the N-type field effect transistor, the capacitor and the comparator respectively.

[0008] The N-type field effect transistor is connected with the P-type field effect transistor, the comparator and the capacitor respectively, and the N-type field effect transistor is grounded.

[0009] The capacitor is connected with the P-type field effect transistor, the N-type field effect transistor and the comparator respectively, and the capacitor is grounded.

[0010] The comparator is connected with the temperature coefficient adjustable bias current circuit, the P-type field effect transistor, the N-type field effect transistor, the capacitor, the logic shaping circuit and a reference voltage respectively.

[0011] The logic shaping circuit is connected to the comparator and the first inverter, respectively.

[0012] The first inverter is connected to the logic shaping circuit, the D flip-flop, and the third inverter, respectively;

[0013] The third inverter is connected to the first inverter and the D flip-flop, and the third inverter outputs a clock CLK signal.

[0014] The D flip-flop is connected to the first inverter, the second inverter, the enable signal, the narrow pulse width generator, and the logic delay circuit, respectively.

[0015] The second inverter is connected to the D flip-flop and the enable signal, respectively;

[0016] The logic delay circuit is connected to the D flip-flop and the narrow pulse width generator, respectively.

[0017] The narrow pulse width generator is connected to the logic delay circuit and the D flip-flop, respectively.

[0018] Optionally, the temperature coefficient adjustable bias current circuit includes: an external current source, a first P-type field-effect transistor, a second P-type field-effect transistor, a third P-type field-effect transistor, a fourth P-type field-effect transistor, a fifth P-type field-effect transistor, a sixth P-type field-effect transistor, a seventh P-type field-effect transistor, an eighth P-type field-effect transistor, a ninth P-type field-effect transistor, a first N-type field-effect transistor, a second N-type field-effect transistor, a third N-type field-effect transistor, a fourth N-type field-effect transistor, a fifth N-type field-effect transistor, a sixth N-type field-effect transistor, a first resistor, a second resistor, a third resistor, a bipolar transistor, a first output port, and a second output port.

[0019] Optionally, the third resistor is a variable resistor.

[0020] Optionally, the connection relationship of the temperature coefficient adjustable bias current circuit is as follows:

[0021] The first P-type field-effect transistor is connected to the second P-type field-effect transistor, the third P-type field-effect transistor, the fourth P-type field-effect transistor, the fifth P-type field-effect transistor, the sixth P-type field-effect transistor, the seventh P-type field-effect transistor, the first resistor, and the power supply, respectively.

[0022] The second P-type field-effect transistor is connected to the first P-type field-effect transistor, the third P-type field-effect transistor, the fourth P-type field-effect transistor, the fifth P-type field-effect transistor, the sixth P-type field-effect transistor, the seventh P-type field-effect transistor, the eighth P-type field-effect transistor, the first resistor, and the power supply, respectively.

[0023] The third P-type field-effect transistor is connected to the first P-type field-effect transistor, the second P-type field-effect transistor, the fourth P-type field-effect transistor, the fifth P-type field-effect transistor, the sixth P-type field-effect transistor, the ninth P-type field-effect transistor, and the power supply, respectively.

[0024] The fourth P-type field-effect transistor is connected to the first P-type field-effect transistor, the second P-type field-effect transistor, the third P-type field-effect transistor, the fifth P-type field-effect transistor, the sixth P-type field-effect transistor, the fifth N-type field-effect transistor, the sixth N-type field-effect transistor, and the power supply, respectively.

[0025] The fifth P-type field-effect transistor is connected to the first P-type field-effect transistor, the second P-type field-effect transistor, the third P-type field-effect transistor, the fourth P-type field-effect transistor, the sixth P-type field-effect transistor, the third N-type field-effect transistor, the sixth N-type field-effect transistor, and the power supply, respectively.

[0026] The sixth P-type field-effect transistor is connected to the first P-type field-effect transistor, the second P-type field-effect transistor, the third P-type field-effect transistor, the fourth P-type field-effect transistor, the fifth P-type field-effect transistor, the third N-type field-effect transistor, the sixth N-type field-effect transistor, the power supply, and the first output port, respectively.

[0027] The seventh P-type field-effect transistor is connected to the first P-type field-effect transistor, the eighth P-type field-effect transistor, and the first resistor, respectively.

[0028] The eighth P-type field-effect transistor is connected to the second P-type field-effect transistor, the seventh P-type field-effect transistor, the ninth P-type field-effect transistor, the first resistor, and the second output port, respectively.

[0029] The ninth P-type field-effect transistor is connected to the third P-type field-effect transistor, the eighth P-type field-effect transistor, the second resistor, the first N-type field-effect transistor, and the third N-type field-effect transistor, respectively.

[0030] The first resistor is connected to the first P-type field-effect transistor, the second P-type field-effect transistor, the seventh P-type field-effect transistor, the eighth P-type field-effect transistor, and the external power supply, respectively.

[0031] The second resistor is connected to the ninth P-type field-effect transistor, the first N-type field-effect transistor, the second N-type field-effect transistor, the third N-type field-effect transistor, and the fourth N-type field-effect transistor, respectively.

[0032] The first N-type field-effect transistor is connected to the second resistor, the second N-type field-effect transistor, the third N-type field-effect transistor, and the fourth N-type field-effect transistor, respectively;

[0033] The second N-type field-effect transistor is connected to the first N-type field-effect transistor, the third N-type field-effect transistor, the fourth N-type field-effect transistor, and the second resistor, respectively, and the second N-type field-effect transistor is grounded;

[0034] The third N-type field-effect transistor is connected to the second resistor, the first N-type field-effect transistor, the second N-type field-effect transistor, the fourth N-type field-effect transistor, the sixth N-type field-effect transistor, the fifth P-type field-effect transistor, and the sixth P-type field-effect transistor, respectively.

[0035] The fourth N-type field-effect transistor is connected to the first N-type field-effect transistor, the second N-type field-effect transistor, the third N-type field-effect transistor, the second resistor, the bipolar transistor, and the third resistor, respectively, and the fourth N-type field-effect transistor is grounded;

[0036] The fifth N-type field-effect transistor is connected to the fourth P-type field-effect transistor, the sixth N-type field-effect transistor, and the bipolar transistor, respectively;

[0037] The sixth N-type field-effect transistor is connected to the fourth P-type field-effect transistor, the fifth P-type field-effect transistor, the sixth P-type field-effect transistor, the third N-type field-effect transistor, the fifth N-type field-effect transistor, the bipolar transistor, and the third resistor, respectively.

[0038] The bipolar transistor is connected to the second N-type field-effect transistor, the fourth N-type field-effect transistor, the fifth N-type field-effect transistor, the sixth N-type field-effect transistor, and the third resistor, respectively, and the bipolar transistor is grounded;

[0039] The third resistor is connected to the second N-type field-effect transistor, the fourth N-type field-effect transistor, the sixth N-type field-effect transistor, and the bipolar transistor, respectively, and the third resistor is grounded.

[0040] Optionally, the temperature coefficient adjustable bias current circuit is used to output two bias currents.

[0041] Optionally, the logic shaping circuit is used to adjust the waveform of the pulse signal.

[0042] Optionally, the logic delay circuit is used to demonstrate the transmission of the pulse signal.

[0043] This application provides an on-chip clock generator. The on-chip clock generator includes a capacitor, a P-type field-effect transistor, an N-type field-effect transistor, a bias current circuit, a comparator, a logic shaping circuit, a D flip-flop, a logic delay circuit, a narrow pulse width generator, a first inverter, a second inverter, and a third inverter. The bias current circuit outputs current to control the charging speed, current temperature, and current magnitude of the capacitor, thereby eliminating output frequency deviation of the on-chip clock generator and improving the output accuracy of the clock frequency. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in this embodiment or the prior art, the drawings used in the description of the embodiment or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 A circuit schematic diagram of an on-chip clock generator provided in an embodiment of this application;

[0046] Figure 2 This is a circuit diagram of a temperature coefficient adjustable bias current circuit provided in an embodiment of this application. Detailed Implementation

[0047] Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0048] See Figure 1 , Figure 1 A circuit schematic diagram of an on-chip clock generator provided in this application embodiment includes:

[0049] exist Figure 1In the diagram, MP1 is a P-type field-effect transistor, C is a capacitor, IBIAS1 and IBIAS2 are the two bias currents output by the temperature coefficient adjustable bias current circuit, MN1 is an N-type field-effect transistor, CMP is a comparator, VREF is a reference voltage, INV1 is the first inverter, INV2 is the second inverter, INV3 is the third inverter, EN is the enable signal, and CLK is the clock signal.

[0050] The on-chip clock generator includes: a capacitor, a P-type field-effect transistor, an N-type field-effect transistor, a temperature coefficient adjustable bias current circuit, a comparator, a logic shaping circuit, a D flip-flop, a logic delay circuit, a narrow pulse width generator, a first inverter, a second inverter, and a third inverter;

[0051] The temperature coefficient adjustable bias current circuit is connected to the P-type field-effect transistor and the comparator, respectively.

[0052] The P-type field-effect transistor is connected to the temperature coefficient adjustable bias current circuit, the N-type field-effect transistor, the capacitor, and the comparator, respectively.

[0053] The N-type field-effect transistor is connected to the P-type field-effect transistor, the comparator, and the capacitor, respectively, and the N-type field-effect transistor is grounded;

[0054] The capacitor is connected to the P-type field-effect transistor, the N-type field-effect transistor, and the comparator, respectively, and the capacitor is grounded;

[0055] The comparator is connected to the temperature coefficient adjustable bias current circuit, the P-type field-effect transistor, the N-type field-effect transistor, the capacitor, the logic shaping circuit, and the reference voltage, respectively.

[0056] The logic shaping circuit is connected to the comparator and the first inverter, respectively.

[0057] The first inverter is connected to the logic shaping circuit, the D flip-flop, and the third inverter, respectively;

[0058] The third inverter is connected to the first inverter and the D flip-flop, and the third inverter outputs a clock CLK signal.

[0059] The D flip-flop is connected to the first inverter, the second inverter, the enable signal, the narrow pulse width generator, and the logic delay circuit, respectively.

[0060] The second inverter is connected to the D flip-flop and the enable signal, respectively;

[0061] The logic delay circuit is connected to the D flip-flop and the narrow pulse width generator, respectively.

[0062] The narrow pulse width generator is connected to the logic delay circuit and the D flip-flop, respectively.

[0063] Specifically, the two outputs of the temperature coefficient adjustable bias current circuit are respectively connected to the source of the P-type field-effect transistor and the comparator. The drain of the P-type field-effect transistor is simultaneously connected to the drain of the N-type field-effect transistor and the positive input of the comparator. The gate of the P-type field-effect transistor is simultaneously connected to the gate of the N-type field-effect transistor and the Q output of the D flip-flop. The source of the N-type field-effect transistor is grounded. The upper end of the capacitor is connected to the drain of the N-type field-effect transistor, and the lower end is grounded. The negative terminal of the comparator is connected to the reference voltage. The output of the comparator is connected to the input of the logic shaping circuit. The output of the logic shaping circuit is connected to the input of the first inverter. The first inverter... The output is simultaneously connected to the input of the third inverter and the SETN terminal of the D flip-flop. The output of the third inverter is the clock signal CLK. The input of the second inverter is simultaneously connected to the enable signal and the CK terminal of the D flip-flop. The output of the second inverter is connected to the D terminal of the D flip-flop. The RESETN terminal of the D flip-flop is connected to the output of the narrow pulse width generator. The Q terminal of the D flip-flop is connected to the input of the logic delay circuit. The output of the logic delay circuit is connected to the input of the narrow pulse width generator. The temperature coefficient adjustable bias current circuit is used to output two bias currents. The logic shaping circuit is used to adjust the pulse signal waveform. The logic delay circuit is used to transmit the pulse signal.

[0064] When the on-chip clock generator is working, the initial state EN is set from 0 to 1. At this time, the CLK pin output is 0, and CLK is connected to the D flip-flop via INV3, making the SETN pin 1. RESETN changes from 0 to 1. The Q output of the D flip-flop remains unchanged at 0. At this time, MP1 is turned on, MN1 is turned off, and the current IBIAS1 generated by the temperature coefficient adjustable bias current circuit charges capacitor C through MP1. This is the charging cycle. When the voltage level charged to C reaches the given bias voltage VREF, the comparator CMP output becomes 1. After passing through the logic shaping circuit and INV1 and INV2, the output CLK changes from 0 to 1. At this time, SETN becomes 0. Due to the logic delay circuit, RESETN is still 1. This delay determines the discharge time. At this time, the Q output becomes 1, causing MN1 to turn on and MP1 to turn off. Capacitor C discharges to ground through MN1. When the voltage level on capacitor C is less than VREF, SETN changes from 0 to 1. When the delay ends, RESETN jumps from 1 to 0, and the Q output becomes 0, restarting the charging cycle. Because of the narrow pulse generator, RESETN becomes 1, and Q maintains its output of 0. The same applies to the next cycle.

[0065] The on-chip clock generator provided in this application embodiment can maintain accurate output current under different voltages through a temperature-adjustable bias current circuit. Simultaneously, because the temperature coefficient of the bias current circuit is adjustable, the charging time of the capacitor by the output INIAS1 becomes controllable at different temperatures, solving the problem of capacitor charging time deviation. Furthermore, at high temperatures, the temperature-adjustable bias current circuit can increase the current to the capacitor, making the capacitor charge faster and compensating for the delay caused by high temperatures in the logic unit. In addition, the output IBIAS2 of the temperature-adjustable bias current circuit serves as the bias current for the comparator. Since the comparator CMP is composed of field-effect transistors, the transistor mobility decreases at high temperatures, resulting in a slower speed and deviation. By increasing the current of IBIAS2 at high temperatures, the carrier concentration is increased to compensate for the deviation caused by the slower speed at high temperatures, effectively eliminating the output frequency deviation of the on-chip clock generator and improving the output accuracy of the clock frequency.

[0066] Additionally, this application provides a preferred temperature-coefficient adjustable bias current circuit. See also... Figure 2 , Figure 2 This is a circuit diagram of a temperature coefficient adjustable bias current circuit provided in an embodiment of this application.

[0067] exist Figure 2In this circuit, VDD is the power supply, I1 is the external current source, I2, I3, and I4 indicate the current flow direction in the circuit, MP1 is the first P-type field-effect transistor, MP2 is the second P-type field-effect transistor, MP3 is the third P-type field-effect transistor, MP4 is the fourth P-type field-effect transistor, MP5 is the fifth P-type field-effect transistor, MP6 is the sixth P-type field-effect transistor, MP7 is the seventh P-type field-effect transistor, MP8 is the eighth P-type field-effect transistor, MP9 is the ninth P-type field-effect transistor, MN1 is the first N-type field-effect transistor, MN2 is the second N-type field-effect transistor, MN3 is the third N-type field-effect transistor, MN4 is the fourth N-type field-effect transistor, MN5 is the fifth N-type field-effect transistor, MN6 is the sixth N-type field-effect transistor, IBIAS1 is the current output from the first output port, IBIAS2 is the current output from the second output port, R1 is the first resistor, R2 is the second resistor, R3 is the third resistor, and NPN1 is a bipolar transistor.

[0068] The temperature-coefficient adjustable bias current circuit includes: an external current source, a first P-type field-effect transistor, a second P-type field-effect transistor, a third P-type field-effect transistor, a fourth P-type field-effect transistor, a fifth P-type field-effect transistor, a sixth P-type field-effect transistor, a seventh P-type field-effect transistor, an eighth P-type field-effect transistor, a ninth P-type field-effect transistor, a first N-type field-effect transistor, a second N-type field-effect transistor, a third N-type field-effect transistor, a fourth N-type field-effect transistor, a fifth N-type field-effect transistor, a sixth N-type field-effect transistor, a first resistor, a second resistor, a third resistor, a bipolar transistor, a first output port, and a second output port. Preferably, the third resistor is a variable resistor.

[0069] The connection relationship of the temperature coefficient adjustable bias current circuit is as follows:

[0070] The first P-type field-effect transistor is connected to the second P-type field-effect transistor, the third P-type field-effect transistor, the fourth P-type field-effect transistor, the fifth P-type field-effect transistor, the sixth P-type field-effect transistor, the seventh P-type field-effect transistor, the first resistor, and the power supply, respectively.

[0071] The second P-type field-effect transistor is connected to the first P-type field-effect transistor, the third P-type field-effect transistor, the fourth P-type field-effect transistor, the fifth P-type field-effect transistor, the sixth P-type field-effect transistor, the seventh P-type field-effect transistor, the eighth P-type field-effect transistor, the first resistor, and the power supply, respectively.

[0072] The third P-type field-effect transistor is connected to the first P-type field-effect transistor, the second P-type field-effect transistor, the fourth P-type field-effect transistor, the fifth P-type field-effect transistor, the sixth P-type field-effect transistor, the ninth P-type field-effect transistor, and the power supply, respectively.

[0073] The fourth P-type field-effect transistor is connected to the first P-type field-effect transistor, the second P-type field-effect transistor, the third P-type field-effect transistor, the fifth P-type field-effect transistor, the sixth P-type field-effect transistor, the fifth N-type field-effect transistor, the sixth N-type field-effect transistor, and the power supply, respectively.

[0074] The fifth P-type field-effect transistor is connected to the first P-type field-effect transistor, the second P-type field-effect transistor, the third P-type field-effect transistor, the fourth P-type field-effect transistor, the sixth P-type field-effect transistor, the third N-type field-effect transistor, the sixth N-type field-effect transistor, and the power supply, respectively.

[0075] The sixth P-type field-effect transistor is connected to the first P-type field-effect transistor, the second P-type field-effect transistor, the third P-type field-effect transistor, the fourth P-type field-effect transistor, the fifth P-type field-effect transistor, the third N-type field-effect transistor, the sixth N-type field-effect transistor, the power supply, and the first output port, respectively.

[0076] The seventh P-type field-effect transistor is connected to the first P-type field-effect transistor, the eighth P-type field-effect transistor, and the first resistor, respectively.

[0077] The eighth P-type field-effect transistor is connected to the second P-type field-effect transistor, the seventh P-type field-effect transistor, the ninth P-type field-effect transistor, the first resistor, and the second output port, respectively.

[0078] The ninth P-type field-effect transistor is connected to the third P-type field-effect transistor, the eighth P-type field-effect transistor, the second resistor, the first N-type field-effect transistor, and the third N-type field-effect transistor, respectively.

[0079] The first resistor is connected to the first P-type field-effect transistor, the second P-type field-effect transistor, the seventh P-type field-effect transistor, the eighth P-type field-effect transistor, and the external power supply, respectively.

[0080] The second resistor is connected to the ninth P-type field-effect transistor, the first N-type field-effect transistor, the second N-type field-effect transistor, the third N-type field-effect transistor, and the fourth N-type field-effect transistor, respectively.

[0081] The first N-type field-effect transistor is connected to the second resistor, the second N-type field-effect transistor, the third N-type field-effect transistor, and the fourth N-type field-effect transistor, respectively;

[0082] The second N-type field-effect transistor is connected to the first N-type field-effect transistor, the third N-type field-effect transistor, the fourth N-type field-effect transistor, and the second resistor, respectively, and the second N-type field-effect transistor is grounded;

[0083] The third N-type field-effect transistor is connected to the second resistor, the first N-type field-effect transistor, the second N-type field-effect transistor, the fourth N-type field-effect transistor, the sixth N-type field-effect transistor, the fifth P-type field-effect transistor, and the sixth P-type field-effect transistor, respectively.

[0084] The fourth N-type field-effect transistor is connected to the first N-type field-effect transistor, the second N-type field-effect transistor, the third N-type field-effect transistor, the second resistor, the bipolar transistor, and the third resistor, respectively, and the fourth N-type field-effect transistor is grounded;

[0085] The fifth N-type field-effect transistor is connected to the fourth P-type field-effect transistor, the sixth N-type field-effect transistor, and the bipolar transistor, respectively;

[0086] The sixth N-type field-effect transistor is connected to the fourth P-type field-effect transistor, the fifth P-type field-effect transistor, the sixth P-type field-effect transistor, the third N-type field-effect transistor, the fifth N-type field-effect transistor, the bipolar transistor, and the third resistor, respectively.

[0087] The bipolar transistor is connected to the second N-type field-effect transistor, the fourth N-type field-effect transistor, the fifth N-type field-effect transistor, the sixth N-type field-effect transistor, and the third resistor, respectively, and the bipolar transistor is grounded;

[0088] The third resistor is connected to the second N-type field-effect transistor, the fourth N-type field-effect transistor, the sixth N-type field-effect transistor, and the bipolar transistor, respectively, and the third resistor is grounded.

[0089] Specifically, the source of the first P-type field-effect transistor is connected to the external current source, the drain of the first P-type field-effect transistor is connected to the source of the seventh P-type field-effect transistor, and the gate of the first P-type field-effect transistor is simultaneously connected to the gate of the second P-type field-effect transistor and the drain of the seventh P-type field-effect transistor; the source of the second P-type field-effect transistor is connected to the external current source, the drain of the second P-type field-effect transistor is connected to the source of the eighth P-type field-effect transistor, the source of the third P-type field-effect transistor is connected to the external current source, the gate of the third P-type field-effect transistor is connected to the gate of the second P-type field-effect transistor, and the drain of the third P-type field-effect transistor is connected to the external current source. The source of the ninth P-type field-effect transistor is connected to the external current source. The drain of the fourth P-type field-effect transistor is simultaneously connected to the drain and gate of the fifth N-type field-effect transistor. The gate of the fourth P-type field-effect transistor is connected to the gate of the first P-type field-effect transistor. The source of the fifth P-type field-effect transistor is connected to the external current source. The drain of the fifth P-type field-effect transistor is simultaneously connected to the drain of the sixth N-type field-effect transistor and the drain of the third N-type field-effect transistor. The gate of the fifth P-type field-effect transistor is simultaneously connected to the gate of the sixth P-type field-effect transistor and the drain of the fifth P-type field-effect transistor. The source of the P-type field-effect transistor is connected to the external current source. The drain of the sixth P-type field-effect transistor is connected to the first output port. The drain of the seventh P-type field-effect transistor is connected to the upper end of the first resistor. The gate of the seventh P-type field-effect transistor is simultaneously connected to the gate of the eighth P-type field-effect transistor and the lower end of the first resistor. The drain of the eighth P-type field-effect transistor is connected to the second output port. The drain of the ninth P-type field-effect transistor is simultaneously connected to the upper end of the second resistor and the gate of the first N-type field-effect transistor. The gate of the ninth P-type field-effect transistor is connected to the gate of the eighth P-type field-effect transistor. The drain of the first N-type field-effect transistor is simultaneously connected to the second resistor. The lower end of the first N-type field-effect transistor is connected to the gate of the second N-type field-effect transistor. The source of the first N-type field-effect transistor is connected to the drain of the second N-type field-effect transistor. The gate of the first N-type field-effect transistor is simultaneously connected to the upper end of the second resistor and the gate of the third N-type field-effect transistor. The source of the second N-type field-effect transistor is grounded. The gate of the second N-type field-effect transistor is simultaneously connected to the lower end of the second resistor and the gate of the fourth N-type field-effect transistor. The drain of the third N-type field-effect transistor is connected to the drain of the sixth N-type field-effect transistor. The drain of the fourth N-type field-effect transistor is connected to the source of the third N-type field-effect transistor. The source of the fourth N-type field-effect transistor is grounded.The gate of the fifth N-type field-effect transistor is simultaneously connected to the drain of the fourth P-type field-effect transistor and the gate of the fifth N-type field-effect transistor. The source of the fifth N-type field-effect transistor is connected to the collector of the bipolar transistor. The gate of the fifth N-type field-effect transistor is connected to the gate of the sixth N-type field-effect transistor. The drain of the fifth N-type field-effect transistor is connected to the drain of the sixth N-type field-effect transistor. The source of the sixth N-type field-effect transistor is simultaneously connected to the base of the bipolar transistor and the upper end of the third resistor. The upper end of the third resistor is simultaneously connected to the base of the bipolar transistor and the source of the sixth N-type field-effect transistor. The lower end of the third resistor is grounded. The emitter of the bipolar transistor is grounded.

[0090] In the aforementioned temperature coefficient adjustable bias current circuit, the current I1 is supplied through other external circuits, typically a reference bandgap, and is a non-adjustable positive temperature coefficient current. After being amplified by the required M1 times by the current mirror composed of MP1, MP2, MP7, and MP8, the output IBIAS2 has a positive temperature coefficient greater than IBIAS1, and is supplied to... Figure 2 The comparator circuit in the middle serves as its current bias. At high temperatures, the comparator speed decreases due to the reduced carrier mobility, but the IBIAS2 current increases to compensate for the speed loss caused by the decreased mobility. The current of MP5 consists of two parts: the current I2 amplified by the current mirror composed of MN1, MN2, MN3, and MN4, and the current I3 generated by the base-collector voltage VBE of NPN1 across the variable resistor R3, i.e., I4 = I2 + I3. Substituting I2 and I3 respectively, we get I4 = M2 * I1 + VBE / R3. From the formula, we can see that I2 is the positive temperature coefficient current and I3 is the negative temperature coefficient current. Increasing the size of M2 and increasing R3 can increase the positive temperature coefficient, making the slope of I4 more pronounced with increasing temperature, or only decreasing R3 can increase the negative temperature coefficient, making the slope of I4 more pronounced with increasing temperature. The temperature-adjustable current I4 is then amplified by M3 times by the current mirror composed of MP5 and MP6 to output IBIAS1. IBIAS1 serves as... Figure 2 The bias current used to charge the capacitor.

[0091] The temperature coefficient adjustable bias current circuit provided by the embodiments of the present invention can effectively control the slope of the current change with temperature, thereby effectively eliminating the output frequency deviation of the on-chip clock generator and improving the output accuracy of the clock frequency.

[0092] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0093] The above description is merely an exemplary implementation of this application and is not intended to limit the scope of protection of this application.

Claims

1. An on-chip clock generator, characterized in that, The on-chip clock generator includes: a capacitor, a P-type field-effect transistor, an N-type field-effect transistor, a temperature coefficient adjustable bias current circuit, a comparator, a logic shaping circuit, a D flip-flop, a logic delay circuit, a narrow pulse width generator, a first inverter, a second inverter, and a third inverter. The temperature coefficient adjustable bias current circuit is connected to the P-type field-effect transistor and the comparator, respectively. The P-type field-effect transistor is connected to the temperature coefficient adjustable bias current circuit, the N-type field-effect transistor, the capacitor, and the comparator, respectively. The N-type field-effect transistor is connected to the P-type field-effect transistor, the comparator, and the capacitor, respectively, and the N-type field-effect transistor is grounded; The capacitor is connected to the P-type field-effect transistor, the N-type field-effect transistor, and the comparator, respectively, and the capacitor is grounded; The comparator is connected to the temperature coefficient adjustable bias current circuit, the P-type field-effect transistor, the N-type field-effect transistor, the capacitor, the logic shaping circuit, and the reference voltage, respectively. The logic shaping circuit is connected to the comparator and the first inverter, respectively. The first inverter is connected to the logic shaping circuit, the D flip-flop, and the third inverter, respectively; The third inverter is connected to the first inverter and the D flip-flop, and the third inverter outputs a clock CLK signal. The D flip-flop is connected to the first inverter, the second inverter, the enable signal, the narrow pulse width generator, and the logic delay circuit, respectively. The second inverter is connected to the D flip-flop and the enable signal, respectively; The logic delay circuit is connected to the D flip-flop and the narrow pulse width generator, respectively. The narrow pulse width generator is connected to the logic delay circuit and the D flip-flop, respectively.

2. The on-chip clock generator according to claim 1, characterized in that, The temperature coefficient adjustable bias current circuit includes: an external current source, a first P-type field-effect transistor, a second P-type field-effect transistor, a third P-type field-effect transistor, a fourth P-type field-effect transistor, a fifth P-type field-effect transistor, a sixth P-type field-effect transistor, a seventh P-type field-effect transistor, an eighth P-type field-effect transistor, a ninth P-type field-effect transistor, a first N-type field-effect transistor, a second N-type field-effect transistor, a third N-type field-effect transistor, a fourth N-type field-effect transistor, a fifth N-type field-effect transistor, a sixth N-type field-effect transistor, a first resistor, a second resistor, a third resistor, a bipolar transistor, a first output port, and a second output port.

3. The on-chip clock generator according to claim 2, characterized in that, The third resistor is a variable resistor.

4. The on-chip clock generator according to claim 2, characterized in that, The connection relationship of the temperature coefficient adjustable bias current circuit is as follows: The first P-type field-effect transistor is connected to the second P-type field-effect transistor, the third P-type field-effect transistor, the fourth P-type field-effect transistor, the fifth P-type field-effect transistor, the sixth P-type field-effect transistor, the seventh P-type field-effect transistor, the first resistor, and the power supply, respectively. The second P-type field-effect transistor is connected to the first P-type field-effect transistor, the third P-type field-effect transistor, the fourth P-type field-effect transistor, the fifth P-type field-effect transistor, the sixth P-type field-effect transistor, the seventh P-type field-effect transistor, the eighth P-type field-effect transistor, the first resistor, and the power supply, respectively. The third P-type field-effect transistor is connected to the first P-type field-effect transistor, the second P-type field-effect transistor, the fourth P-type field-effect transistor, the fifth P-type field-effect transistor, the sixth P-type field-effect transistor, the ninth P-type field-effect transistor, and the power supply, respectively. The fourth P-type field-effect transistor is connected to the first P-type field-effect transistor, the second P-type field-effect transistor, the third P-type field-effect transistor, the fifth P-type field-effect transistor, the sixth P-type field-effect transistor, the fifth N-type field-effect transistor, the sixth N-type field-effect transistor, and the power supply, respectively. The fifth P-type field-effect transistor is connected to the first P-type field-effect transistor, the second P-type field-effect transistor, the third P-type field-effect transistor, the fourth P-type field-effect transistor, the sixth P-type field-effect transistor, the third N-type field-effect transistor, the sixth N-type field-effect transistor, and the power supply, respectively. The sixth P-type field-effect transistor is connected to the first P-type field-effect transistor, the second P-type field-effect transistor, the third P-type field-effect transistor, the fourth P-type field-effect transistor, the fifth P-type field-effect transistor, the third N-type field-effect transistor, the sixth N-type field-effect transistor, the power supply, and the first output port, respectively. The seventh P-type field-effect transistor is connected to the first P-type field-effect transistor, the eighth P-type field-effect transistor, and the first resistor, respectively. The eighth P-type field-effect transistor is connected to the second P-type field-effect transistor, the seventh P-type field-effect transistor, the ninth P-type field-effect transistor, the first resistor, and the second output port, respectively. The ninth P-type field-effect transistor is connected to the third P-type field-effect transistor, the eighth P-type field-effect transistor, the second resistor, the first N-type field-effect transistor, and the third N-type field-effect transistor, respectively. The first resistor is connected to the first P-type field-effect transistor, the second P-type field-effect transistor, the seventh P-type field-effect transistor, the eighth P-type field-effect transistor, and the external current source, respectively. The second resistor is connected to the ninth P-type field-effect transistor, the first N-type field-effect transistor, the second N-type field-effect transistor, the third N-type field-effect transistor, and the fourth N-type field-effect transistor, respectively. The first N-type field-effect transistor is connected to the second resistor, the second N-type field-effect transistor, the third N-type field-effect transistor, and the fourth N-type field-effect transistor, respectively; The second N-type field-effect transistor is connected to the first N-type field-effect transistor, the third N-type field-effect transistor, the fourth N-type field-effect transistor, and the second resistor, respectively, and the second N-type field-effect transistor is grounded; The third N-type field-effect transistor is connected to the second resistor, the first N-type field-effect transistor, the second N-type field-effect transistor, the fourth N-type field-effect transistor, the sixth N-type field-effect transistor, the fifth P-type field-effect transistor, and the sixth P-type field-effect transistor, respectively. The fourth N-type field-effect transistor is connected to the first N-type field-effect transistor, the second N-type field-effect transistor, the third N-type field-effect transistor, the second resistor, the bipolar transistor, and the third resistor, respectively, and the fourth N-type field-effect transistor is grounded; The fifth N-type field-effect transistor is connected to the fourth P-type field-effect transistor, the sixth N-type field-effect transistor, and the bipolar transistor, respectively; The sixth N-type field-effect transistor is connected to the fourth P-type field-effect transistor, the fifth P-type field-effect transistor, the sixth P-type field-effect transistor, the third N-type field-effect transistor, the fifth N-type field-effect transistor, the bipolar transistor, and the third resistor, respectively. The bipolar transistor is connected to the second N-type field-effect transistor, the fourth N-type field-effect transistor, the fifth N-type field-effect transistor, the sixth N-type field-effect transistor, and the third resistor, respectively, and the bipolar transistor is grounded; The third resistor is connected to the second N-type field-effect transistor, the fourth N-type field-effect transistor, the sixth N-type field-effect transistor, and the bipolar transistor, respectively, and the third resistor is grounded.

5. The on-chip clock generator according to claim 1, characterized in that, The temperature coefficient adjustable bias current circuit is used to output two bias currents.

6. The on-chip clock generator according to claim 1, characterized in that, The logic shaping circuit is used to adjust the waveform of the pulse signal.

7. The on-chip clock generator according to claim 1, characterized in that, The logic delay circuit is used to transmit the pulse signal in a demonstration.

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