An oscillator circuit with precise high duty cycle output

Abstract

The present application belongs to the field of integrated circuits, and particularly relates to an oscillator circuit with precise high duty cycle output, comprising two resistors, a current source I1, two PMOS transistors, two NMOS transistors, two capacitors, three comparators, an RS latch LATCH1, an inverter INV1 and a NAND gate NAND1; each device is connected to form an oscillator circuit, which comprises three working stages, namely a capacitor C2 charging stage, a first capacitor C1 charging stage and a second capacitor C1 charging stage; wherein the capacitor C2 charging stage, the first capacitor C1 charging stage and the second capacitor C1 charging stage are sequentially circulated, and each cycle is a period of the oscillator, generating an oscillator output signal V OSC1 and V OSC2 ; the present application can output a high duty cycle signal; the present application can simultaneously output two different duty cycle signals, meeting the demand of complex switching power supply chips for multiple clock signals.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and specifically relates to an oscillator circuit with a precise high duty cycle output. Background Technology

[0002] The oscillator is a common submodule in switching power supply chips. The frequency of its output signal determines the switching frequency, and its duty cycle is also a crucial parameter of the switching power supply chip. A high duty cycle means the switching power supply chip can output higher voltages, thus expanding the output voltage range. To achieve high duty cycle requirements, existing oscillators typically use MOS switches to rapidly discharge the charging capacitor. However, this method cannot precisely control the discharge time. Summary of the Invention

[0003] To address the problems existing in the prior art, this invention proposes an oscillator circuit with accurate high duty cycle output. The circuit structure includes: two resistors, a current source I1, two PMOS transistors, two NMOS transistors, two capacitors, three comparators, an RS latch LATCH1, an inverter INV1, and a NAND gate NAND1; one end of resistor R1 is connected to a reference voltage V. R1 The other end is connected to resistor R2 and then to the positive terminal of comparator CMP1; the other end of resistor R2 is grounded; the positive terminal of current source I1 is connected to the power supply voltage VCC, and the negative terminal V... B Connect the sources of PMOS transistors MP1 and MP2; the gate of MP1 is connected to the gate of NMOS transistor MN1 and the output terminal QN of RS latch LATCH1, and its drain is connected to the drain of MN1, the positive terminal of capacitor C1, the negative terminal of CMP1, and the negative terminal of CMP2; the source of MN1 and the negative terminal of capacitor C1 are both grounded; the gate of MP2 is connected to the gate of MN2, the output terminal Q of LATCH1, and one input terminal of NAND gate NAND1; the drain of MP2 is connected to the drain of MN2, the positive terminal of capacitor C2, and the negative terminal of CMP3; the source of MN2 and the negative terminal of C2 are both grounded; the output of CMP1 is connected to the input terminal of inverter INV1; the output of CMP2 is connected to the input terminal R of LATCH1; the output of CMP3 is connected to the input terminal S of LATCH1; the output terminal of INV1 is connected to the other input terminal of NAND1.

[0004] Preferably, the gate of PMOS transistor MP2 is the second signal output terminal V of the oscillator circuit. OSC2 ;

[0005] The output of NAND1 serves as the first signal output terminal V of the oscillator. OSC1 .

[0006] Preferably, the oscillator circuit includes three operating stages: a charging stage for capacitor C2, a first charging stage for capacitor C1, and a second charging stage for capacitor C1. These stages cycle sequentially, with each cycle constituting one oscillator cycle, generating the oscillator output signal V. OSC1 and V OSC2 .

[0007] Furthermore, the charging stage of capacitor C2 includes: the initial state of the circuit is V1 = 1, V OSC2 =0, at this time MP2 is turned on, MN2 is turned off, and C2 starts constant current charging; since MP1 is turned off and MN2 is turned on, V C1 =0, V OSC1 =1; when V C2 =V R1 At that time, capacitor C2 is fully charged.

[0008] Furthermore, the first charging phase of capacitor C1 includes: when V C2 The voltage reaches the toggling threshold V of comparator CMP3. R2 At that time, V1 = 0, V OSC2 =1, at this time MP2 is off, MN2 is on, and the voltage across C2 drops to 0; since MP1 is on and MN1 is off, C1 begins constant current charging, V C2 =0, V OSC1 =1, when V C1 =V R2 The first charging phase of capacitor C1 is completed.

[0009] Furthermore, the second charging stage of capacitor C1 includes: when V C1 The voltage reaches the toggling threshold V of comparator CMP1. R2 At that time, V1 = 0, V OSC2 =1, V OSC1 =0, C1 continues constant current charging; when V C1 The voltage reaches the toggling threshold V of comparator CMP2. R1 At that time, V1 = 1, V OSC2 =0, V OSC1 =1, the second charging stage of capacitor C1 is completed.

[0010] The beneficial effects of this invention are:

[0011] This invention allows for precise setting of the duty cycle by adjusting the values ​​of capacitors and resistors; it can output high duty cycle signals; and it can simultaneously output two different duty cycle signals, meeting the multi-clock signal requirements of complex switching power supply chips. Attached Figure Description

[0012] Figure 1 This is a circuit block diagram of the present invention;

[0013] Figure 2 The waveforms are the main node voltage waveforms in the circuit of this invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] An oscillator circuit with precise high duty cycle output includes a power supply voltage VCC, ground GND, a reference voltage VREF, and an output signal V. OSC2 and V OSC2 , Resistors R1-R2, Current source I1, PMOS transistors MP1-MP2, NMOS transistors MN1-MN2, Capacitors C1-C2, Comparators CMP1-CMP3, RS latch LATCH1, Inverter INV1, NAND gate NAND1.

[0016] Specifically, an oscillator circuit with precise high duty cycle output, such as Figure 1 As shown, the circuit structure includes: one end of resistor R1 is connected to a reference voltage V. R1 The other end is connected to one end of R2 and then to the positive terminal of comparator CMP1, serving as the reference voltage V. R2 V R1 It is also connected to the positive terminals of CMP2 and CMP3 as a reference voltage; the other end of R2 is connected to ground GND; the positive terminal of current source I1 is connected to the power supply voltage VCC, and the negative terminal V... B Connect the sources of PMOS transistors MP1 and MP2; connect the gate of MP1 to the gate of NMOS transistor MN1 and to the output QN of RS latch LATCH1; connect the drain of MP1 to the drain of MN1 and to the positive terminal of capacitor C1 and the negative terminals of CMP1 and CMP2; connect the source of MN1 and the negative terminal of C1 to GND; connect the gate of MP2 to the gate of MN2 and to the output Q of LATCH1 and one input of NAND gate NAND1, which also serves as the output signal V of the oscillator. OSC2The drain of MP2 is connected to the drain of MN2 and then to the positive terminal of capacitor C2 and the negative terminal of CMP3; the source of MN2 and the negative terminal of C2 are both connected to GND; the output of CMP1 is connected to the input of inverter INV1; the output of CMP1 is connected to the input R of LATCH1; the output of CMP3 is connected to the input S of LATCH1; the output of INV1 is connected to the other input of NAND1; the output of NAND1 serves as the output signal V of the oscillator. OSC1 .

[0017] In this embodiment, the oscillator circuit includes three operating stages: a charging stage for capacitor C2, a first charging stage for capacitor C1, and a second charging stage for capacitor C1. These stages cycle sequentially, with each cycle constituting one oscillator cycle, generating the oscillator output signal V. OSC1 and V OSC2 .

[0018] C2 charging stage: Assume the initial state of the circuit is V1 = 1 (logic high level), V OSC2 = 0 (logic low), at this time MP2 is turned on, MN2 is turned off, and C2 starts constant current charging. Since MP1 is turned off and MN2 is turned on, V C1 =0, V OSC1 =1, until V C2 =V R1 .

[0019] The first charging stage of C1: when V C2 The voltage reaches the toggling threshold V of comparator CMP3. R2 At that time, V1 = 0, V OSC2 =1, at this time MP2 is off, MN2 is on, and the voltage across C2 immediately drops to 0. Since MP1 is on and MN1 is off, C1 begins constant current charging, V C2 =0, V OSC1 =1, until V C1 =V R2 .

[0020] The second charging stage of C1: when V C1 The voltage reaches the toggling threshold V of comparator CMP1. R2 At that time, V1 = 0, V OSC2 =1, V OSC1 =0. C1 continues to charge at a constant current until V = 0. C1 The voltage reaches the toggling threshold V of comparator CMP2. R1 At that time, V1 = 1, V OSC2 =0, V OSC1 =1.

[0021] At this point, MP1 is turned off, MN1 is turned on, and the voltage across C1 immediately drops to 0. Since MP2 is turned on, MN2 is turned off, and the charging phase of C2 begins again. This cycle repeats continuously, generating the oscillator output signal V. OSC1 and V OSC2 .

[0022] Based on the circuit diagram of the oscillator circuit with precise high duty cycle output, the reference voltage V can be determined. R2 The expression is:

[0023]

[0024] Where R1 and R2 are the resistance values ​​of resistors R1 and R2, respectively, V R1 This is the reference voltage.

[0025] For the C2 charging phase, the charging time is:

[0026]

[0027] The charging time for the first charging stage of C1 is:

[0028]

[0029] The charging time for the second charging stage of C1 is:

[0030]

[0031] C1 and C2 are the capacitance values ​​of capacitors C1 and C2, respectively. V R1 V is the reference voltage. R2 I1 is the reference voltage, and I1 is the magnitude of the current source I1.

[0032] like Figure 2 The figure shows the voltage waveforms of the main nodes in the circuit of this invention. The main nodes include the positive terminal V of capacitor C2. C2 The positive terminal V of capacitor C1 C1 The voltage V1 at the output terminal QN of RS latch LATCH1 generates the oscillator output signal V. OSC1 and V OSC2 .pass Figure 2 It can be seen that the three stages of capacitor C2 charging, capacitor C1's first charging stage, and capacitor C1's second charging stage are key intermediate nodes (V). C2 V C1 V1) and output node (V OSC1 V OSC2 The voltage waveform of the oscillator can be used to visually demonstrate the generation process of the oscillator output signal.

[0033] The expression for calculating the oscillator period is:

[0034]

[0035] Oscillator output signal V OSC1 The duty cycle D1 can be expressed as:

[0036]

[0037] Oscillator output signal V OSC2 The duty cycle D2 can be expressed as:

[0038]

[0039] As can be seen from the expression for the duty cycle D1, adjusting the resistance and capacitance values ​​can change the oscillator output signal V. OSC1 The duty cycle, R2 / (R 1+ The larger R2 is, the greater V is. R2 The closer to V R1 V OSC1 The higher the duty cycle, the better. Furthermore, because the same type of resistors and capacitors are used, and the capacitors and resistors are matched on the layout, a precise duty cycle can be achieved.

[0040] As can be seen from the expression for the duty cycle D2, adjusting the capacitor value can change the oscillator output signal V. OSC2 Similarly, a precise duty cycle can also be achieved.

[0041] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An oscillator circuit with precise high duty cycle output, characterized in that, include: Two resistors R1~R2, current source I1, two PMOS transistors MP1~MP2, two NMOS transistors MN1~MN2, two capacitors C1~C2, three comparators CMP1~CMP3, RS latch LATCH1, inverter INV1, and NAND gate NAND1; one end of resistor R1 is connected to the reference voltage V. R1 One end is connected to resistor R2 and then to the positive terminal of comparator CMP1; the other end of resistor R2 is grounded; the positive terminal of current source I1 is connected to the power supply voltage VCC, and the negative terminal is connected to V... B Connect the sources of PMOS transistors MP1 and MP2; the gate of MP1 is connected to the gate of NMOS transistor MN1 and the output QN of RS latch LATCH1, and its drain is connected to the drain of MN1, the positive terminal of capacitor C1, the negative terminal of CMP1, and the negative terminal of CMP2; the source of MN1 and the negative terminal of capacitor C1 are both grounded; the gate of MP2 is connected to the gate of MN2, the output Q of LATCH1, and one input of NAND gate NAND1; the drain of MP2 is connected to the drain of MN2, the positive terminal of capacitor C2, and the negative terminal of CMP3; the source of MN2 and the negative terminal of C2 are both grounded; the output of CMP1 is connected to the input of inverter INV1; the positive terminals of CMP2 and CMP3 are both connected to the reference voltage V. R1 The output of CMP2 is connected to the input terminal R of LATCH1; the output of CMP3 is connected to the input terminal S of LATCH1; the output of INV1 is connected to the other input terminal of NAND1. The oscillator circuit includes three operating stages: a charging stage for capacitor C2, a first charging stage for capacitor C1, and a second charging stage for capacitor C1. These stages cycle sequentially, with each cycle constituting one oscillator cycle, generating the oscillator output signal V. OSC1 and V OSC2 ; The charging phase of capacitor C2 includes: the initial state of the circuit is V1=1, V OSC2 =0, at this time MP2 is turned on, MN2 is turned off, and C2 starts constant current charging; because MP1 is turned off and MN2 is turned on, V C1 =0, V OSC1 =1; when V C2 =V R1 At this time, capacitor C2 is fully charged; The first charging stage of capacitor C1 includes: when V C2 The voltage reaches the toggling threshold V of comparator CMP3. R1 At that time, V1=0, V OSC2 =1, at this time MP2 is off, MN2 is on, and the voltage across C2 drops to 0; since MP1 is on and MN1 is off, C1 begins constant current charging, V C2 =0, V OSC1 =1, when V C1 = V R2 The first charging phase of capacitor C1 is completed. The second charging stage of capacitor C1 includes: when V C1 The voltage reaches the toggling threshold V of comparator CMP1. R2 At that time, V1=0, V OSC2 =1, V OSC1 =0, C1 continues constant current charging; when V... C1 The voltage reaches the toggling threshold V of comparator CMP2. R1 At that time, V1=1, V OSC2 =0, V OSC1 =1, the second charging stage of capacitor C1 is completed.

2. The oscillator circuit with precise high duty cycle output according to claim 1, characterized in that, The gate of PMOS transistor MP2 is the second signal output terminal V of the oscillator circuit. OSC2 The output of NAND1 serves as the first signal output terminal V of the oscillator. OSC1 .

3. The oscillator circuit with precise high duty cycle output according to claim 1, characterized in that, The expression for calculating the oscillator period is: ； in, The charging time for the charging phase of capacitor C2. The charging time for the first charging stage of capacitor C1. The charging time for the second charging stage of capacitor C1. , These are the capacitance values ​​of capacitors C1 and C2, respectively. The reference voltage, Let I be the magnitude of the current source I1.

4. An oscillator circuit with precise high duty cycle output according to claim 1, characterized in that, Output signal V OSC1 The duty cycle is: ； Output signal V OSC2 The duty cycle is: ； in, The charging time for the charging phase of capacitor C2. The charging time for the first charging stage of capacitor C1. The charging time for the second charging stage of capacitor C1. , These are the capacitance values ​​of capacitors C1 and C2, respectively. As the reference voltage, For reference voltage, , R1 and R2 are the resistance values, respectively, and T is the oscillator period.

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