Circuit for generating power from a chip communication terminal

Abstract

The application discloses a circuit for generating power supply from a chip communication terminal, which comprises a plurality of electronic elements and an energy storage capacitor CAP. One end of the energy storage capacitor CAP is connected to a chip power terminal VCC, and the other end is grounded. The electronic elements comprise a diode D1, a PMOS transistor M1, a PMOS transistor M2, a voltage comparator C1 and a two-input AND gate A1. The anode of the diode D1, the drain of the PMOS transistor M1, the drain of the PMOS transistor M2 and the negative input end of the voltage comparator C1 are connected to the chip communication terminal DATA. The cathode of the diode D1, the source of the PMOS transistor M1 and its substrate, the source of the PMOS transistor M2 and its substrate and the positive input end of the voltage comparator C1 are connected to the chip power terminal VCC. The gate of the PMOS transistor M1 and one input end of the two-input AND gate A1 are connected to the output end of the voltage comparator C1, and the other input end of the two-input AND gate A1 is an enhanced drive enable signal terminal OD. The output end of the two-input AND gate A1 is connected to the gate of the PMOS transistor M2. The circuit has the advantages that the power supply pin, the chip terminal and the power supply circuit are reduced, and the chip area and cost are greatly saved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and more particularly, to a circuit for generating power supply from a chip communication terminal. BACKGROUND

[0002] Conventional chips usually use independent pins to introduce power supply for the internal circuits of the chips, and the power supply pins and the power supply circuits connected thereto occupy a large chip area, resulting in high chip cost. SUMMARY

[0003] The present application aims to provide a circuit for generating power supply from a chip communication terminal to overcome the above technical deficiencies.

[0004] The technical solution of the present application is as follows: a circuit for generating power supply from a chip communication terminal, comprising a plurality of electronic elements built in the chip and an energy storage capacitor CAP built in the chip or externally hung on the chip;

[0005] One end of the energy storage capacitor CAP is connected to the chip power terminal VCC, and the other end is grounded.

[0006] The electronic elements include a diode D1, a PMOS transistor M1, a PMOS transistor M2, a voltage comparator C1, and a two-input AND gate A1.

[0007] The anode of the diode D1, the drain of the PMOS transistor M1, the drain of the PMOS transistor M2, and the negative input terminal of the voltage comparator C1 are connected to the chip communication terminal DATA.

[0008] The cathode of the diode D1, the source and substrate of the PMOS transistor M1, the source and substrate of the PMOS transistor M2, and the positive input terminal of the voltage comparator C1 are connected to the chip power terminal VCC.

[0009] The gate of the PMOS transistor M1, one input terminal of the two-input AND gate A1, and the output terminal of the voltage comparator C1 are connected, the other input terminal of the two-input AND gate A1 is an enhanced drive enable signal terminal OD, and the output terminal of the two-input AND gate A1 is connected to the gate of the PMOS transistor M2.

[0010] The electronic elements are each provided with a power input port, and the power input port is connected to and powered by the chip power terminal VCC.

[0011] Preferably, the channel width and channel length ratio W M2 / L M2a channel width and a channel length ratio W M1 / L M1 a gate capacitance C G_M2 of the PMOS transistor M2 is greater than a gate capacitance C G_M1 .

[0012] Preferably, a body diode D2 is formed between a source and a substrate of the PMOS transistor M1, and a body diode D3 is formed between a source and a substrate of the PMOS transistor M2.

[0013] The present application has the following advantages: the circuit for generating power from a chip communication terminal provided by the present application can make the chip power terminal VCC track the high level of the chip communication terminal DATA by using the voltage comparator C1 to detect the voltage change of the chip communication terminal DATA and the chip power terminal VCC; meanwhile, when the chip communication terminal DATA is at low level, the path between the chip power terminal VCC and the chip communication terminal DATA is cut off, and the chip power terminal VCC is powered by the energy storage capacitor CAP, so that the chip power terminal VCC can continuously supply power to the chip; and the enhanced PMOS transistor M2 is simultaneously opened to provide large current, which can ensure that the chip power terminal VCC has strong driving capability. Since the built-in power supply circuit is used, the present application reduces the chip port of the power pin and its power supply circuit, greatly saving the chip area and cost. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a circuit structure schematic diagram of the embodiment of the present application. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0016] The present application is a circuit for generating power from a chip communication terminal, which is suitable for providing power voltage for a chip, the chip including a chip communication terminal DATA and a chip power terminal VCC, and the chip power terminal VCC is built-in and does not need a power pin.

[0017] EMBODIMENT

[0018] As Figure 1As shown, this embodiment presents a circuit for generating power from a chip communication terminal. It includes several electronic components built into the chip and an energy storage capacitor CAP. One end of the energy storage capacitor CAP is connected to the chip's power supply terminal VCC, and the other end is grounded. The electronic components include a diode D1, a PMOS transistor M1, a PMOS transistor M2, a two-input AND gate A1, and a voltage comparator C1. The anode of diode D1, the drain of PMOS transistor M1 and M2, and the negative input of voltage comparator C1 are connected to the chip's communication terminal DATA. The cathode of diode D1, the source and substrate of PMOS transistor M1 and M2, and the positive input of voltage comparator C1 are connected to the chip's power supply terminal VCC. The gate of PMOS transistor M1 is connected to the output of voltage comparator C1. One input of the two-input AND gate A1 is connected to the output of voltage comparator C1, and the other input is the enhancement drive enable signal terminal OD. The gate of PMOS transistor M2 is connected to the output of two-input AND gate A1. All of the above electronic components are equipped with a power input port, which is connected to the chip's power supply terminal VCC and powered by the chip's power supply terminal VCC.

[0019] PMOS transistor M2 is an enhancement-mode PMOS driver transistor. The channel width and channel length of PMOS transistor M2 are compared to W. M2 / L M2 The channel width to channel length ratio W of the PMOS transistor M1 is greater than that of the PMOS transistor M1. M1 / L M1 The gate capacitance C of PMOS transistor M2 G_M2 The gate capacitance C of the PMOS transistor M1 is greater than that of the PMOS transistor M1. G_M1 .

[0020] In this embodiment, a circuit that generates power from the chip communication terminal is provided. A body diode D3 is formed between the source and the substrate of PMOS transistor M2, and a body diode D2 is formed between the source and the substrate of PMOS transistor M1.

[0021] In other embodiments, the energy storage capacitor CAP can also be externally connected to the chip to further reduce chip area and cost.

[0022] like Figure 1 As shown, the working principle of this embodiment is as follows: when the chip is in sleep mode, both the chip communication terminal DATA and the chip power supply terminal VCC are at low levels. When the chip communication terminal DATA is at a high level, the voltage comparator C1 outputs a logic signal "0". This logic signal "0" can drive the PMOS transistor M1 to conduct, and the chip power supply terminal VCC quickly obtains the same high level as the chip communication terminal DATA, which can provide power to the chip. At the same time, the energy storage capacitor CAP charges to the same high level as the chip communication terminal DATA.

[0023] When the chip communication end DATA is low or its level is lower than the level of the chip power end VCC, the voltage comparator C1 outputs a logic signal "1", which can drive the PMOS transistor M1 to quickly turn off. At this time, the chip power end VCC is provided with voltage by the energy storage capacitor CAP.

[0024] When the level of the chip power end VCC is lower than the minimum level required for circuit operation, the diode D1 and the PMOS transistor M1 and the body diode D2 of the PMOS transistor M1 will provide the initial operating voltage required for starting the circuit when the level of the chip communication end DATA is higher than the conduction threshold Vth of the diode D1; and provide a larger driving current when the level of the chip power end VCC is lower than the level of the chip communication end DATA by more than Vth, so that the level of the chip power end VCC quickly follows the level of the chip communication end DATA.

[0025] When the chip communication end DATA is input as high level at the same time, if the enable signal "0" is sent to the enhanced drive enable signal end OD, the two-input AND gate A1 outputs a logic signal "0", which drives the enhanced PMOS transistor M2 to open at the same time, so that the chip power end VCC has a larger current. The PMOS transistor M2 and the PMOS transistor M1 driven by the voltage comparator C1 realize lossless transmission of the DATA level to the VCC level.

[0026] When the enable signal of the off drive enable OD is turned off, that is, the drive enable signal is "1", the PMOS transistor M2 can be turned off, and the voltage comparator C1 outputs to directly drive the PMOS transistor M1. When the level of the chip communication end DATA is lower than the level of the chip power end VCC, the PMOS transistor M1 can be quickly driven to turn off, thereby realizing fast response and preventing current from flowing back.

[0027] In summary, the circuit scheme for generating a power supply from a chip communication end proposed in the application uses the voltage comparator C1 to detect the voltage changes of the chip communication end DATA and the chip power end VCC, so that the chip power end VCC can track the high level of the chip communication end DATA; at the same time, when the chip communication end DATA is low, the path between the chip power end VCC and the chip communication end DATA is cut off, and the energy storage capacitor CAP is used for power supply, so that the chip power end VCC can continuously supply power to the chip; in addition, the enhanced PMOS transistor M2 is opened at the same time to provide a large current, which can ensure that the chip power end VCC has strong driving capability. In addition, the application reduces the power pin, a chip port, and its power supply circuit, thereby greatly saving the chip area and cost.

[0028] The above merely describes preferred embodiments of the present application, and the specific embodiments are not intended to limit the present application. Various modifications and changes can occur to those skilled in the art within the technical concept of the present application, and any modification, change or equivalent replacement made by those skilled in the art based on the above description should fall within the scope of the present application.

Claims

1. A circuit for generating a power supply from a chip communication terminal, characterized by The chip comprises a plurality of electronic components built-in the chip and an energy storage capacitor CAP built-in or externally connected to the chip; One end of the energy storage capacitor CAP is connected to the chip power supply end VCC and the other end is grounded; The electronic components comprise a diode D1, a PMOS transistor M1, a PMOS transistor M2, a voltage comparator C1 and a two-input AND gate A1; The anode of the diode D1, the drain of the PMOS transistor M1, the drain of the PMOS transistor M2 and the negative input end of the voltage comparator C1 are connected to the chip communication end DATA; The cathode of the diode D1, the source and substrate of the PMOS transistor M1, the source and substrate of the PMOS transistor M2 and the positive input end of the voltage comparator C1 are connected to the chip power supply end VCC; The gate of the PMOS transistor M1, one input end of the two-input AND gate A1 and the output end of the voltage comparator C1 are connected, the other input end of the two-input AND gate A1 is an enhanced drive enable signal end OD, and the output end of the two-input AND gate A1 is connected to the gate of the PMOS transistor M2; The electronic components are each provided with a power input port, which is connected to and powered by the chip power supply end VCC.

2. The circuit for generating a power supply from a chip communication terminal according to claim 1, wherein, The channel width and channel length ratio W / L of the PMOS transistor M2 is larger than that of the PMOS transistor Ml M2 The channel width and channel length ratio W / L of the PMOS transistor M2 is larger than that of the PMOS transistor Ml M2 The channel width and channel length ratio W / L of the PMOS transistor M2 is larger than that of the PMOS transistor Ml M1 The channel width and channel length ratio W / L of the PMOS transistor M2 is larger than that of the PMOS transistor Ml M1 The gate capacitance C of the PMOS transistor M2 is larger than that of the PMOS transistor Ml G_M2 The gate capacitance C of the PMOS transistor M2 is larger than that of the PMOS transistor Ml G_M1 .

3. The circuit for generating a power supply from a chip communication terminal according to claim 1, wherein A body diode D2 is formed between the source and substrate of the PMOS transistor M1, and a body diode D3 is formed between the source and substrate of the PMOS transistor M2.

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