Comparator circuit

Abstract

The application discloses a comparator circuit, comprising: an input stage circuit receiving a first input voltage and a second input voltage, comparing the first input voltage and the second input voltage, and providing a comparison signal to a first node; an output stage circuit connected with the first node, generating an output voltage signal according to the potential of the first node; and a current-limiting clamping circuit connected with the output stage circuit, limiting the first static current of the output stage circuit to a preset current when the output voltage signal is a logic high level, thereby providing a comparator circuit with fast response speed and low power consumption.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a comparator circuit. Background Technology

[0002] A comparator circuit is a commonly used signal processing circuit that compares an input voltage with a reference voltage and outputs the result, which can be either a logic high level or a logic low level. In automatic control and automatic measurement systems, comparator circuits are frequently used for over-limit alarms, analog-to-digital conversion, and the generation and manipulation of various non-sinusoidal waves. Therefore, comparator circuits are widely used in communications, PCs, consumer electronics, automotive, and industrial fields.

[0003] Many applications require a certain response speed from comparator circuits. For example, in analog-to-digital converters (ADCs), the performance of the comparator circuit determines the overall performance of the ADC. Current technologies mostly improve the response speed of comparator circuits by increasing power consumption, which not only limits the application scenarios of the comparator circuits but also increases the overall power consumption of the circuit or system.

[0004] Therefore, an improved comparator circuit is needed to solve the problem of the trade-off between fast response speed and low power consumption in the existing technology. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide a comparator circuit with fast response speed and low power consumption.

[0006] According to one aspect of the present invention, a comparator circuit is provided, comprising: an input stage circuit for receiving a first input voltage and a second input voltage, for comparing the first input voltage and the second input voltage, and providing a comparison signal to a first node; an output stage circuit connected to the first node for generating an output voltage signal according to the potential of the first node; and a current-limiting clamping circuit connected to the output stage circuit for limiting a first quiescent current of the output stage circuit to a preset current when the output voltage signal is at a logic high level.

[0007] Optionally, when the output voltage signal is at a logic high level, the ratio of the preset current to the second static current of the current limiting clamping circuit is n.

[0008] Optionally, the input stage circuit includes: a first current source, a first terminal of which is connected to a power supply voltage; a transconductance amplifier, the positive power supply terminal of which is connected to a second terminal of the first current source, the two input terminals receiving the first input voltage and the second input voltage respectively, and the output terminal providing a comparison signal related to the first input voltage and the second input voltage to the first node.

[0009] Optionally, the output stage circuit includes: a second current source, a first terminal of which is connected to a power supply voltage; and a first transistor connected between the second current source and ground, the control terminal of which is connected to the first node, wherein the common node between the second current source and the first transistor is used to generate the output voltage signal.

[0010] Optionally, the current limiting clamping circuit includes: a third current source, the first terminal of which is connected to the power supply voltage; a second transistor connected between the second terminal of the third current source and the first node, the control terminal of the second transistor being connected to the bias voltage; and a third transistor connected between the second terminal of the third current source and ground, the control terminal of the third transistor being connected to the first node.

[0011] Optionally, the ratio of the preset current to the second static current is equal to the ratio of the transistor size of the first transistor to the transistor size of the third transistor.

[0012] Optionally, the second transistor is primarily used to clamp the potential of the first node to the gate-source voltage of the first transistor.

[0013] Optionally, the preset current can be changed by adjusting the size of the third current source and / or the ratio of the transistor size of the first transistor to the transistor size of the third transistor.

[0014] Optionally, the first transistor and the third transistor are selected from N-type field-effect transistors, and the second transistor is selected from P-type field-effect transistors.

[0015] In summary, the comparator circuit of this embodiment can accelerate the charging and discharging speed of the comparator circuit output by adding a third current source, enabling the output voltage signal of the comparator circuit to quickly respond to changes in the first and second input voltages and thus flip. Furthermore, by adding a first current source and a second transistor, a current-limiting loop is formed between the second transistor, the third transistor, and the first current source, ensuring that the ratio of the current flowing through the third transistor to the current flowing through the second transistor is n. Ultimately, the static current of the comparator circuit is independent of the third current source. This improves the response speed of the comparator circuit without increasing additional power consumption, achieving a comparator circuit with fast response and low power consumption.

[0016] Optionally, after the first transistor is turned on, the comparison signal is clamped near the gate-source voltage. When the first input voltage is greater than the second input voltage, the level of the comparison signal starts to rise from the gate-source voltage of the third transistor, making the output voltage flip faster and further improving the response speed of the comparator circuit. Attached Figure Description

[0017] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0018] Figure 1 A circuit diagram of a comparator circuit according to the prior art is shown;

[0019] Figure 2 A circuit diagram of a comparator circuit according to an embodiment of the present invention is shown. Detailed Implementation

[0020] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0021] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0022] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0023] In this application, the transistor may include one selected from bipolar transistors or field-effect transistors. The first terminal and the second terminal of the transistor are respectively the high potential terminal and the low potential terminal on the current path. The control terminal is used to receive a control signal to control the transistor's turn-on and turn-off. A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal, and a control terminal. In the MOSFET's on state, current flows from the first terminal to the second terminal. For a P-type MOSFET, the first terminal, the second terminal, and the control terminal are the source, the drain, and the gate, respectively. For an N-type MOSFET, the first terminal, the second terminal, and the control terminal are the drain, the source, and the gate, respectively.

[0024] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0025] Figure 1 A circuit diagram of a comparator circuit according to the prior art is shown. The comparator circuit 100 includes an input stage circuit 110, a transistor Mp1, and an output stage circuit 130.

[0026] The input stage circuit 110 receives a first input voltage Vin and a second input voltage Vref, compares the first input voltage Vin and the second input voltage Vref, and provides a comparison signal Scomp to the first node Q.

[0027] The output stage circuit 130 is connected to the first node Q and generates an output voltage signal Vout based on the potential of the first node Q.

[0028] Transistor Mp1 clamps the level of the first node Q according to the level of the output voltage signal Vout.

[0029] Specifically, the input stage circuit 110 includes a transconductance amplifier 111 and a first current source Ib1. The positive power supply terminal of the transconductance amplifier 111 is connected to the power supply voltage Vdd through the first current source Ib1, and the negative power supply terminal is grounded. The two input terminals receive the first input signal Vin and the second input signal Vref, respectively. The transconductance amplifier 111 is used to compare the first input signal Vin and the second input signal Vref, and provides the comparison signal Scomp to the first node Q.

[0030] The output stage circuit 130 includes a second current source Ib2 and a transistor Mn1 connected in series between the power supply voltage Vdd and ground. The intermediate node between the second current source Ib2 and the transistor Mn1 is the output terminal of the comparator circuit 100. The control terminal of the transistor Mn1 is connected to the first node Q, and generates an output voltage signal Vout according to the level of the first node Q.

[0031] In this embodiment, the comparator circuit 100 further includes a capacitor Cp, the first end of which is connected to the second end of the current source Ib2, and the second end is grounded.

[0032] The control terminal of transistor Mp1 is connected to the bias voltage Vb, the first terminal is connected to the output terminal of comparator circuit 100, and the second terminal is connected to the first node Q. When the output voltage Vout is greater than the preset voltage, transistor Mp1 is turned on, thereby clamping the comparison signal Scomp at the gate-source voltage Vgs1 of transistor Mn1.

[0033] Existing technology employs the method of adding a second current source Ib2 to accelerate the charging and discharging rate, so that the output voltage Vout of the comparator circuit 100 can quickly respond to the changes in the first input voltage Vin and the second input voltage Vref and flip.

[0034] However, when the first input voltage Vin is greater than the second input voltage Vref, and the output voltage Vout remains at a logic high level, the quiescent current Iq of comparator circuit 100 is equal to Ib1 + Ib2. It is evident that the quiescent current Iq of comparator circuit 100 increases with the increase of the second current Ib2. While increasing the response speed of comparator circuit 100, the increase in the second current Ib2 also increases its quiescent power consumption, limiting the application scenarios of comparator circuit 100 and increasing the power consumption of circuits or systems using comparator circuit 100.

[0035] Figure 2 A circuit diagram of a comparator circuit according to an embodiment of the present invention is shown. The comparator circuit 200 includes an input stage circuit 210, a current limiting clamping circuit 220, and an output stage circuit 230.

[0036] The input stage circuit 210 receives a first input voltage Vin and a second input voltage Vref, compares the first input voltage Vin and the second input voltage Vref, and provides a comparison signal Scomp to the first node Q.

[0037] The output stage circuit 230 is connected to the first node Q and is used to generate an output voltage signal Vout based on the potential of the first node Q.

[0038] The current-limiting clamping circuit 220, connected to the output stage circuit 230 and the first node Q, is used to limit the current to ground of the output stage circuit 230, i.e., the quiescent current Iq1, to a preset current when the output voltage signal Vout is at a logic high level. Specifically, when the output voltage signal Vout is at a logic high level, the ratio of the preset current to the quiescent current Iq2 is n, and the quiescent current Iq2 is the current to ground of the current-limiting clamping circuit 220.

[0039] Specifically, the input stage circuit 210 includes a transconductance amplifier 211 and a current source Ib1. The positive power supply terminal of the transconductance amplifier 211 is connected to the power supply voltage Vdd through the current source Ib1, and the negative power supply terminal is grounded. The two input terminals receive the first input signal Vin and the second input signal Vref, respectively. The transconductance amplifier 211 compares the first input signal Vin and the second input signal Vref, and provides the comparison signal Scomp to the first node Q.

[0040] The output stage circuit 230 includes a current source Ib2 and a transistor Mn1. The first terminal of the current source Ib2 is connected to the power supply voltage Vdd. The first terminal of the transistor Mn1 is connected to the second terminal of the current source Ib2 to generate an output voltage signal Vout. The second terminal is grounded, and the control terminal is connected to the first node Q.

[0041] In this embodiment, the comparator circuit 200 further includes a capacitor Cp, the first end of which is connected to the second end of the current source Ib2, and the second end is grounded.

[0042] The current-limiting clamping circuit 220 includes a current source Ib3, a transistor Mp1, and a transistor Mn2. The first terminal of the current source Ib3 is connected to the power supply voltage Vdd. The first terminal of the transistor Mn2 is connected to the second terminal of the current source Ib3, the second terminal is grounded, and its control terminal is connected to the first node Q. The first terminal of the transistor Mp1 is connected to the second terminal of the current source Ib3, the second terminal is connected to the first node Q, and its control terminal is connected to the bias voltage Vb.

[0043] Among them, transistor Mp1 is selected from P-type field-effect transistor, transistor Mn1 and transistor Mn2 are selected from N-type field-effect transistor, and the ratio of the transistor size of transistor Mn1 to transistor Mn2 is n, that is, the ratio of the width-to-length ratio of transistor Mn1 to the width-to-length ratio of transistor Mn2 is n.

[0044] When the first input voltage Vin is greater than the second input voltage Vref, and the output voltage signal Vout remains at a logic high level, the transconductance amplifier 211 absorbs a current of magnitude ΔV*gm from the first node Q, thereby pulling down the voltage of the first node Q. This reduces the control terminal voltages of transistors Mn1 and Mn2, decreasing their gate-source voltages and consequently reducing the current flowing through them. Here, ΔV represents the difference between the first input voltage Vin and the second input voltage Vref, and gm is the gain of the transconductance amplifier 211. At this time, transistors Mn1 and Mn2, along with the current source Ib3, form a current-limiting loop. The ratio of the quiescent current Iq1 flowing through transistor Mn1 to the quiescent current Iq2 flowing through transistor Mn2 is equal to the ratio of the transistor sizes of transistors Mn1 and Mn2, i.e., Iq1 = n*Iq2. The quiescent current of comparator circuit 200 is Iq = Ib1 + Iq1 + Ib3, where Iq1 = n * Iq2 = n * (Ib3 - ΔV * gm). Simplifying, the quiescent current of comparator circuit 200 for the comparison signal Scomp is Iq = Ib1 + (n+1) * Ib3 - n * ΔV * gm. It is evident that the quiescent current Iq of comparator circuit 200 is independent of the second current source Ib2. Although current source Ib2 is added to improve the response speed of comparator circuit 200, the final quiescent current power consumption of comparator circuit 200 is independent of the magnitude of current source Ib2. Therefore, the response speed of comparator circuit 200 is improved without increasing the additional quiescent current power consumption.

[0045] In one feasible embodiment, transistors Mn1 and Mn2 use the same transistor size, that is, the quiescent current Iq1 is equal to the quiescent current Iq2, and the final quiescent current of comparator circuit 200 is Iq = Ib1 + 2*Ib3 - ΔV*gm.

[0046] Optionally, when transistor Mp1 is turned on, the potential of the first node Q is clamped at the gate-source voltage Vgs1 of transistor Mn1. When the comparison signal Scomp changes, the voltage of the first node Q does not need to rise from zero, further accelerating the response speed of comparator circuit 200.

[0047] In summary, the comparator circuit of this embodiment can accelerate the charging and discharging speed of the comparator circuit output by adding current source Ib2, enabling the output voltage signal of the comparator circuit to quickly respond to changes in the first and second input voltages and thus flip. Furthermore, by adding current source Ib3 and transistor Mn2, transistors Mn1 and Mn2 form a current-limiting loop with current source Ib3, ensuring that the ratio of the current flowing through transistor Mn1 to the current flowing through transistor Mn2 is n. Ultimately, the static current of the comparator circuit is independent of current source Ib2. This improves the response speed of the comparator circuit without increasing additional power consumption, achieving a comparator circuit with fast response and low power consumption.

[0048] Optionally, after transistor Mp1 is turned on, the comparison signal is clamped near the gate-source voltage of transistor Mn1. When the first input voltage is greater than the second input voltage, the level of the comparison signal starts to rise from the gate-source voltage of transistor Mn1, making the output voltage flip faster and further improving the response speed of the comparator circuit.

[0049] It should be noted that those skilled in the art will understand that the terms “during,” “when,” and “when…” used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately upon the commencement of a startup action, but rather that there may be some small but reasonable delays, such as various propagation delays, between the startup action and the reaction action initiated by it. The terms “approximately” or “substantially” used herein mean that an element value is expected to be close to the declared value or position. However, as is well known in the art, there are always small deviations that make it difficult for the value or position to be strictly the declared value. It has been properly determined in the art that a deviation of at least ten percent (10%) (or at least twenty percent (20%) for semiconductor doping concentration) is a reasonable deviation from the described accurate ideal target. When used in conjunction with signal states, the actual voltage value or logic state of the signal (e.g., “1” or “0”) depends on whether positive or negative logic is used.

[0050] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims and their equivalents.

Claims

1. A comparator circuit, comprising: The input stage circuit receives a first input voltage and a second input voltage, compares the first input voltage and the second input voltage, and provides a comparison signal to the first node; An output stage circuit, connected to the first node, is used to generate an output voltage signal based on the potential of the first node. A current-limiting clamping circuit, connected to the output stage circuit, is used to limit the first quiescent current of the output stage circuit to a preset current when the output voltage signal is at a logic high level. The output stage circuit includes: The second current source, the first terminal of which is connected to the power supply voltage; A first transistor is connected between the second current source and ground, and the control terminal of the first transistor is connected to the first node. The common node between the second current source and the first transistor is used to generate the output voltage signal. The current limiting clamping circuit includes: The third current source has its first terminal connected to the power supply voltage; A second transistor is connected between the second terminal of the third current source and the first node, and the control terminal of the second transistor is connected to a bias voltage; and The third transistor is connected between the second terminal of the third current source and ground, and the control terminal of the third transistor is connected to the first node.

2. The comparator circuit according to claim 1, wherein, When the output voltage signal is at a logic high level, the ratio of the preset current to the second static current of the current limiting clamping circuit is n.

3. The comparator circuit according to claim 1, wherein, The input stage circuit includes: A first current source, the first terminal of which is connected to the power supply voltage; A transconductance amplifier is provided, wherein the positive power supply terminal of the transconductance amplifier is connected to the second terminal of the first current source, the two input terminals receive the first input voltage and the second input voltage respectively, and the output terminal provides a comparison signal related to the first input voltage and the second input voltage to the first node.

4. The comparator circuit according to claim 2, wherein, The ratio of the preset current to the second static current is equal to the ratio of the transistor size of the first transistor to the transistor size of the third transistor.

5. The comparator circuit according to claim 2, wherein, The second transistor is mainly used to clamp the potential of the first node to the gate-source voltage of the first transistor.

6. The comparator circuit according to claim 2, wherein the preset current can be changed by adjusting the size of the third current source and / or the ratio of the transistor size of the first transistor to the transistor size of the third transistor.

7. The comparator circuit according to claim 2, wherein, The first transistor and the third transistor are selected from N-type field-effect transistors, and the second transistor is selected from P-type field-effect transistors.

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