Opto-isolated driver

Abstract

This invention discloses an opto-isolated driver, comprising: an optical emitting module, an optical receiving module, a signal processing module, and a push-pull output power module. The optical emitting module generates an optical signal based on an external input voltage signal. The optical receiving module includes at least one PIN junction photodiode for receiving the optical signal and generating a current signal. The signal processing module outputs a drive signal based on the current signal. The push-pull output power module is a complementary output power structure for outputting a voltage signal based on the drive signal. Using this invention, the transmission rate and output current can be improved, meeting the requirements of high current and high transmission rate.

Description

Technical Field

[0001] This invention relates to the field of circuits, and more specifically to an opto-isolated driver. Background Technology

[0002] An opto-isolator is a device that uses light as a medium to transmit electrical signals. It couples the input electrical signal to the output using light, achieving "electric-optical-electrical" control. An opto-isolator driver is a type of opto-isolator that utilizes photoelectric transmission and conversion to achieve complete electrical isolation between the input and output. Simultaneously, it amplifies low-voltage or low-current signals from microcontrollers or other sources to provide drive voltage and current to high-power devices such as transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Opto-isolator drivers are widely used in high-power motor control, industrial drives, solar power supplies and inverters, switching modes, and uninterruptible power supplies.

[0003] The structure of existing conventional opto-isolated drivers is as follows: Figure 1 As shown, the opto-isolated driver 100 includes: a light-emitting diode 11, a light-receiving module 12, a signal processing module 13, and a push-pull output power module 14. The push-pull output power module 14 includes two MOSFETs, namely... Figure 1 The LDPMOS and LDNMOS transistors in the circuit.

[0004] Figure 1 The opto-isolation driver 100 shown typically integrates the optical receiving module 12, the signal processing module 13, and the push-pull output power module 14 onto a single chip. Therefore, the push-pull output power module 14 can only use an integrated LDMOS (laterally-diffused metal-oxide semiconductor) transistor, and the optical receiving module 12 can only use an integrated PN junction photodiode.

[0005] LDMOS transistors have high on-resistance, typically ranging from several hundred mΩ to several Ω. This results in significant power consumption during high-current output, limiting the maximum output current to below 5A, which cannot meet the demands of high-current output.

[0006] In the entire opto-isolation driver, the transmission delay of the optical receiver module accounts for a major proportion. Existing optical receiver modules use integrated PN junction photodiodes, which have low photoelectric sensitivity and require a large chip area to meet the receiving current requirements. This results in a large junction capacitance, which in turn leads to a low transmission rate for the entire opto-isolation driver, with transmission delay times on the order of hundreds of nanoseconds or more, making it impossible to meet the requirements of high-speed transmission. Summary of the Invention

[0007] This invention provides an opto-isolated driver to improve transmission rate and output current, thereby meeting the requirements of high current and high transmission rate.

[0008] Therefore, the embodiments of the present invention provide the following technical solutions:

[0009] This invention provides an opto-isolated driver, comprising: an optical emitting module, an optical receiving module, a signal processing module, and a push-pull output power module;

[0010] The optical emitting module is used to generate an optical signal based on an external input voltage signal;

[0011] The optical receiving module includes at least one PIN junction photodiode for receiving the optical signal and generating a current signal;

[0012] The signal processing module is used to output a drive signal according to the current signal;

[0013] The push-pull output power module is a complementary output power structure, used to output a voltage signal according to the drive signal.

[0014] Optionally, the push-pull output power module includes an upper transistor and a lower transistor, both of which are high-power MOSFETs; the connection point of the upper transistor and the lower transistor serves as the output terminal of the opto-isolation driver; when the upper transistor is working, the lower transistor stops working, and the output terminal outputs a high level; when the lower transistor is working, the upper transistor stops working, and the output terminal outputs a low level.

[0015] Optionally, the upper transistor includes a first PMOS transistor and a first NMOS transistor connected in parallel, and the lower transistor includes a second NMOS transistor.

[0016] Optionally, the first PMOS transistor, the first NMOS transistor, and the second NMOS transistor are three independent chips, each driven by a different drive signal.

[0017] Optionally, the first PMOS transistor can be any one of the following: a VDPMOS transistor or a Trench PMOS transistor.

[0018] Optionally, the first NMOS transistor and the second NMOS transistor can be any one of the following: VDNMOS transistor, Trench_NMOS transistor, or SGT_NMOS transistor.

[0019] Optionally, the signal processing module includes: a current amplifier, a voltage comparator, a cathode drive circuit, a bias circuit, an undervoltage lockout circuit, and an output logic drive circuit;

[0020] The cathode driving circuit is connected to the cathode of the PIN junction photodiode and is used to generate the cathode driving voltage of the PIN junction photodiode.

[0021] The input terminal of the current amplifier is connected to the anode of the PIN junction photodiode, and the output terminal of the current amplifier is connected to the positive input terminal of the voltage comparator.

[0022] The bias circuit is connected to the negative input terminal of the voltage comparator and is used to generate a reference voltage;

[0023] The two input terminals of the output logic drive circuit are respectively connected to the output terminals of the undervoltage lockout circuit and the voltage comparator, and the three output terminals of the output logic drive circuit are respectively connected to the first PMOS transistor, the first NMOS transistor, and the second NMOS transistor, for outputting the drive signal according to the output signals of the undervoltage lockout circuit and the voltage comparator.

[0024] Optionally, the cathode drive circuit is a low-dropout linear regulator.

[0025] Optionally, the output logic driving circuit includes: a signal conversion unit and a driving unit;

[0026] The signal conversion unit is used to generate an intermediate signal based on the output signal of the undervoltage lockout circuit and the output signal of the voltage comparator.

[0027] The driving unit is used to generate the driving signal based on the intermediate signal.

[0028] Optionally, the drive unit includes:

[0029] The first drive signal generation unit is used to generate a first drive signal for driving the first PMOS transistor according to the drive signal.

[0030] The second drive signal generation unit is used to generate a second drive signal for driving the first NMOS transistor according to the drive signal.

[0031] The third drive signal generation unit is used to generate a third drive signal for driving the second NMOS transistor based on the drive signal.

[0032] Optionally, the first drive signal generation unit, the second drive signal generation unit, and the third drive signal generation unit have the same structure, each consisting of a PMOS transistor and an NMOS transistor. The gate of the PMOS transistor is connected to the gate of the NMOS transistor to input the corresponding intermediate signal, and the drain of the PMOS transistor is connected to the drain of the NMOS transistor and serves as the output terminal to output the corresponding drive signal.

[0033] Optionally, the three drive signal generation units use different power supply levels.

[0034] Optionally, an ITO film is deposited on the photosensitive region above the P+ layer of the PIN junction photodiode.

[0035] The opto-isolation driver provided in this embodiment of the invention uses a PIN junction photodiode, which has advantages such as small junction capacitance, short carrier transit time, and high photoelectric sensitivity, thereby greatly improving the transmission rate of the entire opto-isolation driver; moreover, the push-pull output power module adopts a complementary output power structure, which can meet the high current requirements. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the structure of an existing conventional opto-isolated driver;

[0037] Figure 2 This is a schematic diagram of the structure of the opto-isolation driver provided in an embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram of a specific structure of the opto-isolation driver provided in an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram of the PIN junction photodiode in an embodiment of the present invention;

[0040] Figure 5 This is a schematic diagram of the output logic driving circuit in one embodiment of the present invention;

[0041] Figure 6 This is a schematic diagram of a push-pull output power module and its driving unit in an embodiment of the present invention. Detailed Implementation

[0042] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0043] like Figure 2 The figure shown is a schematic diagram of the opto-isolation driver provided in an embodiment of the present invention.

[0044] The opto-isolated driver 200 includes: an optical emitting module 201, an optical receiving module 202, a signal processing module 203, and a push-pull output power module 204. Wherein:

[0045] The optical emitting module 201 is used to generate an optical signal based on an external input voltage signal;

[0046] The optical receiving module 202 includes at least one PIN junction photodiode for receiving the optical signal and generating a current signal.

[0047] The signal processing module 203 is used to output a drive signal according to the current signal;

[0048] The push-pull output power module 204 is a complementary output power structure, used to output a voltage signal according to the drive signal.

[0049] like Figure 3 The diagram shown is a specific structural schematic of an opto-isolation driver provided in an embodiment of the present invention.

[0050] In this embodiment, the light emitting module 201 consists of at least one light-emitting diode. The two ends of the light-emitting diode are connected to an external signal input terminal, with its anode connected to the positive terminal of the input signal and its cathode connected to the negative terminal of the input signal.

[0051] The optical receiving module 202 consists of at least one PIN junction photodiode. Compared to a conventional PN junction photodiode, the PIN junction photodiode incorporates a low-concentration, near-intrinsic semiconductor layer, called the I-layer, within the PN junction. The I-layer is relatively thick, almost completely occupying the depletion region, where most of the incident light is absorbed, generating a large number of electron-hole pairs. On either side of the I-layer are highly doped P+ and N+ semiconductors; these layers are very thin, absorbing only a small proportion of the incident light. The introduction of the I-layer increases the width of the depletion layer, which helps shorten the carrier diffusion process, reducing the influence of diffusion motion. Consequently, the drift component dominates the photocurrent, significantly improving the response speed. The widening of the depletion layer also significantly reduces the junction capacitance, shortens the transit time, and improves photosensitive sensitivity, thereby effectively increasing the transmission rate.

[0052] Furthermore, such as Figure 4 As shown, in a non-limiting embodiment, an ITO (tin-doped indium oxide, a transparent conductive film) film can also be deposited on the photosensitive region above the P+ layer of the PIN junction photodiode, which can greatly improve the light absorption rate and photoelectric sensitivity.

[0053] Continue to refer to Figure 3In this embodiment, the push-pull output power module 204 includes an upper transistor and a lower transistor, both of which are high-power MOSFETs. The connection point between the upper transistor and the lower transistor serves as the output terminal of the opto-isolation driver 200; when the upper transistor is working, the lower transistor is not working, and the output terminal outputs a high level; when the lower transistor is working, the upper transistor is not working, and the output terminal outputs a low level.

[0054] like Figure 3 As shown, the upper transistor includes a first PMOS transistor PM1 and a first NMOS transistor NM1 connected in parallel, and the lower transistor includes a second NMOS transistor NM2. Each of these three transistors is an independent high-power MOS transistor.

[0055] Specifically, the source of the first PMOS transistor PM1 and the drain of the first NMOS transistor NM1 are connected to the power supply VCC, the drain of the first PMOS transistor PM1 is connected to the source of the first NMOS transistor NM1, and the connection node serves as the output terminal of the opto-isolation driver 200.

[0056] The drain of the second NMOS transistor NM2 is connected to the drain of the first PMOS transistor PM1, and the source of the second NMOS transistor NM2 is grounded.

[0057] In this embodiment, the first PMOS transistor PM1, the first NMOS transistor NM1, and the second NMOS transistor NM2 are driven by their respective power supplies. That is, the gates of these three MOS transistors are respectively connected to different output terminals of the signal processing module 203. For ease of description, the gate drive voltages of the first PMOS transistor PM1, the first NMOS transistor NM1, and the second NMOS transistor NM2 are denoted as Vp, Vn1, and Vn2, respectively.

[0058] When the output current is small, the first PMOS transistor PM1 operates as a drain output, pulling the output voltage Vo towards VCC. Since the first NMOS transistor NM1 operates as a source output, it exhibits a bias effect. If VCC-Vo is less than the turn-on voltage VthN of the first NMOS transistor NM1, NM1 is turned off. When the output current is large, due to the poor high-current characteristics of the first PMOS transistor PM1, its output impedance increases proportionally with the output current. If VCC-Vo becomes greater than the turn-on voltage VthN of the first NMOS transistor NM1, then NM1 is turned on. The strong high-current output capability of the first NMOS transistor NM1 compensates for the poor high-current capability of the first PMOS transistor PM1.

[0059] It should be noted that in practical applications, in order to improve the large current output capability, the first PMOS transistor PM1 can be a VDPMOS transistor with a low turn-on voltage and a thin gate oxide layer thickness, or a Trench_PMOS transistor; the first NMOS transistor NM1 can be a VDNMOS transistor with a low turn-on voltage and a thin gate oxide layer thickness, or a Trench_NMOS transistor, or a SGT_NMOS transistor; the second NMOS transistor NM2 can be a VDNMOS transistor with a low turn-on voltage and a thin gate oxide layer thickness, or a Trench_NMOS transistor, or a SGT_NMOS transistor.

[0060] Continue to refer to Figure 3 to describe the specific structure of the signal processing module 203 in the embodiment of the present invention.

[0061] Refer Figure 3 As shown, the signal processing module 203 in this embodiment includes: a transimpedance amplifier TIA, a voltage comparator COMP, a cathode driver circuit LDO, a bias circuit BIAS, an under-voltage lockout circuit UVLO, and an output logic driver circuit DRI. Among them:

[0062] The cathode driver circuit LDO is connected to the cathode of the PIN junction photodiode and is used to generate the cathode drive voltage of the PIN junction photodiode. The cathode driver circuit LDO can specifically adopt a low dropout linear regulator.

[0063] The input end of the transimpedance amplifier TIA is connected to the anode of the PIN junction photodiode, and the output end of the transimpedance amplifier TIA is connected to the positive input end of the voltage comparator COMP, and outputs the amplified voltage Vd to the voltage comparator COMP.

[0064] The bias circuit BIAS is connected to the negative input end of the voltage comparator COMP and is used to generate a reference voltage Vref. When the output voltage Vd of the transimpedance amplifier TIA is greater than the reference voltage Vref, the output signal Vs of the voltage comparator COMP is at a high level; otherwise, the output signal Vs is at a low level.

[0065] The two input ends of the output logic driver circuit DRI are respectively connected to the output ends of the under-voltage lockout circuit UVLO and the voltage comparator COMP, and the three output ends of the output logic driver circuit DRI are respectively connected to the first PMOS transistor PM1, the first NMOS transistor NM1, and the second NMOS transistor NM2, and are used to output drive voltage signals Vp, Vn1, and Vn2 to the three MOS transistors according to the output signal Vr of the under-voltage lockout circuit UVLO and the output signal Vs of the voltage comparator COMP.

[0066] The state transition table of the output logic driver circuit DRI is shown in Table 1 below.

[0067] Table 1

[0068]

[0069] To implement the above control logic, a specific structure of the output logic drive circuit DRI is as follows: Figure 5 As shown, it includes: a signal conversion unit 501 and a driving unit 502.

[0070] The signal conversion unit 501 is used to generate intermediate signals, namely the first intermediate signal S1, the second intermediate signal S2, and the third intermediate signal S3 in Table 1, based on the output signal Vr (corresponding to R in Table 1) of the undervoltage lockout circuit UVLO and the output signal Vs (corresponding to S in Table 1) of the voltage comparator.

[0071] The driving unit 502 is used to generate driving signals for the three MOS transistors in the back-end push-pull output power module 204 using the intermediate signal, namely the driving signal Vp of the first PMOS transistor PM1, the driving signal Vn1 of the first NMOS transistor NM1, and the driving signal Vn2 of the second NMOS transistor NM2.

[0072] In practical applications, the above signal conversion unit 501 can be implemented using corresponding logic devices according to the signal logic relationship in Table 1 above. The specific structure of the present invention is not limited.

[0073] Figure 6 A specific structural example of the aforementioned drive unit 502 is shown.

[0074] In this example, the driving unit 502 includes a first driving signal generation unit, a second driving signal generation unit, and a third driving signal generation unit, for generating the three driving signals Vp, Vn1, and Vn2 respectively.

[0075] The three drive signal generation units mentioned above can adopt the same structure, that is, they consist of one PMOS transistor and one NMOS transistor, such as... Figure 6 The P1 and N1, P2 and N2, and P3 and N3 are defined in the diagram. In each drive signal generation unit, the gate of the PMOS transistor is connected to the gate of the NMOS transistor, receiving the corresponding intermediate signals S1, S2, and S3. The drain of the PMOS transistor is connected to the drain of the NMOS transistor and serves as the output terminal for the corresponding drive signal. Different power levels are applied to the sources of the PMOS and NMOS transistors, and the three drive signal generation units use different operating power levels, as detailed below. Figure 6 As shown:

[0076] The power supply range of P1 and N1 in the first drive signal generation unit is set from VCC-5V to VCC, thereby ensuring that the gate-source voltage Vgs of the first PMOS transistor PM1 in the push-pull output power module 204 is less than or equal to 5V, thus ensuring the safe operation of the first PMOS transistor PM1.

[0077] The power supply range of P2 and N2 in the second drive signal generation unit is set to Vo to Vo+5V, thereby ensuring that the gate-source voltage Vgs of the first NMOS transistor NM1 in the push-pull output power module 204 is less than or equal to 5V, thus ensuring the safe operation of the first NMOS transistor NM1.

[0078] The power supply range of P3 and N3 in the third drive signal generation unit is set from 5V to 0V.

[0079] The opto-isolation driver provided in this embodiment of the invention uses a PIN junction photodiode, which has advantages such as small junction capacitance, short transit time, and high photoelectric sensitivity. This significantly improves the transmission rate of the entire opto-isolation driver and reduces the transmission delay time to less than 10 ns. The push-pull output power module adopts a complementary output power structure, thereby meeting high current requirements.

[0080] Furthermore, the upper transistor of the push-pull output power module is an independent high-power PMOS transistor connected in parallel with an independent high-power NMOS transistor, and the lower transistor is an independent high-power NMOS transistor; its on-resistance is small, ranging from a few mΩ to tens of mΩ, and its power consumption is very small when outputting large currents, with the maximum output current covering the range of 1A to 30A.

[0081] Using the opto-isolated driver provided in the embodiments of the present invention, the optical emitting module, optical receiving module, signal processing module, and push-pull output power module can be assembled using multi-chip technology, and these modules can be designed on different chips and implemented in a single circuit, which can greatly reduce packaging costs.

[0082] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0083] In the embodiments of this invention, "multiple" refers to two or more.

[0084] The descriptions of "first," "second," etc., appearing in the embodiments of this invention are for illustrative purposes and to distinguish the objects being described. They do not indicate any particular order and do not imply any special limitation on the number of devices in the embodiments of this invention. They do not constitute any limitation on the embodiments of this invention.

[0085] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An opto-isolated driver, comprising: An optical transmitting module, an optical receiving module, a signal processing module, and a push-pull output power module; characterized in that: The optical emitting module is used to generate an optical signal based on an external input voltage signal; The optical receiving module includes at least one PIN junction photodiode for receiving the optical signal and generating a current signal; The signal processing module is used to output a drive signal according to the current signal; The push-pull output power module is a complementary output power structure, including an upper transistor and a lower transistor. The upper transistor includes a first PMOS transistor and a first NMOS transistor connected in parallel, and the lower transistor includes a second NMOS transistor. Both the upper and lower transistors are high-power MOS transistors. It is used to output a voltage signal according to the drive signal. The signal processing module includes: a current amplifier, a voltage comparator, a cathode drive circuit, a bias circuit, an undervoltage lockout circuit, and an output logic drive circuit. The cathode driving circuit is connected to the cathode of the PIN junction photodiode and is used to generate the cathode driving voltage of the PIN junction photodiode. The input terminal of the current amplifier is connected to the anode of the PIN junction photodiode, and the output terminal of the current amplifier is connected to the positive input terminal of the voltage comparator. The bias circuit is connected to the negative input terminal of the voltage comparator and is used to generate a reference voltage; The two input terminals of the output logic drive circuit are respectively connected to the output terminals of the undervoltage lockout circuit and the voltage comparator, and the three output terminals of the output logic drive circuit are respectively connected to the first PMOS transistor, the first NMOS transistor, and the second NMOS transistor, for outputting the drive signal according to the output signals of the undervoltage lockout circuit and the voltage comparator.

2. The opto-isolated driver according to claim 1, characterized in that, The connection point between the upper and lower transistors serves as the output terminal of the opto-isolation driver. When the upper transistor is working, the lower transistor stops working, and the output terminal outputs a high level. When the lower transistor is working, the upper transistor stops working, and the output terminal outputs a low level.

3. The opto-isolated driver according to claim 1, characterized in that, The first PMOS transistor, the first NMOS transistor, and the second NMOS transistor are three independent chips, each driven by a different drive signal.

4. The opto-isolated driver according to claim 1, characterized in that, The first PMOS transistor can be any of the following: VDPMOS transistor or Trench PMOS transistor.

5. The opto-isolated driver according to claim 1, characterized in that, The first NMOS transistor and the second NMOS transistor can be any one of the following: VDNMOS transistor, Trench_NMOS transistor, or SGT_NMOS transistor.

6. The opto-isolated driver according to claim 1, characterized in that, The cathode drive circuit is a low-dropout linear regulator.

7. The opto-isolated driver according to claim 1, characterized in that, The output logic driving circuit includes: a signal conversion unit and a driving unit; The signal conversion unit is used to generate an intermediate signal based on the output signal of the undervoltage lockout circuit and the output signal of the voltage comparator. The driving unit is used to generate the driving signal based on the intermediate signal.

8. The opto-isolated driver according to claim 7, characterized in that, The driving unit includes: The first drive signal generation unit is used to generate a first drive signal for driving the first PMOS transistor according to the drive signal. The second drive signal generation unit is used to generate a second drive signal for driving the first NMOS transistor according to the drive signal. The third drive signal generation unit is used to generate a third drive signal for driving the second NMOS transistor based on the drive signal.

9. The opto-isolated driver according to claim 8, characterized in that, The first drive signal generation unit, the second drive signal generation unit, and the third drive signal generation unit have the same structure, each consisting of a PMOS transistor and an NMOS transistor. The gate of the PMOS transistor is connected to the gate of the NMOS transistor to input the corresponding intermediate signal, and the drain of the PMOS transistor is connected to the drain of the NMOS transistor to output the corresponding drive signal as the output terminal.

10. The opto-isolated driver according to claim 9, characterized in that, The three drive signal generation units use different power supply levels.

11. The opto-isolated driver according to any one of claims 1 to 10, characterized in that, An ITO film is deposited on the photosensitive region above the P+ layer of the PIN junction photodiode.

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