Synchronization circuit, serializer and data output circuit using the same

Abstract

The present disclosure relates to a synchronization circuit, a serializer, and a data output circuit using the same. A synchronization circuit includes a precharge circuit and a signal driving circuit. The precharge circuit precharges an output node to a first logic level. The signal driving circuit detects a logic level of an input signal in synchronization with a second clock signal having a phase leading a first clock signal, and drives the output node to a second logic level in synchronization with the first clock signal according to the logic level of the input signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0141132, filed with the Korean Intellectual Property Office on October 28, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The various embodiments generally relate to integrated circuit technology, and more specifically, to synchronization circuits, serializers using synchronization circuits, and data output circuits using synchronization circuits and serializers. Background Technology

[0004] Electronic devices include multiple electronic components, and a computer system, as such an electronic device, includes multiple semiconductor devices. The semiconductor devices forming the computer system can communicate with each other by sending and receiving clock signals and data. Semiconductor devices can be coupled to each other via buses and / or signal transmission lines, and can send and receive clock signals and data. Serial data can be sent via a data bus. On the other hand, to increase the amount of data to be processed at once, parallel data is utilized within the semiconductor devices. Therefore, to accommodate both types of data, the semiconductor devices are equipped with parallelizers and serializers. A parallelizer is configured to convert serial data provided via a data bus into parallel data, while a serializer is configured to convert parallel data into serial data for output via a data bus. A serializer is configured to synchronize multiple data segments with clock signals of different phases for sequential output of the multiple data segments. A serializer may include multiple multiplexers configured to synchronize multiple data segments with clock signals of different phases. According to the prior art, multiplexers include many stages of components, which increases the load on the output nodes of the serializer. As the load on the output nodes increases, the slope of the serializer's output signal decreases, making it difficult for the serializer to perform high-speed operation. Summary of the Invention

[0005] In one embodiment, a synchronization circuit may include a pre-charge circuit and a signal driving circuit. The pre-charge circuit may be configured to pre-charge the output node to a first logic level. The signal driving circuit may be configured to receive a first clock signal, a second clock signal, and an input signal, and is configured to detect the logic level of the input signal synchronously with the second clock signal, and to drive the output node to the second logic level synchronously with the first clock signal based on the logic level of the input signal. The second clock signal may have a phase leading the first clock signal.

[0006] In one embodiment, a synchronization circuit may include a pull-up driver, a pull-up control driver, a first pull-down control driver, a second pull-down control driver, and a pull-down driver. The pull-up driver may be configured to drive an output node to a first logic level based on an enable signal. The pull-up control driver may be configured to drive a pull-down control signal to the first logic level based on an input signal and a second clock signal. The first pull-down control driver may be configured to drive the pull-down control signal to a second logic level based on the first clock signal. The second pull-down control driver may be configured to drive the pull-down control signal to the second logic level based on the second clock signal. The pull-down driver may be configured to drive an output node to the second logic level based on the pull-down control signal. The second clock signal may have a phase leading the first clock signal.

[0007] In one embodiment, a serializer may include a first synchronization circuit, a second synchronization circuit, a third synchronization circuit, and a fourth synchronization circuit. The first synchronization circuit may be configured to drive an output node to a logic level corresponding to a first input signal based on a first clock signal and a fourth clock signal having a phase leading the first clock signal by a unit phase. The second synchronization circuit may be configured to drive an output node to a logic level corresponding to a second input signal based on a second clock signal and a first clock signal having a phase leading the second clock signal by a unit phase. The third synchronization circuit may be configured to drive an output node to a logic level corresponding to a third input signal based on a third clock signal and a second clock signal having a phase leading the third clock signal by a unit phase. The fourth synchronization circuit may be configured to drive an output node to a logic level corresponding to a fourth input signal based on the fourth clock signal and the third clock signal.

[0008] In one embodiment, a serializer may include a precharge circuit, a first synchronization circuit, a second synchronization circuit, a third synchronization circuit, and a fourth synchronization circuit. The precharge circuit may be configured to precharge an output node to a first logic level. The first synchronization circuit may be configured to receive a first clock signal, a fourth clock signal, and a first input signal, configured to detect the logic level of the first input signal at the falling edge of the fourth clock signal, and configured to drive the output node to a second logic level based on the logic level of the first input signal during a period from the falling edge of the first clock signal to the rising edge of the fourth clock signal. The fourth clock signal may have a phase leading the first clock signal by a unit phase amount. The second synchronization circuit may be configured to receive a second clock signal, the first clock signal, and a second input signal, configured to detect the logic level of the second input signal at the falling edge of the first clock signal, and configured to drive the output node to a second logic level based on the logic level of the second input signal during a period from the falling edge of the second clock signal to the rising edge of the first clock signal. The first clock signal may have a phase leading the second clock signal by a unit phase amount. The third synchronization circuit can be configured to receive a third clock signal, a second clock signal, and a third input signal. It is configured to detect the logic level of the third input signal at the falling edge of the second clock signal and to drive the output node to the second logic level based on the logic level of the third input signal during the period from the falling edge of the third clock signal to the rising edge of the second clock signal. The second clock signal may have a phase leading the third clock signal by a unit phase amount. The fourth synchronization circuit can be configured to receive a fourth clock signal, a third clock signal, and a fourth input signal. It is configured to detect the logic level of the fourth input signal at the falling edge of the third clock signal and to drive the output node to the second logic level based on the logic level of the fourth input signal during the period from the falling edge of the fourth clock signal to the rising edge of the third clock signal.

[0009] In one embodiment, a data output circuit may include a serializer, a pre-driver, and a master driver. The serializer may be configured to output a plurality of data signals as serial data signals based on a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, each having a phase difference corresponding to a unit phase amount between them. The pre-driver may be configured to generate an output control signal based on the serial data signals. The master driver may be configured to drive a data transmission line to a first logic level or a second logic level based on the output control signal. The serializer may include a first synchronization circuit, a second synchronization circuit, a third synchronization circuit, and a fourth synchronization circuit. The first synchronization circuit may be configured to generate a serial data signal having a logic level corresponding to the first data signal based on the first clock signal and the fourth clock signal. The second synchronization circuit may be configured to generate a serial data signal having a logic level corresponding to the second data signal based on the second clock signal and the first clock signal. The third synchronization circuit may be configured to generate a serial data signal having a logic level corresponding to the third data signal based on the third clock signal and the second clock signal. The fourth synchronization circuit may be configured to generate a serial data signal having a logic level corresponding to the fourth data signal based on the fourth clock signal and the third clock signal.

[0010] In one embodiment, a data output circuit may include a serializer, a pre-driver, and a master driver. The serializer may be configured to output a plurality of data signals as serial data signals based on a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal having a phase difference corresponding to a unit phase amount between them sequentially. The pre-driver may be configured to generate an output control signal based on the serial data signals. The master driver may be configured to drive a data transmission line to a first logic level or a second logic level based on the output control signal. The serializer may include a pre-charge circuit, a first synchronization circuit, a second synchronization circuit, a third synchronization circuit, and a fourth synchronization circuit. The pre-charge circuit may be configured to pre-charge an output node through which it outputs serial data signals to a first logic level. The first synchronization circuit may be configured to receive the first clock signal, the fourth clock signal, and the first data signal, and is configured to drive the output node to a second logic level based on the first data signal during a period from the falling edge of the first clock signal to the rising edge of the fourth clock signal. A second synchronization circuit can be configured to receive a second clock signal, a first clock signal, and a second data signal, and is configured to drive the output node to a second logic level based on the second data signal during the period from the falling edge of the second clock signal to the rising edge of the first clock signal. A third synchronization circuit can be configured to receive a third clock signal, a second clock signal, and a third data signal, and is configured to drive the output node to a second logic level based on the third data signal during the period from the falling edge of the third clock signal to the rising edge of the second clock signal. A fourth synchronization circuit can be configured to receive a fourth clock signal, a third clock signal, and a fourth data signal, and is configured to drive the output node to a second logic level based on the fourth data signal during the period from the falling edge of the fourth clock signal to the rising edge of the third clock signal.

[0011] In one embodiment, a data output circuit may include a first serializer, a second serializer, a pre-driver, and a main driver. The first serializer may be configured to sequentially output a plurality of data signals as a first serial data signal based on a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal having a phase difference corresponding to a unit phase amount between them. The second serializer may be configured to sequentially output a plurality of data signals as a second serial data signal based on the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal. The pre-driver may be configured to generate a first output control signal based on the first serial data signal and to generate a second output control signal based on the second serial data signal. The main driver may be configured to drive the data transmission line to a first logic level or a second logic level based on the first output control signal and the second output control signal. Attached Figure Description

[0012] Figure 1 This is a diagram illustrating an example configuration of a serializer according to one embodiment of the present disclosure.

[0013] Figure 2 It is shown Figure 1 A diagram illustrating an example configuration of the first synchronization circuit.

[0014] Figure 3 It is shown Figure 2 The timing diagram shows an example of the operation of the first synchronous circuit.

[0015] Figure 4 It is shown Figure 1 A diagram illustrating an example configuration of the duty cycle correction circuit.

[0016] Figure 5 This is a timing diagram illustrating an example of the operation of a serializer according to one embodiment of the present disclosure.

[0017] Figure 6 This is a diagram illustrating an example configuration of a serializer according to one embodiment of the present disclosure.

[0018] Figure 7 This is a diagram illustrating an example configuration of a data output circuit according to an embodiment of the present disclosure.

[0019] Figure 8 This is a diagram illustrating an example configuration of a data output circuit according to an embodiment of the present disclosure.

[0020] Figure 9A and Figure 9B This is a diagram illustrating an example configuration of a main drive according to one embodiment of the present disclosure.

[0021] Figure 10 This is a diagram illustrating an example configuration of a semiconductor system according to one embodiment of the present disclosure. Detailed Implementation

[0022] Figure 1 This is a diagram illustrating an example configuration of a serializer 100 according to one embodiment of the present disclosure. (Refer to...) Figure 1The serializer 100 can sequentially output multiple input signals as output signals OUT based on a first clock signal CK1, a second clock signal CK2, a third clock signal CK3, and a fourth clock signal CK4, wherein the first to fourth clock signals CK1, CK2, CK3, and CK4 can have the same frequency. However, this disclosure is not limited thereto. In other words, more than four clock signals can be used, but they are not shown here. The first to fourth clock signals CK1, CK2, CK3, and CK4 can sequentially have a phase difference corresponding to a unit phase amount. For example, the first clock signal CK1 can have a phase leading the second clock signal CK2 by a predetermined unit phase amount. Additionally, the second clock signal CK2 can have a phase leading the third clock signal CK3 by a predetermined unit phase amount, and the third clock signal CK3 can have a phase leading the fourth clock signal CK4 by a predetermined unit phase amount. Furthermore, the fourth clock signal CK4 can have a phase leading the first clock signal CK1 by a predetermined unit phase amount. Typically, a unit phase can correspond to 90° and can correspond to one-quarter of the period of the first clock signal CK1. The multiple input signals can include at least two input signals. In order to clarify Figure 1 In this example shown, the serializer 100 is configured to receive input signals, the number of which corresponds to the number of synchronization circuits included in the serializer 100.

[0023] Therefore, as Figure 1As shown, in one embodiment, there are four input signals and four synchronization circuits (one for each input signal). The serializer 100 may include a first synchronization circuit 110, a second synchronization circuit 120, a third synchronization circuit 130, and a fourth synchronization circuit 140. The first synchronization circuit 110 can receive a first clock signal CK1, a fourth clock signal CK4, and a first input signal IN1. The second synchronization circuit 120 can receive a second clock signal CK2, a first clock signal CK1, and a second input signal IN2. The third synchronization circuit 130 can receive a third clock signal CK3, a second clock signal CK2, and a third input signal IN3. The fourth synchronization circuit 140 can receive a fourth clock signal CK4, a third clock signal CK3, and a fourth input signal IN4. The first to fourth synchronization circuits 110, 120, 130, and 140 can be jointly coupled to an output node ON. The output signal OUT can be generated through the output node ON. The first to fourth synchronization circuits 110, 120, 130, and 140 can sequentially output the first to fourth input signals IN1, IN2, IN3, and IN4 as output signals OUT, respectively. The first to fourth input signals IN1, IN2, IN3, and IN4 can be synchronized with the first to fourth clock signals CK1, CK2, CK3, and CK4, respectively. Each of the first to fourth input signals IN1, IN2, IN3, and IN4 can include multiple information segments, which can be changed at predetermined unit intervals (hereinafter referred to as "UI"). For example, in one embodiment, the predetermined UI can correspond to a single cycle of the first clock signal CK1.

[0024] In one embodiment, based on a first clock signal CK1 and a fourth clock signal CK4, a first synchronization circuit 110 can generate an output signal OUT having a logic level corresponding to the first input signal IN1. Synchronized with the fourth clock signal CK4, which has a leading phase, the first synchronization circuit 110 can detect the logic level of the first input signal IN1, and synchronized with the first clock signal CK1, the first synchronization circuit 110 can generate an output signal OUT corresponding to the logic level of the first input signal IN1. In one embodiment, the first synchronization circuit 110 can detect the logic level of the first input signal IN1 at the falling edge of the fourth clock signal CK4, and the first synchronization circuit 110 can generate an output signal OUT having a logic level corresponding to the first input signal IN1 during the period from the falling edge of the first clock signal CK1 to the rising edge of the fourth clock signal CK4. The first synchronization circuit 110 can precharge the output node ON to the first logic level. Furthermore, during the period when both the first clock signal CK1 and the fourth clock signal CK4 have a second logic level, the first synchronization circuit 110 can drive the output node ON to the second logic level based on the first input signal IN1. For example, the first logic level can be a high logic level, and the second logic level can be a low logic level. The first synchronization circuit 110 can repeatedly precharge the output node ON to a high logic level during operation, so that when both the first clock signal CK1 and the fourth clock signal CK4 are at a low logic level, the first synchronization circuit 110 can drive the output node ON to a low logic level because the first input signal IN1 is at a low logic level, and when the first input signal IN1 is at a high logic level, it can not drive the output node ON to a low logic level.

[0025] In one embodiment, based on the second clock signal CK2 and the first clock signal CK1, the second synchronization circuit 120 can generate an output signal OUT having a logic level corresponding to the second input signal IN2. Synchronized with the first clock signal CK1, which has a leading phase, the second synchronization circuit 120 can detect the logic level of the second input signal IN2, and synchronized with the second clock signal CK2, the second synchronization circuit 120 can generate an output signal OUT corresponding to the logic level of the second input signal IN2. In one embodiment, the second synchronization circuit 120 can detect the logic level of the second input signal IN2 at the falling edge of the first clock signal CK1, and the second synchronization circuit 120 can generate the output signal OUT having a logic level corresponding to the second input signal IN2 during the period from the falling edge of the second clock signal CK2 to the rising edge of the first clock signal CK1. Then, the second synchronization circuit 120 can precharge the output node ON to the first logic level. Therefore, during the period when both the second clock signal CK2 and the first clock signal CK1 have the second logic level, the second synchronization circuit 120 can drive the output node ON to the second logic level based on the second input signal IN2. The second synchronization circuit 120 can repeatedly precharge the output node ON to a high logic level during operation. That is, when both the second clock signal CK2 and the first clock signal CK1 are at a low logic level, the second synchronization circuit 120 can drive the output node ON to a low logic level because the second input signal IN2 is at a low logic level, and when the second input signal IN2 is at a high logic level, it can choose not to drive the output node ON to a low logic level.

[0026] In one embodiment, based on a third clock signal CK3 and a second clock signal CK2, a third synchronization circuit 130 can generate an output signal OUT having a logic level corresponding to the third input signal IN3. Synchronized with the second clock signal CK2, which has a leading phase, the third synchronization circuit 130 can detect the logic level of the third input signal IN3, and synchronized with the third clock signal CK3, the third synchronization circuit 130 can generate an output signal OUT corresponding to the logic level of the third input signal IN3. In one embodiment, the third synchronization circuit 130 can detect the logic level of the third input signal IN3 at the falling edge of the second clock signal CK2, and the third synchronization circuit 130 can generate the output signal OUT having a logic level corresponding to the third input signal IN3 during the period from the falling edge of the third clock signal CK3 to the rising edge of the second clock signal CK2. The third synchronization circuit 130 can precharge the output node ON to a first logic level, and during the period when both the third clock signal CK3 and the second clock signal CK2 have a second logic level, the third synchronization circuit 130 can drive the output node ON to the second logic level based on the third input signal IN3. The third synchronization circuit 130 can repeatedly precharge the output node ON to a high logic level during operation, so that when both the third clock signal CK3 and the second clock signal CK2 are at a low logic level, the third synchronization circuit 130 can drive the output node ON to a low logic level because the third input signal IN3 is at a low logic level, and when the third input signal IN3 is at a high logic level, the output node ON can not be driven to a low logic level.

[0027] In one embodiment, based on the fourth clock signal CK4 and the third clock signal CK3, the fourth synchronization circuit 140 can generate an output signal OUT having a logic level corresponding to the fourth input signal IN4. Synchronized with the third clock signal CK3, which has a leading phase, the fourth synchronization circuit 140 can detect the logic level of the fourth input signal IN4, and synchronized with the fourth clock signal CK4, the fourth synchronization circuit 140 can generate an output signal OUT corresponding to the logic level of the fourth input signal IN4. In one embodiment, the fourth synchronization circuit 140 can detect the logic level of the fourth input signal IN4 at the falling edge of the third clock signal CK3, and the fourth synchronization circuit 140 can generate an output signal OUT having a logic level corresponding to the fourth input signal IN4 during the period from the falling edge of the fourth clock signal CK4 to the rising edge of the third clock signal CK3. The fourth synchronization circuit 140 can precharge the output node ON to a first logic level, such that during the period when both the fourth clock signal CK4 and the third clock signal CK3 have a second logic level, the fourth synchronization circuit 140 can drive the output node ON to the second logic level based on the fourth input signal IN4. The fourth synchronization circuit 140 can repeatedly precharge the output node ON to a high logic level during operation, so that when both the fourth clock signal CK4 and the third clock signal CK3 are at a low logic level, the fourth synchronization circuit 140 can drive the output node ON to a low logic level because the fourth input signal IN4 is at a low logic level, and when the fourth input signal IN4 is at a high logic level, the output node ON can not be driven to a low logic level.

[0028] like Figure 1As shown, the serializer 100 may further include a duty cycle correction circuit 150, which may be coupled to the output node ON. The duty cycle correction circuit 150 may receive a duty cycle control signal DC<1:n> (“n” is an integer of 2 or greater) and may adjust the phase of the output signal OUT from the output node ON based on the duty cycle control signal DC<1:n>. The duty cycle control signal DC<1:n> may have a dynamically changing value by monitoring the duty cycle of the output signal OUT from the serializer 100. Alternatively, the duty cycle control signal DC<1:n> may have a predetermined value that takes into account the operating characteristics of the serializer 100. The serializer 100 may further include an equalization circuit 160, which may perform pre-emphasis and / or de-emphasis operations on the output node ON. The equalization circuit 160 may further change the voltage level of the output node ON based on the voltage level of the output node ON changed according to any one of the first to fourth input signals IN1, IN2, IN3, and IN4. The equalization circuit 160 may include any known equalization circuit, any known pre-emphasis circuit, or any known de-emphasis circuit. The serializer 100 may also include an output buffer circuit 170, which may be coupled to the output node ON and buffer the output signal OUT. In one embodiment, the output buffer circuit 170 may include an even number of inverters.

[0029] Figure 2 It is shown Figure 1 A diagram illustrating the configuration of an embodiment of the first synchronization circuit 110. Each of the second to third synchronization circuits 120, 130, and 140 may have the same configuration as the first synchronization circuit 110, except for the input signal. (Refer to...) Figure 2The first synchronization circuit 110 may include a pre-charge circuit 210 and a signal driving circuit 220. The pre-charge circuit 210 may pre-charge the output node ON during operation of the first synchronization circuit 110. The pre-charge circuit 210 may pre-charge the output node ON to a first logic level. The signal driving circuit 220 may receive a first clock signal CK1, a fourth clock signal CK4, and a first input signal IN1. During periods when both the first clock signal CK1 and the fourth clock signal CK4 have a second logic level, the signal driving circuit 220 may selectively drive the output node ON to the second logic level based on the first input signal IN1. When the first input signal IN1 has a first logic level, the signal driving circuit 220 may not drive the output node ON to the second logic level. However, when the first input signal IN1 has a second logic level, the signal driving circuit 220 may drive the output node ON to the second logic level. The driving capability of the signal driving circuit 220 to drive the output node ON to the second logic level may be greater than the driving capability of the pre-charge circuit 210 to pre-charge the output node ON.

[0030] The precharge circuit 210 may include a first transistor T21. The first transistor T21 may be coupled between the output node ON and the node from which a first voltage V1 is supplied, and may receive an enable signal ENB at its gate. The first voltage V1 may have a voltage level high enough to be determined as a high logic level. The enable signal ENB may remain enabled while the first synchronization circuit 110 operates. The first transistor T21 may be a pull-up control driver configured to pull up the output node ON to the first voltage V1 based on the enable signal ENB. The first transistor T21 may be a P-channel MOS transistor. When the enable signal ENB is enabled to a low logic level, the first transistor T21 may provide the first voltage V1 to the output node ON to precharge the output node ON to the voltage level of the first voltage V1.

[0031] The signal driving circuit 220 may include a pull-down control circuit 221 and a pull-down driver 222. The pull-down control circuit 221 may receive a first clock signal CK1, a fourth clock signal CK4, and a first input signal IN1 to generate a pull-down control signal COND. During periods when both the first clock signal CK1 and the fourth clock signal CK4 have a second logic level, the pull-down control circuit 221 may generate the pull-down control signal COND based on the logic level of the first input signal IN1. During periods when either the first clock signal CK1 or the fourth clock signal CK4 has a first logic level, the pull-down control circuit 221 may drive the pull-down control signal COND to a second logic level. When both the first clock signal CK1 and the fourth clock signal CK4 have a second logic level and the first input signal IN1 has a second logic level, the pull-down control circuit 221 may drive the pull-down control signal COND to a first logic level. When both the first clock signal CK1 and the fourth clock signal CK4 have the second logic level and the first input signal IN1 has the first logic level, the pull-down control circuit 221 can make the node at which the pull-down control signal COND is generated floated, without driving the pull-down control signal COND.

[0032] The pull-down control circuit 221 may include a pull-up control driver 221-1, a first pull-down control driver 221-2, and a second pull-down control driver 221-3. The pull-up control driver 221-1 can receive a first input signal IN1 and a fourth clock signal CK4. The pull-up control driver 221-1 can drive the pull-down control signal COND to a first logic level based on the first input signal IN1 and the fourth clock signal CK4. Synchronized with the fourth clock signal CK4, the pull-down control circuit 221 can detect the logic level of the first input signal IN1. The pull-down control circuit 221 can drive the pull-down control signal COND to the first logic level according to the logic level of the first input signal IN1. During the period when the first input signal IN1 has a first logic level or the fourth clock signal CK4 has a first logic level, the pull-up control driver 221-1 may not drive the pull-down control signal COND to the first logic level. During the period when the fourth clock signal CK4 has the second logic level, when the first input signal IN1 has the second logic level, the pull-up control driver 221-1 can drive the pull-down control signal COND to the first logic level.

[0033] The first pull-down control driver 221-2 can receive a first clock signal CK1. During the period when the first clock signal CK1 has a first logic level, the first pull-down control driver 221-2 can drive the pull-down control signal COND to a second logic level. During the period when the first clock signal CK1 has a second logic level, the first pull-down control driver 221-2 can not drive the pull-down control signal COND. The second pull-down control driver 221-3 can receive a fourth clock signal CK4. During the period when the fourth clock signal CK4 has a first logic level, the second pull-down control driver 221-3 can drive the pull-down control signal COND to a second logic level. During the period when the fourth clock signal CK4 has a second logic level, the second pull-down control driver 221-3 can not drive the pull-down control signal COND. The driving capability of each of the first pull-down control driver 221-2 and the second pull-down control driver 221-3 to drive the pull-down control signal COND to the second logic level can be greater than the driving capability of the pull-up control driver 221-1 to drive the pull-down control signal COND to the first logic level.

[0034] The pull-down driver 222 can receive a pull-down control signal COND. The pull-down driver 222 can drive the output node ON to a second logic level based on the pull-down control signal COND. For example, if the pull-down control signal COND has a second logic level or is floating, the pull-down driver 222 may not drive the output node ON to the second logic level. If the pull-down control signal COND has a first logic level, the pull-down driver 222 can drive the output node ON to the second logic level. The driving capability of the pull-down driver 222 in driving the output node ON to the second logic level can be greater than the driving capability of the pre-charge circuit 210 in pre-charging the output node ON. Therefore, the driving capability of the output signal OUT is determined by whichever is greater, either the driving capability implemented by the pre-charge circuit 210 or the pull-down driver 222.

[0035] The pull-up control driver 221-1 may include a NOR gate NR, an inverter INV, and a second transistor T22. The NOR gate NR can receive a first input signal IN1 and a fourth clock signal CK4. The inverter INV can receive the output of the NOR gate NR. The inverter INV can invert the output of the NOR gate NR to output a pull-up control signal CONP. The NOR gate NR and the inverter INV can operate together as an OR gate, configured to output a high logic level signal when either the first input signal IN1 or the fourth clock signal CK4 is at a high logic level. When both the first input signal IN1 and the fourth clock signal CK4 are at a low logic level, the NOR gate NR and the inverter INV can output a low logic level signal. Therefore, when the fourth clock signal CK4 transitions to a low logic level, the NOR gate NR and the inverter INV can change the logic level of the pull-up control signal CONP according to the logic level of the first input signal IN1. The second transistor T22 may be a P-channel MOS transistor. The second transistor T22 can receive the output of the inverter INV at its gate, receive the first voltage V1 at its source, and be coupled at its drain to the node that generates the pull-down control signal COND.

[0036] The first pull-down control driver 221-2 may include a third transistor T23. The third transistor T23 may be an N-channel MOS transistor. The third transistor T23 may receive a first clock signal CK1 at its gate, may be coupled to the node at which the pull-down control signal COND is generated at its drain, and may receive a second voltage V2 at its source. The second voltage V2 may have a voltage level lower than the first voltage V1, and may have a voltage level low enough to be determined as a low logic level. When the first clock signal CK1 has a high logic level, the third transistor T23 may drive the pull-down control signal COND to the second voltage V2, and when the first clock signal CK1 has a low logic level, the third transistor T23 may float the node at which the pull-down control signal COND is generated.

[0037] The second pull-down control driver 221-3 may include a fourth transistor T24. The fourth transistor T24 may be an N-channel MOS transistor. The fourth transistor T24 may receive a fourth clock signal CK4 at its gate, may be coupled at its drain to the node where the pull-down control signal COND is generated, and may receive a second voltage V2 at its source. When the fourth clock signal CK4 has a high logic level, the fourth transistor T24 may drive the pull-down control signal COND to the second voltage V2, and when the fourth clock signal CK4 has a low logic level, the fourth transistor T24 may float the node where the pull-down control signal COND is generated. The size and / or current drive capability of each of the third transistor T23 and the fourth transistor T24 may be greater than the size and / or current drive capability of the second transistor T22.

[0038] The pull-down driver 222 may include a fifth transistor T25. The fifth transistor T25 may be an N-channel MOS transistor. The fifth transistor T25 may receive a pull-down control signal COND at its gate, be coupled to the output node ON at its drain, and receive a second voltage V2 at its source. When the pull-down control signal COND has a high logic level, the fifth transistor T25 may drive the output node ON to the second voltage V2; when the pull-down control signal COND has a low logic level, the fifth transistor T25 may not drive the output node ON. The size and / or current drive capability of the fifth transistor T25 may be greater than the size and / or current drive capability of the first transistor T21.

[0039] Figure 3 It is shown Figure 2 The timing diagram of the operation of the first synchronization circuit 110 is shown. Refer to the following... Figure 2 and Figure 3The operation of the first synchronization circuit 110 is described. In this example, the first input signal IN1 may have four unit intervals (UI). However, this disclosure is not limited thereto. One UI may correspond to a quarter of the period of the first clock signal CK1, while four UIs may correspond to a single period of the first clock signal CK1. The first input signal IN1 may include different information in four UIs. The different information may have the same logic level or may have different logic levels. For example, in the first four UIs, the first input signal IN1 may have either a high logic level or a low logic level. Then, in the second four UIs, the first input signal IN1 may remain at the same logic level or may transition to a different logic level. In this example, the first input signal IN1 has a high logic level H in the first four UIs (i.e., in the period from T1 to T5) and a low logic level L in the second four UIs (i.e., in the period from T5 to T9). The first clock signal CK1 may be synchronized with the first input signal IN1. For example, the rising edge of the first clock signal CK1 can be synchronized with the timing of the four UIs starting from the first input signal IN1 (i.e., T1 and T5). At T1, the precharge circuit 210 can precharge the output node ON to a high logic level. From T1 to T2, the fourth clock signal CK4 can have a high logic level, so the pull-up control signal CONP can have a high logic level. At T2, the fourth clock signal CK4 can transition to a low logic level, but the first input signal IN1 has a high logic level, so the pull-up control signal CONP can remain at a high logic level. Therefore, the pull-up control driver 221-1 can not drive the pull-down control signal COND. From T1 to T3, the first clock signal CK1 can have a high logic level, so the first pull-down control driver 221-2 can drive the pull-down control signal COND to a low logic level. From T1 to T2 and from T4 to T5, the fourth clock signal CK4 can have a high logic level, so the second pull-down control driver 221-3 can drive the pull-down control signal COND to a low logic level. At time T3, the first clock signal CK1 can transition to a low logic level, therefore the first pull-down control driver 221-2 and the second pull-down control driver 221-3 do not need to drive the pull-down control signal COND. However, the pull-up control signal CONP can remain at a high logic level, therefore the pull-up control driver 221-1 does not need to drive the pull-down control signal COND. Therefore, between T3 and T4, the pull-down control signal COND can float, i.e., it can remain in a high impedance (Hi-Z) state, and the pull-down driver 222 does not need to drive the output node ON to a low logic level. Between T3 and T4, the voltage level of the output node ON can be maintained at a high logic level, and the logic level of the output signal OUT can be limited to a high logic level H.From T4 to T5, the fourth clock signal CK4 can have a high logic level, so the pull-down control signal COND can be driven to a low logic level, and the output node ON can be precharged to a high logic level again by the precharge circuit 210.

[0040] From T5 to T6, the fourth clock signal CK4 can be at a high logic level, so the pull-up control signal CONP can remain at a high logic level, and the pull-up control driver 221-1 does not need to drive the pull-down control signal COND. From T5 to T7, the first pull-down control driver 221-2 and the second pull-down control driver 221-3 can drive the pull-down control signal COND to a low logic level. When the fourth clock signal CK4 transitions to a low logic level at T6, the pull-up control driver 221-1 can drive the pull-up control signal CONP to a low logic level according to the logic level of the first input signal IN1. Between T6 and T8, the fourth clock signal CK4 is at a low logic level, and the first input signal IN1 is at a low logic level, so the pull-up control signal CONP can transition to a low logic level. When processing the first input signal IN1 and the fourth clock signal CK4, the NOR gate NR and the inverter INV may cause a delay; therefore, the pull-up control signal CONP can transition to a low logic level between T6 and T7 and can actually transition to a high logic level between T8 and T9. Therefore, the pull-up control driver 221-1 can drive the pull-down control signal COND to a high logic level. However, the first pull-down control driver 221-2 can maintain the pull-down control signal COND at a low logic level, thus keeping it at a low logic level. When the first clock signal CK1 transitions to a low logic level at T7, the first pull-down control driver 221-2 can not drive the pull-down control signal COND. Therefore, between T7 and T8, the pull-down control signal COND can have a high logic level due to the pull-up control driver 221-1. The pull-down driver 222 can drive the output node ON to a low logic level based on the pull-down control signal COND, and the logic level of the output signal OUT can be limited to a low logic level L. At T8, the fourth clock signal CK4 can transition to a high logic level, and the pull-down control signal COND can transition back to a low logic level. Therefore, the precharge circuit 210 can precharge the output node ON to a high logic level.

[0041] When the fourth clock signal CK4, which has a phase leading the first clock signal CK1, is at a low logic level, the first synchronization circuit 110 can drive the pull-down control signal COND to a high logic level based on the logic level of the first input signal IN1. Then, at the point when the first clock signal CK1 transitions to a low logic level, the pull-down driver 222 is driven by the pull-down control signal COND. Therefore, the first synchronization circuit 110 can accurately generate an output signal OUT with a logic level corresponding to the logic level of the first input signal IN1. That is, because the pull-up control signal CONP can have two UIs based on the fourth clock signal CK4, there is sufficient time margin to change the voltage level of the pull-down control signal COND. Furthermore, because the pull-down driver 222 drives the output node ON to a low logic level at the point when the first clock signal CK1 transitions to a low logic level, the operational reliability of the first synchronization circuit 110 can be improved. Furthermore, since the first synchronization circuit 110 has a structure in which the first clock signal CK1 can affect the voltage level change of the output node ON through only two elements (i.e., the fourth transistor T24 and the fifth transistor T25), the first synchronization circuit 110 can operate faster. Moreover, since the pull-down driver 222 is only turned on during periods when both the first clock signal CK1 and the fourth clock signal CK4 are at low logic levels, and the current path through the pull-down driver is blocked during other periods, the amount of current consumed by the first synchronization circuit 110 can be reduced.

[0042] Figure 4 It is shown Figure 1 A diagram showing the configuration of the duty cycle correction circuit 150. (Refer to...) Figure 4 The duty cycle correction circuit 150 may include multiple transistors. The number of transistors in the duty cycle correction circuit 150 corresponds to the number of bits in the duty cycle control signal DC<1:n>. Figure 4 As shown, the duty cycle correction circuit 150 may include a first transistor T41, a second transistor T42, and up to an nth transistor T4n. Each of the first transistor T41, the second transistor T42, and up to the nth transistor T4n may be a P-channel MOS transistor. The first transistor T41 may receive the first bit DC of the duty cycle control signal DC<1:n>. <1> It can also provide a first voltage V1 to the output node ON. The second transistor T42 can receive the second bit DC of the duty cycle control signal DC<1:n>. <2> It can also provide the first voltage V1 to the output node ON. The nth transistor T4n can receive the nth bit DC of the duty cycle control signal DC<1:n>. <n>Furthermore, a first voltage V1 can be provided to the output node ON. The duty cycle correction circuit 150 can be a variable current source. Based on the logic value of the duty cycle control signal DC<1:n>, the duty cycle correction circuit 150 can change the amount of current supplied from the node supplying the first voltage V1 to the output node ON, thereby changing the voltage level of the output node ON. In one embodiment, each of the first transistor T41, the second transistor T42, and up to the nth transistor (where n can be a positive integer) T4n can be replaced with an N-channel MOS transistor and can be modified to provide a second voltage V2 to the output node ON based on the duty cycle control signal DC<1:n>.

[0043] Figure 5 This is a timing diagram illustrating the operation of a serializer 100 according to one embodiment. In the following text, reference will be made to... Figure 1 and Figure 5 The operation of the serializer 100 is described. In one embodiment, each of the first to fourth input signals IN1, IN2, IN3, and IN4 may have a single information segment every four UIs, and may be changed to have the same or different information every four UIs. The first to fourth input signals IN1, IN2, IN3, and IN4 may be synchronized with the first to fourth clock signals CK1, CK2, CK3, and CK4, respectively. The first to fourth input signals IN1, IN2, IN3, and IN4 may sequentially have a phase difference corresponding to a unit phase (1 UI) between them. The first input signal IN1 may be synchronized with the rising edge of the first clock signal CK1 at T1 and T5. The second input signal IN2 may be synchronized with the rising edge of the second clock signal CK2 at T2 and T6. The third input signal IN3 may be synchronized with the rising edge of the third clock signal CK3 at T3 and T7. The fourth input signal IN4 may be synchronized with the rising edge of the fourth clock signal CK4 at T4 and T8. Between T1 and T2, both the second clock signal CK2 and the third clock signal CK3 can have a low logic level, so the third synchronization circuit 130 can generate an output signal OUT corresponding to the logic level of the third input signal IN3. Between T2 and T3, both the third clock signal CK3 and the fourth clock signal CK4 can have a low logic level, so the fourth synchronization circuit 140 can generate an output signal OUT corresponding to the logic level of the fourth input signal IN4. Between T3 and T4, both the first clock signal CK1 and the fourth clock signal CK4 can have a low logic level, so the first synchronization circuit 110 can generate an output signal OUT corresponding to the logic level of the first input signal IN1. Between T4 and T5, both the first clock signal CK1 and the second clock signal CK2 can have a low logic level, so the second synchronization circuit 120 can generate an output signal OUT corresponding to the logic level of the second input signal IN2. Then, between T5 and T9, output signals OUT corresponding to the logic levels of the third input signal IN3, the fourth input signal IN4, the first input signal IN1, and the second input signal IN2 can be output sequentially at unit phase intervals.

[0044] Figure 6 This is a diagram illustrating an example configuration of a serializer 600 according to one embodiment of the present disclosure. (Refer to...) Figure 6 The serializer 600 may include a precharge circuit 610, a first synchronization circuit 620, a second synchronization circuit 630, a third synchronization circuit 640, and a fourth synchronization circuit 650. The precharge circuit 610 can precharge the output node ON to a first logic level. The first synchronization circuit 620 can receive a first clock signal CK1, a fourth clock signal CK4, and a first input signal IN1. The fourth clock signal CK4 may have a phase leading the first clock signal CK1 by a unit phase amount. Synchronized with the fourth clock signal CK4 with the leading phase, the first synchronization circuit 620 can detect the logic level of the first input signal IN1. Synchronized with the first clock signal CK1, the first synchronization circuit 620 can generate an output signal OUT corresponding to the logic level of the first input signal IN1. The first synchronization circuit 620 can drive the output node ON to a second logic level based on the first input signal IN1 during the period from the falling edge of the first clock signal CK1 to the rising edge of the fourth clock signal CK4. The second synchronization circuit 630 can receive a second clock signal CK2, the first clock signal CK1, and the second input signal IN2. The first clock signal CK1 may have a phase lead of one unit phase over the second clock signal CK2. Synchronized with the leading first clock signal CK1, the second synchronization circuit 630 can detect the logic level of the second input signal IN2. Synchronized with the second clock signal CK2, the second synchronization circuit 630 can generate an output signal OUT corresponding to the logic level of the second input signal IN2. The second synchronization circuit 630 can drive the output node ON to the second logic level based on the second input signal IN2 during the period from the falling edge of the second clock signal CK2 to the rising edge of the first clock signal CK1. The third synchronization circuit 640 can receive the third clock signal CK3, the second clock signal CK2, and the third input signal IN3. The second clock signal CK2 may have a phase lead of one unit phase over the third clock signal CK3. Synchronized with the leading second clock signal CK2, the third synchronization circuit 640 can detect the logic level of the third input signal IN3. Synchronized with the third clock signal CK3, the third synchronization circuit 640 can generate an output signal OUT corresponding to the logic level of the third input signal IN3. The third synchronization circuit 640 can drive the output node ON to the second logic level based on the third input signal IN3 during the period from the falling edge of the third clock signal CK3 to the rising edge of the second clock signal CK2. The fourth synchronization circuit 650 can receive the fourth clock signal CK4, the third clock signal CK3, and the fourth input signal IN4. The third clock signal CK3 can have a phase lead of one phase amount over the fourth clock signal CK4. Synchronized with the third clock signal CK3 with the leading phase, the fourth synchronization circuit 650 can detect the logic level of the fourth input signal IN4.Synchronized with the fourth clock signal CK4, the fourth synchronization circuit 650 can generate an output signal OUT corresponding to the logic level of the fourth input signal IN4. The fourth synchronization circuit 650 can drive the output node ON to the second logic level based on the fourth input signal IN4 during the period from the falling edge of the fourth clock signal CK4 to the rising edge of the third clock signal CK3. The first to fourth synchronization circuits 620, 630, 640, and 650 can share a single precharge circuit 610. The precharge circuit 610 may include... Figure 2 The configuration of the pre-charge circuit 210 in the first synchronization circuit 110 configuration shown. Each of the first to fourth synchronization circuits 620, 630, 640 and 650 may include Figure 2 The configuration of the first synchronization circuit 110 shown includes all configurations except for the pre-charge circuit 210.

[0045] Figure 7 This is a diagram illustrating an embodiment of the configuration of a data output circuit 700 according to an embodiment of the present disclosure. (Refer to...) Figure 7 The data output circuit 700 may include a serializer 710, a pre-driver 720, and a master driver 730. The serializer 710 can receive a first clock signal CK1, a second clock signal CK2, a third clock signal CK3, a fourth clock signal CK4, and multiple data signals. The first to fourth clock signals CK1, CK2, CK3, and CK4 may sequentially have a phase difference corresponding to a unit phase amount. Synchronized with the first to fourth clock signals CK1, CK2, CK3, and CK4, the serializer 710 can sequentially output multiple data signals as a serial data signal SOUT. For ease of description, multiple data signals are illustrated, including a first data signal D1, a second data signal D2, a third data signal D3, and a fourth data signal D4. The serializer 710 can sequentially output a serial data signal SOUT having a logic level corresponding to the corresponding first to fourth data signals D1, D2, D3, and D4 at the falling edge of the respective first to fourth clock signals CK1, CK2, CK3, and CK4. Figure 1 and Figure 6 Either of the serializers 100 and 600 shown in the diagram can be used as serializer 710.

[0046] The pre-driver 720 can receive a serial data signal SOUT and can generate an output control signal MD based on the serial data signal SOUT. For example, the pre-driver 720 can invert the serial data signal SOUT to generate an output control signal MD with a logic level complementary to the serial data signal SOUT. The pre-driver 720 may include a driver 721, which can invert the serial data signal SOUT to output the output control signal MD.

[0047] The main driver 730 can receive the output control signal MD from the pre-driver 720. The main driver 730 can be coupled to the data transmission line 701 and can drive the data transmission line 701 to a high or low logic level based on the output control signal MD. The data transmission line 701 can be a data bus coupled between a semiconductor device including the data output circuit 700 and another semiconductor device. When the data transmission line 701 is driven to a high or low logic level, data DQ can be transmitted through the data transmission line 701. The main driver 730 can drive the data transmission line 701 to a high logic level when the output control signal MD is low, and can drive the data transmission line 701 to a low logic level when the output control signal MD is high.

[0048] The main driver 730 may include a pull-up transistor 731, a first resistor 732, a second resistor 733, and a pull-down transistor 734. The pull-up transistor 731 may be a pull-up driver configured to drive the data transmission line 701. The pull-up transistor 731 may be a P-channel MOS transistor. The pull-up transistor 731 may receive an output control signal MD at its gate and a first data supply voltage VDDQ at its source. The first data supply voltage VDDQ may have a voltage level high enough to be determined as a high logic level. The first data supply voltage VDDQ may have a voltage level that is similar to... Figure 1 The voltage level may be the same as or different from the first voltage V1. Even if the first data power supply voltage VDDQ has the same voltage level as the first voltage V1, the power supply configured to supply the first data power supply voltage VDDQ may be different from the power supply configured to supply the first voltage V1 in order to prevent noise in the data DQ output through the data transmission line 701. The first resistor 732 may be coupled at one end to the drain of the pull-up transistor 731 and at the other end to the data transmission line 701. In one embodiment, the first resistor 732 may be replaced by being coupled at one end to the node from which the first data power supply voltage VDDQ is supplied, and the pull-up transistor 731 may be replaced by being coupled between the other end of the first resistor 732 and the data transmission line 701.

[0049] The second resistor 733 can be coupled to the data transmission line 701 at one end. The pull-down transistor 734 can be a pull-down driver configured to drive the data transmission line 701. The pull-down transistor 734 can be an N-channel MOS transistor. The pull-down transistor 734 can receive an output control signal MD at its gate, can be coupled to the other end of the second resistor 733 at its drain, and can receive a second data power supply voltage VSSQ at its source. The second data power supply voltage VSSQ can have a voltage level lower than the first data power supply voltage VDDQ. The second data power supply voltage VSSQ can have a sufficiently low voltage level to be determined as a low logic level. The second data power supply voltage VSSQ can have a voltage level lower than the first data power supply voltage VDDQ. Figure 2 The second voltage V2 shown may have the same voltage level as or be different from the second voltage V2. Even if the second data power supply voltage VSSQ has the same voltage level as the second voltage V2, the power supply configured to supply the second data power supply voltage VSSQ may be different from the power supply configured to supply the second voltage V2 in order to prevent noise in the data DQ output through the data transmission line 701. In one embodiment, the second resistor 733 may be replaced by being coupled at the other end to the node from which the second data power supply voltage VSSQ is supplied, and the pull-down transistor 734 may be replaced by being coupled between said end of the second resistor 733 and the data transmission line 701.

[0050] Figure 8 This is a diagram illustrating an embodiment of the configuration of a data output circuit 800 according to an embodiment of the present disclosure. (Refer to...) Figure 8 The data output circuit 800 may include a first serializer 811, a second serializer 812, a pre-driver 820, and a main driver 830. The first serializer 811 and the second serializer 812 can jointly receive a first clock signal CK1, a second clock signal CK2, a third clock signal CK3, a fourth clock signal CK4, a first data signal D1, a second data signal D2, a third data signal D3, and a fourth data signal D4. Based on the first to fourth clock signals CK1, CK2, CK3, and CK4, the first serializer 811 can sequentially output the first to fourth data signals D1, D2, D3, and D4 as the first serial data signal SOUT1. Based on the first to fourth clock signals CK1, CK2, CK3, and CK4, the second serializer 812 can sequentially output the first to fourth data signals D1, D2, D3, and D4 as the second serial data signal SOUT2. The first serializer 811 and the second serializer 812 can have the same configuration as each other. For example, respectively in... Figure 1 and Figure 6 Either of the serializers 100 and 600 shown can be used as each of the first serializer 811 and the second serializer 812.

[0051] The pre-driver 820 can be coupled to the first serializer 811 and the second serializer 812. The pre-driver 820 can receive a first serial data signal SOUT1 and a second serial data signal SOUT2. The pre-driver 820 can generate a first output control signal MD1 based on the first serial data signal SOUT1. The pre-driver 820 can generate a second output control signal MD2 based on the second serial data signal SOUT2.

[0052] The main driver 830 can receive a first output control signal MD1 and a second output control signal MD2 from the pre-driver 820. Based on the first output control signal MD1 and the second output control signal MD2, the main driver 830 can drive the data transmission line 801 to a high logic level or a low logic level. The main driver 830 can drive the data transmission line 801 to a high logic level based on the first output control signal MD1, and can drive the data transmission line 801 to a low logic level based on the second output control signal MD2. That is, the main driver 830 can pull up the data transmission line 801 based on the first output control signal MD1, and can pull down the data transmission line 801 based on the second output control signal MD2. In one embodiment, the main driver 830 can drive the data transmission line 801 to a high logic level based on both the first output control signal MD1 and the second output control signal MD2, and can also drive the data transmission line 801 to a low logic level based on both the first output control signal MD1 and the second output control signal MD2.

[0053] like Figure 8 As shown, when the data output circuit 800 includes two serializers coupled in parallel, the drive capability for driving the pull-up control driver and pull-down control driver included in the main driver 830 can be allocated. Therefore, the drive capability of the pre-driver 820 and the area occupied by the pre-driver 820 can be minimized. However, when the data output circuit 800 includes two serializers, a mismatch may occur between the first output control signal MD1 generated based on the first serial data signal SOUT1 output from the first serializer 811 and the second output control signal MD2 generated based on the second serial data signal SOUT2 output from the second serializer 812 due to local process variation. To solve this problem, the pre-driver 820 can generate the first output control signal MD1 by mixing the second output control signal MD2 into the first output control signal MD1, and can generate the second output control signal MD2 by mixing the first output control signal MD1 into the second output control signal MD2. By mixing the phases of the first output control signal MD1 and the second output control signal MD2 in this manner by the pre-driver 820, the first output control signal MD1 and the second output control signal MD2 can have an intermediate phase corresponding to the phase difference of the mismatch. Therefore, the mismatch caused by local process variations can be compensated, and the performance of the data output circuit 800 can be improved.

[0054] The pre-driver 820 may include a first driver 821, a second driver 822, a third driver 823, and a fourth driver 824. The first driver 821 and the fourth driver 824 can jointly receive a first serial data signal SOUT1. The second driver 822 and the third driver 823 can jointly receive a second serial data signal SOUT2. The first driver 821 and the third driver 823 can generate a first output control signal MD1. The second driver 822 and the fourth driver 824 can generate a second output control signal MD2. The first driver 821 can invert the first serial data signal SOUT1 to generate the first output control signal MD1. The second driver 822 can invert the second serial data signal SOUT2 to generate the second output control signal MD2. The third driver 823 can invert the second serial data signal SOUT2 to generate the first output control signal MD1. The fourth driver 824 can invert the first serial data signal SOUT1 to generate the second output control signal MD2.

[0055] Figure 9A This is a diagram illustrating an embodiment of the configuration of a main drive 900A according to an embodiment of the present disclosure. The main drive 900A can be applied as... Figure 8 The main driver 830 is shown. (See reference...) Figure 9A The main driver 900A may include a pull-up transistor 911, a first resistor 912, a second resistor 913, and a pull-down transistor 914. The pull-up transistor 911 may be a pull-up driver configured to drive the data transmission line 901. The pull-up transistor 911 may be a P-channel MOS transistor. The pull-up transistor 911 may receive a first output control signal MD1 at its gate and a first data supply voltage VDDQ at its source. The first resistor 912 may be coupled at one end to the drain of the pull-up transistor 911 and at the other end to the data transmission line 901. In one embodiment, the first resistor 912 may be replaced by being coupled at one end to the node from which the first data supply voltage VDDQ is provided, and the pull-up transistor 911 may be replaced by being coupled between the other end of the first resistor 912 and the data transmission line 901.

[0056] The second resistor 913 can be coupled to the data transmission line 901 at one end. The pull-down transistor 914 can be a pull-down driver configured to drive the data transmission line 901. The pull-down transistor 914 can be an N-channel MOS transistor. The pull-down transistor 914 can receive a second output control signal MD2 at its gate, can be coupled to the other end of the second resistor 913 at its drain, and can receive a second data power supply voltage VSSQ at its source. In one embodiment, the second resistor 913 can be replaced by being coupled at the other end to the node from which the second data power supply voltage VSSQ is supplied, and the pull-down transistor 914 can be replaced by being coupled between said end of the second resistor 913 and the data transmission line 901.

[0057] Figure 9B This is a diagram illustrating an embodiment of the configuration of a main drive 900B according to an embodiment of the present disclosure. The main drive 900B can be applied as... Figure 8 The main driver 830 is shown. (See reference...) Figure 9B The main driver 900B may include a first pull-up transistor 921, a second pull-up transistor 922, a first resistor 923, a second resistor 924, a first pull-down transistor 925, and a second pull-down transistor 926. Each of the first pull-up transistor 921 and the second pull-up transistor 922 may be a pull-up driver configured to pull up the data transmission line 901. Each of the first pull-up transistor 921 and the second pull-up transistor 922 may be a P-channel MOS transistor. The first pull-up transistor 921 may receive a first output control signal MD1 at its gate and a first data power supply voltage VDDQ at its source. The second pull-up transistor 922 may receive a second output control signal MD2 at its gate and a first data power supply voltage VDDQ at its source. The first resistor 923 may be coupled at one end to the drain of both the first pull-up transistor 921 and the second pull-up transistor 922, and at the other end to the data transmission line 901. In one embodiment, the first resistor 923 may be modified to be coupled at one end to the node from which the first data power supply voltage VDDQ is provided, and the first pull-up transistor 921 and the second pull-up transistor 922 may be modified to be coupled together between the other end of the first resistor 923 and the data transmission line 901.

[0058] The second resistor 924 can be coupled to the data transmission line 901 at one end. Each of the first pull-down transistor 925 and the second pull-down transistor 926 can be a pull-down driver configured to drive the data transmission line 901. Each of the first pull-down transistor 925 and the second pull-down transistor 926 can be an N-channel MOS transistor. The first pull-down transistor 925 can receive a first output control signal MD1 at its gate, can be coupled to the other end of the second resistor 924 at its drain, and can receive a second data power supply voltage VSSQ at its source. The second pull-down transistor 926 can receive a second output control signal MD2 at its gate, can be coupled to the other end of the second resistor 924 at its drain, and can receive the second data power supply voltage VSSQ at its source. In one embodiment, the second resistor 924 can be replaced by being coupled to the node from which the second data power supply voltage VSSQ is provided, and the first pull-down transistor 925 and the second pull-down transistor 926 can be replaced by being commonly coupled between one end of the second resistor 924 and the data transmission line 901.

[0059] Figure 10 This is a diagram illustrating an embodiment of the configuration of a semiconductor system 1000 according to an embodiment of the present disclosure. (Refer to...) Figure 10 The semiconductor system 1000 may include a first semiconductor device 1010 and a second semiconductor device 1020. The first semiconductor device 1010 can provide various control signals required for the operation of the second semiconductor device 1020. The first semiconductor device 1010 may include various types of devices. For example, the first semiconductor device 1010 may be a host device such as a central processing unit (CPU), a graphics processing unit (GPU), a multimedia processor (MMP), a digital signal processor, an application processor (AP), and a memory controller. For example, the second semiconductor device 1020 may be a memory device, and the memory device may include volatile memory and non-volatile memory. Volatile memory may include static random access memory (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically erasable programmable ROM (EEPROM), electrically programmable ROM (EPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM), etc.

[0060] The second semiconductor device 1020 can be coupled to the first semiconductor device 1010 via multiple buses. These buses can be signal transmission paths, links, or channels for transmitting signals. The multiple buses may include a clock bus 1001 and a data bus 1002. The clock bus 1001 can be a unidirectional bus, while the data bus 1002 can be a bidirectional bus. Although not shown, the semiconductor system 1000 may also include a command bus and an address bus configured to transmit command signals and address signals from the first semiconductor device 1010 to the second semiconductor device 1020. The second semiconductor device 1020 can be coupled to the first semiconductor device 1010 via the clock bus 1001 and can receive the system clock signal SCK from the first semiconductor device 1010 via the clock bus 1001. The system clock signal SCK can be transmitted as a single-ended signal and can be transmitted as a differential signal together with a complementary system clock signal SCKB. The second semiconductor device 1020 can be coupled to the first semiconductor device 1010 via the data bus 1002, and can receive data DQ from the first semiconductor device 1010 and send data DQ to the first semiconductor device 1010 via the data bus 1002.

[0061] The first semiconductor device 1010 may include a system clock generation circuit 1011 and a data input / output circuit 1012. The system clock generation circuit 1011 can generate a system clock signal SCK. The system clock generation circuit 1011 can provide the system clock signal SCK to the second semiconductor device 1120 via a clock bus 1101. The system clock generation circuit 1011 can generate and transmit a complementary system clock signal SCKB together with the system clock signal SCK. The system clock generation circuit 1011 may include clock generation circuitry, such as a ring oscillator and a phase-locked loop circuit. The system clock generation circuit 1011 can generate multiple first internal clock signals INCK1 that have a constant phase difference between each other sequentially from the system clock signal SCK. Figure 1 The first to fourth clock signals CK1, CK2, CK3, and CK4 shown can correspond to multiple first internal clock signals INCK1. Data input / output circuit 1012 can receive multiple first internal clock signals INCK1 from system clock generation circuit 1011. Data input / output circuit 1012 can be coupled to data bus 1002, and can transmit data DQ through data bus 1002, and can receive data DQ provided through data bus 1002. Data input / output circuit 1012 can transmit data DQ to second semiconductor device 1020 synchronously with multiple first internal clock signals INCK1, and can receive data DQ transmitted from second semiconductor device 1020 synchronously with multiple first internal clock signals INCK1. Data input / output circuit 1012 may include data output circuit (TX) 1012-1 and data input circuit (RX) 1012-2. Synchronized with multiple first internal clock signals INCK1, data output circuit 1012-1 can output the internal data signal of first semiconductor device 1010 as data DQ. In respectively Figure 7 Either the data output circuit 700 or the data output circuit 800 shown in Figure 8 can be used as data output circuit 1012-1. The internal data signal of the first semiconductor device 1010 can correspond to multiple data signals received by data output circuits 700 and 800. Synchronized with multiple first internal clock signals INCK1, data input circuit 1012-2 can receive data DQ provided from the second semiconductor device 1020 to generate the internal data signal of the first semiconductor device 1010.

[0062] The second semiconductor device 1020 may include an internal clock generation circuit 1021 and a data input / output circuit 1022. The internal clock generation circuit 1021 may be coupled to a clock bus 1001 and may receive a system clock signal SCK and a complementary system clock signal SCKB transmitted via the clock bus 1001. The internal clock generation circuit 1021 may include a delay-locked loop circuit configured to generate a delay-locked clock signal by delaying the system clock signal SCK. The internal clock generation circuit 1021 may generate a plurality of second internal clock signals INCK2 that are sequentially arranged with a constant phase difference from each other from the delay-locked clock signal. Figure 1 The first to fourth clock signals CK1, CK2, CK3, and CK4 shown can correspond to multiple second internal clock signals INCK2. The data input / output circuit 1022 can be coupled to the data bus 1002, and can transmit data DQ through the data bus 1002, and can receive data DQ provided through the data bus 1002. The data input / output circuit 1022 can transmit data DQ to the first semiconductor device 1010 synchronously with the multiple second internal clock signals INCK2, and can receive data DQ transmitted from the first semiconductor device 1010 synchronously with the multiple second internal clock signals INCK2. The data input / output circuit 1022 may include a data output circuit (TX) 1022-1 and a data input circuit (RX) 1022-2. Synchronized with the multiple second internal clock signals INCK2, the data output circuit 1022-1 can output the internal data signal of the second semiconductor device 1020 as data DQ. Figure 7 and Figure 8 Either of the data output circuits 700 and 800 shown can be used as data output circuit 1022-1. The internal data signal of the second semiconductor device 1020 can correspond to multiple data signals received by data output circuits 700 and 800. Synchronized with multiple second internal clock signals INCK2, data input circuit 1022-2 can receive data DQ provided from the first semiconductor device 1010 to generate the internal data signal of the second semiconductor device 1020.

[0063] Although certain embodiments have been described above, those skilled in the art will understand that the described embodiments are merely exemplary. Therefore, the synchronization circuits, serializers, and data output circuits using them should not be limited based on the described embodiments. Rather, the synchronization circuits, serializers, and data output circuits using them described herein should only be limited according to the appended claims in conjunction with the foregoing description and drawings.< / n>

Claims

1. A synchronization circuit, comprising: A pre-charge circuit is configured to pre-charge the output node to a first logic level; as well as A signal driving circuit is configured to receive a first clock signal, a second clock signal, and an input signal, wherein the phase of the second clock signal leads the phase of the first clock signal; The logic level of the input signal is configured to be detected synchronously with the second clock signal; And configured to drive the output node to a second logic level in sync with the first clock signal based on the logic level of the input signal.

2. The synchronization circuit according to claim 1, wherein, The pre-charging circuit's ability to pre-charge the output node to the first logic level is less than the signal driving circuit's ability to drive the output node to the second logic level.

3. The synchronization circuit according to claim 1, wherein, The precharge circuit includes a pull-up driver configured to drive the output node to the first logic level based on an enable signal.

4. The synchronization circuit according to claim 1, wherein, The signal driving circuit includes: A pull-down control circuit configured to generate a pull-down control signal based on the logic level of the input signal during a period when the first clock signal and the second clock signal have the second logic level; and A pull-down driver configured to drive the output node to the second logic level based on the pull-down control signal.

5. The synchronization circuit according to claim 4, wherein, The pull-down control circuit includes: A pull-up control driver configured to drive the pull-down control signal to the first logic level based on the input signal and the second clock signal; A first pull-down control driver is configured to drive the pull-down control signal to the second logic level based on the first clock signal; and A second pull-down control driver is configured to drive the pull-down control signal to the second logic level based on the second clock signal.

6. The synchronization circuit according to claim 5, wherein, The driving capability of each of the first pull-down control driver and the second pull-down control driver is greater than the driving capability of the pull-up control driver.

7. A synchronization circuit, comprising: A pull-up driver, configured to drive the output node to a first logic level based on an enable signal; A pull-up control driver configured to drive a pull-down control signal to the first logic level based on an input signal and a second clock signal; A first pull-down control driver is configured to drive the pull-down control signal to a second logic level based on a first clock signal; A second pull-down control driver is configured to drive the pull-down control signal to the second logic level based on the second clock signal; as well as A pull-down driver configured to drive the output node to the second logic level based on the pull-down control signal. The second clock signal has a phase that leads the first clock signal.

8. The synchronization circuit according to claim 7, wherein, The pull-down driver has a greater driving capability to drive the output node to the second logic level than the pull-up driver has a greater driving capability to drive the output node to the first logic level.

9. The synchronization circuit according to claim 7, wherein, The driving capability of each of the first pull-down control driver and the second pull-down control driver to drive the pull-down control signal to the second logic level is greater than the driving capability of the pull-up control driver to drive the pull-down control signal to the first logic level.

10. A serializer, comprising: A first synchronization circuit is configured to detect the logic level of a first input signal based on a fourth clock signal, the fourth clock signal being a unit phase ahead of the first clock signal. And configured to drive the output node based on the logic level of the first input signal according to the first clock signal; A second synchronization circuit is configured to detect the logic level of a second input signal based on the first clock signal, wherein the phase of the first clock signal leads the second clock signal by a unit phase amount. And configured to drive the output node based on the logic level of the second input signal according to the second clock signal; A third synchronization circuit is configured to detect the logic level of a third input signal based on the second clock signal, wherein the phase of the second clock signal leads the third clock signal by a unit phase amount. And configured to drive the output node based on the logic level of the third input signal according to the third clock signal; as well as A fourth synchronization circuit is configured to detect the logic level corresponding to a fourth input signal based on the third clock signal, wherein the phase of the third clock signal leads the fourth clock signal by a unit phase amount. And configured to drive the output node based on the logic level of the fourth input signal according to the fourth clock signal.

11. The serializer according to claim 10, wherein, The first synchronization circuit is configured to precharge the output node to a first logic level and to drive the output node to the second logic level based on the first input signal during a period when the first clock signal and the fourth clock signal have a second logic level.

12. The serializer according to claim 10, wherein, The second synchronization circuit is configured to precharge the output node to a first logic level and to drive the output node to the second logic level based on the second input signal during a period when the second clock signal and the first clock signal have a second logic level.

13. The serializer according to claim 10, wherein, The third synchronization circuit is configured to precharge the output node to a first logic level and to drive the output node to the second logic level based on the third input signal during a period when the third clock signal and the second clock signal have a second logic level.

14. The serializer according to claim 10, wherein, The fourth synchronization circuit is configured to precharge the output node to a first logic level, and is configured to drive the output node to the second logic level based on the fourth input signal during a period when the fourth clock signal and the third clock signal have a second logic level.

15. The serializer according to claim 10, It also includes a duty cycle correction circuit coupled to the output node. in, The duty cycle correction circuit is configured to change the voltage level of the output node based on the duty cycle control signal.

16. The serializer of claim 10, further comprising an equalization circuit configured to: additionally change the voltage level of the output node based on the voltage level of the output node changed according to any one of the first input signal to the fourth input signal.

17. A serializer, comprising: A pre-charge circuit is configured to pre-charge the output node to a first logic level; A first synchronization circuit is configured to receive a first clock signal, a fourth clock signal, and a first input signal, wherein the phase of the fourth clock signal leads the phase of the first clock signal by a unit phase amount. It is configured to detect the logic level of the first input signal at the falling edge of the fourth clock signal; And configured to drive the output node to a second logic level based on the logic level of the first input signal during the period from the falling edge of the first clock signal to the rising edge of the fourth clock signal; A second synchronization circuit is configured to receive a second clock signal, a first clock signal, and a second input signal, wherein the phase of the first clock signal leads the phase of the second clock signal by a unit phase amount. It is configured to detect the logic level of the second input signal on the falling edge of the first clock signal; And configured to drive the output node to the second logic level based on the logic level of the second input signal during the period from the falling edge of the second clock signal to the rising edge of the first clock signal; A third synchronization circuit is configured to receive a third clock signal, a second clock signal, and a third input signal, wherein the phase of the second clock signal leads the third clock signal by a unit phase amount; and is configured to detect the logic level of the third input signal at the falling edge of the second clock signal. And configured to drive the output node to the second logic level based on the logic level of the third input signal during the period from the falling edge of the third clock signal to the rising edge of the second clock signal; as well as A fourth synchronization circuit is configured to receive the fourth clock signal, the third clock signal, and the fourth input signal; It is configured to detect the logic level of the fourth input signal on the falling edge of the third clock signal; And configured to drive the output node to the second logic level based on the logic level of the fourth input signal during the period from the falling edge of the fourth clock signal to the rising edge of the third clock signal.

18. The serializer as claimed in claim 17, It also includes a duty cycle correction circuit coupled to the output node. in, The duty cycle correction circuit is configured to change the voltage level of the output node based on the duty cycle control signal.

19. The serializer of claim 17, further comprising an equalization circuit configured to: additionally change the voltage level of the output node based on the voltage level of the output node changed according to any one of the first input signal to the fourth input signal.

20. A data output circuit, comprising: A serializer is configured to output multiple data signals as serial data signals based on a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal that have a phase difference between each other in sequence corresponding to a unit phase amount. A pre-driver configured to generate an output control signal based on the serial data signal; as well as The main driver is configured to drive the data transmission line to a first logic level or a second logic level based on the output control signal. The serializer includes: A first synchronization circuit is configured to generate a serial data signal having a logic level corresponding to the first data signal based on the first clock signal and the fourth clock signal. The second synchronization circuit is configured to generate a serial data signal having a logic level corresponding to the second data signal based on the second clock signal and the first clock signal. A third synchronization circuit is configured to generate a serial data signal having a logic level corresponding to the third data signal based on the third clock signal and the second clock signal; and A fourth synchronization circuit is configured to generate a serial data signal having a logic level corresponding to the fourth data signal based on the fourth clock signal and the third clock signal.

21. A data output circuit, comprising: A serializer is configured to output multiple data signals as serial data signals based on a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal that have a phase difference between each other in sequence corresponding to a unit phase amount. A pre-driver configured to generate an output control signal based on the serial data signal; as well as The main driver is configured to drive the data transmission line to a first logic level or a second logic level based on the output control signal. The serializer includes: A pre-charge circuit is configured to pre-charge the output node that outputs the serial data signal to a first logic level. A first synchronization circuit is configured to receive a first clock signal, a fourth clock signal, and a first data signal, and is configured to drive the output node to a second logic level based on the first data signal during a period from the falling edge of the first clock signal to the rising edge of the fourth clock signal. A second synchronization circuit is configured to receive a second clock signal, a first clock signal, and a second data signal, and is configured to drive the output node to the second logic level based on the second data signal during a period from the falling edge of the second clock signal to the rising edge of the first clock signal. A third synchronization circuit is configured to receive the third clock signal, the second clock signal, and the third data signal, and is configured to drive the output node to the second logic level based on the third data signal during a period from the falling edge of the third clock signal to the rising edge of the second clock signal; and A fourth synchronization circuit is configured to receive the fourth clock signal, the third clock signal, and the fourth data signal, and is configured to drive the output node to the second logic level based on the fourth data signal during the period from the falling edge of the fourth clock signal to the rising edge of the third clock signal.

22. A data output circuit, comprising: The first serializer is configured to sequentially output multiple data signals as a first serial data signal based on a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal that have phase differences between each other corresponding to a unit phase amount. The second serializer is configured to sequentially output the plurality of data signals as a second serial data signal based on the first clock signal, the second clock signal, the third clock signal and the fourth clock signal; A pre-driver configured to generate a first output control signal based on the first serial data signal, and configured to generate a second output control signal based on the second serial data signal; as well as The main driver is configured to drive the data transmission line to a first logic level or a second logic level based on the first output control signal and the second output control signal.

23. The data output circuit according to claim 22, wherein, The first serializer includes: A first synchronization circuit is configured to generate a first serial data signal having a logic level corresponding to the first data signal based on the first clock signal and the fourth clock signal. A second synchronization circuit is configured to generate a first serial data signal having a logic level corresponding to the second data signal based on the second clock signal and the first clock signal; A third synchronization circuit is configured to generate a first serial data signal having a logic level corresponding to the third data signal based on the third clock signal and the second clock signal; and A fourth synchronization circuit is configured to generate a first serial data signal having a logic level corresponding to the fourth data signal based on the fourth clock signal and the third clock signal.

24. The data output circuit according to claim 23, wherein, The second serializer includes: A first synchronization circuit is configured to generate a second serial data signal having a logic level corresponding to the first data signal based on the first clock signal and the fourth clock signal. A second synchronization circuit is configured to generate a second serial data signal having a logic level corresponding to the second data signal based on the second clock signal and the first clock signal; A third synchronization circuit is configured to generate a second serial data signal having a logic level corresponding to the third data signal based on the third clock signal and the second clock signal; and A fourth synchronization circuit is configured to generate a second serial data signal having a logic level corresponding to the fourth data signal based on the fourth clock signal and the third clock signal.

25. The data output circuit according to claim 22, wherein, The pre-driver is configured to generate the first output control signal by mixing the second output control signal into the first output control signal, and is configured to generate the second output control signal by mixing the first output control signal into the second output control signal.

26. The data output circuit according to claim 22, wherein, The pre-driver includes: A first driver is configured to drive the first serial data signal in reverse phase to generate the first output control signal; A second driver is configured to drive the second serial data signal in reverse phase to generate the second output control signal; A third driver, configured to invert the second serial data signal to generate the first output control signal; and A fourth driver is configured to drive the first serial data signal in reverse phase to generate the second output control signal.

27. The data output circuit according to claim 22, wherein, The main drive includes: A pull-up driver configured to drive the data transmission line to the first logic level based on the first output control signal; and A pull-down driver configured to drive the data transmission line to the second logic level based on the second output control signal.

28. The data output circuit according to claim 22, wherein, The main drive includes: A first pull-up driver is configured to drive the data transmission line to the first logic level based on the first output control signal; A second pull-up driver is configured to drive the data transmission line to the first logic level based on the second output control signal; A first pull-down driver is configured to drive the data transmission line to the second logic level based on the first output control signal; and A second pull-down driver is configured to drive the data transmission line to the second logic level based on the second output control signal.

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