An auxiliary locking loop applied to a double-path sampling phase-locked loop

Abstract

The application discloses an auxiliary locking loop applied to a double-path sampling phase-locked loop, comprising a sampling phase detector, a low-pass filter, a transconductance charge pump, a unit gain operational amplifier, a capacitor, a voltage-controlled oscillator, a multi-mode programmable frequency divider and a two-phase non-overlapping clock generator. The auxiliary locking loop adds a unit gain operational amplifier module between the sampling phase detector and the capacitor, and shares the sampling phase detector and the voltage-controlled oscillator with the main path to form the fast auxiliary locking loop. The loop structure is simple, the area is saved, and the design complexity is reduced. The bandwidth of the auxiliary locking loop is related to the gain of the sampling phase detector, the pole brought by the sampling phase detector, the pole of the unit gain operational amplifier and the gain of the voltage-controlled oscillator. The gain of the sampling phase detector is larger than that of a traditional charge pump type frequency-locked loop, so the auxiliary locking loop also reduces the locking time compared with the traditional charge pump type frequency-locked loop, and realizes the fast locking of the sampling phase-locked loop.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of digital-analog hybrid integrated circuit design, and particularly relates to an auxiliary locking loop applied to a double-path sampling phase-locked loop. BACKGROUND

[0002] For a phase-locked loop system, performance indicators such as phase noise, spurs, power consumption, area, and locking time are crucial. The traditional charge pump phase-locked loop is limited due to the problem of sacrificing large power consumption and filter area for the improvement of phase noise and clock jitter performance, thereby promoting the demand for a better phase-locked loop architecture. The sub-sampling phase-locked loop and the injection-locked phase-locked loop proposed in the past also have the problems of too small phase detection range and spurs affected by harmonics, respectively. In recent years, the sampling phase-locked loop architecture is used to convert the phase difference between the input reference signal and the feedback signal of the phase-locked loop into a voltage for comparison by using a sampling phase detector (SPD) to improve the in-band gain, thereby optimizing the phase noise and clock jitter. In order to further reduce spurs, reduce noise, and improve loop stability, see Figure 1 , Figure 1 A low-jitter double-loop sampling phase-locked loop structure schematic diagram of a frequency-locked loop for CPPLL is provided in the prior art, and the zero point (ω Z ) in the double path is determined by the ratio of K VCO_I of the integral path to K VCO_P of the proportional path (generally different by an order of magnitude) and the ratio of Gm to CI. In the case where ω Z is determined, the charge and discharge speed is slow (Gm is of the order of tens of muS, and CI is of the order of hundreds of pf). Therefore, an auxiliary frequency-locked loop is needed, Figure 1 The phase-locked loop uses the auxiliary loop of the traditional charge pump phase-locked loop. However, due to the low DC gain, if the loop bandwidth is made large, that is, fast locking is achieved, a certain cost is paid, for example, the gain of the frequency-locked loop in the form of the traditional charge pump is increased, the current is increased, and the power consumption of the circuit is increased.

[0003] Therefore, how to improve the fast locking of the sampling phase-locked loop has become a technical problem to be solved at present. SUMMARY

[0004] In order to solve the above problems in the prior art, the present application provides an auxiliary locking loop applied to a double-path sampling phase-locked loop. The technical problem to be solved by the present application is realized by the following technical scheme:

[0005] The auxiliary locking loop applied to the double-path sampling phase-locked loop provided by the embodiment of the present application comprises a sampling phase detector, a low-pass filter, a transconductance charge pump, a unit gain operational amplifier, a capacitor, a voltage-controlled oscillator, a multi-mode programmable frequency divider, and a two-phase non-overlapping clock generator, wherein

[0006] The sampling input terminal of the sampling phase detector receives a reference signal. The first clock input terminal is connected to the first output terminal of the two-phase non-overlapping clock generator, and the second clock input terminal is connected to the second output terminal of the two-phase non-overlapping clock generator. The sampling output terminal is connected to the non-inverting input terminal of the unity-gain operational amplifier and the input terminal of the low-pass filter. The output terminal of the low-pass filter is connected to the input terminal of the transconductance charge pump and the first control voltage input terminal of the voltage-controlled oscillator. The output terminal of the unity-gain operational amplifier is connected to the input terminal of the capacitor, the inverting input terminal of the unity-gain operational amplifier, and the output terminal of the transconductance charge pump. The output terminal of the capacitor is connected to the second control voltage input terminal of the voltage-controlled oscillator. The output terminal of the voltage-controlled oscillator is connected to the input terminal of the multi-mode programmable frequency divider. The output terminal of the multi-mode programmable frequency divider is connected to the input terminal of the two-phase non-overlapping clock generator.

[0007] The sampling phase detector, low-pass filter, voltage-controlled oscillator, multi-mode programmable frequency divider, and two-phase non-overlapping clock generator form a proportional path;

[0008] The sampling phase detector, low-pass filter, transconductance charge pump, capacitor, voltage-controlled oscillator, multi-mode programmable frequency divider, and two-phase non-overlapping clock generator form an integration path;

[0009] The sampling phase detector, unity-gain operational amplifier, capacitor, voltage-controlled oscillator, multi-mode programmable frequency divider, and two-phase non-overlapping clock generator form an auxiliary frequency locking path.

[0010] In one embodiment of the present invention, the auxiliary locking loop is a type I phase-locked loop.

[0011] In one embodiment of the present invention, the sampling phase detector includes a first switch, a second switch, a first sampling capacitor, and a second sampling capacitor, wherein,

[0012] The reference signal is input at one end of the first switch, and the other end is connected to one end of the first sampling capacitor and one end of the second switch. The other end of the second switch is connected to one end of the second sampling capacitor, and the other ends of the first sampling capacitor and the second sampling capacitor are connected to the ground terminal.

[0013] In one embodiment of the present invention, the locking speed of the auxiliary locking loop is directly proportional to the loop bandwidth of the auxiliary locking loop.

[0014] In one embodiment of the present invention, the DC gain of the sampling phase detector is:

[0015]

[0016] Where ΔV represents the output voltage change, Δφ DIV K represents the phase of the input change. slope The slope of the output voltage variation is represented by ω, Δt represents the time of the minute change, and ω represents the slope of the voltage variation. DIV f represents the frequency of the frequency divider in radians. DIV Indicates the frequency of the frequency divider;

[0017] The loop gain of the fast-assisted locking loop is:

[0018]

[0019] Where A(s) represents the forward loop gain, Let s denote the poles of a unity-gain op-amp, s denote the operator in the S-domain, and ω denote the poles of the op-amp. pSPD Indicates the poles of the sampling phase detector. Depend on The calculations yielded the following results: C S C H V is the sampling capacitor in the SPD. smp Vslope represents the voltage output by the SPD, Vslope represents the sampled voltage after processing the input reference clock, and T represents the period of the reference frequency.

[0020] If the loop gain of the fast assisted locking loop is set to 1, then the loop bandwidth of the fast assisted locking loop is:

[0021]

[0022] Among them, K SPD K represents the DC gain of the sampling phase detector. VCO_I This represents the gain of the voltage-controlled oscillator in the integral path, and N represents the division ratio of the multi-mode programmable frequency divider.

[0023] In one embodiment of the present invention, the low-pass filter includes a resistor and a capacitor, wherein,

[0024] One end of the resistor is connected to the output terminal of the sampling phase detector, and the other end of the resistor is connected to one end of the capacitor, the input terminal of the transconductance charge pump, and the first control voltage input terminal of the voltage-controlled oscillator.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] The auxiliary locking loop of this invention, applied to a dual-path sampling phase-locked loop, adds a unity-gain operational amplifier module between the sampling phase detector and the capacitor, and shares the sampling phase detector and voltage-controlled oscillator with the main loop. This simplifies the loop structure, saves area, and reduces design complexity. The fast auxiliary locking loop of this invention also addresses the bandwidth, sampling phase detector gain, resulting poles, unity-gain operational amplifier poles, and voltage-controlled oscillator gain K. VCO The sampling phase detector gain is greater than that of a traditional charge pump type frequency lock loop. Therefore, compared with the traditional charge pump type frequency lock loop, the fast auxiliary locking loop of the present invention also reduces the locking time and realizes fast locking of the sampling phase lock loop. Attached Figure Description

[0027] Figure 1 A schematic diagram of a low-jitter dual-loop sampling phase-locked loop structure with a frequency-locked loop of CPPLL provided for the prior art;

[0028] Figure 2 This is a schematic diagram of an auxiliary locking loop applied to a dual-path sampling phase-locked loop, provided by an embodiment of the present invention.

[0029] Figure 3 A schematic diagram of the auxiliary locking loop provided in this example;

[0030] Figure 4 This is a schematic diagram of the sampling phase detector provided in an embodiment of the present invention. Detailed Implementation

[0031] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0032] Example 1

[0033] Please see Figure 2 , Figure 2 This is a schematic diagram of an auxiliary locking loop applied to a dual-path sampling phase-locked loop, provided in an embodiment of the present invention.

[0034] The auxiliary locking loop applied to the dual-path sampling phase-locked loop includes: a sampling phase detector (SPD), a low-pass filter (LPF), a transconductance charge pump (Gm), a capacitor (CI), a voltage-controlled oscillator (VCO), a multi-mode programmable divider (MMDIV), a two-phase non-overlapping clock generator (NCG), and a unity-gain operational amplifier (OA).

[0035] The sampling input terminal of the sampling phase detector (SPD) receives the reference signal F. refThe first clock input is connected to the first output of the two-phase non-overlapping clock generator NCG, and the second clock input is connected to the second output of the two-phase non-overlapping clock generator NCG. The sampling output is connected to the non-inverting input of the unity-gain operational amplifier OA and the input of the low-pass filter LPF. The output of the low-pass filter LPF is connected to the input of the transconductance charge pump Gm and the first control voltage input VP of the voltage-controlled oscillator VCO. The output of the unity-gain operational amplifier OA is connected to the input of the capacitor CI, the inverting input of the unity-gain operational amplifier OA, and the output of the transconductance charge pump Gm. The output of the capacitor CI is connected to the second control voltage input VI of the voltage-controlled oscillator VCO. The output of the voltage-controlled oscillator VCO is connected to the input of the multi-mode programmable divider MMDIV. The output of the multi-mode programmable divider MMDIV is connected to the input of the two-phase non-overlapping clock generator NCG.

[0036] Furthermore, the sampling phase detector (SPD), low-pass filter (LPF), voltage-controlled oscillator (VCO), multi-mode programmable frequency divider (MMDIV), and two-phase non-overlapping clock generator (NCG) form a proportional path. That is, the sampling input terminal of the SPD is connected to the input reference signal F. ref The two clock inputs are connected to the outputs of the two NCGs, and the sampling output is connected to the input of the LPF. The output of the LPF is connected to the first control voltage input VP of the proportional path VCO. The output of the proportional path VCO is connected to the input of the MMDIV. The output of the MMDIV is connected to the input of the NCG. The outputs of the NCGs are connected to the clock inputs of the two identical SPDs.

[0037] The sampling phase detector (SPD), low-pass filter (LPF), transconductance charge pump (Gm), capacitor (CI), voltage-controlled oscillator (VCO), multi-mode programmable divider (MMDIV), and two-phase non-overlapping clock generator (NCG) form the integration path. That is, the sampling input terminal of the SPD is connected to the input reference signal F. ref The two clock inputs are connected to the outputs of the two NCGs. The sampling output of the SPD is connected to the input of the LPF. The output of the LPF is connected to the input of the Gm of the integration path. The output of Gm is connected to the input of CI. The output of CI is connected to the second control voltage input VI of the VCO of the integration path. The output of the VCO of the integration path is connected to the input of MMDIV. The output of MMDIV is connected to the input of the NCG. The two outputs of the NCG are each connected to the clock inputs of the two identical SPDs.

[0038] Please see Figure 3 , Figure 3This is a schematic diagram of the auxiliary locking loop provided in this example. The sampling phase detector (SPD), unity-gain operational amplifier (OA), capacitor (CI), voltage-controlled oscillator (VCO), multi-mode programmable frequency divider (MMDIV), and two-phase non-overlapping clock generator (NCG) form the auxiliary frequency locking path, i.e., the fast auxiliary locking loop. The sampling input terminal of the sampling phase detector (SPD) receives the reference signal F. ref The first clock input is connected to the first output of the two-phase non-overlapping clock generator NCG, and the second clock input is connected to the second output of the two-phase non-overlapping clock generator NCG. The sampling output is connected to the non-inverting input of the unity-gain operational amplifier OA. The output of the unity-gain operational amplifier OA is connected to the input of the capacitor CI and the inverting input of the unity-gain operational amplifier OA. The output of the capacitor CI is connected to the second control voltage input VI of the voltage-controlled oscillator VCO. The output of the voltage-controlled oscillator VCO is connected to the input of the multi-mode programmable divider MMDIV. The output of the multi-mode programmable divider MMDIV is connected to the input of the two-phase non-overlapping clock generator NCG. The two outputs of the two-phase non-overlapping clock generator NCG are respectively connected to the two identical clock inputs of the sampling phase detector SPD.

[0039] The aforementioned fast-assisted locking loop can be applied to circuits requiring frequency-locking loops, such as dual-path sampling phase-locked loops and subsampling phase-locked loops. This embodiment does not impose further limitations. In one embodiment, when applied in a subsampling phase-locked loop, the capacitor CI can be replaced by a filter.

[0040] The working principle of the auxiliary locking loop is as follows: First, the two non-overlapping narrow pulse signals CK1 and CK2 are fed back, and the input reference signal F is sampled by the phase detector SPD. ref Perform sample-and-hold tracking to obtain the sampled output V. smp Voltage signal V smp The capacitor CI is charged by the unity-gain operational amplifier OA to obtain voltage VI. Voltage VI is used as the control voltage for the voltage-controlled oscillator (VCO) to control the output frequency of the VCO, resulting in the output signal F. OUT The output signal F of the voltage-controlled oscillator OUT The frequency is divided by the multi-mode programmable frequency divider (MMDIV) to obtain the frequency-divided output signal F, which serves as the feedback signal for the phase-locked loop. div Frequency division output signal F div After timing processing by the two-phase non-overlapping clock generator (NCG), two-phase non-overlapping narrow pulse signals CK1 and CK2 operating at the divided frequency are generated. The phase-locked loop (PLL) operates cyclically through negative feedback, following the above process, until the output voltage F of the voltage-controlled oscillator (VCO) is achieved. OUT and input reference signal F ref The frequencies are similar, thus completing the function of phase-locked loop frequency locking.

[0041] Furthermore, the working principle of the above-mentioned auxiliary locking loop when applied to a dual-path sampling phase-locked loop is as follows: First, the two non-overlapping narrow pulse signals CK1 and CK2 fed back are processed by the sampling phase detector SPD to compare the input reference signal F. ref Perform sample-and-hold tracking to obtain the sampled output V. smp Voltage signal V smp After passing through the low-pass filter (LPF), there are two paths to the voltage-controlled oscillator (VCO): a proportional path and an integral path. The proportional path only affects the bandwidth; during final loop locking, the VCO will be clamped by the transconductance charge pump (Gm). p Voltage stabilized at V cm The other path is the integration path. The voltage signal after passing through the low-pass filter LPF controls the transconductance charge pump Gm to charge CI, resulting in voltage VI. Voltage VI is used as the control voltage of the voltage-controlled oscillator (VCO) to control the output frequency of the VCO, thus obtaining the output signal F. OUT The output signal F of the voltage-controlled oscillator (VCO) OUT The frequency is divided by the multi-mode programmable frequency divider (MMDIV) to obtain the frequency-divided output signal F, which serves as the feedback signal for the phase-locked loop. div Frequency division output signal F div After timing processing by the two-phase non-overlapping clock generator (NCG), two-phase non-overlapping narrow pulse signals CK1 and CK2 are generated. The phase-locked loop (PLL) operates cyclically through negative feedback, following the above process, until the output voltage F of the voltage-controlled oscillator (VCO) is achieved. OUT and input reference signal F ref The frequencies are equal, thus completing the phase-locked loop phase-locking function.

[0042] In one specific embodiment, the auxiliary locking loop is a type I phase-locked loop with a simple loop structure. It shares the sampling phase detector (SPD) and voltage-controlled oscillator (VCO) with the main loop. It only requires adding a unity-gain operational OA module between the sampling phase detector (SPD) and the capacitor CI in the integration path to form a fast frequency-locked loop (FLL).

[0043] Please see Figure 4 , Figure 4 This is a schematic diagram of the sampling phase detector (SPD) provided in an embodiment of the present invention. The sampling phase detector (SPD) includes a first switch S1, a second switch S2, a first sampling capacitor Cs, and a second sampling capacitor C. H .

[0044] Among them, one end of the first switch S1 is input with a reference signal F. ref The other end is connected to one end of the first sampling capacitor Cs and one end of the second switch S2, and the other end of the second switch S2 is connected to the second sampling capacitor Cs. H One end of the first sampling capacitor Cs, the other end of the second sampling capacitor CH The other end is connected to the ground terminal.

[0045] In one specific embodiment, the locking speed of the fast-assisted locking loop is directly proportional to the loop bandwidth of the fast-assisted locking loop.

[0046] Specifically, the calculation process for the loop bandwidth of the fast-assisted locking loop is as follows:

[0047] The DC gain of the sampling phase detector (SPD) is:

[0048]

[0049] Where ΔV represents the output voltage change, Δφ DIV K represents the phase of the input change. slope The slope of the output voltage variation is represented by ω, Δt represents the time of the minute change, and ω represents the slope of the voltage variation. DIV f represents the frequency of the frequency divider in radians. DIV This indicates the frequency of the frequency divider.

[0050] The transfer function of the sampling switch is calculated using charge conservation, and the Z-domain is transformed into the S-domain to obtain the pole correlation calculation formula for the sampling phase detector (SPD):

[0051]

[0052] Among them, C S C H V is the sampling capacitor in the SPD. smp Vslope represents the voltage output by the SPD, and Vslope represents the sampled voltage after processing the input reference clock. Figure 3 Vs, where T represents the period of the reference frequency and s represents the operator in the S domain;

[0053]

[0054] Among them, C S C H This refers to the sampling capacitor in the SPD.

[0055] Finally, ignoring the high-frequency poles, the forward loop gain is:

[0056]

[0057] in, This represents the pole of a unity-gain op-amp. The poles of the sampling phase detector are represented by equation (2), which are obtained through further processing. Thus obtain

[0058] The loop gain of the fast-assisted locking loop is:

[0059]

[0060] Where N represents the division ratio of the multi-mode programmable frequency divider.

[0061] If the loop gain of the fast assisted locking loop is set to 1, then the loop bandwidth of the fast assisted locking loop is:

[0062]

[0063] Among them, K SPD K represents the DC gain of the sampling phase detector. VCO_I This represents the gain of the voltage-controlled oscillator in the integral path.

[0064] The bandwidth of a traditional charge pump lock loop is:

[0065]

[0066] Comparing formulas (6) and (7), it can be seen that the fast auxiliary locking loop in this embodiment is more conducive to the fast locking of the loop.

[0067] It is important to note that when designing a fast assist-lock loop, attention must be paid to the drive capability of the unity-gain op-amp OA and the issue of zeros and poles. Specifically, regarding the drive capability of the OA, the greater the drive capability of the unity-gain op-amp OA, the faster the VI is charged. The drive capability of the OA should be determined based on actual requirements during the design process. Regarding the zeros and poles of the OA, their influence on the loop should be avoided, thereby preventing any impact on the bandwidth of the fast assist-lock loop.

[0068] In one specific embodiment, the low-pass filter LPF includes a resistor R0 and a capacitor C0, wherein one end of the resistor R0 is connected to the output terminal of the sampling phase detector SPD, and the other end of the resistor R0 is connected to one end of the capacitor C0 and the input terminal of the transconductance charge pump Gm and the second control voltage input terminal VP of the voltage-controlled oscillator VCO.

[0069] The fast auxiliary locking loop in this embodiment adds a unity-gain operational amplifier module between the sampling phase detector and the capacitor, and shares the sampling phase detector and voltage-controlled oscillator with the main loop. The loop structure is simple, saves area, and reduces design complexity.

[0070] In this embodiment, the bandwidth of the fast assisted locking loop, the gain of the sampling phase detector and the resulting poles, the poles of the unity-gain op-amp, and the gain K of the voltage-controlled oscillator are discussed. VCO_IThe gain of the sampling phase detector is several orders of magnitude greater than that of the traditional charge pump type frequency-locked loop (PFD-CP). Therefore, compared with the traditional charge pump type frequency-locked loop, the fast frequency-locked loop of the present invention reduces the locking time. Thus, the auxiliary locking loop applied to the dual-path sampling phase-locked loop achieves fast locking of the dual-path sampling phase-locked loop with low spurious noise and low jitter.

[0071] In addition to rapidly reducing the loop locking time, the fast auxiliary locking loop in this embodiment can be turned off after locking, without affecting the normal operation of the loop and avoiding unnecessary power consumption waste.

[0072] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An auxiliary locking loop applied to a dual-path sampling phase-locked loop, characterized in that, include: The circuit includes a sampling phase detector (SPD), a low-pass filter (LPF), a transconductance charge pump (Gm), a unity-gain operational amplifier (OA), a capacitor (CI), a voltage-controlled oscillator (VCO), a multi-mode programmable divider (MMDIV), and a two-phase non-overlapping clock generator (NCG). The sampling input terminal of the sampling phase detector (SPD) receives a reference signal (F). ref The first clock input is connected to the first output of the two-phase non-overlapping clock generator (NCG), the second clock input is connected to the second output of the two-phase non-overlapping clock generator (NCG), and the sampling output is connected to the non-inverting input of the unity-gain operational amplifier (OA) and the input of the low-pass filter (LPF). The output of the low-pass filter (LPF) is connected to the input of the transconductance charge pump (Gm) and the first control voltage input (VP) of the voltage-controlled oscillator (VCO). The unity-gain operational amplifier (OA)... The output terminal of the capacitor (CI) is connected to the input terminal of the unity-gain operational amplifier (OA) and the output terminal of the transconductance charge pump (Gm); the output terminal of the capacitor (CI) is connected to the second control voltage input terminal (VI) of the voltage-controlled oscillator (VCO); the output terminal of the voltage-controlled oscillator (VCO) is connected to the input terminal of the multi-mode programmable divider (MMDIV); the output terminal of the multi-mode programmable divider (MMDIV) is connected to the input terminal of the two-phase non-overlapping clock generator (NCG); The sampling phase detector (SPD), low-pass filter (LPF), voltage-controlled oscillator (VCO), multi-mode programmable frequency divider (MMDIV), and two-phase non-overlapping clock generator (NCG) form a proportional path; The sampling phase detector (SPD), low-pass filter (LPF), transconductance charge pump (Gm), capacitor (CI), voltage-controlled oscillator (VCO), multimode programmable frequency divider (MMDIV), and two-phase non-overlapping clock generator (NCG) form the integration path. The sampling phase detector (SPD), unity gain operational amplifier (OA), capacitor (CI), voltage-controlled oscillator (VCO), multimode programmable frequency divider (MMDIV), and two-phase non-overlapping clock generator (NCG) form an auxiliary frequency locking path.

2. The auxiliary locking loop applied to a dual-path sampling phase-locked loop according to claim 1, characterized in that, The auxiliary locking loop is a type I phase-locked loop.

3. The auxiliary locking loop applied to a dual-path sampling phase-locked loop according to claim 1, characterized in that, The sampling phase detector (SPD) includes a first switch (S1), a second switch (S2), a first sampling capacitor (Cs), and a second sampling capacitor (C). H ),in, The reference signal (F) is input to one end of the first switch (S1). ref One end is connected to one end of the first sampling capacitor (Cs) and one end of the second switch (S2), and the other end of the second switch (S2) is connected to the second sampling capacitor (Cs). H One end of the first sampling capacitor (Cs), the other end of the second sampling capacitor (C) H The other end of the connector is connected to the grounding terminal.

4. The auxiliary locking loop applied to a dual-path sampling phase-locked loop according to claim 3, characterized in that, The locking speed of the auxiliary locking loop is directly proportional to the loop bandwidth of the auxiliary locking loop.

5. The auxiliary locking loop applied to a dual-path sampling phase-locked loop according to claim 4, characterized in that, The DC gain of the sampling phase detector is: Where ΔV represents the output voltage change, Δφ DIV K represents the phase of the input change. slope The slope of the output voltage variation is represented by ω, Δt represents the time of the minute change, and ω represents the slope of the voltage variation. DIV f represents the frequency of the frequency divider in radians. DIV Indicates the frequency of the frequency divider; The loop gain of the auxiliary locking loop is: Where A(s) represents the forward loop gain, ωP ＝A Let s denote the poles of a unity-gain op-amp, s denote the operator in the S-domain, and ω denote the poles of the op-amp. p＝PD Indicates the poles of the sampling phase detector. Depend on The calculations yielded the following results: C S C H V is the sampling capacitor in the SPD. smp Vslope represents the voltage output by the SPD, Vslope represents the sampled voltage after processing the input reference clock, and T represents the period of the reference frequency. If the loop gain of the fast assisted locking loop is set to 1, then the loop bandwidth of the fast assisted locking loop is: Among them, K SPD K represents the DC gain of the sampling phase detector. VCO_I This represents the gain of the voltage-controlled oscillator in the integral path, and N represents the division ratio of the multi-mode programmable frequency divider.

6. The auxiliary locking loop applied to a dual-path sampling phase-locked loop according to claim 1, characterized in that, The low-pass filter (LPF) includes a resistor (R0) and a capacitor (C0), wherein, One end of the resistor (R0) is connected to the output of the sampling phase detector (SPD), and the other end of the resistor (R0) is connected to one end of the capacitor (C0), the input of the transconductance charge pump (Gm), and the first control voltage input (VP) of the voltage-controlled oscillator (VCO).

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