A differential sampling circuit, an analog-to-digital converter and a chip

Abstract

The embodiment of the present application provides a differential sampling circuit, an analog-to-digital converter and a chip. The differential sampling circuit comprises a first dynamic matching switch, a sampling capacitor, a switch assembly, an integration capacitor and an operational amplifier. The first end and the second end of the first switch assembly are connected with positive and negative voltage signal ends respectively, the third end and the fourth end of the first switch assembly are connected with the first end and the second end of the first dynamic matching switch respectively, the third end and the fourth end of the first dynamic matching switch are connected with the first pole plates of two sampling capacitors respectively, the second pole plates of the two sampling capacitors are connected with the first end and the second end of the second switch assembly respectively, the third end of the second switch assembly is connected with a common-mode voltage, the fourth end and the fifth end of the second switch assembly are connected with the positive and negative input ends of the operational amplifier respectively, and the two integration capacitors are connected between the positive output input end and the negative output input end respectively. The differential sampling circuit can reduce the offset voltage in the circuit, thereby reducing the error of the circuit.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of signal sampling, and in particular to a differential sampling circuit, an analog-to-digital converter and a chip. BACKGROUND

[0002] The sampling circuit is included in the analog-to-digital converter. In the sampling stage of the sampling circuit, the input signal is conducted to the first plate of the sampling capacitor, and the second plate of the sampling capacitor is conducted to the common-mode voltage, so that the input signal can be sampled onto the sampling capacitor. In the integration stage of the sampling circuit, the input signal is disconnected from the first plate of the sampling capacitor, the second plate of the sampling capacitor is disconnected from the common-mode voltage, and the second plate of the sampling capacitor is conducted to the integration capacitor, so that the charge on the sampling capacitor can be transferred to the integration capacitor. Generally, the disconnection time of the common-mode voltage and the second plate of the sampling capacitor is earlier than the disconnection time of the input signal and the first plate of the sampling capacitor, so as to eliminate the error introduced by the charge injection on the switch connecting the common-mode voltage and the first plate of the sampling capacitor.

[0003] In the prior art, the sampling circuit can be set to a differential structure. When the two switches connected to the common-mode voltage are matched, the errors introduced by the two switches when turned off are matched, so that the final differential voltage for integration is not affected. However, due to non-ideal factors in semiconductor technology, the two switches connected to the common-mode voltage cannot be matched, so the errors introduced on the two sampling capacitors cannot be matched, resulting in errors in the circuit due to the offset voltage. SUMMARY

[0004] In view of the above problems, embodiments of the present application provide a differential sampling circuit, an analog-to-digital converter and a chip, which can reduce the offset voltage in the circuit, thereby reducing the error of the circuit.

[0005] In a first aspect, embodiments of the present application provide a differential sampling circuit, comprising: a first dynamic matching switch, a first sampling capacitor, a second sampling capacitor, a first switch component, a second switch component, a first integration capacitor, a second integration capacitor and an operational amplifier.

[0006] The first end of the first switch assembly is electrically connected to a positive voltage signal end, the second end of the first switch assembly is electrically connected to a negative voltage signal end, the third end of the first switch assembly is electrically connected to the first end of the first dynamic matching switch, the fourth end of the first switch assembly is electrically connected to the second end of the first dynamic matching switch, the third end of the first dynamic matching switch is electrically connected to the first plate of the first sampling capacitor, the fourth end of the first dynamic matching switch is electrically connected to the first plate of the second sampling capacitor, the second plate of the first sampling capacitor is electrically connected to the first end of the second switch assembly, the second plate of the second sampling capacitor is electrically connected to the second end of the second switch assembly, and the third end of the second switch assembly is electrically connected to a common mode voltage signal; wherein the positive voltage signal end and the negative voltage signal end are respectively electrically connected to a group of differential signals.

[0007] The fourth end of the second switch assembly is electrically connected to the positive input end of the operational amplifier, the fifth end of the second switch assembly is electrically connected to the negative input end of the operational amplifier, the first integration capacitor is connected across the positive output end and the positive input end of the operational amplifier, and the second integration capacitor is connected across the negative output end and the negative input end of the operational amplifier.

[0008] The first dynamic matching switch is configured to control the first mismatched charge to flow into a first voltage signal end in a first state and to flow into a second voltage signal end in a second state; wherein the first voltage signal end is the positive voltage signal end and the second voltage signal end is the negative voltage signal, or the first voltage signal end is the negative voltage signal end and the second voltage signal end is the positive voltage signal end, and the first state and the second state appear alternately.

[0009] In some embodiments, the first dynamic matching switch is configured to turn on the negative voltage signal end and the first plate of the first sampling capacitor and turn on the positive voltage signal end and the first plate of the second sampling capacitor in the first state, and turn on the positive voltage signal end and the first plate of the first sampling capacitor and turn on the negative voltage signal end and the first plate of the second sampling capacitor in the second state.

[0010] In some embodiments, the first dynamic matching switch includes a first control switch, a second control switch, a third control switch, and a fourth control switch.

[0011] The first end of the first control switch and the first end of the second control switch are both electrically connected to the third end of the first switch assembly. The first end of the third control switch and the first end of the fourth control switch are both electrically connected to the fourth end of the first switch assembly. The second end of the first control switch and the second end of the third control switch are both electrically connected to the first plate of the first sampling capacitor. The second end of the second control switch and the second end of the fourth control switch are both electrically connected to the first plate of the second sampling capacitor.

[0012] In some embodiments, the control terminals of the first control switch and the fourth control switch are both electrically connected to a dynamic matching control signal, and the control terminals of the second control switch and the third control switch are both electrically connected to the inverted signal of the dynamic matching control signal.

[0013] In some embodiments, the period T1 of the control signal of the first switching component and the period T2 of the dynamic matching control signal satisfy: T2 / T1=2*n, where n is a positive integer.

[0014] In some embodiments, a second dynamic matching switch is also included;

[0015] The first terminal of the second dynamic matching switch is electrically connected to the fourth terminal of the second switch assembly, the second terminal of the second dynamic matching switch is electrically connected to the fifth terminal of the second switch assembly, the third terminal of the second dynamic matching switch is electrically connected to the positive input terminal, and the fourth terminal of the second dynamic matching switch is electrically connected to the negative input terminal.

[0016] The second dynamic matching switch is used to control the flow of the second mismatch charge into the first output terminal in the third state and to control the flow of the second mismatch charge into the second output terminal in the fourth state; wherein the first output terminal is the positive output terminal and the second output terminal is the negative output terminal, or the first output terminal is the negative output terminal and the second output terminal is the positive output terminal, and the third state and the fourth state alternate.

[0017] In some embodiments, the second dynamic matching switch is used to connect the first plate of the first integrating capacitor and the fifth terminal of the second switching assembly in the third state, and to connect the first plate of the second integrating capacitor and the fourth terminal of the second switching assembly; and to connect the first plate of the first integrating capacitor and the fourth terminal of the second switching assembly in the fourth state, and to connect the first plate of the second integrating capacitor and the fifth terminal of the second switching assembly.

[0018] In some embodiments, the second dynamic matching switch includes a fifth control switch, a sixth control switch, a seventh control switch, and an eighth control switch;

[0019] The first end of the fifth control switch and the first end of the sixth control switch are both electrically connected to the fourth end of the second switch assembly. The first end of the seventh control switch and the first end of the eighth control switch are both electrically connected to the fifth end of the second switch assembly. The second end of the fifth control switch and the second end of the seventh control switch are both electrically connected to the first plate of the first integrating capacitor. The second end of the sixth control switch and the second end of the eighth control switch are both electrically connected to the first plate of the second integrating capacitor.

[0020] In some embodiments, the first switching assembly includes a first switch, a second switch, a third switch, and a fourth switch;

[0021] The first terminal of the first switch and the first terminal of the fourth switch are both electrically connected to the positive voltage signal terminal. The first terminal of the second switch and the first terminal of the third switch are both electrically connected to the negative voltage signal terminal. The second terminal of the first switch and the second terminal of the second switch are both electrically connected to the first terminal of the first dynamic matching switch. The second terminal of the third switch and the second terminal of the fourth switch are both electrically connected to the second terminal of the first dynamic matching switch.

[0022] In some embodiments, the second switching assembly includes: a fifth switch, a sixth switch, a seventh switch, and an eighth switch;

[0023] The first terminal of the fifth switch and the first terminal of the sixth switch are both electrically connected to the common-mode voltage signal. The second terminal of the fifth switch is electrically connected to the second plate of the first sampling capacitor and the first terminal of the seventh switch. The second terminal of the sixth switch is electrically connected to the second plate of the second sampling capacitor and the first terminal of the eighth switch. The second terminal of the seventh switch is electrically connected to the first terminal of the second dynamic matching switch. The eighth switch is electrically connected to the second terminal of the second dynamic matching switch.

[0024] Secondly, embodiments of this application provide an analog-to-digital converter, including: any of the differential sampling circuits provided in the first aspect.

[0025] Thirdly, embodiments of this application provide a chip, including: any of the analog-to-digital converters provided in the first aspect.

[0026] In the technical solution of this application embodiment, the differential sampling circuit includes a first dynamic matching switch, a first sampling capacitor, a second sampling capacitor, a first switching assembly, a second switching assembly, a first integrating capacitor, a second integrating capacitor, and an operational amplifier. The first terminal of the first switching assembly is electrically connected to a positive voltage signal terminal, the second terminal of the first switching assembly is electrically connected to a negative voltage signal terminal, the third terminal of the first switching assembly is electrically connected to the first terminal of the first dynamic matching switch, the fourth terminal of the first switching assembly is electrically connected to the second terminal of the first dynamic matching switch, the third terminal of the first dynamic matching switch is electrically connected to the first plate of the first sampling capacitor, the fourth terminal of the first dynamic matching switch is electrically connected to the first plate of the second sampling capacitor, the second plate of the first sampling capacitor is electrically connected to the first terminal of the second switching assembly, the second plate of the second sampling capacitor is electrically connected to the second terminal of the second switching assembly, the third terminal of the second switching assembly is electrically connected to a common-mode voltage signal, the fourth terminal of the second switching assembly is electrically connected to the positive input terminal of the operational amplifier, and the fifth terminal of the second switching assembly is electrically connected to the operational amplifier. The negative input terminal of the operational amplifier is connected to the positive output terminal and the positive input terminal of the operational amplifier. The second integrating capacitor is connected to the negative input terminal of the negative output terminal of the operational amplifier. The positive voltage signal terminal and the negative voltage signal terminal are electrically connected to a set of differential signals. The first dynamic matching switch can control the first mismatch charge to flow into the first voltage signal terminal in the first state and control the first mismatch charge to flow into the second voltage signal terminal in the second state. The first voltage signal terminal is a positive voltage signal terminal and the second voltage signal terminal is a negative voltage signal terminal, or the first voltage signal terminal is a negative voltage signal terminal and the second voltage signal terminal is a positive voltage signal terminal. The first state and the second state alternate. In this way, the first mismatch charge is periodically distributed to the positive voltage signal terminal and the negative voltage signal terminal. During the integration process, the first mismatch charge stored in the positive voltage signal terminal can cancel each other out with the first mismatch charge stored in the negative voltage signal terminal. This can reduce the offset voltage caused by the mismatch charge in the circuit, thereby reducing the error introduced by the offset voltage.

[0027] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 A schematic diagram of a differential sampling circuit provided for the present technology;

[0030] Figure 2 This is a schematic diagram of a differential sampling circuit provided in an embodiment of this application;

[0031] Figure 3 for Figure 2 The diagram shown is a schematic of the differential sampling circuit in its first state.

[0032] Figure 4 for Figure 2 The diagram shown is a schematic of the differential sampling circuit in the second state.

[0033] Figure 5 This is a schematic diagram of another differential sampling circuit provided in an embodiment of this application;

[0034] Figure 6 A switching drive timing diagram of a differential sampling circuit is provided for the example of this application;

[0035] Figure 7 This is a schematic diagram of another differential sampling circuit provided in an embodiment of this application;

[0036] Figure 8 This is a schematic diagram of a switch provided in an embodiment of this application. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims and drawings of this application are intended to cover non-exclusive inclusion.

[0039] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0040] Furthermore, the terms "first," "second," etc., in the specification and claims of this application or in the aforementioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0041] In the description of this application, unless otherwise expressly specified and limited, the terms "connected" and "connected" shall be interpreted broadly. For example, "connected" or "connected" in circuit structure can refer not only to physical connection, but also to electrical connection or signal connection. For example, it can be a direct connection, i.e., a physical connection, or an indirect connection through at least one intermediate element, as long as the circuit is connected. It can also refer to the internal connection of two elements. Signal connection can refer not only to signal connection through circuit, but also to signal connection through a medium, such as radio waves.

[0042] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists, A and B exist simultaneously, or B exists. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0043] In the description of this application, unless otherwise stated, "multiple" and "at least two" mean two or more (including two), and similarly, "multiple groups" and "at least two groups" mean two or more (including two groups).

[0044] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0045] Figure 1 A schematic diagram of a differential sampling circuit provided for the prior art, such as... Figure 1 As shown, the differential sampling circuit includes: a first capacitor C1, a second capacitor C2, a first control component, a second control component, a third capacitor C3, a fourth capacitor C4, and an operational amplifier; wherein, the first control component includes four switches S1D, S2D, S3D, and S4D, and the second control component includes four switches S1, S2, S3, and S4.

[0046] Specifically, the positive voltage signal terminal SRP is electrically connected to the first terminals of switches S1D ​​and S4D, respectively; the negative voltage signal terminal SRN is electrically connected to the first terminals of switches S2D and S3D, respectively; the second terminal of switch S1D is electrically connected to the second terminal of switch S2D and the first plate of the first capacitor C1, respectively; the second terminal of switch S3D is electrically connected to the second terminal of switch S4D and the first plate of the second capacitor C2, respectively; the second plate of the first capacitor C1 is electrically connected to the first terminals of switches S1 and S2, respectively; the second plate of the second capacitor C2 is electrically connected to the first terminals of switches S3 and S4, respectively; the second terminals of switches S1 and S3 are both electrically connected to the common-mode voltage signal VCM; the second terminal of switch S2 is electrically connected to the first plate of the third capacitor C3 and the positive input terminal of the operational amplifier, respectively; the second terminal of switch S4 is electrically connected to the first plate of the fourth capacitor C4 and the negative input terminal of the operational amplifier, respectively; the second plate of the third capacitor C3 is electrically connected to the positive output terminal of the operational amplifier, and the second plate of the fourth capacitor C4 is connected to the negative output terminal of the operational amplifier.

[0047] For example, during the transition from the sampling phase to the integration phase, switches S1, S3, S1D, and S3D need to be opened, while switches S2, S4, S2D, and S4D need to be closed. Typically, the opening times of switches S1D ​​and S3D are later than those of switches S1 and S3. Figure 1 As shown. When switches S1 and S3 are open, channel charge flows out of the MOSFET, introducing error into the first capacitor C1 and the second capacitor C2; when switches S2 and S4 are closed, charge is absorbed from the outside to form a channel, introducing error into the third capacitor C3 and the fourth capacitor C4. Because... Figure 1 The sampling circuit shown uses a differential structure, so if the errors introduced by switches S1 and S3 are matched, or are exactly the same, it will not affect the final integrated differential voltage. However, due to non-ideal factors in semiconductor manufacturing, switches S1 and S3 cannot be perfectly matched, so the introduced errors cannot be perfectly matched either, thus affecting the final integrated differential voltage and causing the offset voltage to appear.

[0048] To address the aforementioned problems, this application proposes a differential sampling circuit, comprising: a first dynamic matching switch, a first sampling capacitor, a second sampling capacitor, a first switching assembly, a second switching assembly, a first integrating capacitor, a second integrating capacitor, and an operational amplifier. The first terminal of the first switching assembly is electrically connected to a positive voltage signal terminal, the second terminal of the first switching assembly is electrically connected to a negative voltage signal terminal, the third terminal of the first switching assembly is electrically connected to the first terminal of the first dynamic matching switch, the fourth terminal of the first switching assembly is electrically connected to the second terminal of the first dynamic matching switch, the third terminal of the first dynamic matching switch is electrically connected to the first plate of the first sampling capacitor, the fourth terminal of the first dynamic matching switch is electrically connected to the first plate of the second sampling capacitor, the second plate of the first sampling capacitor is electrically connected to the first terminal of the second switching assembly, the second plate of the second sampling capacitor is electrically connected to the second terminal of the second switching assembly, and the third terminal of the second switching assembly is electrically connected to a common-mode voltage signal. The positive and negative voltage signal terminals are each electrically connected to a set of differential signals. The first integration capacitor is electrically connected to the positive input terminal of the operational amplifier, and the fifth terminal of the second switching assembly is electrically connected to the negative input terminal of the operational amplifier. The first integrating capacitor is connected across the positive output terminal and the positive input terminal of the operational amplifier, and the second integrating capacitor is connected across the negative input terminal of the negative output terminal of the operational amplifier. The first dynamic matching switch can control the flow of the first mismatch charge into the first voltage signal terminal in the first state and control the flow of the first mismatch charge into the second voltage signal terminal in the second state. The first voltage signal terminal is a positive voltage signal terminal and the second voltage signal terminal is a negative voltage signal terminal, or the first voltage signal terminal is a negative voltage signal terminal and the second voltage signal terminal is a positive voltage signal terminal. The first state and the second state alternate. In this way, the first mismatch charge is periodically distributed to the positive voltage signal terminal and the negative voltage signal terminal, so that during the integration process, the first mismatch charge stored in the positive voltage signal terminal can cancel each other out with the first mismatch charge stored in the negative voltage signal terminal, thereby reducing the offset voltage caused by the mismatch charge in the circuit and thus reducing the error introduced by the offset voltage.

[0049] Figure 2 This is a schematic diagram of a differential sampling circuit provided in an embodiment of this application, as shown below. Figure 2 As shown, the differential sampling circuit 100 includes: a first dynamic matching switch 110, a first sampling capacitor C1p, a second sampling capacitor C1n, a first switching component 120, a second switching component 130, a first integrating capacitor C2p, a second integrating capacitor C2n, and an operational amplifier AMP.

[0050] In this configuration, the positive voltage signal terminal SRP is electrically connected to the first terminal of the first switching assembly 120, the negative voltage signal terminal SRN is electrically connected to the second terminal of the first switching assembly 120, the third terminal of the first switching assembly 120 is electrically connected to the first terminal of the first dynamic matching switch 110, the fourth terminal of the first switching assembly 120 is electrically connected to the second terminal of the first dynamic matching switch 110, the third terminal of the first dynamic matching switch 110 is electrically connected to the first plate of the first sampling capacitor C1p, the fourth terminal of the first dynamic matching switch 110 is electrically connected to the first plate of the second sampling capacitor C1n, the second plate of the first sampling capacitor C1p is electrically connected to the first terminal of the second switching assembly 130, the second plate of the second sampling capacitor C1n is electrically connected to the second terminal of the second switching assembly 130, and the third terminal of the second switching assembly 130 is electrically connected to the common-mode voltage signal VCM. The positive voltage signal terminal SRP is electrically connected to the positive voltage signal, and the negative voltage signal terminal SRN is electrically connected to the negative voltage signal. The positive and negative voltage signals form a differential signal.

[0051] The fourth terminal of the second switching component 130 is electrically connected to the positive input terminal of the operational amplifier AMP, the fifth terminal of the second switching component 130 is electrically connected to the negative input terminal of the operational amplifier AMP, the first integrating capacitor C2p is connected across the positive output terminal and the positive input terminal of the operational amplifier AMP, and the second integrating capacitor C2n is connected across the negative output terminal and the negative input terminal of the operational amplifier AMP.

[0052] The first dynamic matching switch 110 is used to control the first mismatch charge to flow into the first voltage signal terminal in the first state and to control the first mismatch charge to flow into the second voltage signal terminal in the second state; wherein the first voltage signal terminal is a positive voltage signal terminal SRP and the second voltage signal terminal is a negative voltage signal SRN, or the first voltage signal terminal is a negative voltage signal terminal SRN and the second voltage signal terminal is a positive voltage signal terminal SRP, and the first state and the second state alternate.

[0053] For example, when the differential sampling circuit 100 is in the sampling phase, it conducts the positive voltage signal terminal SRP and the first plate of the first sampling capacitor C1p, conducts the negative voltage signal terminal SRN and the first plate of the second sampling capacitor C1n, conducts the second plate of the first sampling capacitor C1p and the common-mode voltage signal VCM, and conducts the second plate of the second sampling capacitor C1n and the common-mode voltage signal VCM. At this time, the charge provided by the positive voltage signal terminal SRP is stored in the first sampling capacitor C1p, and the charge provided by the negative voltage signal terminal SRN is stored in the second sampling capacitor C1n. Thus, the sampled differential voltage VCM is... sample It can be represented as V sample =V SRP -V SRN , where V SRP The voltage input to the positive voltage signal input terminal SRP, VSRN The voltage input to the negative voltage signal input terminal SRN.

[0054] When the differential sampling circuit 100 is in the integration phase, the connection between the positive voltage signal terminal SRP and the first plate of the first sampling capacitor C1p is disconnected; the connection between the negative voltage signal terminal SRN and the first plate of the second sampling capacitor C1n is disconnected; the connection between the second plate of the first sampling capacitor C1p and the common-mode voltage signal VCM is disconnected; the connection between the second plate of the second sampling capacitor C1n and the common-mode voltage signal VCM is also disconnected. The negative voltage signal terminal SRN and the first plate of the first sampling capacitor C1p are connected; the positive voltage signal terminal SRP and the first plate of the second sampling capacitor C1n are connected; the second plate of the first sampling capacitor C1p and the positive input terminal of the operational amplifier AMP are connected; and the second plate of the second sampling capacitor C1n and the negative input terminal of the operational amplifier AMP are connected. At this time, the charge collected by the first sampling capacitor C1p during the sampling phase is transferred to the first integrating capacitor C2p, and the charge collected by the second sampling capacitor C2n during the sampling phase is transferred to the second integrating capacitor C2n.

[0055] During the transition from the sampling phase to the integration phase, the disconnection times of the first and third terminals of the first switch component 120, and the disconnection times of the second and fourth terminals of the first switch component 120, are later than the disconnection times of the first and third terminals of the second switch component 130, and the disconnection times of the second and third terminals of the second switch component 130. In other words, when the first and third terminals of the second switch component 130 are disconnected, and when the second and third terminals of the second switch component 130 are disconnected, the first and third terminals of the first switch component 120 are connected, and the second and fourth terminals of the first switch component 120 are connected. Since the first terminal of the first switching assembly 120 is electrically connected to the positive voltage signal terminal SRP, the third terminal of the first switching assembly 120 is electrically connected to the first terminal of the first dynamic matching switch 110, the second terminal of the first switching assembly 120 is electrically connected to the negative voltage signal terminal SRN, and the fourth terminal of the first switching assembly 120 is electrically connected to the second terminal of the first dynamic matching switch 110, the positive voltage signal terminal SRP is connected to the first terminal of the first dynamic matching switch 110, and the negative voltage signal terminal SRN is connected to the second terminal of the first dynamic matching switch 110.

[0056] One working cycle of the first dynamic matching switch 110 includes two states: a first state and a second state. The first dynamic matching switch 110 switches back and forth between the first state and the second state. In the first state, the first dynamic matching switch 110 can conduct its first and fourth terminals, and also conduct its second and third terminals. Figure 3 As shown, Figure 3 for Figure 2 The diagram shows the structure of the differential sampling circuit in the first state. Since the fourth terminal of the first dynamic matching switch 110 is electrically connected to the first plate of the second sampling capacitor C1n, and the third terminal of the first dynamic matching switch 110 is electrically connected to the first plate of the first sampling capacitor C1p, the positive voltage signal terminal SRP and the first plate of the second sampling capacitor C1n can be turned on, and the negative voltage signal terminal SRN and the first plate of the first sampling capacitor C1p can be turned on. In the second state, the first dynamic matching switch 110 can turn on its first and third terminals, and also turn on its second and fourth terminals, as shown below. Figure 4 As shown, Figure 4 for Figure 2 The diagram shows the structure of the differential sampling circuit in the second state. In this way, the positive voltage signal terminal SRP and the first plate of the first sampling capacitor C1p can be turned on, and the negative voltage signal terminal SRN and the first plate of the second sampling capacitor C1n can be turned on.

[0057] Thus, in a first state, the first dynamic matching switch 110 can conduct the negative voltage signal terminal SRN and the first plate of the first sampling capacitor C1p, and also conduct the positive voltage signal terminal SRP and the first plate of the second sampling capacitor C1n. In a second state, it can also conduct the positive voltage signal terminal SRP and the first plate of the first sampling capacitor C1p, and also conduct the negative voltage signal terminal SRN and the first plate of the second sampling capacitor C1n.

[0058] When the first terminal and the third terminal of the second switching assembly 130 are disconnected, and the second terminal and the third terminal of the second switching assembly 130 are also disconnected, the switch in the second switching assembly 130 electrically connected to the positive input side of the differential sampling circuit 100 generates injected charge. The switch in the second switching assembly 130 electrically connected to the negative input side of the differential sampling circuit 100 also generates injected charge. The amount of injected charge on the positive input side is different from the amount of injected charge on the negative input side. Thus, the injected charge after the two cancel each other out is the first mismatch charge. If the amount of injected charge on the positive input side is greater than the amount of injected charge on the negative input side, then the flow direction of the first mismatch charge is the same as the flow direction of the injected charge on the positive input side, and the amount of the first mismatch charge is equal to the amount of injected charge on the positive input side minus the amount of injected charge on the negative input side. In the first state, the first plate of the first sampling capacitor C1p is connected to the negative voltage signal terminal SRN, meaning the injected charge from the positive input side flows to the negative voltage signal terminal SRN, and therefore, the first mismatch charge flows into the negative voltage signal terminal SRN. In the second state, the first plate of the first sampling capacitor C1p is connected to the positive voltage signal terminal SRP, meaning the injected charge from the positive input side flows to the positive voltage signal terminal SRP, and therefore, the first mismatch charge flows into the positive voltage signal terminal SRP. Thus, the first dynamic matching switch 110 can alternately distribute the first mismatch charge generated by the second switching assembly 130 to the positive voltage signal terminal SRP and the negative voltage signal terminal SRN.

[0059] Considering the first mismatch charge, the differential voltage V sampled in the first state sample1 It can be represented as V sample1 =V SRP -(V SRN +Q1 / C), where Q1 is the charge of the first mismatch charge, and C is the capacitance of the first sampling capacitor C1p and the second sampling capacitor C1n; the differential voltage V sampled in the second state sample2 It can be represented as V sample2 =(V SRP +Q1 / C)-V SRN The integral result of the two stages is V. sample1 +V sample2 =2*(V SRP -V SRN Obviously, by using the first dynamic matching switch 110 to alternately distribute the first mismatch charge generated by the second switching component 130 to the positive voltage signal terminal SRP and the negative voltage signal terminal SRN, the neutralization of the entire sampling stage can be achieved, thereby reducing the offset voltage.

[0060] It should be noted that the embodiments in this application are only illustrated by the example that the amount of charge injected on the positive input side is greater than the amount of charge injected on the negative input side. In practical applications, the amount of charge injected on the positive input side may also be less than the amount of charge injected on the negative input side. In this case, the flow direction of the first mismatch charge is the same as the flow direction of the charge injected on the negative input side, and the amount of the first mismatch charge is equal to the amount of charge injected on the negative input side minus the amount of charge injected on the positive input side. In the first state, the first plate of the second sampling capacitor C1n and the positive voltage signal terminal SRP are connected, that is, the charge injected on the negative input side flows to the positive voltage signal terminal SRP. Therefore, the first mismatch charge flows into the positive voltage signal terminal SRP. In the second state, the first plate of the second sampling capacitor C1n and the negative voltage signal terminal SRN are connected, that is, the charge injected on the negative input side flows to the negative voltage signal terminal SRN. Therefore, the first mismatch charge flows into the negative voltage signal terminal SRN.

[0061] In this embodiment, the differential sampling circuit includes a first dynamic matching switch, a first sampling capacitor, a second sampling capacitor, a first switching assembly, a second switching assembly, a first integrating capacitor, a second integrating capacitor, and an operational amplifier. The first terminal of the first switching assembly is electrically connected to a positive voltage signal terminal, the second terminal of the first switching assembly is electrically connected to a negative voltage signal terminal, the third terminal of the first switching assembly is electrically connected to the first terminal of the first dynamic matching switch, the fourth terminal of the first switching assembly is electrically connected to the second terminal of the first dynamic matching switch, the third terminal of the first dynamic matching switch is electrically connected to the first plate of the first sampling capacitor, the fourth terminal of the first dynamic matching switch is electrically connected to the first plate of the second sampling capacitor, the second plate of the first sampling capacitor is electrically connected to the first terminal of the second switching assembly, the second plate of the second sampling capacitor is electrically connected to the second terminal of the second switching assembly, and the third terminal of the second switching assembly is electrically connected to a common-mode voltage signal. The positive and negative voltage signal terminals are each electrically connected to a set of differential signals. The fourth terminal of the second switching assembly is connected to the operational amplifier. The positive input terminal is electrically connected, and the fifth terminal of the second switching assembly is electrically connected to the negative input terminal of the operational amplifier. The first integrating capacitor is connected across the positive output terminal and the positive input terminal of the operational amplifier, and the second integrating capacitor is connected across the negative input terminal of the negative output terminal of the operational amplifier. The first dynamic matching switch can control the first mismatch charge to flow into the first voltage signal terminal in the first state and control the first mismatch charge to flow into the second voltage signal terminal in the second state. The first voltage signal terminal is a positive voltage signal terminal and the second voltage signal terminal is a negative voltage signal terminal, or the first voltage signal terminal is a negative voltage signal terminal and the second voltage signal terminal is a positive voltage signal terminal. The first state and the second state alternate. In this way, the first mismatch charge is periodically distributed to the positive voltage signal terminal and the negative voltage signal terminal, so that during the integration process, the first mismatch charge stored in the positive voltage signal terminal can cancel each other out with the first mismatch charge stored in the negative voltage signal terminal, thereby reducing the offset voltage caused by the mismatch charge in the circuit and thus reducing the error introduced by the offset voltage.

[0062] In some embodiments, Figure 5 This is a schematic diagram of another differential sampling circuit provided in an embodiment of this application. Figure 5 for Figure 2 Based on the embodiment shown, the first dynamic matching switch 110 includes a first control switch K1, a second control switch K2, a third control switch K3, and a fourth control switch K4.

[0063] Specifically, the first end of the first control switch K1 and the first end of the second control switch K2 are both electrically connected to the third end of the first switch assembly 120; the first end of the third control switch K3 and the first end of the fourth control switch K4 are both electrically connected to the fourth end of the first switch assembly 120; the second end of the first control switch K1 and the second end of the third control switch K3 are both electrically connected to the first plate of the first sampling capacitor C1p; and the second end of the second control switch K2 and the second end of the fourth control switch K4 are both electrically connected to the first plate of the second sampling capacitor C1n.

[0064] For example, in the first state, the third control switch K3 is turned on. Since the first terminal of the third control switch K3 is electrically connected to the fourth terminal of the first switch assembly 120, and the second terminal of the third control switch K3 is electrically connected to the first plate of the first sampling capacitor C1p, the fourth terminal of the first switch assembly 120 is connected to the first plate of the first sampling capacitor C1p. That is, the negative voltage signal terminal SRN and the first plate of the first sampling capacitor C1p can be connected. Furthermore, the second control switch K2 is turned on. Since the first terminal of the second control switch K2 is electrically connected to the third terminal of the first switch assembly 120, and the second terminal of the second control switch K2 is electrically connected to the first plate of the second sampling capacitor C1n, the third terminal of the first switch assembly 120 is connected to the first plate of the second sampling capacitor C1n. That is, the positive voltage signal terminal SRP and the first plate of the second sampling capacitor C1n can be connected.

[0065] In the second state, the first control switch K1 is turned on. Since the first terminal of the first control switch K1 is electrically connected to the third terminal of the first switch assembly 120, and the second terminal of the first control switch K1 is electrically connected to the first plate of the first sampling capacitor C1p, the first plate of the first sampling capacitor C1p is connected to the third terminal of the first switch assembly 120. That is, the positive voltage signal terminal SRP and the first plate of the first sampling capacitor C1p can be connected. Furthermore, the fourth control switch K4 is turned on. Since the first terminal of the fourth control switch K4 is electrically connected to the fourth terminal of the first switch assembly 120, and the second terminal of the fourth control switch K4 is electrically connected to the first plate of the second sampling capacitor C1n, the first plate of the second sampling capacitor C1n is connected to the fourth terminal of the first switch assembly 120. That is, the negative voltage signal terminal SRN and the first plate of the second sampling capacitor C1n can be connected.

[0066] In some embodiments, the control terminals of the first control switch K1 and the fourth control switch K4 are both electrically connected to the dynamic matching control signal DEM, and the control terminals of the second control switch K2 and the third control switch K3 are both electrically connected to the inverted signal DEMZ of the dynamic matching control signal DEM.

[0067] For example, if the dynamic matching control signal DEM is a high-level signal, then the inverted signal DEMZ is a low-level signal. The first control switch K1 and the fourth control switch K4 are in the ON state under the influence of the high-level signal, while the second control switch K2 and the third control switch K3 are in the OFF state under the influence of the low-level signal. In this case, the first dynamic matching switch 110 is in the second state. If the dynamic matching control signal DEM is a low-level signal, then the inverted signal DEMZ is a high-level signal. The first control switch K1 and the fourth control switch K4 are in the OFF state under the influence of the low-level signal, while the second control switch K2 and the third control switch K3 are in the ON state under the influence of the high-level signal. In this case, the first dynamic matching switch 110 is in the first state.

[0068] In this embodiment, the control terminals of the first control switch and the fourth control switch are both electrically connected to the dynamic matching control signal, and the control terminals of the second control switch and the third control switch are both electrically connected to the inverted signal of the dynamic matching control signal. Thus, the dynamic matching control signal can be directly inverted and input to the control terminals of the second control switch and the third control switch. Therefore, the state of the first dynamic matching switch can be controlled based on the dynamic matching control signal, which is simple to implement and can reduce control errors.

[0069] In some embodiments, Figure 6 A switching drive timing diagram of a differential sampling circuit provided for this application example is shown below. Figure 6 As shown, the period T1 of the control signal DEM' of the first switching component 120 and the period T2 of the dynamic matching control signal DEM satisfy: T2 / T1=2*n, where n is a positive integer.

[0070] For example, such as Figure 6 As shown, the period of the control signal DEM' of the first switching component 120 is T1, the period of the dynamic matching control signal DEM is T2, and T2 / T1=2*3, that is, the frequency of the dynamic matching control signal DEM is 1 / 2*3 of the frequency of the control signal DEM'.

[0071] If the sampling results in the first state will be negatively affected by compensation, then the sampling results in the second state will be positively affected by compensation. Since the first state lasts for four sampling periods and the second state also lasts for the same four sampling periods, the effects of positive and negative compensation cancel each other out.

[0072] It should be noted that, Figure 6 This example only demonstrates that the period T2 of the dynamic matching control signal DEM is 2*3 times the period T1 of the control signal DEM'. In practical applications, the period T2 of the dynamic matching control signal DEM can be 2*n times the period T1 of the control signal DEM', where n is a positive integer.

[0073] In some embodiments, see also [link to previous document]. Figures 2-5 The differential sampling circuit 100 further includes a second dynamic matching switch 140, wherein the first end of the second dynamic matching switch 140 is electrically connected to the fourth end of the second switching assembly 130, the second end of the second dynamic matching switch 140 is electrically connected to the fifth end of the second switching assembly 130, the third end of the second dynamic matching switch 140 is electrically connected to the positive input terminal, and the fourth end of the second dynamic matching switch 140 is electrically connected to the negative input terminal.

[0074] The second dynamic matching switch 140 is used to control the flow of the second mismatch charge into the first output terminal in the third state and to control the flow of the second mismatch charge into the second output terminal in the fourth state; wherein the first output terminal is a positive output terminal and the second output terminal is a negative output terminal, or the first output terminal is a negative output terminal and the second output terminal is a positive output terminal, and the third and fourth states alternate.

[0075] For example, one operating cycle of the second dynamic matching switch 140 includes two states, namely a third state and a fourth state, thus the second dynamic matching switch 140 switches back and forth between the third state and the fourth state. In the third state, the second dynamic matching switch 140 can conduct both its first and fourth terminals, and also conduct both its second and third terminals. Figure 3 As shown. Since the first terminal of the second dynamic matching switch 140 is electrically connected to the fourth terminal of the second switching assembly 130, the second terminal of the second dynamic matching switch 140 is electrically connected to the fifth terminal of the second switching assembly 130, the third terminal of the second dynamic matching switch 140 is electrically connected to the first plate of the first integrating capacitor C2p, and the fourth terminal of the second dynamic matching switch 140 is electrically connected to the first plate of the second integrating capacitor C2n, the fourth terminal of the second switching assembly 130 and the first plate of the second integrating capacitor C2n can be connected, as can the fifth terminal of the second switching assembly 130 and the first plate of the first integrating capacitor C2p.

[0076] In the fourth state, the second dynamic matching switch 140 can connect its first and third terminals, and also connect its second and fourth terminals, as shown below. Figure 4As shown. Thus, the fourth terminal of the second switching assembly 130 and the first plate of the first integrating capacitor C2p can be connected, as can the fifth terminal of the second switching assembly 130 and the first plate of the second integrating capacitor C2n. Therefore, the second dynamic matching switch 140 can, in the third state, connect the first plate of the first integrating capacitor C2p and the fifth terminal of the second switching assembly 130, and also connect the second integrating capacitor C2n and the fourth terminal of the second switching assembly 130; in the fourth state, it connects the first plate of the first integrating capacitor C2p and the fourth terminal of the second dynamic matching switch 140, and also connects the first plate of the second integrating capacitor C2n and the fifth terminal of the second dynamic matching switch 140.

[0077] Furthermore, the first plate of the first integrating capacitor C2p is electrically connected to the positive output terminal of the operational amplifier AMP, and the second plate of the second integrating capacitor C2n is electrically connected to the negative output terminal of the operational amplifier AMP. Thus, in the third state, the fourth terminal of the second switching component 130 is connected to the negative output terminal of the operational amplifier AMP through the second integrating capacitor C2n, and the fifth terminal of the second switching component 130 is connected to the positive output terminal of the operational amplifier AMP through the first integrating capacitor C2p; in the fourth state, the fourth terminal of the second switching component 130 is connected to the positive output terminal of the operational amplifier AMP through the first integrating capacitor C2p, and the fifth terminal of the second switching component 130 is connected to the negative output terminal of the operational amplifier AMP through the second integrating capacitor C2n.

[0078] After disconnecting the connection between the first terminal and the third terminal of the second switching component 130, and disconnecting the connection between the second terminal and the third terminal of the second switching component 130, the first terminal and the fourth terminal of the second switching component 130 are connected, and the second terminal and the fifth terminal of the second switching component 130 are connected. At this time, the second switching component 130 absorbs charge from the positive input side and the negative input side of the differential sampling circuit 100, respectively. The amount of charge absorbed by the positive input side is different from the amount of charge absorbed by the negative input side. Thus, the absorbed charge after the two cancel each other out is the second mismatch charge.

[0079] For example, if the amount of charge absorbed on the positive input side is less than the amount of charge absorbed on the negative input side, then the flow direction of the second mismatch charge is the same as the flow direction of the charge absorbed on the negative input side, and the amount of the second mismatch charge is equal to the amount of charge absorbed on the negative input side minus the amount of charge absorbed on the positive input side. In the third state, the fifth terminal of the second switching component 130 is connected to the positive output terminal of the operational amplifier AMP, that is, the charge absorbed on the negative input side flows to the positive output terminal of the operational amplifier AMP, therefore, the second mismatch charge flows into the positive output terminal of the operational amplifier AMP. In the fourth state, the fifth terminal of the second switching component 130 is connected to the negative output terminal of the operational amplifier AMP, that is, the charge absorbed on the negative input side flows to the negative output terminal of the operational amplifier AMP, therefore, the second mismatch charge flows into the negative output terminal of the operational amplifier AMP.

[0080] If the absorbed charge on the positive input side is greater than the absorbed charge on the negative input side, then the flow direction of the second mismatch charge is the same as the flow direction of the absorbed charge on the positive input side, and the amount of the second mismatch charge is equal to the absorbed charge on the positive input side minus the absorbed charge on the negative input side. In the third state, the fourth terminal of the second switching component 130 is connected to the negative output terminal of the operational amplifier AMP, meaning the absorbed charge on the positive input side flows to the negative output terminal of the operational amplifier AMP. Therefore, the second mismatch charge flows into the negative output terminal of the operational amplifier AMP. In the fourth state, the fourth terminal of the second switching component 130 is connected to the positive output terminal of the operational amplifier AMP, meaning the absorbed charge on the positive input side flows to the positive output terminal of the operational amplifier AMP. Therefore, the second mismatch charge flows into the positive output terminal of the operational amplifier AMP.

[0081] In summary, the second dynamic matching switch 140 can alternately distribute the second mismatch charge generated by the second switching component 130 to the positive output terminal and the negative output terminal of the operational amplifier AMP. In this way, during the integration process, the integration effect of the absorbed charge will cancel each other out because it is distributed to the positive output terminal and the negative output terminal of the operational amplifier AMP cycle by cycle.

[0082] In this implementation, the differential sampling circuit further includes a second dynamic matching switch. The first terminal of the second dynamic matching switch is electrically connected to the fourth terminal of the second switching assembly, the second terminal of the second dynamic matching switch is electrically connected to the fifth terminal of the second switching assembly, the third terminal of the second dynamic matching switch is electrically connected to the positive input terminal, and the fourth terminal of the second dynamic matching switch is electrically connected to the negative input terminal. The second dynamic matching switch can control the flow of the second mismatch charge into the first output terminal in the third state and into the second output terminal in the fourth state. The first output terminal is either a positive output terminal and the second output terminal is a negative output terminal, or vice versa. The third and fourth states alternate. Thus, the second mismatch charge is periodically distributed to the positive and negative output terminals of the operational amplifier, allowing the second mismatch charge stored at the positive output terminal to cancel out the second mismatch charge stored at the negative output terminal during integration. This further reduces the offset voltage caused by the mismatch charge in the circuit, thereby further reducing the error introduced by the offset voltage.

[0083] In some embodiments, see also [link to previous document]. Figure 5 As shown, the second dynamic matching switch 140 includes a fifth control switch K5, a sixth control switch K6, a seventh control switch K7, and an eighth control switch K8.

[0084] Specifically, the first terminals of the fifth control switch K5 and the sixth control switch K6 are both electrically connected to the fourth terminal of the second switch assembly 130; the first terminals of the seventh control switch K7 and the eighth control switch K8 are both electrically connected to the fifth terminal of the second switch assembly 130; the second terminals of the fifth control switch K5 and the seventh control switch K7 are both electrically connected to the first plate of the first integrating capacitor C2p; and the second terminals of the sixth control switch K6 and the eighth control switch K8 are both electrically connected to the first plate of the second integrating capacitor C2n.

[0085] For example, in the third state, the seventh control switch K7 is turned on. Since the first terminal of the seventh control switch K7 is electrically connected to the fifth terminal of the second switch assembly 130, and the second terminal of the seventh control switch K7 is electrically connected to the first plate of the first integrating capacitor C2p, the fifth terminal of the second switch assembly 130 is connected to the first plate of the first integrating capacitor C2p. Furthermore, the sixth control switch K6 is turned on. Since the first terminal of the sixth control switch K6 is electrically connected to the fourth terminal of the second switch assembly 130, and the second terminal of the sixth control switch K6 is electrically connected to the first plate of the second integrating capacitor C2n, the fourth terminal of the second switch assembly 130 is connected to the first plate of the second integrating capacitor C2n.

[0086] In the fourth state, the fifth control switch K5 is turned on. Since the first terminal of the fifth control switch K5 is electrically connected to the fourth terminal of the second switch assembly 130, and the second terminal of the fifth control switch K5 is electrically connected to the first plate of the first integrating capacitor C2p, the fourth terminal of the second switch assembly 130 is connected to the first plate of the first integrating capacitor C2p. Furthermore, the eighth control switch K8 is turned on. Since the first terminal of the eighth control switch K8 is electrically connected to the fifth terminal of the second switch assembly 130, and the second terminal of the eighth control switch K8 is electrically connected to the first plate of the second integrating capacitor C2n, the fifth terminal of the second switch assembly 130 is connected to the first plate of the second integrating capacitor C2n.

[0087] In some embodiments, the control terminals of the fifth control switch K5 and the eighth control switch K8 are both electrically connected to the dynamic matching control signal DEM, and the control terminals of the sixth control switch K6 and the seventh control switch K7 are both electrically connected to the inverted signal DEMZ of the dynamic matching control signal DEM.

[0088] For example, if the dynamic matching control signal DEM is a high-level signal, then the inverted signal DEMZ is a low-level signal. The fifth control switch K5 and the eighth control switch K8 are in the ON state under the influence of the high-level signal, while the sixth control switch K6 and the seventh control switch K7 are in the OFF state under the influence of the low-level signal. In this case, the second dynamic matching switch 140 is in the third state. If the dynamic matching control signal DEM is a low-level signal, then the inverted signal DEMZ is a high-level signal. The fifth control switch K5 and the eighth control switch K8 are in the OFF state under the influence of the low-level signal, while the sixth control switch K6 and the seventh control switch K7 are in the ON state under the influence of the high-level signal. In this case, the second dynamic matching switch 140 is in the fourth state.

[0089] Thus, both the second dynamic matching switch 140 and the first dynamic matching switch 110 are controlled by the dynamic matching control signal DEM, meaning that the second dynamic matching switch 140 and the first dynamic matching switch 110 change synchronously without affecting the normal signal sampling polarity.

[0090] In some embodiments, Figure 7 This is a schematic diagram of another differential sampling circuit provided in an embodiment of this application. Figure 7 for Figure 2 Based on the embodiment shown, the first switch assembly 120 includes a first switch M1, a second switch M2, a third switch M3, and a fourth switch M4.

[0091] Specifically, the first terminal of the first switch M1 and the first terminal of the fourth switch M4 are both electrically connected to the positive voltage signal terminal SRP, the first terminal of the second switch M2 and the first terminal of the third switch M3 are both electrically connected to the negative voltage signal terminal SRN, the second terminal of the first switch M1 and the second terminal of the second switch M2 are both electrically connected to the first terminal of the first dynamic matching switch 110, and the second terminal of the third switch M3 and the second terminal of the fourth switch M4 are both electrically connected to the second terminal of the first dynamic matching switch 110.

[0092] For example, during the sampling phase of the differential sampling circuit 100, the first switch M1 is closed and the second switch M2 is closed, causing the positive voltage signal input terminal SRP and the first plate of the first sampling capacitor C1p to conduct. The third switch M3 is closed and the fourth switch M4 is closed, causing the negative voltage signal input terminal SRN and the first plate of the second sampling capacitor C1n to conduct.

[0093] During the integration phase of the differential sampling circuit 100, the first switch M1 is turned off and the second switch M2 is closed, causing the negative voltage signal input terminal SRN and the first plate of the first sampling capacitor C1p to conduct. The third switch M3 is turned off and the fourth switch M4 is closed, causing the positive voltage signal input terminal SRP and the first plate of the second sampling capacitor C2p to conduct.

[0094] In some embodiments, see also [link to previous document]. Figure 7 The second switch assembly 130 includes a fifth switch M5, a sixth switch M6, a seventh switch M7, and an eighth switch M8.

[0095] Specifically, the first terminal of the fifth switch M5 and the first terminal of the sixth switch M6 are both electrically connected to the common-mode voltage signal VCM. The second terminal of the fifth switch M5 is electrically connected to the second plate of the first sampling capacitor C1p and the first terminal of the seventh switch M7. The second terminal of the sixth switch M6 is electrically connected to the second plate of the second sampling capacitor C1n and the first terminal of the eighth switch M8. The second terminal of the seventh switch M7 is electrically connected to the first terminal of the second dynamic matching switch 140. The eighth switch M8 is electrically connected to the second terminal of the second dynamic matching switch 140.

[0096] For example, during the sampling phase of the differential sampling circuit 100, the fifth switch M5 is closed and the seventh switch M7 is turned off, causing the second plate of the first sampling capacitor C1p and the common-mode voltage signal VCM to conduct. The sixth switch M6 is closed and the eighth switch M8 is turned off, causing the second plate of the second sampling capacitor C1n and the common-mode voltage signal VCM to conduct.

[0097] During the integration phase of the differential sampling circuit 100, the fifth switch M5 is turned off and the seventh switch M7 is closed, causing the second plate of the first sampling capacitor C1p to conduct through the first integrating capacitor C2p to the positive output terminal of the operational amplifier AMP. The sixth switch M6 is turned off and the eighth switch M8 is closed, causing the second plate of the second sampling capacitor C1n to conduct through the second integrating capacitor C2n to the negative output terminal of the operational amplifier AMP.

[0098] When the fifth switch M5 and the sixth switch M6 are turned off, channel charge flows out of the fifth switch M5 and the sixth switch M6, introducing errors into the first sampling capacitor C1p and the second sampling capacitor C1n. Since the fifth switch M5 and the sixth switch M6 cannot achieve perfect matching, the second switch assembly 130 generates a first mismatch charge. When the seventh switch M7 and the eighth switch M8 are closed, they absorb charge from the outside to form a channel, introducing errors into the first integrating capacitor C2p and the second integrating capacitor C2n. The seventh switch M7 and the eighth switch M8 also cannot achieve perfect matching, and the second switch assembly 130 generates a second mismatch charge.

[0099] If the injected charge of the fifth switch M5 is greater than the injected charge of the sixth switch M6, part of the injected charge of the fifth switch M5 is canceled out by the injected charge of the sixth switch M6, and the remaining injected charge in the fifth switch M5 is the first mismatch charge. If the absorbed charge of the eighth switch M8 is greater than the absorbed charge of the seventh switch M7, part of the absorbed charge of the eighth switch M8 is canceled out by the charge of the seventh switch M7, and the remaining absorbed charge in the eighth switch M8 is the second mismatch charge.

[0100] In some embodiments, Figure 8 This is a schematic diagram of a switch provided in an embodiment of this application. The control switch and the switch structure in this embodiment are as follows. Figure 8 As shown, it includes an NMOS transistor and a PMOS transistor, wherein the first terminal of the NMOS transistor is electrically connected to the first terminal of the PMOS transistor, the second terminal of the NMOS transistor is electrically connected to the second terminal of the PMOS transistor, and the control signal ON of the NMOS transistor is the inverted signal ONZ of the control signal ON of the PMOS transistor.

[0101] This application also provides an analog-to-digital converter, which includes the differential sampling circuit 100 provided in any of the above embodiments.

[0102] The differential sampling circuit 100 provided by the analog-to-digital converter in this application embodiment has the same functional modules and beneficial effects as the differential sampling circuit 100, which will not be described in detail here.

[0103] This application also provides a chip, including: the analog-to-digital converter provided in any of the above embodiments.

[0104] For example, integrating the analog-to-digital converter provided in any of the above embodiments into a chip can reduce the size of the analog-to-digital converter, which is beneficial to the miniaturization of the analog-to-digital converter.

[0105] The chip provided in this application includes the analog-to-digital converter provided in any of the above embodiments, and has the same functional modules and beneficial effects as the analog-to-digital converter, which will not be repeated here.

[0106] The above-disclosed embodiments are merely specific examples of this application. However, the embodiments of this application are not limited thereto, and any variations that can be conceived by those skilled in the art should fall within the protection scope of this application.

[0107] The term "comprising" as used in this application does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims listing several means, several units of these means may be embodied by the same item of hardware. The use of "first," "second," and "third," etc., does not indicate any order and should be interpreted as names. Unless otherwise specified, the steps in the above embodiments should not be construed as limiting the order of execution.

[0108] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A differential sampling circuit, characterized in that, include: The system comprises a first dynamic matching switch, a first sampling capacitor, a second sampling capacitor, a first switching assembly, a second switching assembly, a first integrating capacitor, a second integrating capacitor, and an operational amplifier. The first terminal of the first switching assembly is electrically connected to a positive voltage signal terminal, the second terminal of the first switching assembly is electrically connected to a negative voltage signal terminal, the third terminal of the first switching assembly is electrically connected to the first terminal of the first dynamic matching switch, the fourth terminal of the first switching assembly is electrically connected to the second terminal of the first dynamic matching switch, the third terminal of the first dynamic matching switch is electrically connected to the first plate of the first sampling capacitor, the fourth terminal of the first dynamic matching switch is electrically connected to the first plate of the second sampling capacitor, the second plate of the first sampling capacitor is electrically connected to the first terminal of the second switching assembly, the second plate of the second sampling capacitor is electrically connected to the second terminal of the second switching assembly, and the third terminal of the second switching assembly is electrically connected to a common-mode voltage signal; wherein, the positive voltage signal terminal and the negative voltage signal terminal are respectively electrically connected to a set of differential signals; The fourth terminal of the second switching assembly is electrically connected to the positive input terminal of the operational amplifier, the fifth terminal of the second switching assembly is electrically connected to the negative input terminal of the operational amplifier, the first integrating capacitor is connected across the positive output terminal and the positive input terminal of the operational amplifier, and the second integrating capacitor is connected across the negative input terminal of the negative output terminal of the operational amplifier. The first dynamic matching switch is used to control the first mismatch charge to flow into the first voltage signal terminal in a first state and to control the first mismatch charge to flow into the second voltage signal terminal in a second state; wherein the first voltage signal terminal is the positive voltage signal terminal and the second voltage signal terminal is the negative voltage signal, or the first voltage signal terminal is the negative voltage signal terminal and the second voltage signal terminal is the positive voltage signal terminal, and the first state and the second state alternate.

2. The differential sampling circuit according to claim 1, characterized in that, The first dynamic matching switch is used to connect the negative voltage signal terminal and the first plate of the first sampling capacitor in the first state, and to connect the positive voltage signal terminal and the first plate of the second sampling capacitor; and to connect the positive voltage signal terminal and the first plate of the first sampling capacitor in the second state, and to connect the negative voltage signal terminal and the first plate of the second sampling capacitor.

3. The differential sampling circuit according to claim 1 or 2, characterized in that, The first dynamic matching switch includes a first control switch, a second control switch, a third control switch, and a fourth control switch; The first end of the first control switch and the first end of the second control switch are both electrically connected to the third end of the first switch assembly. The first end of the third control switch and the first end of the fourth control switch are both electrically connected to the fourth end of the first switch assembly. The second end of the first control switch and the second end of the third control switch are both electrically connected to the first plate of the first sampling capacitor. The second end of the second control switch and the second end of the fourth control switch are both electrically connected to the first plate of the second sampling capacitor.

4. The differential sampling circuit according to claim 3, characterized in that, The control terminals of the first control switch and the fourth control switch are both electrically connected to the dynamic matching control signal, and the control terminals of the second control switch and the third control switch are both electrically connected to the inverted signal of the dynamic matching control signal.

5. The differential sampling circuit according to claim 4, characterized in that, The period T1 of the control signal of the first switching component and the period T2 of the dynamic matching control signal satisfy: T2 / T1=2*n, where n is a positive integer.

6. The differential sampling circuit according to claim 1 or 2, characterized in that, It also includes a second dynamic matching switch; The first terminal of the second dynamic matching switch is electrically connected to the fourth terminal of the second switch assembly, the second terminal of the second dynamic matching switch is electrically connected to the fifth terminal of the second switch assembly, the third terminal of the second dynamic matching switch is electrically connected to the positive input terminal, and the fourth terminal of the second dynamic matching switch is electrically connected to the negative input terminal. The second dynamic matching switch is used to control the flow of the second mismatch charge into the first output terminal in the third state and to control the flow of the second mismatch charge into the second output terminal in the fourth state; wherein the first output terminal is the positive output terminal and the second output terminal is the negative output terminal, or the first output terminal is the negative output terminal and the second output terminal is the positive output terminal, and the third state and the fourth state alternate.

7. The differential sampling circuit according to claim 6, characterized in that, The second dynamic matching switch is used to connect the first plate of the first integrating capacitor and the fifth terminal of the second switching assembly in the third state, and to connect the first plate of the second integrating capacitor and the fourth terminal of the second switching assembly. In the fourth state, the first plate of the first integrating capacitor and the fourth terminal of the second switching assembly are connected, and the first plate of the second integrating capacitor and the fifth terminal of the second switching assembly are also connected.

8. The differential sampling circuit according to claim 7, characterized in that, The second dynamic matching switch includes a fifth control switch, a sixth control switch, a seventh control switch, and an eighth control switch; The first end of the fifth control switch and the first end of the sixth control switch are both electrically connected to the fourth end of the second switch assembly. The first end of the seventh control switch and the first end of the eighth control switch are both electrically connected to the fifth end of the second switch assembly. The second end of the fifth control switch and the second end of the seventh control switch are both electrically connected to the first plate of the first integrating capacitor. The second end of the sixth control switch and the second end of the eighth control switch are both electrically connected to the first plate of the second integrating capacitor.

9. The differential sampling circuit according to claim 6, characterized in that, The first switch assembly includes a first switch, a second switch, a third switch, and a fourth switch; The first terminal of the first switch and the first terminal of the fourth switch are both electrically connected to the positive voltage signal terminal. The first terminal of the second switch and the first terminal of the third switch are both electrically connected to the negative voltage signal terminal. The second terminal of the first switch and the second terminal of the second switch are both electrically connected to the first terminal of the first dynamic matching switch. The second terminal of the third switch and the second terminal of the fourth switch are both electrically connected to the second terminal of the first dynamic matching switch.

10. The differential sampling circuit according to claim 9, characterized in that, The second switch assembly includes: a fifth switch, a sixth switch, a seventh switch, and an eighth switch; The first terminal of the fifth switch and the first terminal of the sixth switch are both electrically connected to the common-mode voltage signal. The second terminal of the fifth switch is electrically connected to the second plate of the first sampling capacitor and the first terminal of the seventh switch. The second terminal of the sixth switch is electrically connected to the second plate of the second sampling capacitor and the first terminal of the eighth switch. The second terminal of the seventh switch is electrically connected to the first terminal of the second dynamic matching switch. The eighth switch is electrically connected to the second terminal of the second dynamic matching switch.

11. An analog-to-digital converter, characterized in that, Includes the differential sampling circuit as described in any one of claims 1-10.

12. A chip, characterized in that, Includes the analog-to-digital converter as described in claim 11.

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