Data acquisition system based on two n-bit ad synthesizing n+1-bit ad

Abstract

The application is a data acquisition system for synthesizing an N+1-bit AD based on two N-bit ADs. Based on the ADC sampling principle, the target signal is amplified and processed in a series of processes, and then a programmable logic gate array FPGA is used as a central processor to control two low-resolution AD chips to sample the signal, and the signal transmitted by the AD chip is synthesized to the programmable logic gate array FPGA, so as to achieve the goal of higher resolution ADC sampling. Finally, the programmable logic gate array FPGA transmits data to a static random access memory SRAM, and after the data processing is completed, the data is transmitted to a host computer for display. The problem of high-precision data acquisition under the condition that part of the chips cannot be acquired is solved, so as to reduce the cost of the ADC data acquisition system and ensure the stability of data acquisition.

Description

Technical Field

[0001] This invention relates to the field of signal acquisition and processing technology. Background Technology

[0002] Data acquisition circuit systems are an indispensable component in research, testing, and development, and high-precision data acquisition can improve the performance and reliability of the entire testing system. Data acquisition technology refers to the conversion of different types of physical signals into digital signals (electrical signals) that can be recognized, processed, and stored by a computer through a series of operations. In this entire process, the input signal needs to be processed in advance: through signal amplification, filtering, sampling and holding, and finally through an analog-to-digital converter to obtain the corresponding digital signal, which is very costly. Summary of the Invention

[0003] The purpose of this invention is to provide an ADC data acquisition system that uses a low-bit analog-to-digital converter chip to replace a high-bit analog-to-digital converter chip, resulting in high data acquisition accuracy and low cost.

[0004] This invention is implemented as follows:

[0005] This FPGA-controlled data acquisition system combines two N-bit analog-to-digital converters (ADCs) to form an N+1-bit ADC. The single-ended signal under test is converted into two analog signals with different amplitudes but the same phase after passing through a single-ended to differential amplifier circuit. The single-ended to differential amplifier circuit is shown below. Figure 1 As shown, these two signals represent the greater-than and less-than-zero portions of the original signal, respectively, and are then input to the first and second analog-to-digital converters (AD) for conversion. The data output and control terminals of the AD converters are connected to the programmable gate array (FPGA). Simultaneously, the input signal is connected to the FPGA via a zero-crossing comparator. This signal, SIGN, distinguishes between the greater-than and less-than-zero states of the input signal. The zero-crossing comparator is as follows: Figure 2 As shown. The output of the FPGA is connected to two memory processing subsystems. Each subsystem consists of a switching chip ADG734 and a static random access memory (SRAM). The signal under test is converted from analog to digital by the first and second analog-to-digital converters (AD), and then output to the FPGA. The FPGA reads the signals from the two AD converters separately using the SIGN signal. The read data is arranged according to the internal sampling timing of the FPGA, and thus synthesized into complete test data. The data processing steps are as follows:

[0006] (1) The signal under test is converted into analog signals 1 and 2 with doubled amplitude and unchanged phase by the first and second single-ended to differential amplifier circuits.

[0007] (2) The first analog signal processed by the single-ended to differential amplifier circuit is converted into the first test signal by the adder. After the signal passes through the adder, the voltage increases by 0.512V and is input to the first analog-to-digital converter circuit (AD), where it is sampled.

[0008] (3) The second analog signal processed by the single-ended to differential amplifier circuit is converted into the second test signal by adders and subtractors respectively. After the signal passes through the subtractor, the voltage is reduced by 0.512V and then input to the second analog-to-digital converter circuit, where it is sampled by the second analog-to-digital converter circuit (AD).

[0009] (4) The FPGA controls the analog-to-digital converter (AD) circuit through two control lines. The first control line, PWRDWN, controls the start and stop of the AD circuit, and the second control line, ENCODE, is the sampling clock for the AD circuit. Sampling is performed on the rising edge of this signal.

[0010] (5) When the comparator output signal SIGN is high, the FPGA starts the first analog-to-digital converter (AD) through the second control line ENCODE signal. The obtained conversion code is the case where the signal is greater than zero. At this time, the first control line PWRDWN is low, the second control line ENCODE is sampled on the rising edge, and the first AD receives the instructions written by the external FPGA through 8 data lines.

[0011] (6) After the first analog-to-digital converter (AD) completes one data conversion, the first control line PWRDWN pin is pulled low for one clock cycle. The first AD then transmits the digital signal to the programmable gate array (FPGA) through 8 data lines. The FPGA then reduces the received sampled signal value by 0.512V.

[0012] (7) After the first analog-to-digital converter (AD) completes one data transmission, when the comparator output signal SIGN is low, the programmable gate array (FPGA) starts the second AD through the second control line ENCODE signal to perform conversion. The obtained conversion code is the case where the signal is less than zero. The second AD repeats steps 5) and 6). When repeating step 6), the received sampled signal value in the FPGA is increased by 0.512V.

[0013] (8) After receiving the two sampling signals respectively, the FPGA combines them according to the sampling order.

[0014] (9) When data needs to be transmitted again, first pull the first control line PWRDWN pin high to separate the two sets of data, and then repeat the above read and write operations to transmit the next set of data.

[0015] (10) The ADG734 switching chip is used to control the connection relationship of the SPI interface of the static random access memory (SRAM). When the control line pin of the ADG734 switching chip is pulled low, the FPGA has write access to the SRAM; when the control line pin of the ADG734 switching chip is pulled high, the FPGA has read access to the SRAM.

[0016] (11) The first static random access memory (SRAM) chip in the first storage processing subsystem CM1 sends a read command to the programmable gate array (FPGA). The control line pins of the first switching chip ADG734 in the first storage processing subsystem CM1 are pulled low. At this time, the SPI interface between the first SRAM in the first storage processing subsystem CM1 and the programmable gate array (FPGA) is connected, and data is written to the first SRAM in a sequential manner through the SPI interface.

[0017] (12) When the first static random access memory (SRAM) is full, the control line pin of the first switch chip ADG734 in the first storage processing subsystem CM1 is pulled high. At this time, the SPI interface between the first storage processing subsystem CM1 and the first SRAM and the FPGA is connected, and data is read through the SPI interface.

[0018] (13) When the control line pin of the FPGA and the ADG734 switching chip in the first storage processing subsystem CM1 is pulled high, stopping the transmission of data to it, the second static random access memory (SRAM) in the second storage processing subsystem CM2 sends a read command to the FPGA. The processing procedure of the second storage processing subsystem is the same as steps 11) and 12).

[0019] (14) After the FPGA has finished processing all the data, it transmits the data to the USB chip through the SPI interface. The USB chip then transmits the data to the host computer for display through the USB bus.

[0020] (15) By dividing the signal to be tested into different parts and sending them to two N-bit analog-to-digital converter (AD) modules for acquisition and processing, and then using the FPGA to restore the two acquired signals to the initial signal, the two N-bit AD modules are combined to realize one N+1-bit AD module.

[0021] The analog-to-digital converter (AD) circuit is connected to the programmable gate array (FPGA) via eight data lines and two control lines. The FPGA is connected to the ADG734 switching chip in each memory processing subsystem via five lines, including a serial peripheral interface (SPI) and one control line. The ADG734 is connected to the static random access memory (SRAM) via the SPI interface, and to the universal serial communication chip (USB) outside the memory processing subsystem via the SPI interface. The USB chip is connected to the host computer via a universal serial bus (USB bus).

[0022] The advantages of this invention are as follows:

[0023] While ensuring signal reproduction, higher-cost high-bit AD chips can be synthesized from lower-cost low-bit AD chips. This effectively reduces production costs and achieves better data processing results without signal loss. It also solves the problem of achieving high-precision data acquisition when some chips are unavailable, thereby reducing the cost of the ADC data acquisition system and ensuring data acquisition stability. Attached Figure Description

[0024] Figure 1 Single-ended to differential amplifier circuit

[0025] Figure 2 Zero-crossing comparator

[0026] Figure 3 Diagram showing the connection between the analog-to-digital converter (AD) and the programmable gate array (FPGA).

[0027] Figure 4 Connection diagram of FPGA and a single memory subsystem

[0028] Figure 5 This is a schematic diagram of the overall structure of the present invention. Detailed Implementation

[0029] Each storage module of this invention consists of a switching chip ADG734 and a static random access memory (SRAM) forming a storage subsystem (such as CM1, CM2...). The analog-to-digital converter (AD) module and the programmable gate array (FPGA) are connected by 8 data lines and PWRDWN and ENCODE control lines. PWRDWN controls the start and stop of the AD chip, and ENCODE is the sampling clock for the AD chip, which performs sampling on the rising edge of this signal. The connection structure diagram between the AD module and the FPGA is shown below. Figure 2As shown in the diagram, the FPGA (Programmable Gate Array) is connected to the ADG734 switching chip in each memory processing subsystem via five signal lines, including CLK, CS, SDI, and SDO of the SPI (Serial Peripheral Interface) interface (CS generates the device enable signal, CLK provides the clock pulse, and SDI and SDO complete data transmission based on this pulse) and one control line. The ADG734 switching chip is connected to the SRAM (Static Random Access Memory) within its memory processing subsystem via the SPI interface line, and to the USB (Universal Serial Bus) chip outside the memory processing subsystem via the SPI interface line. The USB chip is connected to the host computer via the USB bus. The connection diagram between the FPGA and a single memory processing subsystem is shown in the diagram. Figure 3 As shown in the figure, the overall result is as follows. Figure 4 As shown.

[0030] The data processing steps are as follows:

[0031] (1) The signal to be measured is amplified and converted into an analog signal with doubled amplitude but unchanged phase.

[0032] (2) The first analog signal processed by the single-ended to differential amplifier circuit is converted into the first test signal by the adder. After the signal passes through the adder, the voltage increases by 0.512V and is input to the first analog-to-digital converter circuit (AD), where it is sampled.

[0033] (3) The second analog signal processed by the single-ended to differential amplifier circuit is converted into the second test signal by adders and subtractors respectively. After the signal passes through the subtractor, the voltage is reduced by 0.512V and then input to the second analog-to-digital converter circuit, where it is sampled by the second analog-to-digital converter circuit (AD).

[0034] (4) The FPGA controls the analog-to-digital converter (AD) circuit through two control lines. The first control line, PWRDWN, controls the start and stop of the AD circuit, and the second control line, ENCODE, is the sampling clock for the AD circuit. Sampling is performed on the rising edge of this signal.

[0035] (5) When the comparator output signal SIGN is high, the FPGA starts the first analog-to-digital converter (AD) through the second control line ENCODE signal. The obtained conversion code is the case where the signal is greater than zero. At this time, the first control line PWRDWN is low, the second control line ENCODE is sampled on the rising edge, and the first AD receives the instructions written by the external FPGA through 8 data lines.

[0036] (6) After the first analog-to-digital converter (AD) completes one data conversion, the first control line PWRDWN pin is pulled low for one clock cycle. The first AD then transmits the digital signal to the programmable gate array (FPGA) through 8 data lines. The FPGA then reduces the received sampled signal value by 0.512V.

[0037] (7) After the first analog-to-digital converter (AD) completes one data transmission, when the comparator output signal SIGN is low, the programmable gate array (FPGA) starts the second AD through the second control line ENCODE signal to perform conversion. The obtained conversion code is the case where the signal is less than zero. The second AD repeats steps 6) and 7) once. When repeating step 7), the received sampled signal value in the FPGA is increased by 0.512V.

[0038] (8) After receiving the two sampling signals respectively, the FPGA combines them according to the sampling order.

[0039] (9) When data needs to be transmitted again, first pull the PWRDWN pin high to separate the two sets of data, and then repeat the above read and write operations to transmit the next set of data.

[0040] (10) The ADG734 switching chip is used to control the connection relationship of the SPI interface of the static random access memory (SRAM). When the control line pin of the ADG734 switching chip is pulled low, the FPGA has write access to the SRAM; when the control line pin of the ADG734 switching chip is pulled high, the FPGA has read access to the SRAM.

[0041] (11) The Static Random Access Memory (SRAM) chip in the first storage processing subsystem CM1 sends a read command to the Programmable Gate Array (FPGA). The control line pins of the FPGA and the ADG734 switching chip in the first storage processing subsystem CM1 are pulled low, and data is written to the SRAM in sequence through the SPI interface.

[0042] (12) When the static random access memory (SRAM) is full, the control line pins of the switching chip ADG734 in the programmable gate array (FPGA) and the first storage processing subsystem CM1 are pulled high to read data through the SPO interface.

[0043] (13) When the control line pin of the FPGA and the ADG734 switching chip in the first memory processing subsystem CM1 is pulled high, data transmission to them is stopped.

[0044] (14) The Static Random Access Memory (SRAM) in the second storage processing subsystem CM2 sends a read command to the Programmable Gate Array (FPGA). The processing of the second storage processing subsystem is the same as in steps 12, 13, and 14.

[0045] (15) After the FPGA has finished processing all the data, it transmits the data to the USB chip through the SPI interface. The USB chip then transmits the data to the host computer for display through the USB bus.

[0046] (16) By dividing the signal to be tested into different parts and sending them to multiple analog-to-digital converter (AD) modules for acquisition and processing, and then using a programmable gate array (FPGA) to restore the acquired signal to the initial signal, an N+1 bit AD module is realized by combining two N-bit AD modules.

Claims

1. A data acquisition system based on combining two N-bit AD converters into one N+1-bit AD converter, characterized in that, The single-ended signal under test is converted into two analog differential signals with different amplitudes but the same phase after passing through the first and second single-ended to differential amplifier circuits. These two analog differential signals represent the positive and negative portions of the original signal, respectively. These signals are then input to the first and second analog-to-digital converter (AD) circuits for conversion. The data output and control terminals of the first and second AD circuits are connected to a programmable gate array (FPGA). Simultaneously, the single-ended signal under test is connected to the FPGA via a zero-crossing comparator. The comparator's output signal SIGN distinguishes between the positive and negative states of the input signal. The output of the FPGA is connected to the first and second storage processing subsystems. Each storage processing subsystem consists of a switching chip ADG734 and a static random access memory (SRAM). After the signal under test is converted into a digital signal by the first and second AD circuits, it is transmitted to the FPGA. The FPGA reads the digital signals transmitted from the first and second AD circuits and synthesizes the read signals into a complete signal under test. The data processing steps are as follows: (1) The signal under test is converted into analog signals 1 and 2 with doubled amplitude and unchanged phase by the first and second single-ended to differential amplifier circuits. (2) The first analog signal processed by the single-ended to differential amplifier circuit is converted into the first test signal by the adder. After the signal passes through the adder, the voltage increases by 0.512V and is input to the first analog-to-digital converter circuit (AD), where it is sampled. (3) The second analog signal processed by the single-ended to differential amplifier circuit is converted into the second test signal by adders and subtractors respectively. After the signal passes through the subtractor, the voltage is reduced by 0.512V and then input to the second analog-to-digital converter circuit, where it is sampled by the second analog-to-digital converter circuit (AD). (4) The FPGA controls the analog-to-digital converter (AD) circuit through two control lines. The first control line, PWRDWN, controls the start and stop of the AD circuit, and the second control line, ENCODE, is the sampling clock for the AD circuit. Sampling is performed on the rising edge of this signal. (5) When the comparator output signal SIGN is high, the FPGA starts the first analog-to-digital converter (AD) through the second control line ENCODE signal. The obtained conversion code is the case where the signal is greater than zero. At this time, the first control line PWRDWN is low, the second control line ENCODE is sampled on the rising edge, and the first AD receives the instructions written by the external FPGA through 8 data lines. (6) After the first analog-to-digital converter (AD) completes one data conversion, the first control line PWRDWN pin is pulled low for one clock cycle. The first AD then transmits the digital signal to the programmable gate array (FPGA) through 8 data lines. The FPGA then reduces the received sampled signal value by 0.512V. (7) After the first analog-to-digital converter (AD) completes one data transmission, when the comparator output signal SIGN is low, the programmable gate array (FPGA) starts the second AD through the second control line ENCODE signal to perform conversion. The obtained conversion code is the case where the signal is less than zero. The second AD repeats steps 5) and 6). When repeating step 6), the received sampled signal value in the FPGA is increased by 0.512V. (8) After receiving the two sampling signals respectively, the FPGA combines them according to the sampling order. (9) When data needs to be transmitted again, first pull the first control line PWRDWN pin high to separate the two sets of data, and then repeat the above read and write operations to transmit the next set of data. (10) The ADG734 switching chip is used to control the connection relationship of the SPI interface of the static random access memory (SRAM). When the control line pin of the ADG734 switching chip is pulled low, the FPGA has write access to the SRAM; when the control line pin of the ADG734 switching chip is pulled high, the FPGA has read access to the SRAM. (11) The first static random access memory (SRAM) chip in the first storage processing subsystem CM1 sends a read command to the programmable gate array (FPGA). The control line pins of the first switching chip ADG734 in the first storage processing subsystem CM1 are pulled low. At this time, the SPI interface between the first SRAM in the first storage processing subsystem CM1 and the programmable gate array (FPGA) is connected, and data is written to the first SRAM in a sequential manner through the SPI interface. (12) When the first static random access memory (SRAM) is full, the control line pin of the first switch chip ADG734 in the first storage processing subsystem CM1 is pulled high. At this time, the SPI interface between the first storage processing subsystem CM1 and the first SRAM and the FPGA is connected, and data is read through the SPI interface. (13) When the control line pin of the FPGA and the ADG734 switching chip in the first storage processing subsystem CM1 is pulled high, stopping the transmission of data to it, the second static random access memory (SRAM) in the second storage processing subsystem CM2 sends a read command to the FPGA. The processing procedure of the second storage processing subsystem is the same as steps 11) and 12). (14) After the FPGA has finished processing all the data, it transmits the data to the USB chip through the SPI interface. The USB chip then transmits the data to the host computer for display through the USB bus.

2. The data acquisition system based on synthesizing an N+1 bit AD from two N-bit AD converters according to claim 1, characterized in that... The analog-to-digital converter (AD) circuit is connected to the programmable gate array (FPGA) via eight data lines and two control lines. The FPGA is connected to the ADG734 switching chip in each storage processing subsystem via five lines, including the serial peripheral interface (SPI) and one control line. The ADG734 switching chip is connected to the static random access memory (SRAM) via the SPI interface line and to the universal serial chip (USB) outside the storage processing subsystem via the SPI interface line. The USB chip is connected to the host computer via the universal serial bus (USB bus).

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