A successive approximation analog-to-digital converter and chip

Abstract

This application discloses a successive approximation analog-to-digital converter (ADC) and chip, comprising: an oversampling rate counting circuit and a shifting circuit; wherein, the oversampling rate counting circuit calculates the oversampling rate by counting based on the length value of the ADC sequence configured in the register, and the shifting circuit is used to perform summation and shifting processing on the digital signal after ADC conversion. This application implements the oversampling and shifting function of the original converted data of the successive approximation ADC, making the oversampling process completely hardware-based, eliminating the need to wait for the upper-level software to perform oversampling, reducing the resource consumption of the central processing unit (CPU), lowering the CPU's computational load, and improving the oversampling and shifting efficiency.

Description

Technical Field

[0001] This application relates to the field of analog-to-digital converters, specifically to a successive approximation analog-to-digital converter and chip. Background Technology

[0002] Successive approximation analog-to-digital converters (SAR ADCs) are commonly used in low-power, simple-structure, low-to-medium speed, and high-precision applications. They can sample analog signals in real time across multiple channels and convert them into digital signals for the central processing unit (CPU). Currently, common oversampling processing typically involves the CPU reading the data after analog-to-digital conversion by the SAR ADC, followed by processing of the data by upper-level software algorithms. However, in large-scale SoCs, this oversampling method can lead to issues with the CPU's processing speed. The CPU may not be able to process the data in time at the software level, or it may be occupied for extended periods processing the SAR ADC data, impacting oversampling efficiency or excessively consuming CPU memory. Summary of the Invention

[0003] This application provides a successive approximation analog-to-digital converter and chip, the specific technical solution of which is as follows:

[0004] A successive approximation analog-to-digital converter includes an oversampling rate counting circuit and a shift circuit; wherein the oversampling rate counting circuit calculates the oversampling rate by counting based on the length value of the analog-to-digital conversion sequence configured in the register, and the shift circuit is used to perform summation and shifting processing on the digital signal after analog-to-digital conversion.

[0005] Further, the oversampling rate counting circuit includes: a first counter, a second flip-flop, a third counter, and a fourth flip-flop; wherein, the first counter is used to receive a pre-configured analog-to-digital conversion sequence length value, count the length of the analog-to-digital converter conversion sequence to obtain a first count value, and transmit the first count value to the second flip-flop; the second flip-flop is used to receive an analog-to-digital conversion flag signal and the first count value, and output an oversampling end time pulse signal to the third counter according to the analog-to-digital conversion flag signal and the first count value; the third counter is used to receive the oversampling end time pulse signal, and count when the oversampling end time pulse signal is at a low level to obtain a second count value, and transmit the second count value to the fourth flip-flop; the fourth flip-flop is used to receive the second count value, and output an oversampling end flag signal according to whether the second count value is equal to a preset oversampling number threshold.

[0006] Further, the shift circuit includes: a fifth accumulator, a sixth flip-flop, and a seventh shift register; wherein, the fifth accumulator is used to receive the digital signal after analog-to-digital conversion, and to perform accumulation and summation processing on the received digital signal to obtain an accumulated digital signal and transmit it to the sixth flip-flop; the sixth flip-flop is used to receive the accumulated digital signal transmitted by the fifth accumulator, and to filter out the final accumulated digital signal from the received accumulated digital signal, and transmit the final accumulated digital signal to the seventh shift register; the seventh shift register is used to receive the final accumulated digital signal transmitted by the sixth flip-flop with a pre-configured bit width, to perform shift processing on the final accumulated digital signal according to the pre-configured bit width, and to output the shifted final accumulated digital signal to the corresponding data register for storage, so as to be read by the central processing unit.

[0007] Furthermore, the first counter, second flip-flop, third counter, fourth flip-flop, fifth accumulator, sixth flip-flop, and seventh shift register respectively receive the analog-to-digital converter operating clock signal, the oversampling enable signal, and the reset signal; wherein, the analog-to-digital converter operating clock signal is used to unify the sampling time points of the first counter, second flip-flop, third counter, fourth flip-flop, fifth accumulator, sixth flip-flop, and seventh shift register; the oversampling enable signal is used to indicate whether the oversampling function is enabled or disabled; and the reset signal is used to control whether the reset function is enabled or disabled.

[0008] Furthermore, the first counter is also used to receive the oversampling end flag signal output by the fourth flip-flop; when the oversampling enable signal is in a high level state, the oversampling end flag signal is in a high level state, and the first count value is equal to the pre-configured analog-to-digital conversion sequence length value, the first counter will reset the first count value to zero.

[0009] Furthermore, the second flip-flop is also used to receive the oversampling end flag signal output by the fourth flip-flop; when the analog-to-digital conversion flag signal is in a low-level state, the oversampling end time pulse signal output by the second flip-flop is in a low-level state; when the analog-to-digital conversion flag signal is in a high-level state, if the first count value is equal to the pre-configured analog-to-digital conversion sequence length value and the oversampling end flag signal is in a high-level state, then the oversampling end time pulse signal output by the second flip-flop is in a high-level state; otherwise, if the first count value is not equal to the pre-configured analog-to-digital conversion sequence length value and / or the oversampling end flag signal is in a low-level state, the oversampling end time pulse signal output by the second flip-flop maintains the level state it was in during the last output.

[0010] Furthermore, the third counter is also used to receive the first sampling end flag signal, and the third counter is also used to receive the second count value output by itself; the first sampling end flag signal is used to indicate the rising edge of the signal at the end of sampling of the capture analog circuit; when the first sampling end flag signal is in a high level state and the oversampling enable signal is in a high level state, it is determined whether the current second count value is equal to the sum of the preset oversampling number threshold and the number 1. If yes, the third counter sets the current second count value to zero; if no, the third counter counts when the oversampling end pulse signal is in a low level state.

[0011] Furthermore, the fourth flip-flop is also used to receive the first sampling end flag signal; when the first sampling end flag signal is in a high level state and the oversampling enable signal is in a high level state, it determines whether the current second count value is equal to the preset oversampling number threshold. If yes, the oversampling end flag signal output by the fourth flip-flop is in a high level state; if no, the oversampling end flag signal output by the fourth flip-flop is in a low level state, and the same second count value as the previous time is output when the pulse signal is in a high level at the time of oversampling end.

[0012] Furthermore, the fifth accumulator performs summation calculations on the received analog-to-digital converted digital signal a number of times equal to a preset oversampling threshold.

[0013] Furthermore, the fifth accumulator is also used to receive the second count value and the first sampling end flag signal; when the first sampling end flag signal is in a high level state and the second count value is equal to the sum of the preset oversampling number threshold and the digit 1, the accumulated digital signal output by the fifth accumulator is equal to the received analog-to-digital converted digital signal.

[0014] Furthermore, the sixth trigger is also used to receive the second count value and the first sampling end flag signal; when the first sampling end flag signal is in a low level state and the second count value is equal to the sum of the preset oversampling number threshold and the number 1, the sixth trigger filters the accumulated digital signal received at this time point into the final accumulated digital signal.

[0015] Furthermore, the pre-configured bit width is less than or equal to the logarithm of the sum of a preset oversampling threshold with base 2 and a base 1.

[0016] This application also discloses a chip that includes a successive approximation analog-to-digital converter as described above.

[0017] The successive approximation analog-to-digital converter described in this application addresses the problems of large channel number, large number of sampled targets, and large variation in sampling conditions in analog-to-digital converters using the successive approximation method. By setting up an oversampling rate counting circuit and a shift circuit in the successive approximation analog-to-digital converter, and using multiple sampling, summation, and shifting methods, the resolution of the sampled target data is improved. The oversampling algorithm is hardware-based, reducing the burden of data oversampling processing in the SOC chip, and achieving the technical effect of digital amplification of the sampled data. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the signal flow of the oversampling rate counting circuit according to one embodiment of this application.

[0019] Figure 2 This is a schematic diagram of the signal flow of the shift circuit according to one embodiment of this application.

[0020] Figure 3 This is a schematic diagram of the oversampling conversion state of a successive approximation analog-to-digital converter according to one embodiment of this application. Detailed Implementation

[0021] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings. All modules involved in the following embodiments are logic circuit units. In practical applications, a logic circuit unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of the present invention, units that are not closely related to solving the technical problem proposed by the present invention are not introduced in the embodiments of the present invention. However, this does not mean that other units are absent from the embodiments of the present invention.

[0022] One embodiment of this application provides a successive approximation analog-to-digital converter (ADC). The ADC incorporates an oversampling rate counting circuit and a shift circuit, enabling the oversampling processing algorithm to be hardware-based. This eliminates the need for the CPU to read the data before processing it in upper-level software algorithms, solving the problem of the CPU being occupied for extended periods for oversampling processing, thus impacting its data processing efficiency. Simultaneously, it addresses the issue of upper-level software algorithms failing to perform timely oversampling processing, effectively improving the efficiency and accuracy of oversampling processing after analog-to-digital conversion. Specifically, the oversampling rate counting circuit calculates the oversampling rate based on the length of the analog-to-digital conversion sequence configured in the register. The shift circuit performs summation and shifting processing on the digital signal after analog-to-digital conversion, accumulating the digital signal and achieving digital amplification or reduction through shifting.

[0023] In one embodiment of this application, a successive approximation analog-to-digital converter is provided, such as Figure 1As shown, the oversampling rate counting circuit includes: a first counter, a second flip-flop, a third counter, and a fourth flip-flop.

[0024] Specifically, the first counter, second flip-flop, third counter, and fourth flip-flop each receive an analog-to-digital converter (ADC) clock signal, an oversampling enable signal, and a reset signal, respectively. The ADC clock signal provides a stable time interval, ensuring that each counter and flip-flop samples at the same point in time, such as the rising edge of the ADC clock signal. The oversampling enable signal indicates whether the oversampling function is enabled or disabled. A high level indicates that the oversampling function is enabled, while a low level indicates that the oversampling function is disabled. The reset signal indicates whether the reset function is enabled or disabled. A high level indicates that the reset function is enabled, resetting the count values ​​of each counter and the level of the signals output by each flip-flop. Conversely, a low level indicates that the reset function is disabled.

[0025] Specifically, the first counter is used to receive a pre-configured analog-to-digital conversion sequence length value, obtain a first count value by counting the length of the analog-to-digital converter conversion sequence, and transmit the first count value to the second flip-flop; wherein, the pre-configured analog-to-digital conversion sequence length value comes from a value pre-configured by the register design module in software, and is used in this application to limit the length of the analog-to-digital converter conversion sequence; the first count value generated by the first flip-flop is a count of the length of the analog-to-digital converter conversion sequence.

[0026] The second trigger receives the analog-to-digital conversion flag signal and the first count value transmitted by the first counter, and outputs an oversampling end time pulse signal to the third counter according to the level state of the analog-to-digital conversion flag signal CONV_REGULAR and the first count value. The analog-to-digital conversion flag signal CONV_REGULAR indicates the progress of an oversampling conversion process. When CONV_REGULAR is high, it indicates that the oversampling conversion process is in progress; conversely, when CONV_REGULAR is low, it indicates that the oversampling conversion process has ended. Specifically, when CONV_REGULAR is low, the second trigger directly outputs the low-level oversampling end time pulse signal; when CONV_REGULAR is high, the first count value is considered when outputting the corresponding oversampling end time pulse signal. Specifically, in order to improve the accuracy of state transitions during the oversampling process, an analog-to-digital conversion timing flag signal CONV_REGULAR_PLUS is used to extend the analog-to-digital conversion flag signal CONV_REGULAR. The analog-to-digital conversion timing flag signal is used to capture the rising edge of the analog-to-digital conversion flag signal.

[0027] The third counter is used to receive the oversampling end time pulse signal transmitted by the second trigger. When the oversampling end time pulse signal is at a low level, it counts to obtain a second count value and transmits the second count value to the fourth trigger. The fourth trigger is used to receive the second count value transmitted by the third counter and output an oversampling end flag signal according to the second count value and the preset oversampling number threshold.

[0028] In some embodiments of this application, the oversampling end flag signal output by the fourth flip-flop is transmitted to the first counter and the second flip-flop. The counting process of the first counter is affected by the oversampling end flag signal. When the oversampling enable signal is in a high-level state (i.e., the oversampling function is enabled), the oversampling end flag signal is in a high-level state (i.e., indicating the end of oversampling), and the current first count value is equal to the pre-configured analog-to-digital converter conversion sequence length value, the first counter is controlled to clear the first count value to zero. Similarly, the level of the oversampling end pulse signal output by the second trigger is also affected by the sampling end flag signal. When the analog-to-digital conversion flag signal is low, the oversampling end pulse signal output by the second trigger is low. When the analog-to-digital conversion flag signal is high, if the first count value is equal to the pre-configured analog-to-digital conversion sequence length value and the oversampling end flag signal is high, the oversampling end pulse signal output by the second trigger is high. Otherwise, if the first count value is not equal to the pre-configured analog-to-digital conversion sequence length value and / or the oversampling end flag signal is low, the oversampling end pulse signal output by the second trigger maintains the level state it was at during the last output.

[0029] In some embodiments of this application, the third counter is further configured to receive a first sampling end flag signal ECO_PLUS, and the third counter is further configured to receive a second count value output by itself. Specifically, the first sampling end flag signal is used to indicate the rising edge of the signal at the end of the sampling of the analog circuit. When the first sampling end flag signal is in a high-level state (i.e., the rising edge of the signal at the end of the sampling of the analog circuit is captured at the current moment) and the oversampling enable signal is in a high-level state (i.e., the oversampling function is enabled), the second count value received by the third counter at the current moment (i.e., the current second count value) is equal to the sum of the preset oversampling number threshold and the number 1 as the counting control condition. It can be understood that, under the premise that the first sampling end flag signal is in a high-level state and the oversampling enable signal is in a high-level state, when the current second count value is equal to the sum of the preset oversampling number threshold and the number 1, the third counter is controlled to set the current second count value to zero. Conversely, when the current second count value is not equal to the sum of the preset oversampling number threshold and the number 1, the third counter is controlled to count when the pulse signal at the end of the oversampling moment is at a low level, and the third counter is controlled to output the same second count value as the previous moment when the pulse signal at the end of the oversampling moment is at a high level.

[0030] In some embodiments of this application, the sampling of the analog circuit in the successive approximation analog-to-digital converter includes an analog circuit sampling start time signal SOC and an analog circuit sampling end time signal EOC. The analog circuit sampling start time signal SOC and the analog circuit sampling end time signal EOC are in opposite levels. When the analog circuit sampling start time signal SOC is in a high level state, it means that the analog circuit can start sampling the externally input analog signal. At this time, the analog circuit sampling end time signal EOC is in a low level state. Conversely, when the analog circuit sampling start time signal SOC is in a low level state and the analog circuit sampling end time signal EOC is in a high level state, it means that the analog circuit has ended sampling the externally input analog signal. To make the control nodes of the data oversampling process more precise, this application extends the use of the analog circuit sampling end time delay signal EOC_D and the first sampling end flag signal ECO_PLUS, based on the analog circuit sampling end time signal EOC. The analog circuit sampling end time delay signal EOC_D is the signal obtained by delaying the analog circuit sampling end time signal EOC for one clock cycle at the rising edge of the successive approximation analog-to-digital converter's operating clock. The first sampling end flag signal ECO_PLUS is the AND logic result of the analog circuit sampling end time signal EOC and the analog circuit sampling end time delay signal EOC_D, and is used to indicate the captured rising edge of the analog circuit sampling end time signal EOC.

[0031] In some embodiments of this application, the provided successive approximation analog-to-digital converter (ADC) includes a reversible timer (CNTR). This reversible timer is used to calculate the time interval between two ADC samples, and the calculation of the time interval is based on the rising edge of the ADC's operating clock. For example... Figure 3 As shown, the oversampling conversion process of the successive approximation analog-to-digital converter (ADC) can be represented by three states: the first state indicates the start of the conversion process, the second state indicates the conversion is in progress, and the third state indicates the end of the conversion process. If the ADC is in the first state, when the count value of the reversible counter reaches a preset time interval threshold, the ADC transitions from the first state to the second state. If the ADC is in the second state, when the analog-to-digital conversion flag signal is low, the ADC transitions from the second state to the third state; when the first sampling end flag signal, the analog-to-digital conversion flag signal, and the oversampling end flag signal are all high, the ADC transitions from the second state to the first state. If the ADC is in the third state, when the analog-to-digital conversion time flag signal is high (i.e., the rising edge of the analog-to-digital conversion flag signal is captured), the ADC transitions from the third state to the first state.

[0032] In some embodiments of this application, the fourth flip-flop is further configured to receive a first sampling end flag signal ECO_PLUS. The first sampling end flag signal affects the level of the oversampling end flag signal output by the fourth flip-flop; when both the first sampling end flag signal and the oversampling enable signal are at a high level, the level of the oversampling end flag signal output by the fourth flip-flop is controlled by the second count value currently received by the fourth flip-flop and a preset oversampling count threshold. Specifically, when the second count value currently received by the fourth flip-flop is equal to the preset oversampling count threshold, the oversampling end flag signal output by the fourth flip-flop is at a high level; conversely, when the second count value currently received by the fourth flip-flop is not equal to the preset oversampling count threshold, the oversampling end flag signal output by the fourth flip-flop is at a low level.

[0033] In some embodiments of this application, such as Figure 2 As shown, the shift circuit includes at least a fifth accumulator, a sixth flip-flop, and a seventh shift register. Specifically, the fifth accumulator, the sixth flip-flop, and the seventh shift register each receive an analog-to-digital converter (ADC) clock signal, an oversampling enable signal, and a reset signal. The ADC clock signal provides a stable time interval signal, ensuring that each counter and flip-flop samples at the same time point, such as sampling at the rising edge of the ADC clock signal. The oversampling enable signal indicates whether the oversampling function is enabled or disabled. When the oversampling enable signal is high, the oversampling function is enabled; conversely, when the oversampling enable signal is low, the oversampling function is disabled. The reset signal indicates whether the reset function is enabled or disabled. When the reset signal is high, the reset function is enabled, resetting the count values ​​of each counter and the level of the signals output by each flip-flop; conversely, when the reset signal is low, the reset function is disabled.

[0034] Specifically, the fifth accumulator receives the digital signal after analog-to-digital conversion and performs summation on the received digital signal to obtain an accumulated digital signal. The fifth accumulator then transmits the acquired accumulated digital signal to the sixth flip-flop. The number of times the fifth accumulator performs summation on the received digital signal is equal to a preset oversampling threshold. By limiting the number of summations performed by the fifth accumulator, the validity of the output accumulated digital signal is avoided due to the accumulation of excess digital signals. The sixth flip-flop receives the accumulated digital signal transmitted by the fifth accumulator, filters out the final accumulated digital signal from the received accumulated digital signal, and transmits the final accumulated digital signal to the seventh shift register. The seventh shift register receives the final accumulated digital signal transmitted by the sixth flip-flop with a pre-configured bit width, performs shift processing on the final accumulated digital signal according to the pre-configured bit width, enabling the final accumulated digital signal to achieve amplification or reduction based on the shift. The seventh shift register then transmits the shifted final accumulated digital signal to the corresponding data register for storage, so that the central processing unit can read it. Preferably, the seventh shift register has a pre-configured bit width for shifting and adjusting the digital signal. The pre-configured bit width can be, but is not limited to, 0, 1, 2, 3, etc. In some embodiments of this application, the pre-configured bit width is limited to less than or equal to the logarithm of the sum of a preset oversampling threshold (base 2) and a digit 1.

[0035] In some embodiments of this application, the fifth accumulator is further configured to receive a first sampling end flag signal and a second count value output by the third counter in the oversampling rate counting circuit. Specifically, the first sampling end flag signal and the second count value affect the digital signal accumulation process of the fifth accumulator. When the first sampling end flag signal is at a high level, if the second count value currently received by the fifth accumulator is equal to the sum of a preset oversampling number threshold and the number 1, it indicates the end of one oversampling process. The accumulated digital signal output by the fifth accumulator at this time is equal to the analog-to-digital converted digital signal received by the fifth accumulator at this time.

[0036] In some embodiments of this application, the sixth flip-flop is further configured to receive a first sampling end flag signal and a second count value output by a third counter in the oversampling rate counting circuit. Specifically, the filtering of the accumulated digital signal by the sixth flip-flop is affected by the level state of the first sampling end flag signal and the magnitude of the second count value; the triggering condition for the sixth flip-flop to filter the final accumulated digital signal from the accumulated digital signal is: when the first sampling end flag signal is at a low level and the second count value is equal to the sum of a preset oversampling number threshold and the digit 1, the accumulated digital signal at this moment is filtered to output the final accumulated digital signal.

[0037] This application provides a chip in some embodiments that includes the successive approximation analog-to-digital converter. This chip implements an oversampling and shifting function for the original converted data of the successive approximation analog-to-digital converter, making the oversampling process entirely hardware-based, eliminating the need to wait for upper-layer software to perform oversampling, reducing resource consumption on the central processing unit (CPU), lowering the CPU's computational load, and improving oversampling and shifting efficiency.

[0038] In the embodiments provided by this invention, it should be understood that the disclosed chips and circuits can be implemented in other ways. For example, the chip and circuit embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another module, or some features may be ignored or not executed.

[0039] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions or improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A successive approximation analog-to-digital converter, characterized in that, The successive approximation analog-to-digital converter includes an oversampling rate counting circuit and a shift circuit; wherein, the oversampling rate counting circuit calculates the oversampling rate by counting based on the analog-to-digital conversion sequence length value configured in the register, and the shift circuit is used to perform summation and shifting processing on the digital signal after analog-to-digital conversion; The oversampling rate counting circuit includes: a first counter, a second flip-flop, a third counter, and a fourth flip-flop; wherein, The first counter is used to receive a pre-configured analog-to-digital conversion sequence length value, count the length of the analog-to-digital converter conversion sequence to obtain a first count value, and transmit the first count value to the second trigger. The second trigger is used to receive the analog-to-digital conversion flag signal and the first count value, and output the oversampling end pulse signal to the third counter according to the analog-to-digital conversion flag signal and the first count value; The third counter is used to receive the pulse signal at the end of the oversampling time, and counts when the pulse signal at the end of the oversampling time is at a low level to obtain the second count value, and then transmits the second count value to the fourth flip-flop; The fourth trigger is used to receive the second count value and output an oversampling end flag signal according to whether the second count value is equal to the preset oversampling number threshold. The shift circuit includes: a fifth accumulator, a sixth flip-flop, and a seventh shift register; wherein, The fifth accumulator is used to receive the digital signal after analog-to-digital conversion, and to accumulate and sum the received digital signal to obtain the accumulated digital signal and transmit it to the sixth flip-flop. The sixth flip-flop is used to receive the accumulated digital signal transmitted by the fifth accumulator, and to filter out the final accumulated digital signal from the received accumulated digital signal and transmit the final accumulated digital signal to the seventh shift register. The seventh shift register is used to receive the final accumulated digital signal transmitted by the pre-configured bit width and the sixth flip-flop, perform shift processing on the final accumulated digital signal according to the pre-configured bit width, and output the shifted final accumulated digital signal to the corresponding data register for storage, so that the central processing unit can read it. The first counter, second flip-flop, third counter, fourth flip-flop, fifth accumulator, sixth flip-flop, and seventh shift register respectively receive the analog-to-digital converter (ADC) clock signal, oversampling enable signal, and reset signal. The ADC clock signal is used to unify the sampling time points of the first counter, second flip-flop, third counter, fourth flip-flop, fifth accumulator, sixth flip-flop, and seventh shift register. The oversampling enable signal is used to indicate whether the oversampling function is enabled or disabled. The reset signal is used to control whether the reset function is enabled or disabled.

2. The successive approximation analog-to-digital converter according to claim 1, characterized in that, The first counter is also used to receive the oversampling end flag signal output by the fourth flip-flop; when the oversampling enable signal is in a high level state, the oversampling end flag signal is in a high level state, and the first count value is equal to the pre-configured analog-to-digital conversion sequence length value, the first counter will reset the first count value to zero.

3. The successive approximation analog-to-digital converter according to claim 2, characterized in that, The second flip-flop is also used to receive the oversampling end flag signal output by the fourth flip-flop; when the analog-to-digital conversion flag signal is in a low-level state, the oversampling end time pulse signal output by the second flip-flop is in a low-level state; when the analog-to-digital conversion flag signal is in a high-level state, if the first count value is equal to the pre-configured analog-to-digital conversion sequence length value and the oversampling end flag signal is in a high-level state, then the oversampling end time pulse signal output by the second flip-flop is in a high-level state; otherwise, if the first count value is not equal to the pre-configured analog-to-digital conversion sequence length value and / or the oversampling end flag signal is in a low-level state, the oversampling end time pulse signal output by the second flip-flop maintains the level state it was in during the last output.

4. The successive approximation analog-to-digital converter according to claim 3, characterized in that, The third counter is also used to receive the first sampling end flag signal, and the third counter is also used to receive the second count value output by itself; the first sampling end flag signal is used to indicate the rising edge of the signal at the end of sampling of the capture analog circuit; when the first sampling end flag signal is in a high level state and the oversampling enable signal is in a high level state, it is determined whether the current second count value is equal to the sum of the preset oversampling number threshold and the number 1. If yes, the third counter sets the current second count value to zero. If no, the third counter counts when the oversampling end pulse signal is in a low level state, and outputs the same second count value as the previous time when the oversampling end pulse signal is in a high level state.

5. The successive approximation analog-to-digital converter according to claim 4, characterized in that, The fourth flip-flop is also used to receive the first sampling end flag signal; when the first sampling end flag signal is in a high level state and the oversampling enable signal is in a high level state, it determines whether the current second count value is equal to the preset oversampling number threshold. If yes, the oversampling end flag signal output by the fourth flip-flop is in a high level state; if no, the oversampling end flag signal output by the fourth flip-flop is in a low level state.

6. The successive approximation analog-to-digital converter according to claim 5, characterized in that, The fifth accumulator performs summation calculations on the received analog-to-digital converted digital signals a number of times equal to a preset oversampling threshold.

7. The successive approximation analog-to-digital converter according to claim 6, characterized in that, The fifth accumulator is also used to receive the second count value and the first sampling end flag signal; when the first sampling end flag signal is in a high level state and the second count value is equal to the sum of the preset oversampling number threshold and the number 1, the accumulated digital signal output by the fifth accumulator is equal to the received analog-to-digital converted digital signal.

8. The successive approximation analog-to-digital converter according to claim 7, characterized in that, The sixth trigger is also used to receive the second count value and the first sampling end flag signal; when the first sampling end flag signal is in a low level state and the second count value is equal to the sum of the preset oversampling number threshold and the number 1, the sixth trigger filters the accumulated digital signal received at this time point into the final accumulated digital signal.

9. The successive approximation analog-to-digital converter according to claim 8, characterized in that, The pre-configured bit width is less than or equal to the logarithm of the sum of a preset oversampling threshold (base 2) and a base 1.

10. A chip, characterized in that, The chip includes a successive approximation analog-to-digital converter as described in any one of claims 1 to 9.

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