A single-bit multi-bit hybrid ADC ultra-wideband receiver
By designing a single Bit Dorti -Bit hybrid ADC ultra -broadband receiver in the UWB system, using the single -bit mode to reduce the capture stage power consumption, and processing the entire bit data after completing the capture, it is difficult to achieve the single -bit receiver at high sampling frequency. The problem of quantification of high -bit has improved the ranging accuracy and communication capabilities of the UWB system.
Patent Information
- Application Number
- CN202211093685.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-09-08
- Publication Date
- 2025-01-24
- Estimated Expiration
- 2042-09-08
AI Technical Summary
In existing UWB systems, it is difficult for single-bit receivers to achieve high bit quantization at high sampling frequency, resulting in limited ranging accuracy and communication capabilities, which has become a bottleneck in performance breakthroughs.
Design a single-bit multi-bit hybrid ADC ultra-wideband receiver that periodically samples the I/Q signal through an analog-to-digital converter, outputs multi-bit complex signals, and uses single-bit mode for digital processing during the signal capture stage to reduce power consumption. After acquisition is completed, the receiver processes the full bit data to ensure channel estimation and arrival time estimation performance.
Combined with the advantages of single -bit and Dobit receiving machines, the system power consumption of the capture phase is reduced, while ensuring good channel estimates and arrival time estimation performance, which improves the range accuracy and communication capabilities of the UWB system.
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Figure CN116318211B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of ultra-wideband positioning, and in particular to a single-bit and multi-bit hybrid ADC ultra-wideband receiver. Background Art
[0002] The ultra-wideband (UWB) system is a communication system that uses nanosecond pulses as symbols. Due to its short pulses and large bandwidth, it has an excellent ability to distinguish multipath signals. In complex environments such as indoors, it can accurately measure the flight time of electromagnetic waves and perform high-precision ranging and positioning.
[0003] Since the bandwidth of UWB system is generally above 500MHz, the receiver analog-to-digital converter (ADC) uses a frequency of at least Nyquist sampling frequency, that is, 1GHz. It is difficult to quantize high bits when the ADC is required to work at such a high sampling frequency. In the previous mainstream chip solutions, the 1G sampling rate single-bit receiver solution was basically adopted. Single-bit receivers have been widely used and verified in the market. However, with the development of technology and applications, UWB systems are expected to obtain more accurate ranging capabilities and higher communication capabilities, and single-bit receivers have become the main bottleneck for performance breakthroughs.
[0004] The mainstream parameters currently used by multi-bit receivers are 7- to 8-bit quantization at a 2G sampling rate. Thanks to technological advances, this has become technically feasible. Improved ADC performance helps UWB obtain more accurate channel estimation and arrival time estimation, but it will lead to higher computational complexity and power consumption. Summary of the invention
[0005] The technical problem to be solved by the present invention is to provide a single-bit multi-bit hybrid ADC ultra-wideband receiver, which can ensure good channel estimation and arrival time estimation performance.
[0006] The technical solution adopted by the present invention to solve the technical problem is: to provide a single-bit multi-bit hybrid ADC ultra-wideband receiver, comprising:
[0007] The analog-to-digital converter is used to periodically sample the I / Q signal and output a multi-bit complex signal, wherein the first bit of the multi-bit complex signal is a sign bit;
[0008] The input end of the signal capture module is connected to the output end of the analog-to-digital converter through a single-bit data line to determine whether an ultra-wideband preamble code is sent, and the single-bit data line is used to transmit the first bit of the multi-bit complex signal;
[0009] The enable end of the signal tracking module is connected to the output end of the signal capture module, and the input end is connected to the output end of the analog-to-digital converter through a multi-bit data line, for tracking and estimating the ultra-wideband preamble and data signal; the multi-bit data line is used to transmit the multi-bit complex signal in parallel in sequence;
[0010] In the initial state, the signal capture module is in the on state and the signal tracking module is in the off state; when the signal capture module determines that the ultra-wideband preamble code exists, the signal capture module outputs an enable signal to the signal tracking module, so that the signal tracking module is turned on and the signal capture module is turned off at the same time.
[0011] The signal capture module comprises:
[0012] A correlation peak acquisition unit, used to perform a despreading operation by correlating with the preamble sequence to obtain a correlation peak;
[0013] A correlation peak processing unit, used for processing the correlation peak to obtain a correlation peak value;
[0014] A decision unit is used to determine whether an ultra-wideband preamble code exists according to the correlation peak value.
[0015] The correlation peak acquisition unit includes a first buffer, a downsampler and a first correlator, the input end of the first buffer is connected to the output end of the analog-to-digital converter, the output end is connected to the input end of the downsampler, the output end of the downsampler is connected to the first input end of the first correlator, the second input end of the first correlator is connected to the preamble code sequence, and the output end is connected to the correlation peak processing unit.
[0016] The correlation peak processing unit includes a second buffer, a delayer and a second correlator; the input end of the second buffer is connected to the output end of the correlation peak acquisition unit, and the output end is divided into two paths, one path is connected to the first input end of the second correlator through the delayer, and the other path is directly connected to the second input end of the second correlator; the output end of the second correlator is connected to the input end of the decision unit; the delayer delays one sampling period.
[0017] The correlation peak processing unit includes a second buffer, a first delay, a 1-bit multiplier, a second delay and an accumulator, the input end of the second buffer is connected to the output end of the correlation peak acquisition unit, and the output end is divided into two paths, one path is connected to the first input end of the 1-bit multiplier through the delay, and the other path is directly connected to the second input end of the 1-bit multiplier; the output end of the 1-bit multiplier is divided into two paths, one path is directly connected to the first input end of the accumulator, and the other path is connected to the second input end of the accumulator through the second delay, and the output end of the accumulator is connected to the input end of the decision unit; the output end of the accumulator is also fed back to the third input end of the accumulator; the first input end and the third input end of the accumulator are plus input ends, and the second input end is a minus input end; the first delay delays one sampling cycle, and the second delay delays eight sampling cycles.
[0018] Beneficial Effects
[0019] Due to the adoption of the above-mentioned technical scheme, the present invention has the following advantages and positive effects compared with the prior art: the present invention combines the respective advantages of single-bit and multi-bit receivers, and greatly reduces the system power consumption in the capture stage by adopting a single-bit mode for digital processing in the signal capture stage, while the power consumption in the capture stage accounts for a large part of the overall power consumption of the system. After the capture is completed, the receiver starts to process the full-bit data output by the ADC, thereby ensuring good channel estimation and arrival time estimation performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 It is a schematic structural diagram of an embodiment of the present invention;
[0021] Figure 2 is a structural diagram of a signal acquisition module in an embodiment of the present invention;
[0022] Figure 3 It is a structural diagram of another correlation peak processing unit in an embodiment of the present invention. DETAILED DESCRIPTION
[0023] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only intended to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art may make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.
[0024] The embodiment of the present invention relates to a single-bit multi-bit hybrid ADC ultra-wideband receiver, comprising: an analog-to-digital converter for periodically sampling an I / Q signal and outputting a multi-bit complex signal, wherein the first bit in the multi-bit complex signal is a sign bit; the input end of a signal capture module is connected to the output end of the analog-to-digital converter via a single-bit data line, and is used to determine whether an ultra-wideband preamble is sent; an enable end of a signal tracking module is connected to the output end of the signal capture module, and the input end is connected to the output end of the analog-to-digital converter via a multi-bit data line, and is used to track and estimate the ultra-wideband preamble and data signal. The single-bit data line is used to transmit the first bit in the multi-bit complex signal; and the multi-bit data line is used to transmit the multi-bit complex signal in sequence and in parallel.
[0025] like Figure 1 As shown, for a zero intermediate frequency receiver, the I channel and the Q channel are each periodically sampled by an ADC to output a multi-bit complex signal, wherein the first bit in the multi-bit complex signal is a sign bit. In the initial state, the signal capture module is in an on state and the signal tracking module is in an off state. The signal capture module processes the single-bit ADC data to determine whether a UWB preamble code is sent. If the preamble code is detected, the signal tracking module is immediately enabled and the signal capture module is turned off. The signal tracking module processes the full-bit data of the ADC to achieve continuous tracking and estimation of the preamble code and data signal, and completes functions such as channel estimation, arrival time estimation, and data demodulation.
[0026] In this implementation, the signal acquisition module includes: a correlation peak acquisition unit, used to perform a despreading operation by correlation with the preamble sequence to obtain a correlation peak; and a correlation peak processing unit, used to process the correlation peak to obtain a correlation peak value.
[0027] The correlation peak acquisition unit includes a first buffer, a downsampler and a first correlator, wherein the input end of the first buffer is connected to the output end of the analog-to-digital converter, the output end is connected to the input end of the downsampler, the output end of the downsampler is connected to the first input end of the first correlator, the second input end of the first correlator is connected to the preamble sequence, and the output end is connected to the correlation peak processing unit. The first buffer is used to output the number of sample points of a UWB symbol at the sampling rate of the analog-to-digital converter; the downsampler is used to downsample the number of sample points output by the first buffer to obtain sample points with the same length as the preamble sequence; the first correlator is used to perform correlation operation on the sample points output by the downsampler and the preamble sequence to complete the despreading operation.
[0028] The correlation peak processing unit includes a second buffer, a delayer, and a second correlator; the input end of the second buffer is connected to the output end of the correlation peak acquisition unit, and the output end is divided into two paths, one path is connected to the first input end of the second correlator through the delayer, and the other path is directly connected to the second input end of the second correlator; the output end of the second correlator is connected to the input end of the decision unit; the delayer delays one sampling cycle. The second buffer is used to output the first-level correlator output of a UWB symbol with a buffer length of N times the number of sample points at the sampling rate of the analog-to-digital converter. The second correlator is used to perform a correlation operation on the output of the second buffer and the output of the second buffer after being delayed by the delayer.
[0029] Figure 2The structure diagram of the signal capture module is shown in FIG. Among them, the solid arrow represents the 1G frequency, the dotted arrow represents the 1M frequency, the C in the bracket represents a complex number, and the R in the bracket represents a real number. After the UWB signal passes through the 1GHz sampling rate ADC, it passes through the buffer and outputs 992 1-bit (992 corresponds to the number of sample points of 1 UWB symbol at a 1GHz sampling rate) sample points. Since it is IQ two-way sampling, it is a complex number, and the output frequency is still 1G. The output at the next moment is the output at the previous moment shifted by one sampling point. The downsampling module extracts 992 samples to obtain 31 sample points (31 is the length of the preamble sequence used. According to the UWB specification 802.15.4, the preamble sequence length can be 31 or 127), and is correlated with the preamble sequence to complete the despreading operation. If there is a preamble code, a correlation peak should be obtained here. When the signal-to-noise ratio is not ideal, the correlation peak may be submerged by noise and difficult to identify. Considering that the UWB preamble code symbol is sent periodically, the received channel impulse response signal will also be repeated periodically. The 1GHz complex result output by the first-level correlator is sent to the cache again. The length of the cache is 992*N, where N is a natural number greater than 1. The larger the N configuration, the higher the correlation gain. However, the frequency deviation that may exist at both ends of the transmitter and receiver will cause the sampling deviation to be non-negligible. For a 20ppm frequency difference between the transmitter and receiver, N can be 8 or 16. At this time, the sampling deviation between each UWB symbol can be ignored. The frequency of the buffer output is 992 times the sampling frequency of the ADC, which is about 1MHz. Each output is shifted by 992 sample points relative to the output sample at the previous moment. The 992*N sample point outputs at the current moment are correlated with the 992*N sample point outputs at the previous moment. Since there is only 1 bit of operation here, the overhead is very low. If there is a periodic preamble, an obvious correlation peak should be obtained here. The result of the correlator output is sent to the decision device to determine whether there is a preamble. If the decision is yes, the phase difference in the correlation result is the phase deviation value of 1 symbol apart, so that a relatively accurate frequency deviation estimate can be obtained. Then, the N symbols are phase rotated sample by sample and added to obtain an estimate of the channel impulse response. After the coarse capture process is completed, the signal tracking process begins.
[0030] Figure 2 The circuit shown by the dashed arrow can be realized in a simpler way. Figure 3As shown, the correlation peak processing unit in this embodiment can also be the following structure, that is, the correlation peak processing unit includes a second buffer, a first delay, a 1-bit multiplier, a second delay and an accumulator, the input end of the second buffer is connected to the output end of the correlation peak acquisition unit, and the output end is divided into two paths, one path is connected to the first input end of the 1-bit multiplier through the delay, and the other path is directly connected to the second input end of the 1-bit multiplier; the output end of the 1-bit multiplier is divided into two paths, one path is directly connected to the first input end of the accumulator, and the other path is connected to the second input end of the accumulator through the second delay, and the output end of the accumulator is connected to the input end of the decision unit; the output end of the accumulator is also fed back to the third input end of the accumulator; the first input end and the third input end of the accumulator are plus input ends, and the second input end is a minus input end; the first delay delays one sampling cycle, and the second delay delays eight sampling cycles. This structure changes the second correlator into a combination of a 1-bit multiplier, a second delay and an accumulator. Therefore, this structure does not need to perform correlation operations, but only needs to perform 1-bit multiplication and addition. Figure 2 The method in the above method has less computational effort.
[0031] This structure only needs to perform a 1-bit multiplication operation on the 992 sample points of the current UWB symbol and the 992 sample points of the previous UWB symbol. Each time the accumulator adds a new multiplication result and subtracts the previous 8th result to complete the accumulation. The amount of calculation is small. The amount of calculation for each UWB symbol time (about 1us) is: 992 1-bit complex multiplications and 993 complex additions. One advantage of this processing algorithm is that it can detect the existence of the preamble code at intervals of UWB symbols, and has good real-time performance.
[0032] It is not difficult to find that the present invention combines the respective advantages of single-bit and multi-bit receivers. By adopting the single-bit mode for digital processing in the signal capture stage, the system power consumption in the capture stage is greatly reduced. The power consumption in the capture stage accounts for a large part of the overall power consumption of the system. After the capture is completed, the receiver starts to process the full-bit data output by the ADC, ensuring good channel estimation and arrival time estimation performance.
Claims
1. A single-bit multi-bit hybrid ADC ultra-wideband receiver, characterized in that: include: The analog-to-digital converter is used to periodically sample the I / Q signal and output a multi-bit complex signal, wherein the first bit of the multi-bit complex signal is a sign bit; The input end of the signal capture module is connected to the output end of the analog-to-digital converter through a single-bit data line to determine whether an ultra-wideband preamble code is sent, and the single-bit data line is used to transmit the first bit of the multi-bit complex signal; The enable end of the signal tracking module is connected to the output end of the signal capture module, and the input end is connected to the output end of the analog-to-digital converter through a multi-bit data line, for tracking and estimating the ultra-wideband preamble and data signal; the multi-bit data line is used to transmit the multi-bit complex signal in parallel in sequence; In the initial state, the signal capture module is in the on state and the signal tracking module is in the off state; when the signal capture module determines that the ultra-wideband preamble code exists, the signal capture module outputs an enable signal to the signal tracking module, so that the signal tracking module is turned on and the signal capture module is turned off at the same time.
2. The single-bit multi-bit hybrid ADC ultra-wideband receiver according to claim 1, characterized in that: The signal capture module comprises: A correlation peak acquisition unit, used to perform a despreading operation by correlating with the preamble sequence to obtain a correlation peak; A correlation peak processing unit, used for processing the correlation peak to obtain a correlation peak value; A decision unit is used to determine whether an ultra-wideband preamble code exists according to the correlation peak value.
3. The single-bit multi-bit hybrid ADC ultra-wideband receiver according to claim 2, characterized in that: The correlation peak acquisition unit includes a first buffer, a downsampler and a first correlator, the input end of the first buffer is connected to the output end of the analog-to-digital converter, the output end is connected to the input end of the downsampler, the output end of the downsampler is connected to the first input end of the first correlator, the preamble code sequence is input to the second input end of the first correlator, and the output end of the first correlator is connected to the correlation peak processing unit.
4. The single-bit multi-bit hybrid ADC ultra-wideband receiver according to claim 2, characterized in that: The correlation peak processing unit includes a second buffer, a delayer and a second correlator; the input end of the second buffer is connected to the output end of the correlation peak acquisition unit, and the output end is divided into two paths, one path is connected to the first input end of the second correlator through the delayer, and the other path is directly connected to the second input end of the second correlator; the output end of the second correlator is connected to the input end of the decision unit; the delayer delays one sampling period.
5. The single-bit multi-bit hybrid ADC ultra-wideband receiver according to claim 2, characterized in that: The correlation peak processing unit includes a second buffer, a first delay, a 1-bit multiplier, a second delay and an accumulator, the input end of the second buffer is connected to the output end of the correlation peak acquisition unit, and the output end is divided into two paths, one path is connected to the first input end of the 1-bit multiplier through the delay, and the other path is directly connected to the second input end of the 1-bit multiplier; the output end of the 1-bit multiplier is divided into two paths, one path is directly connected to the first input end of the accumulator, and the other path is connected to the second input end of the accumulator through the second delay, and the output end of the accumulator is connected to the input end of the decision unit; the output end of the accumulator is also fed back to the third input end of the accumulator; the first input end and the third input end of the accumulator are plus input ends, and the second input end is a minus input end; the first delay delays one sampling cycle, and the second delay delays eight sampling cycles.
Citation Information
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