An inverter made of vertical organic transistors

Abstract

The present invention belongs to the field of semiconductor device physics, and discloses an inverter composed of a vertical organic transistor, the inverter includes a PMOS of a vertical structure and an NMOS of a vertical structure connected in series, the PMOS of the vertical structure includes a substrate, a bottom gate, a gate oxide layer, graphene on the surface of the gate oxide layer, an organic semiconductor layer DPPT-TT+N2200 on the upper layer of the graphene, and a source and drain Au of an evaporated electrode, and the NMOS of the vertical structure includes a substrate, a bottom gate, a gate oxide layer, graphene on the surface of the gate oxide layer, an organic semiconductor layer N2200+DPPT-TT on the upper layer of the graphene, and a source and drain Au of an evaporated electrode, and DPPT-TT+N2200 and N2200+DPPT-TT form a film by a pulling method. Compared with the inverter of the traditional horizontal structure, the present invention has a lower operating voltage.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor device physics, and in particular relates to an inverter composed of vertical organic transistors. Background Art

[0002] An inverter is a basic logic circuit, usually composed of a transistor and several resistors. Its function is to invert the input signal and output it, that is, if the input signal is high, the output is low; if the input signal is low, the output is high. Inverters are often used in digital circuits, such as in computer memory, to amplify and restore data signals in the memory, and also to amplify and drive signals in other circuits such as transistors. Inverters are one of the most basic units in logic circuits and the basis of various digital circuits.

[0003] Compared with traditional horizontal organic transistors, vertical organic field-effect transistors (VOFET) are smaller in size, which can effectively reduce the occupied area of ​​the transistor, thereby realizing the preparation of high-density integrated circuits. At the same time, the current switching capability is stronger, which can better meet the needs of high-performance computing, and can achieve lower voltage operation, thereby reducing power consumption and heat generation problems.

[0004] The application number is ZL201410442661X, which discloses an inverter based on a thin film transistor and provides a basic structure of the inverter. This structure is based on a traditional horizontal transistor, and an inverter based on a vertical structure has not yet been designed.

[0005] The application number is ZL2022102320530, which discloses a method for preparing a vertical organic transistor and provides a production method for a vertical organic transistor. The disadvantage of this manufacturing method is that when the organic matter is spin-coated, there will be organic matter on the source and drain electrodes, which reduces the contact of graphene in the device structure and curbs the performance of the transistor. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides an inverter, which is designed to be composed of vertical organic transistors.

[0007] In order to achieve the above object, the present invention is achieved through the following technical solutions:

[0008] The present invention is an inverter composed of vertical organic transistors, including a vertical structure PMOS and a vertical structure NMOS connected in series, wherein the PMOS and NMOS have basically the same structure and both include a substrate SiO 2 , bottom gate Si, gate oxide SiO 2, graphene on the surface of the gate oxide layer, and the semiconductor layer DPPT-TT+N2200 (PMOS) or N2200+DPPT-TT (NMOS) on the graphene, and finally the source and drain electrodes Au are evaporated. In the vertical structure PMOS, the DPPT-TT+N2200 organic matter is formed into a film by pulling, and in the vertical structure NMOS, the N2200+DPPT-TT organic matter is formed into a film by pulling.

[0009] Furthermore, the PMOS and NMOS are vertical structure organic transistors.

[0010] Furthermore, the substrate is a silicon wafer covered with an oxide layer.

[0011] Furthermore, the graphene is single-layer graphene.

[0012] Furthermore, the organic semiconductor layer is: DPPT-TT+N2200 for PMOS, and N2200+DPPT-TT for NMOS, with a film thickness of about 50 nm.

[0013] Furthermore, the source and drain electrodes are made of metal Au with a thickness of about 30 nm.

[0014] The beneficial effects of the present invention are:

[0015] The inverter formed by the vertical PMOS and NMOS of the present invention has a lower operating voltage of about 5-55mv compared with the traditional horizontal inverter.

[0016] The vertical structure PMOS and NMOS of the present invention are easier to prepare ultra-short channels without using a photolithography machine. Generally, without the aid of a photolithography machine, the channel formed by thermal evaporation using a mask plate is about 50-100 microns, while the vertical channel of the method of the present invention is about 50nm.

[0017] The present invention uses the pulling method instead of the spin coating method. Compared with the prior art, the present invention has made some optimizations in the preparation process, which can avoid direct contact between organic matter and the source of the device, so that the movement of charges is completely moved through graphene, thereby improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the inverter structure of the present invention.

[0019] Figure 2 It is a schematic diagram of the inverter circuit structure of the present invention.

[0020] Figure 3Schematic diagram of graphene transfer to SiO2 / heavily doped Si substrate. a is copper-based graphene, b is spin coating PMMA on the copper-based graphene surface, and c is graphene transfer to SiO2 / heavily doped Si substrate. 2 / Si substrate, d is the PMMA removed from the sample surface.

[0021] Figure 4 Figure 2 shows the surface of graphene etched with plasma. a shows the PMMA residue on the graphene surface before plasma is used, and b shows the PMMA on the graphene surface after plasma is used.

[0022] Figure 5 It is to pull P-type organic matter and N-type organic matter. Among them, a is to pull N-type organic matter N2200+DPPT-TT to prepare NMOS, and b is to pull P-type organic matter DPPT-TT+N2200 to prepare PMOS.

[0023] Figure 6 Schematic diagram of evaporation deposition of source and drain electrodes. a is the evaporation deposition of source and drain electrodes on an N-type sample, and b is the evaporation deposition of source and drain electrodes on a P-type sample. DETAILED DESCRIPTION

[0024] The following will disclose the embodiments of the present invention with drawings. For the purpose of clear description, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is to say, in some embodiments of the present invention, these practical details are not necessary.

[0025] like Figure 1-2 As shown, the present invention is an inverter composed of vertical organic transistors, including a vertical PMOS and a vertical NMOS, the vertical PMOS and the vertical NMOS are connected in series, the vertical PMOS includes a substrate, a bottom gate, a gate oxide layer, graphene on the surface of the gate oxide layer, an organic semiconductor layer DPPT-TT+N2200 on the upper layer of the graphene, and a source and drain Au deposited; the vertical NMOS includes a substrate, a bottom gate, a gate oxide layer, graphene on the surface of the gate oxide layer, an organic semiconductor layer N2200+DPPT-TT on the upper layer of the graphene, and a source and drain Au deposited. The DPPT-TT+N2200 organic matter is formed into a film by a pulling method, and the N2200+DPPT-TT organic matter is formed into a film by a pulling method, and the film thickness is about 50nm, the graphene is a single-layer graphene, the substrate is a silicon wafer covered with an oxide layer, the bottom gate is Si, and the gate oxide layer is SiO 2 , the source and drain are metal Au with a thickness of 30nm.

[0026] The specific steps of the preparation process of the inverter composed of vertical organic transistors of the present invention are as follows:

[0027] Step 1: Prepare the etching solution FeCl 3 :Weigh 10g of FeCl 3 Put the powder into a glass container and pour 50 ml of deionized water into the glass container to dissolve the FeCl 3 .

[0028] Step 2: Prepare PMMA solution (40 mg / ml): Weigh 400 mg of PMMA solid and put it into a glass bottle, then put it into a nitrogen environment glove box, inject 10 ml of NBA solvent into the glass bottle in the glove box, and then heat it on a heating table at 80°C for 24 hours to complete the preparation of 40 mg / ml PMMA solution.

[0029] Step 3: Spin-coat PMMA on the copper-based graphene surface. Figure 3 (b) First, cut a copper-based graphene of appropriate size and fix it on a glass sheet, then put it into a nitrogen environment glove box. In the glove box, fix the glass sheet with copper-based graphene on a spin coater, and then spin coat PMMA at 500 rpm for 10 seconds, then spin coat PMMA at 1500 rpm for 20 seconds. The concentration of PMMA is 40 mg / ml. After spin coating, heat at 100°C for 10 minutes to solidify the PMMA film.

[0030] Step 4: Graphene transfer on copper substrate. Figure 3 (c) First, the copper base on the copper-based graphene needs to be removed. At this time, the sample is placed in FeCl 3 The specific steps are as follows: prepare two glass culture dishes, each containing FeCl 3 Pinch a corner of the copper-based graphene with PMMA spin-coated on it with tweezers and gently place the sample on the surface of a petri dish solution, with the back side in contact with FeCl 3 After 3 hours of corrosion, hold one corner of the sample with tweezers and lift the sample vertically out of the culture dish. Then use a plastic dropper to absorb FeCl 3 Solution, rinse the corroded side of the sample, rinse this side three times, the graphene and copper substrate on this side can be basically washed off; then clean the graphene with PMMA, the specific steps are as follows: use a glass slide to pick up the sample from bottom to top, put it in a petri dish filled with deionized water, and dilute the remaining FeCl3 solution. Repeat this process three times, each time using a glass slide to pick up the graphene film into new deionized water, soaking for 10 minutes each time, three times in a row to remove the FeCl3 solution. 3 The residue is basically removed. Finally, the etched graphene is transferred to the prepared SiO 2 / Si substrate, the specific steps are as follows: Use silicon dioxide / heavily doped silicon wafers to lift the graphene film from the bottom up, so that the graphene film is in the center of the sample. After the water is removed, keep the sample vertically and let the remaining water drip in one direction. Then place the sample nearly vertically on the water-absorbing material to allow the water on the surface of the sample and between the substrate and the graphene to dry naturally. After natural air drying, put the sample into a 90°C oven and heat it for about 1 hour. Make the graphene and the substrate fit tightly.

[0031] Step 5: Clean the PMMA on the graphene surface. Figure 3 (d) It is necessary to remove the PMMA film on the graphene surface. The specific steps are as follows: After the sample cools down, put the sample into acetone solution to remove PMMA. This process is repeated three times, and each time the new acetone is soaked for 30 minutes. If the acetone is heated to 50°C, the time can be reduced by half. Heating the acetone helps to completely remove the PMMA, but it may cause more graphene damage defects.

[0032] Step 6: Plasma etching of graphene. Figure 4 (b) PMMA residues on the graphene surface are etched using a plasma machine.

[0033] Step 7: Pull up the organic matter.

[0034] like Figure 5 (a) Pulling organic matter N2200+DPPT-TT to prepare NMOS. The specific operation steps are as follows: set the N2200 concentration to 7 mg / ml, the immersion speed to 12 mm / min, the pulling speed to 12 mm / min, the immersion time to 100 s, and the pulling interval to 300 s; set the DPPT-TT concentration to 3 mg / ml, the immersion speed to 12 mm / min, the pulling speed to 12 mm / min, the immersion time to 100 s, and the pulling interval to 300 s, then pre-anneal at 80 ° C for 5 min, anneal at 150 ° C for 2 h to complete the curing of the N2200+DPPT-TT film. The thickness of the N2200+DPPT-TT film is 50 nm.

[0035] like Figure 5(b) Pulling the material DPPT-TT+N2200 to prepare PMOS. The specific operation steps are as follows: first, set the concentration of DPPT-TT solution to 7 mg / ml, where the immersion speed is set to 12 mm / min, the pulling speed is set to 12 mm / min, the immersion time is 100 s, and the pulling interval is 300 s, then set the N2200 concentration to mg / ml, where the immersion speed is set to 12 mm / min, the pulling speed is set to 12 mm / min, the immersion time is 100 s, and the pulling interval is 300 s, then pre-anneal at 80 ° C for 5 minutes, and anneal at 150 ° C for 2 hours to complete the curing of the DPPT-TT+N2200 film. The thickness of the DPPT-TT+N2200 film is 50 nm.

[0036] Step 8: Source and drain metal evaporation deposition. Figure 6 , use an evaporator to evaporate and deposit metal source and drain electrodes through a mask plate. The material is Au with a thickness of 30nm.

[0037] The prepared vertical organic transistors are connected to form an inverter. Figure 6 As shown in (a), the prepared P-type vertical organic transistor is Figure 6 (b) is shown. The structure of the inverter is as follows: Figure 1 shown.

[0038] The inverter formed by the vertical structure of PMOS and NMOS in the present invention has a lower operating voltage of about 5-55mv, which provides a direction for the future research of inverters. Without using a photolithography machine, a 50-nanometer-level channel is prepared, which provides a direction for the research of short-channel inverters.

[0039] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. An inverter composed of vertical organic transistors, characterized in that: The inverter includes a vertical structure PMOS and a vertical structure NMOS, wherein the vertical structure PMOS and the vertical structure NMOS are connected in series, wherein: The vertical structure PMOS includes a substrate, a bottom gate, a gate oxide layer, graphene on the surface of the gate oxide layer, an organic semiconductor layer DPPT-TT+N2200 on the graphene layer, and a vapor-deposited source and drain Au; The vertical structure NMOS comprises a substrate, a bottom gate, a gate oxide layer, graphene on the surface of the gate oxide layer, an organic semiconductor layer N2200+DPPT-TT on the graphene layer, and a vapor-deposited source and drain Au.

2. An inverter composed of vertical organic transistors according to claim 1, characterized in that: In the vertical structure PMOS, DPPT-TT+N2200 organic matter is formed into a film by pulling method, and in the vertical structure NMOS, N2200+DPPT-TT organic matter is formed into a film by pulling method.

3. An inverter composed of vertical organic transistors according to claim 2, characterized in that: In the vertical structure PMOS, the film thickness of the organic semiconductor layer DPPT-TT+N2200 is 50 nm, and in the vertical structure NMOS, the film thickness of the organic semiconductor layer N2200+DPPT-TT is 50 nm.

4. The inverter composed of vertical organic transistors according to claim 1, characterized in that: The graphene is a single-layer graphene.

5. The inverter composed of vertical organic transistors according to claim 1, characterized in that: The substrate is a silicon wafer covered with an oxide layer, the bottom gate is Si, and the gate oxide layer is SiO2.

6. The inverter composed of vertical organic transistors according to claim 1, characterized in that: The source and drain electrodes are made of metal Au with a thickness of 30nm.

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