Capacitor assembly of array substrate, array substrate and manufacturing method and display panel

Abstract

This application provides a capacitor assembly for an array substrate, an array substrate, a manufacturing method thereon, and a display panel. The capacitor assembly includes: a first electrode layer and a second electrode layer spaced apart; at least a portion of the capacitor assembly has a rolled structure extending along a first direction, and the first electrode layer and the second electrode layer are respectively rolled up when projected onto a plane perpendicular to the first direction. By providing a capacitor assembly with a rolled structure, compared to a planar capacitor, the projected area of ​​the capacitor assembly on the array substrate can be reduced, improving the light transmittance of the array substrate and thus improving the display effect; furthermore, the rolled shape of the capacitor assembly can increase the area of ​​the first electrode layer and the second electrode layer, that is, further increase the capacitance of the capacitor assembly and improve the display effect of the array substrate.

Description

Technical Field

[0001] This application relates to the field of display device technology, and in particular to a capacitor assembly for an array substrate, an array substrate and its manufacturing method, and a display panel. Background Technology

[0002] Thin-film transistor array (TFT) driving circuits are a crucial component of high-resolution displays. In existing technologies, TFTs often employ thin-film capacitors, which are formed by sandwiching an insulating dielectric film between two conductive thin films in the TFT circuit. Thin-film capacitors are typically regular rectangular planes disposed on the substrate. Users usually increase the capacitance by increasing the area of ​​the thin-film capacitor, i.e., increasing the overlap area between the upper and lower conductive electrodes and the dielectric layer in the cross-sectional direction.

[0003] Increasing the area of ​​the thin-film capacitor can easily affect the light output of the array substrate, resulting in poor light transmittance of the array substrate and impacting the user experience. Summary of the Invention

[0004] This application provides a capacitor assembly for an array substrate, an array substrate, a manufacturing method thereof, and a display panel, to solve the technical problem of poor light transmittance of array substrates in the prior art.

[0005] On one hand, this application provides a capacitor assembly for an array substrate, the capacitor assembly comprising:

[0006] A first electrode layer and a second electrode layer are spaced apart;

[0007] At least a portion of the capacitor assembly is a coiled structure that extends along a first direction, and the first electrode layer and the second electrode layer are respectively coiled when projected onto a plane perpendicular to the first direction.

[0008] In one possible implementation of this application, the capacitor assembly has a fixed end and a free end, the free end having a tendency to curl toward the fixed end, the free end abutting against the fixed end.

[0009] In one possible implementation of this application, the capacitor assembly includes:

[0010] A first curled layer is disposed between the first electrode layer and the second electrode layer, and the first curled layer covers the first electrode layer;

[0011] The second curled layer is disposed on the side of the second electrode layer away from the first curled layer;

[0012] The third curled layer is disposed on the side of the first electrode layer away from the first curled layer;

[0013] A sacrificial layer is disposed on the side of the third coiled layer away from the first electrode layer.

[0014] In one possible implementation of this application, the materials of the first crimped layer, the second crimped layer, and the third crimped layer each independently include at least one of aluminum oxide, silicon nitride, silicon oxide, silicon oxynitride, titanium dioxide, hafnium dioxide, zinc oxide, magnesium oxide, and zirconium oxide; and / or

[0015] The sacrificial layer is made of at least one of polyimide, phenolic resin, isobutyl methacrylate, polyacrylamide, and cinnamic acid ester; and / or

[0016] The materials of the first electrode layer and the second electrode layer each independently include at least one of indium tin oxide, indium zinc oxide, 3,4-ethylenedioxythiophene monomer, aluminum, molybdenum, titanium, copper, silver, and gold; and / or

[0017] The thicknesses of the first curled layer, the second curled layer, and the third curled layer are each independently 0.02µm to 1µm; and / or

[0018] The thickness of the sacrificial layer is 0.01µm to 1µm; and / or

[0019] The thickness of the first electrode layer and the second electrode layer is 50nm~300nm.

[0020] In one possible implementation of this application, at least a portion of the capacitor assembly is cylindrical, the cylinder having a hollow inner cavity with a diameter of 0.1 μm to 5.5 μm.

[0021] On the other hand, this application also provides an array substrate, the array substrate comprising:

[0022] Substrate;

[0023] A thin-film transistor disposed on the substrate;

[0024] A common electrode line is disposed on the substrate and spaced apart from the thin-film transistor;

[0025] A planarization layer covering the thin-film transistor and the common electrode line;

[0026] As described above, the capacitor assembly is disposed on the planarization layer, the first electrode layer is electrically connected to the common electrode line, and the second electrode layer is electrically connected to the first electrode in the thin-film transistor.

[0027] In one possible implementation of this application, the array substrate further includes:

[0028] A pixel defining layer extends along the first direction and is disposed on the planarization layer and covers the capacitor assembly, with two adjacent pixel defining layers defining an opening;

[0029] A pixel electrode is disposed in the opening and is electrically connected to the first electrode.

[0030] In one possible implementation of this application, the area ratio of the capacitor assembly in the pixel defining layer is less than or equal to 80% in a cross section perpendicular to the first direction.

[0031] On the other hand, this application also provides a method for manufacturing an array substrate, comprising:

[0032] Provide array substrate preforms;

[0033] A capacitor assembly is formed on the array substrate preform. The capacitor assembly includes a first electrode layer and a second electrode layer disposed at intervals. At least a portion of the capacitor assembly is a curled structure that extends along a first direction. The first electrode layer and the second electrode layer are respectively curled when projected onto a plane perpendicular to the first direction.

[0034] In one possible implementation of this application, the array substrate preform includes a substrate, thin-film transistors and common electrode lines spaced apart on the substrate, and a planarization layer covering the thin-film transistors and the common electrode lines;

[0035] The step of forming a capacitor assembly on the array substrate preform includes:

[0036] A sacrificial layer precursor film is formed on the planarization layer, and the sacrificial layer precursor film is patterned and modified to form an interconnected sacrificial layer and a modified layer.

[0037] A pre-rollable film is formed on the sacrificial layer and the modified layer, and the pre-rollable film is patterned to form a pre-rollable film. The pre-rollable film covers at least a portion of the sacrificial layer and at least a portion of the modified layer. The pre-rollable film includes a third pre-rollable layer, a first electrode pre-rollable layer, a first pre-rollable layer, a second electrode pre-rollable layer, and a second pre-rollable layer stacked sequentially.

[0038] The modified layer is etched sequentially along the end of the modified layer away from the sacrificial layer toward the sacrificial layer to remove the modified layer. The film to be rolled up is rolled up from the side away from the sacrificial layer toward the sacrificial layer to form the capacitor assembly. The sacrificial layer forms a fixing layer. The third roll-up precursor layer forms a third roll-up layer. The first electrode precursor layer forms a first electrode layer. The first roll-up precursor layer forms a first roll-up layer. The second electrode precursor layer forms a second electrode layer. The second roll-up precursor layer forms a second roll-up layer.

[0039] In one possible implementation of this application, the etch selectivity ratio of the material of the modified layer to the material of the film to be rolled is not less than 200:1; and / or

[0040] The etching process is an isotropic etching process.

[0041] In one possible implementation of this application, before forming the sacrificial layer precursor film on the substrate, the method further includes: forming a pixel electrode on the planarization layer, the pixel electrode being electrically connected to the first electrode; and / or

[0042] After forming a capacitor assembly on the array substrate preform, the method further includes: forming a pixel defining layer that extends along the first direction and is disposed on the planarization layer and covers the capacitor assembly, wherein two adjacent pixel defining layers define an opening.

[0043] On the other hand, this application also provides a display panel, the display panel comprising:

[0044] The array substrate described above or the array substrate prepared by the manufacturing method described above;

[0045] A light-emitting layer is disposed on the side of the array substrate having the capacitor assembly;

[0046] A top electrode is disposed on the side of the light-emitting layer away from the pixel electrode.

[0047] This application provides a capacitor assembly for an array substrate, an array substrate, a manufacturing method thereon, and a display panel. The assembly includes: a first electrode layer and a second electrode layer spaced apart; at least a portion of the capacitor assembly has a rolled structure extending along a first direction, and the first electrode layer and the second electrode layer are respectively rolled up when projected onto a plane perpendicular to the first direction. By providing a capacitor assembly with a rolled structure, compared to a planar capacitor, the projected area of ​​the capacitor assembly on the array substrate can be reduced, improving the light transmittance of the array substrate and thus improving the display effect; furthermore, the rolled shape of the capacitor assembly can increase the area of ​​the first electrode layer and the second electrode layer, thereby further increasing the capacitance of the capacitor assembly and improving the display effect of the array substrate. Attached Figure Description

[0048] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0049] Figure 1 A side view of the array substrate provided in an embodiment of this application;

[0050] Figure 2 A side view of an array substrate provided in another embodiment of this application;

[0051] Figure 3 This is a side view of the array substrate without the sacrificial layer etched, provided in an embodiment of this application.

[0052] Figure 4 for Figure 1 Enlarged view of point E in the middle;

[0053] Figure 5 A side view provided for manufacturing the sacrificial layer according to an embodiment of this application;

[0054] Figure 6 A top view of the sacrificial layer provided in an embodiment of this application;

[0055] Figure 7 A top view of the array substrate provided in an embodiment of this application;

[0056] Figure 8 A top view of an array substrate provided in another embodiment of this application.

[0057] Figure label:

[0058] The array substrate 100, substrate 200, thin film transistor 210, common electrode line 220, planarization layer 230, via 231, gate conductive layer 240, pixel electrode 250, anode conductive layer 251, scan line 260, data line 270, capacitor assembly 300, first electrode layer 310, second electrode layer 320, first curled layer 330, second curled layer 340, third curled layer 350, free end 360, fixed end 370, sacrificial layer precursor film 400, sacrificial layer 410, modified layer 420, patterned area 430, pixel defining layer 500, mask 600, and first direction F1. Detailed Implementation

[0059] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0060] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0061] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0062] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0063] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0064] Please refer to Figure 1 , Figure 3 , Figure 4 and Figure 7 This application provides a capacitor assembly 300 for an array substrate 100, including a first electrode layer 310 and a second electrode layer 320 spaced apart; at least a portion of the capacitor assembly 300 is a rolled structure, the rolled structure extends along a first direction F1, and the first electrode layer 310 and the second electrode layer 320 are respectively rolled in the orthographic projection on a plane perpendicular to the first direction F1.

[0065] It should be noted that the first direction F1 is the extending direction of the capacitor assembly 300. For example, when the coiled structure capacitor assembly 300 is cylindrical, the capacitor assembly 300 extends along the center line, that is, the first direction F1 is the center line of the capacitor assembly 300.

[0066] By setting the capacitor assembly 300 with a curled structure, the projected area of ​​the capacitor assembly 300 on the array substrate 100 can be reduced compared to a planar capacitor, thereby improving the light transmittance of the array substrate 100 and thus improving the display effect; and the curled shape of the capacitor assembly 300 can increase the area of ​​the first electrode layer 310 and the second electrode layer 320, that is, further increase the capacity of the capacitor assembly 300 and improve the display effect of the array substrate 100.

[0067] In some embodiments, the capacitor assembly 300 has a fixed end 370 and a free end 360, the fixed end 370 being fixed to the array substrate 100, and the free end 360 having a tendency to curl toward the fixed end 370.

[0068] Optionally, the fixed end 370 is electrically connected to components such as the thin-film transistor 210 (TFT) or the common electrode line 220 in the array substrate 100; the free end 360 is not connected to components such as the thin-film transistor 210 or the common electrode line 220, nor is it fixed on the array substrate 100.

[0069] The free end 360 has a tendency to curl toward the fixed end 370, that is, the capacitor assembly 300 has an automatic curling motion tendency, which can improve the manufacturing efficiency of the capacitor assembly 300.

[0070] In some embodiments, the free end 360 abuts against the fixed end 370.

[0071] It is understandable that the free end 360 has a tendency to curl toward the fixed end 370, and the free end 360 abuts against the fixed end 370. That is, the capacitor assembly 300 is circular in the orthographic projection of the plane perpendicular to the first direction F1, that is, the cross-sectional shape of the capacitor assembly 300 is circular.

[0072] Furthermore, in other embodiments, the cross-sectional shape of the capacitor assembly 300 may also be a spiral, a semi-circle, a triangle, or a polygon, etc., without further limitation.

[0073] In some embodiments, the capacitor assembly 300 includes a first curled layer 330, a second curled layer 340, a third curled layer 350, and a sacrificial layer 410. The first curled layer 330 is disposed between the first electrode layer 310 and the second electrode layer 320, and the first curled layer 330 covers the first electrode layer 310; the second curled layer 340 is disposed on the side of the second electrode layer 320 away from the first curled layer 330; the third curled layer 350 is disposed on the side of the first electrode layer 310 away from the first curled layer 330; and the sacrificial layer 410 is disposed on the side of the third curled layer 350 away from the first electrode layer 310.

[0074] It should be noted that the capacitor assembly 300 consists of two closely spaced conductive plates sandwiched in between a non-conductive insulating medium. When a voltage is applied between the two plates of the capacitor assembly 300, the capacitor assembly 300 stores electrical charge. Therefore, the first curled layer 330 can be composed of an insulating medium with a curling tendency. Correspondingly, the second curled layer 340 and the third curled layer 350 can also be composed of an insulating medium with a curling tendency.

[0075] As can be understood from the above description, when the cross-sectional shape of the capacitor assembly 300 is circular, the end of the capacitor assembly 300 not connected to the circuit is curled up and abuts against the second electrode layer 320. This can easily cause an electrical connection between the first electrode layer 310 and the second electrode layer 320, thereby causing a short circuit in the capacitor assembly 300.

[0076] By setting the first curled layer 330 and covering the first electrode layer 310, the first electrode layer 310 and the second electrode layer 320 can form a capacitor assembly 300 to store charge, and the contact between the first electrode layer 310 and the second electrode layer 320 can be avoided, thus ensuring the safety of the capacitor assembly 300.

[0077] By providing a second coiled layer 340, when the capacitor assembly 300 is coiled, the ends of the first electrode layer 310 and the second electrode layer 320 that are not electrically connected can abut against the second coiled layer 340. This avoids electrical connection between the first electrode layer 310 and the second electrode layer 320 in the coiled state, improving the safety of the capacitor assembly 300.

[0078] The third curled layer 350 is disposed on the side of the first electrode layer 310 away from the first curled layer 330, that is, at the bottom of the first electrode layer 310. This can prevent the first electrode layer 310 from being electrically connected to other components on the substrate 200, thereby improving the safety of the capacitor assembly 300.

[0079] Therefore, by setting the second curled layer 340 and the third curled layer 350 to cooperate with each other, the first electrode layer 310 and the second electrode layer 320 are isolated from each other, and the first electrode layer 310 and the second electrode layer 320 are wrapped up and isolated from other components; this avoids electrical connection between the first electrode layer 310 and the second electrode layer 320, and also avoids electrical connection between the first electrode layer 310 and the second electrode layer 320 and other components, thus improving the safety of the capacitor assembly 300; the sacrificial layer 410 is used to support the capacitor assembly 300, that is, the fixed end 370 of the capacitor assembly 300 is fixed on the sacrificial layer 410, and finally the capacitor assembly 300 is fixed on the planarization layer 230, and also avoids direct contact between the capacitor assembly 300 and the planarization layer 230.

[0080] In some embodiments, the materials of the first, second, and third rolled layers independently include at least one of aluminum oxide, silicon nitride, silicon oxide, silicon oxynitride, titanium dioxide, hafnium dioxide, zinc oxide, magnesium oxide, and zirconium oxide; in some embodiments, the material of the sacrificial layer includes at least one of polyimide, phenolic resin, isobutyl methacrylate, polyacrylamide, and cinnamic acid ester; in some embodiments, the materials of the first and second electrode layers independently include at least one of indium tin oxide, indium zinc oxide, 3,4-ethylenedioxythiophene monomer, aluminum, molybdenum, titanium, copper, silver, and gold; in some embodiments, the thicknesses of the first, second, and third rolled layers are independently 0.02 μm to 1 μm; and / or the thickness of the sacrificial layer is 0.01 μm to 1 μm; in some embodiments, the thicknesses of the first and second electrode layers are 50 nm to 300 nm.

[0081] In some embodiments, the first rolled layer 330 is an AlOx thin film, i.e., an aluminum oxide thin film. Wherein, x is a positive number.

[0082] AlOx films have a high dielectric constant, which can provide sufficient capacitance for capacitor assembly 300. In addition, AlOx films have internal stresses between mutually attractive molecules / atoms, that is, AlOx films themselves are in a tensile stress state and have a tendency to curl when at rest; this can provide power for the curling of the first electrode layer 310 and the second electrode layer 320, helping to quickly form the curled capacitor assembly 300.

[0083] Furthermore, in other embodiments, the material of the first curled layer 330 may also be silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, titanium dioxide, hafnium dioxide, zinc oxide, magnesium oxide, zirconium oxide, etc., without further limitation.

[0084] Furthermore, the materials of the second curled layer 340 and the third curled layer 350 are the same as or similar to the material of the first electrode layer 310 mentioned above, and will not be elaborated further here.

[0085] Furthermore, in other embodiments, the second curled layer 340 may be made of other materials with higher adhesion, or the adhesion of the second curled layer 340 may be no less than that of the first or third curled layer 350. Thus, when the capacitor assembly 300 is curled, the side of the capacitor assembly 300 not connected to the circuit curls and adheres to the second electrode layer 320, which can improve the structural stability of the capacitor assembly 300.

[0086] The sacrificial layer 410 is formed by coating photoresist on the planarization layer 230. The photoresist material can be polyimide, phenolic resin, isobutyl methacrylate, polyacrylamide, cinnamic acid ester, etc., without much limitation here.

[0087] Furthermore, both the first electrode layer 310 and the second electrode layer 320 are Ti (titanium) films.

[0088] Titanium film has good electrical conductivity and good film-forming properties. While ensuring the capacitance of capacitor assembly 300, the thickness can be further reduced, thereby reducing the thickness of capacitor assembly 300, and the procurement cost is lower.

[0089] Furthermore, in other embodiments, the materials of the first electrode layer 310 and the second electrode layer 320 may also be conductive metal oxide materials such as ITO (indium tin oxide) or IZO (indium zinc oxide), organic conductive materials such as PEDOT (3,4-ethylenedioxythiophene monomer), conductive metals such as aluminum, molybdenum, titanium, copper, silver, or gold, and their alloys, or combinations thereof, etc., without being overly limited here.

[0090] Furthermore, the film thicknesses of the first rolled layer 330, the second rolled layer 340, and the third rolled layer 350 can be 0.05µm to 1µm, respectively.

[0091] Furthermore, the sacrificial layer 410 can have a thickness of 0.01µm to 1µm.

[0092] Furthermore, the thicknesses of the first electrode layer 310 and the second electrode layer 320 can be 50 nm to 300 nm, respectively.

[0093] Furthermore, in other embodiments, the thickness of each of the above-mentioned film layers can be selected by those skilled in the art according to actual needs, without making excessive limitations here.

[0094] In some embodiments, at least a portion of the capacitor assembly 300 is cylindrical, the cylinder having a hollow inner cavity with a diameter of 0.1 μm to 5.5 μm.

[0095] It should be noted that the capacitor assembly 300 is formed by rolling up multiple layers of film, and has a hollow inner cavity inside. The rolled structure in the capacitor assembly 300 is a cylinder with a hollow inner cavity; and the cross section of the hollow inner cavity along the first direction F1 is approximately circular, and the diameter of the hollow inner cavity is 0.1um~5.5um, that is, the inner diameter of the capacitor assembly 300 is 0.1um~5.5um.

[0096] Correspondingly, since there are no further restrictions on the other film layers of the capacitor assembly 300, the outer diameter of the capacitor assembly 300 is its inner diameter plus the sum of the thicknesses of each film layer, which will not be elaborated on here.

[0097] The cylindrical shape of the capacitor assembly 300 allows for smoother winding and a smoother, flatter surface. Furthermore, this diameter allows the capacitor assembly 300 to store sufficient capacitance, ensuring optimal display performance.

[0098] Furthermore, in other embodiments, the diameter of the hollow cavity in the cylinder can be 0.05um~0.1um, or 5.5um~8.5um, etc., without further limitation.

[0099] Please refer to Figure 2 , Figure 3 , Figure 4 and Figure 6 This application also provides an array substrate 100, including: a substrate 200, a thin-film transistor 210, a common electrode line 220, a planarization layer 230, and a capacitor assembly 300 as described above. The thin-film transistor 210 is disposed on the substrate 200; the common electrode line 220 is disposed on the substrate 200 and spaced apart from the thin-film transistor 210; the planarization layer 230 covers the thin-film transistor 210 and the common electrode line 220; the capacitor assembly 300 is disposed on the planarization layer 230, a first electrode layer 310 is electrically connected to the common electrode line 220, and a second electrode layer 320 is electrically connected to the first electrode in the thin-film transistor 210.

[0100] Specifically, the substrate 200 is used to support thin-film transistors 210, OLEDs, QLEDs, or liquid crystal components, etc. The substrate 200 can be a rigid substrate 200 or a flexible substrate 200. Among them, the rigid substrate 200 can be made of materials such as ceramic or glass; the flexible substrate 200 can be PI (polyimide film) and its derivatives, or PEN (polyethylene naphthalate), or PEP (phosphoenolpyruvate), or diphenylene ether resin, etc., without too many limitations.

[0101] It should be noted that a thin-film transistor 210 typically controls one display sub-pixel (red sub-pixel, blue sub-pixel, and blue sub-pixel, etc.), therefore the array substrate 100 includes a plurality of arrayed thin-film transistors 210. Correspondingly, a thin-film transistor 210 is provided with a capacitor assembly 300, and a plurality of pixel defining layers 500 disposed on the capacitor assembly 300 and arranged in an array constitute a plurality of arrayed openings, each opening corresponding to one or more display sub-pixels.

[0102] It should also be noted that the first electrode is usually composed of a source, a drain, and a gate. The thin film transistor 210 connects the scan line 260 and the data line 270. Multiple thin film transistors 210 are arrayed on the substrate 200. A common electrode line 220 is usually provided next to the thin film transistors 210 in the same column or row.

[0103] It is understood that the thin-film transistor 210 has various structures. Furthermore, in this embodiment, the second electrode layer 320 can be electrically connected to the source or drain portion of the first electrode, and the first electrode layer 310 can be electrically connected to the common electrode line 220.

[0104] It should also be noted that the pixel electrode 250 can be an anode, i.e., the anode conductive layer 251 in this embodiment, or a cathode, etc., without being overly limited here. The opening can be the recessed area described above, i.e., the pixel electrode 250 is provided with the corresponding display material.

[0105] Furthermore, in some embodiments, the second electrode layer 320 may also be electrically connected to the circuitry of the gate conductive layer 240. Therefore, the devices electrically connected to the capacitor assembly 300 can be flexibly configured according to the specific structure of the thin-film transistor 210, without being overly limited in this regard.

[0106] Please refer to Figures 2 to 4 , Figure 7 and Figure 8 In some embodiments, the planarization layer 230 is provided with at least two vias 231, the capacitor assembly 300 is disposed on the planarization layer 230, and the first electrode layer 310 and the second electrode layer 320 are electrically connected to the common electrode line 220 and the thin film transistor 210 through a via 231, respectively.

[0107] By setting the planarization layer 230, components such as the thin-film transistor 210 and the common electrode line 220 can be protected; it can also provide a relatively flat mounting surface for the arrangement of the capacitor assembly 300.

[0108] In some embodiments, the planarization layer 230 is further provided with an anode conductive layer 251, and the planarization layer 230 is further provided with a via 231 for electrically connecting the anode conductive layer 251 to the thin film transistor 210, that is, the planarization layer 230 is provided with at least three vias 231.

[0109] It should also be noted that the array substrate 100 provided in this embodiment is applicable to LCD panels, OLED panels, QLED panels, and other types of panels. The anode conductive layer 251 is a conductive material and, in an LCD panel, is part of the upper and lower electrodes that drive the movement of liquid crystal. In an OLED panel, the anode conductive layer 251 is part of the OLED light-emitting device structure and is used to inject holes or electrons.

[0110] Specifically, the material of the anode conductive layer 251 can be a conductive metal oxide material such as ITO or IZO, an organic conductive material such as PEDOT, or a conductive metal such as aluminum, molybdenum, titanium, copper, silver, or gold, or their alloys, or a combination of these materials. No further limitations are specified here.

[0111] For example, when the OLED light-emitting device emits light in a top-emitting manner, the anode conductive layer 251 is preferably a stacked layer composed of ITO / Ag / ITO.

[0112] The Ag coating acts as a reflective layer, concentrating the light emitted from the OLED in all directions towards the top; while ITO allows electrons / holes to be better injected into the OLED light-emitting layer, improving the luminous efficiency of the OLED device.

[0113] It should be noted that during the deposition of the anode conductive layer 251 pattern, due to the step of the via 231, i.e. the influence of the thickness of the planarization layer 230, the slope angle at the via 231 is relatively large. The thin film material deposited on the via 231 is prone to breakage or thinning of the film layer, which in turn affects the transmission stability of electrical signals.

[0114] Therefore, the anode material at via 231 is retained to reduce the impact of the step difference of via 231, i.e., the thickness of the planarization layer, and to ensure the stability of electrical signal transmission. In addition, to avoid electrical connection between the first electrode layer 310 and the second electrode layer 320, the anode materials in the two vias 231 are not electrically connected to each other.

[0115] Furthermore, the anode conductive layer 251 may be electrically connected to the via 231 that connects the thin-film transistor 210 and the second electrode layer 320, or may not be electrically connected to the via 231 that connects the thin-film transistor 210 and the second electrode layer 320, etc., without further limitation here.

[0116] In some embodiments, the array substrate 100 further includes a pixel defining layer 500 and a pixel electrode 250. The pixel defining layer 500 extends along a first direction F1 and is disposed on the planarization layer 230, and covers the capacitor assembly 300. Two adjacent pixel defining layers 500 define an opening. The pixel electrode 250 is disposed in the opening and is electrically connected to the first electrode.

[0117] It should be noted that, because the capacitor assembly 300 is rolled up, its height is relatively high on the plane perpendicular to the array substrate 100, compared to planar capacitors in the prior art. Other film layers in the display panel, such as the display pixel film layer or the glass cover, are easily pressed onto the capacitor assembly 300, and the structure of the capacitor assembly 300 is easily deformed by pressure. Furthermore, the inconsistent heights of the various capacitor assemblies 300 can easily lead to loose adhesion of other film layers, potentially resulting in Newton's rings and affecting the display effect of the display panel. Additionally, the pixel defining layer 500 can also define the opening for placing the pixel electrode 250.

[0118] By setting the pixel delimiting layer 500, direct contact between other film layers and capacitor assembly 300 can be avoided, thereby improving the display effect of array substrate 100.

[0119] Furthermore, the pixel defining layer 500 is made of polyimide.

[0120] Polyimide has high fluidity, and the pixel defining layer 500 has a strong planarization effect during its formation, thus forming a relatively flat upper surface on the basis of wrapping the capacitor assembly 300; the structure composed of multiple pixel defining layers 500 can better support other film layers.

[0121] Furthermore, in some other embodiments, the pixel defining layer 500 may also be made of other organic materials, without further limitation.

[0122] Specifically, the height of the pixel boundary layer 500 is 0.5um to 6um.

[0123] Furthermore, since the cross-sectional shape of the capacitor assembly 300 is rolled up, the pixel defining layer 500 appears as a linear dam on the orthographic projection of the plane containing the substrate 200.

[0124] When the array substrate 100 is applied to an LCD panel, the pixel defining layer 500 can serve as a support layer, and the height of the multiple dam-shaped pixel defining layers 500 is consistent. When the two glass cover plates of the LCD panel are bonded together, the cross-sectional spacing (Gap) between the two cover plates is kept basically consistent at any point after the two glass cover plates are bonded together, thereby avoiding the formation of Newton's rings and improving the display effect.

[0125] When the array substrate 100 is applied to an OLED panel, the pixel defining layer 500 can also be a pixel defining layer, that is, after being patterned, the pixel defining layer 500 forms some recessed areas that can be filled with OLED material. By filling the recessed areas with OLED material, the pixel defining layer 500 can be used to protect the OLED material and reduce the risk of short circuits / open circuits in the OLED device.

[0126] Specifically, in the existing inkjet printing process for manufacturing OLED materials, by setting the height and arranging the pixel defining layer 500 as described above, the ejected OLED material can be confined within the recessed area, thereby effectively preventing bridging during inkjet printing.

[0127] In some embodiments, in a cross section perpendicular to the first direction F1, the area ratio of the capacitor assembly 300 in the pixel defining layer 500 is less than or equal to 80%.

[0128] It is understandable that when the cross-sectional shape of the capacitor assembly 300 along the first direction F1 is approximately circular, the cross-sectional shape of the pixel defining layer 500 along the first direction F1 is approximately square, and the capacitor assembly 300 abuts against the side of the pixel defining layer 500; according to the area formula of a circle and a square, the area ratio of the capacitor assembly 300 in the pixel defining layer 500 is approximately 78.54%.

[0129] Therefore, the area ratio of the capacitor component 300 in the pixel defining layer 500 is less than or equal to 80%, and further 80%. This ensures that the pixel defining layer 500 can better cover the capacitor component 300, and also minimizes the projected area of ​​the pixel defining layer 500, thereby improving the display effect of the array substrate 100.

[0130] Furthermore, in some other embodiments, the area ratio of the capacitor assembly 300 in the pixel defining layer 500 may also be 60% or 70%, etc., without further limitation.

[0131] Please refer to Figures 2 to 7 This application embodiment also provides a method for manufacturing an array substrate 100, including:

[0132] S100: Provides array substrate preforms;

[0133] S200: A capacitor assembly 300 is formed on an array substrate preform.

[0134] The capacitor assembly 300 includes a first electrode layer 310 and a second electrode layer 320 spaced apart. At least a portion of the capacitor assembly 300 is a coiled structure that extends along a first direction F1. The first electrode layer 310 and the second electrode layer 320 are respectively coiled when projected onto a plane perpendicular to the first direction F1.

[0135] The array substrate preform includes a substrate 200, thin film transistors 210 and common electrode lines 220 spaced on the substrate 200, and a planarization layer 230 covering the thin film transistors 210 and common electrode lines 220.

[0136] Specifically, a patterned semiconductor layer, a gate insulating layer, a gate conductive layer 240, an intermediate dielectric layer, a source conductive electrode layer, a drain conductive electrode layer, a planarization layer 230, and an anode conductive layer 251 are sequentially formed on the substrate 200.

[0137] Specifically, the source electrode is disposed in the source conductive electrode layer, and the drain electrode is disposed in the drain conductive electrode layer; wherein, in addition to electrically connecting the OLED anode to the driving line of the thin film transistor 210 through the via 231 of the planarization layer, the anode conductive layer 251 is also provided with at least two vias 231 for electrically connecting the capacitor assembly 300 to the common electrode line 220 and the driving line of the thin film transistor 210, respectively.

[0138] The step of forming capacitor assembly 300 on array substrate preform includes:

[0139] S210: A sacrificial layer precursor film 400 is formed on the planarization layer 230, and the sacrificial layer precursor film 400 is patterned and modified to form a connected sacrificial layer 410 and modified layer 420.

[0140] Specifically, a photoresist layer is coated on the substrate 200; the photoresist layer can be a regular square shape, adapted to the shape of the flat capacitor assembly 300.

[0141] Furthermore, in other embodiments, the photoresist layer may also be circular or irregular in shape, etc., without further limitation.

[0142] Optionally, a slit coating process is used to form a full-surface photoresist film on the substrate 200, namely the photoresist layer, also known as the sacrificial layer precursor film 400.

[0143] Furthermore, the photoresist layer is made of photosensitive polyimide.

[0144] Specifically, the photoresist layer is exposed and developed to form a patterned area 430 with vias 231. The patterned area 430 is used to support the pre-film to be rolled up, which is the capacitor assembly 300 in a flat state.

[0145] Patterned areas 430 are formed by exposure and development processes. Multiple patterned areas 430 are arrayed on the substrate 200, wherein the patterned areas 430 do not block the vias 231.

[0146] Then, a mask 600 is placed on the photoresist layer and the pattern area 430 is exposed and modified, and a sacrificial layer 410 and a modified layer 420 are formed on the pattern area 430.

[0147] Specifically, the mask 600 is a plate with multiple openings, and the openings correspond to the modified layer 420. That is, the area of ​​the mask 600 without openings corresponds to the sacrificial layer 410 and the via 231. In other words, only the modified layer 420 is exposed. The modified layer 420 is the modified pattern area, and the sacrificial layer 410 is the non-modified pattern area.

[0148] After exposure and masking, polyimide forms a modified layer 420 that is easily etched and a sacrificial layer 410 that is not easily etched; and the etching selectivity ratio of polyimide to inorganic material of capacitor assembly 300 is close to or exceeds 100%, which can better form the rolled capacitor assembly 300.

[0149] S220: A pre-rollable film is formed on the sacrificial layer 410 and the modified layer 420, and the pre-rollable film is patterned to form a pre-rollable film. The pre-rollable film covers at least a portion of the sacrificial layer 410 and at least a portion of the modified layer 420. The pre-rollable film includes a third pre-rollable layer, a first electrode pre-rollable layer, a first pre-rollable layer, a second electrode pre-rollable layer, and a second pre-rollable layer, which are sequentially stacked in the direction away from the sacrificial layer pre-rollable film 400.

[0150] It should be noted that the first electrode precursor layer is a first electrode layer 310 in a flat state, the second electrode precursor layer is a second electrode layer 320 in a flat state; the first curled precursor layer is a first curled layer 330 in a flat state, the second curled precursor layer is a second curled layer 340 in a flat state, and the third curled precursor layer is a third curled layer 350 in a flat state.

[0151] First, an atomic layer deposition process is used to deposit a film on the patterned area 430, namely the third curl-up precursor layer. Then, a photolithography process is used to pattern the third curl-up precursor layer.

[0152] By employing atomic layer deposition (ALD) for film deposition, the film thickness can be well controlled, and the alumina film is typically under tensile stress, possessing a strong driving force for upward curling. Furthermore, patterning the third curling precursor layer using photolithography exposes part of the sacrificial layer 410 and / or the modified layer 420, facilitating subsequent etching of the sacrificial layer 410 and / or the modified layer 420. In summary, by controlling the width of the patterned third curling precursor layer, the diameter of the microchannels after the third curling precursor layer curls to form the third curling layer 350 can be precisely controlled.

[0153] Furthermore, in other embodiments, the coating process on the sacrificial layer 410 and / or the modified layer 420 can also be magnetron sputtering, vapor deposition, chemical vapor deposition, atomic layer deposition, or molecular layer deposition, etc., without further limitation.

[0154] Then, a first electrode precursor layer is formed on the third curled precursor layer. On the orthographic projection of the plane where the substrate 200 is located, the first electrode precursor layer overlaps with the sacrificial layer 410 and the modified layer 420. A first curled precursor layer is formed on the first electrode precursor layer, and the first curled precursor layer covers the surface of the first electrode precursor layer. A second electrode precursor layer is formed on the first curled precursor layer. A second curled precursor layer is formed on the second electrode precursor layer.

[0155] Optionally, in this embodiment, the first electrode precursor layer is formed on the third curled precursor layer; in other embodiments, since the sacrificial layer 410 and the modified layer 420 can also be insulating materials, the first electrode precursor layer can also be formed directly on the sacrificial layer 410 and the modified layer 420.

[0156] It should also be noted that in the coiled capacitor assembly 300, a portion of its film layer needs to be electrically connected to the connection lines of the array substrate 100. Therefore, the film layer of the capacitor assembly 300 has a region to be coiled and an uncoiled region, wherein the uncoiled region is the region connected to the thin-film transistor 210 or the common electrode line 220.

[0157] Furthermore, firstly, a Ti film, namely the first electrode precursor layer, is fabricated using a magnetron sputtering process. Then, the first electrode precursor layer is patterned so that the non-curved region of the first electrode precursor layer is electrically connected to the via 231 of the common electrode line 220. Specifically, the non-curved region of the first electrode precursor layer is not electrically connected to another via 231 of the thin-film transistor 210.

[0158] Optionally, the first electrode precursor layer may be fabricated using the same material used to fabricate the anode conductive layer 251.

[0159] In this way, one photolithography process can be reduced in the manufacturing of the array substrate 100, thereby improving the manufacturing efficiency of the array substrate 100.

[0160] Furthermore, in other embodiments, the process for forming the first electrode precursor layer can also be magnetron sputtering, vapor deposition, chemical vapor deposition, atomic layer deposition, or molecular layer deposition, etc., without further limitation.

[0161] Correspondingly, the manufacturing process steps of the second electrode precursor layer are the same as or similar to those of the first electrode precursor layer described above, and will not be elaborated further here. It is sufficient that the non-curved region of the first electrode precursor layer is electrically connected to the via 231 of the electrically connected thin-film transistor 210, while another via 231 that is not electrically connected to the first electrode layer 310 is electrically connected.

[0162] Similarly, the manufacturing process steps of the first and second curled precursor layers are the same as or similar to those of the third curled precursor layer described above, and will not be elaborated further here.

[0163] S230: Along the end of the modified layer 420 away from the sacrificial layer 410 toward the sacrificial layer 410, the modified layer 420 is etched sequentially to remove the modified layer 420. The film to be rolled up is rolled up from the side away from the sacrificial layer 410 toward the side toward the sacrificial layer 410 to form a capacitor assembly 300. The sacrificial layer 410 forms a fixing layer. The third roll-up precursor layer forms a third roll-up layer 350. The first electrode precursor layer forms a first electrode layer 310. The first roll-up precursor layer forms a first roll-up layer 330. The second electrode precursor layer forms a second electrode layer 320. The second roll-up precursor layer forms a second roll-up layer 340.

[0164] By etching away the modified layer 420, the adhesion of the modified layer 420 to the capacitor assembly 300 can be eliminated; this causes the first, second, and third curled precursor layers to automatically curl, which in turn drives the automatic curling of the first and second electrode precursor layers to form a curled structure capacitor assembly 300. This improves the manufacturing efficiency of the array substrate 100. Furthermore, the remaining sacrificial layer 410 forms a fixing layer, which can be used to support the capacitor assembly 300.

[0165] In some embodiments, the etching selectivity ratio of the material of the modified layer 420 to the material of the thin film to be rolled is not less than 200:1; in some embodiments, the etching process is an isotropic etching process.

[0166] It should be noted that the etching selectivity refers to the different etching rates in different regions or film layers under the same etching process due to the different materials.

[0167] By selecting a modified layer 420 with a larger etch selectivity and a thin film to be rolled, the modified layer 420 can be etched away while only a small amount or no thin film to be rolled away is etched away. This can eliminate the adhesion of the modified layer 420 to the capacitor assembly 300, causing the capacitor assembly 300 to automatically roll up, and also ensuring the capacitance of the capacitor assembly 300.

[0168] Furthermore, in some other embodiments, the etching ratio of the material of the modified layer 420 to the material of the film to be rolled can be no less than 150:1 or 250:1, etc., without further limitation.

[0169] Furthermore, in some other embodiments, the etch selectivity of the modified layer 420 is not less than the etch selectivity of the sacrificial layer 410.

[0170] In this way, while completely etching away the modified layer 420, a portion of the sacrificial layer 410 can be retained to support the capacitor assembly 300.

[0171] Specifically, the modified layer 420 is etched by wet etching. The sacrificial layer 410 and the modified layer 420 are etched isotropically by wet etching process. The etching solution is dropped onto the partially exposed sacrificial layer 410 and modified layer 420, which can effectively and gradually etch away the modified layer 420 covering the bottom of the capacitor assembly 300.

[0172] During this process, the tensile stress of each pre-rolled layer is released, causing the film to be rolled up to be in an upward-curving state; as etching proceeds, the film to be rolled up gradually and eventually forms a rolled capacitor assembly 300.

[0173] In some embodiments, before forming the sacrificial layer precursor film 400 on the substrate 200, the method further includes forming a pixel electrode 250 on the substrate, the pixel electrode 250 being electrically connected to the first electrode.

[0174] In some embodiments, after forming the capacitor assembly 300 on the array substrate preform, the method further includes: forming a pixel defining layer 500, the pixel defining layer 500 extending along a first direction F1 and disposed on the planarization layer 230 and covering the capacitor assembly 300, with adjacent two pixel defining layers 500 defining an opening.

[0175] By forming a pixel electrode 250 electrically connected to the first electrode, the color rendering of the display sub-pixels can be subsequently controlled, thereby displaying an image.

[0176] As described above, the pixel defining layer 500 arranged in an array forms multiple array openings, each opening corresponding to one or more display sub-pixels, thereby improving the display effect of the array substrate 100.

[0177] Specifically, a PI containing a photosensitive material is coated on the capacitor assembly 300 and / or the anode conductive layer 251, and the PI is patterned to form a pixel defining layer 500.

[0178] Similar to photoresist, PI can be cured from a liquid into a thin film. Therefore, after coating and curing PI on the capacitor assembly 300, the pixel defining layer 500 can form a relatively flat surface, and each pixel defining layer 500 has better coverage ability, thus effectively covering the capacitor assembly 300.

[0179] This application embodiment also provides a display panel (not shown in the figure), the display panel including the array substrate 100 as described above or the array substrate 100 prepared by the manufacturing method described above; a light-emitting layer disposed on the side of the array substrate 100 having the capacitor assembly 300; and a top electrode disposed on the side of the light-emitting layer away from the pixel electrode 250.

[0180] Since the display panel has the array substrate 100 described above, it has all the same beneficial effects, which will not be repeated here.

[0181] It should be noted that different types of panels require different types of light-emitting layers.

[0182] For example, when the display panel is an LCD panel, the light-emitting layer can be a color filter, and a pixel defining layer 500 is not required. When the display panel is an OLED panel, the light-emitting layer can be an organic light-emitting layer. The above are common technologies in the prior art and will not be elaborated further here.

[0183] Furthermore, by setting pixel electrode 250 and top electrode, the top electrode and pixel electrode 250 can work together to control the light-emitting layer to display different images.

[0184] This application does not impose specific limitations on the applicability of the display panel, which can be any product or component with display function, such as a television, laptop, tablet, wearable display device (such as a smart bracelet, smartwatch, etc.), mobile phone, virtual reality device, augmented reality device, vehicle display, advertising light box, etc.

[0185] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0186] The capacitor assembly, array substrate, manufacturing method, and display panel of the array substrate provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An array substrate, characterized in that, The array substrate includes: Substrate; A thin-film transistor disposed on the substrate; A common electrode line is disposed on the substrate and spaced apart from the thin-film transistor; A planarization layer covering the thin-film transistor and the common electrode line; A capacitor assembly includes a first electrode layer and a second electrode layer spaced apart. At least a portion of the capacitor assembly is a coiled structure extending along a first direction. The first electrode layer and the second electrode layer are respectively coiled when projected onto a plane perpendicular to the first direction. The capacitor assembly is disposed on the planarization layer. The first electrode layer is electrically connected to the common electrode line, and the second electrode layer is electrically connected to the first electrode in the thin-film transistor. The first electrode includes a source, a drain, and a gate. A pixel defining layer, extending along a first direction on the planarization layer and covering the capacitor assembly, wherein two adjacent pixel defining layers define an opening; and A pixel electrode is disposed in the opening and is electrically connected to the first electrode.

2. The array substrate as described in claim 1, characterized in that, The capacitor assembly has a fixed end and a free end, the free end having a tendency to curl toward the fixed end, and the free end abutting against the fixed end.

3. The array substrate as described in claim 1, characterized in that, The capacitor assembly includes: A first curled layer is disposed between the first electrode layer and the second electrode layer, and the first curled layer covers the first electrode layer; The second curled layer is disposed on the side of the second electrode layer away from the first curled layer; The third curled layer is disposed on the side of the first electrode layer away from the first curled layer; A sacrificial layer is disposed on the side of the third coiled layer away from the first electrode layer.

4. The array substrate as described in claim 3, characterized in that, The materials of the first crimped layer, the second crimped layer, and the third crimped layer each independently include at least one of aluminum oxide, silicon nitride, silicon oxide, silicon oxynitride, titanium dioxide, hafnium dioxide, zinc oxide, magnesium oxide, and zirconium oxide; and / or The sacrificial layer is made of at least one of polyimide, phenolic resin, isobutyl methacrylate, polyacrylamide, and cinnamic acid ester; and / or The materials of the first electrode layer and the second electrode layer each independently include at least one of indium tin oxide, indium zinc oxide, 3,4-ethylenedioxythiophene monomer, aluminum, molybdenum, titanium, copper, silver, and gold; and / or The thicknesses of the first curled layer, the second curled layer, and the third curled layer are each independently 0.02µm to 1µm; and / or The thickness of the sacrificial layer is 0.01µm to 1µm; and / or The thickness of the first electrode layer and the second electrode layer is 50nm~300nm.

5. The array substrate as described in claim 3 or 4, characterized in that, At least a portion of the capacitor assembly is cylindrical, the cylinder having a hollow inner cavity with a diameter of 0.1 μm to 5.5 μm.

6. The array substrate according to claim 1, characterized in that, In a cross section perpendicular to the first direction, the area ratio of the capacitor assembly in the pixel defining layer is less than or equal to 80%.

7. A method for manufacturing an array substrate, characterized in that, The manufacturing method for preparing the array substrate as described in any one of claims 1 to 6 includes: Provide array substrate preforms; A capacitor assembly is formed on the array substrate preform. The capacitor assembly includes a first electrode layer and a second electrode layer disposed at intervals. At least a portion of the capacitor assembly is a curled structure that extends along a first direction. The first electrode layer and the second electrode layer are respectively curled when projected onto a plane perpendicular to the first direction.

8. The manufacturing method as described in claim 7, characterized in that, The array substrate preform includes a substrate, thin-film transistors and common electrode lines spaced apart on the substrate, and a planarization layer covering the thin-film transistors and the common electrode lines; The step of forming a capacitor assembly on the array substrate preform includes: A sacrificial layer precursor film is formed on the planarization layer, and the sacrificial layer precursor film is patterned and modified to form an interconnected sacrificial layer and a modified layer. A pre-rollable film is formed on the sacrificial layer and the modified layer, and the pre-rollable film is patterned to form a pre-rollable film. The pre-rollable film covers at least a portion of the sacrificial layer and at least a portion of the modified layer. The pre-rollable film includes a third pre-rollable layer, a first electrode pre-rollable layer, a second electrode pre-rollable layer, and a second pre-rollable layer stacked sequentially. The modified layer is etched sequentially along the end of the modified layer away from the sacrificial layer toward the sacrificial layer to remove the modified layer. The film to be rolled up is rolled up from the side away from the sacrificial layer toward the sacrificial layer to form the capacitor assembly. The sacrificial layer forms a fixing layer. The third roll-up precursor layer forms a third roll-up layer. The first electrode precursor layer forms a first electrode layer. The first roll-up precursor layer forms a first roll-up layer. The second electrode precursor layer forms a second electrode layer. The second roll-up precursor layer forms a second roll-up layer.

9. The manufacturing method as described in claim 8, characterized in that, The etching selectivity ratio of the material of the modified layer to the material of the film to be rolled is not less than 200:1; and / or The etching process is an isotropic etching process.

10. The manufacturing method as described in claim 8, characterized in that, Before forming the sacrificial layer precursor film on the substrate, the method further includes: forming a pixel electrode on the planarization layer, the pixel electrode being electrically connected to the first electrode; and / or After forming a capacitor assembly on the array substrate preform, the method further includes: forming a pixel defining layer that extends along the first direction and is disposed on the planarization layer and covers the capacitor assembly, wherein two adjacent pixel defining layers define an opening.

11. A display panel, characterized in that, The display panel includes: The array substrate as described in any one of claims 1-6 or the array substrate prepared by any one of claims 7-10; A light-emitting layer is disposed on the side of the array substrate having the capacitor assembly; A top electrode is disposed on the side of the light-emitting layer away from the pixel electrode.

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