Semiconductor device

Abstract

A semiconductor device includes a plurality of first line structures extending in a first direction, each of the plurality of first line structures including a first pinned layer exhibiting magnetization in a fixed magnetization direction; a plurality of second line structures spaced apart from the first line structures and extending in a second direction crossing the first direction; a plurality of first free layers each exhibiting magnetization having a variable magnetization direction, the first free layers overlapping the first line structures and the second line structures at intersection regions of the first line structures and the second line structures, respectively; and a first tunnel barrier layer interposed between the first line structures and the first free layers.

Description

[0001] Cross Reference to Related Applications

[0002] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2021-0182952, filed on December 20, 2021, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present patent document relates to a storage circuit or a storage device. BACKGROUND

[0004] Recent trends in the electrical and electronic industry toward miniaturization, low power consumption, high performance, and multi-functionality have prompted semiconductor manufacturers to focus on high-performance, high-capacity semiconductor devices. Examples of such high-performance, high-capacity semiconductor devices include semiconductor devices such as storage devices capable of storing data using characteristics that switch between different resistance states according to an applied voltage or current, for example, resistive random access memory (RRAM), phase change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electrical fuse (E-fuse). SUMMARY

[0005] The technology disclosed in this patent document includes a plurality of embodiments of a storage device having improved operating characteristics and a simple manufacturing process.

[0006] In an embodiment, a semiconductor device includes a plurality of first line structures extending in a first direction, each of the plurality of first line structures including a first pinned layer exhibiting magnetization in a fixed magnetization direction; a plurality of second line structures spaced apart from the first line structures and extending in a second direction crossing the first direction; a plurality of first free layers each exhibiting magnetization having a variable magnetization direction, the first free layers overlapping with intersection regions of the first line structures and the second line structures between the first line structures and the second line structures, respectively; and a first tunnel barrier layer interposed between the first line structures and the first free layers. BRIEF DESCRIPTION OF DRAWINGS

[0007] FIG. 1A is a plan view showing a storage device based on some embodiments of the disclosed technology.

[0008] FIG. 1B is FIG. 1A a cross-sectional view taken along line A-A'.

[0009] FIG. 1C is FIG. 1A a cross-sectional view taken along line B-B'.

[0010] FIG. 1Dis a view showing a first magnetic tunnel junction (MTJ) structure based on some embodiments of the disclosed technology.

[0011] FIG. 2A is a plan view showing a memory device based on some embodiments of the disclosed technology.

[0012] FIG. 2B is FIG. 2A a cross-sectional view taken along line A-A'.

[0013] FIG. 2C is FIG. 2A a cross-sectional view taken along line B-B'.

[0014] FIG. 3A is a cross-sectional view showing a memory device based on some embodiments of the disclosed technology.

[0015] FIG. 3B is a view showing a first magnetic tunnel junction (MTJ) structure based on some embodiments of the disclosed technology.

[0016] FIG. 4A is a plan view showing a memory device based on some embodiments of the disclosed technology.

[0017] FIG. 4B is FIG. 4A a cross-sectional view taken along line A-A'.

[0018] FIG. 4C is FIG. 4A a cross-sectional view taken along line B-B'.

[0019] FIG. 5A is a plan view showing a memory device based on some embodiments of the disclosed technology.

[0020] FIG. 5B is FIG. 5A a cross-sectional view taken along line A-A'.

[0021] FIG. 5C is FIG. 5A a cross-sectional view taken along line B-B'. DETAILED DESCRIPTION

[0022] In the following, a number of embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0023] The drawings are not necessarily to scale. In some instances, the proportions of at least some of the structures in the drawings can have been exaggerated in order to clearly demonstrate certain features of the embodiments. When a particular example is presented in a multi-layer structure having two or more layers in the drawings or the specification, the relative positional relationship of such layers or the order of arranging the layers shown reflects a particular implementation for the described or shown example, while a different relative positional relationship or order of arranging the layers is possible. Further, the described or shown example of the multi-layer structure can not reflect all the layers present in that particular multi-layer structure (e.g., one or more additional layers can be present between two of the described layers). As a particular example, when a first layer in a described or shown multi-layer structure is referred to as being "on" or "over" a second layer or a substrate, the first layer can be formed directly on the second layer or substrate, but it is also possible that one or more other intervening layers can be present in the structure between the first layer and the second layer or substrate.

[0024] FIG. 1A is a plan view showing a memory device based on some embodiments of the disclosed technology, FIG. 1B is FIG. 1A is a cross-sectional view taken along line A-A', and FIG. 1C is FIG. 1A is a cross-sectional view taken along line B-B'. Hereinafter, for the sake of convenience of description, a direction substantially parallel to the line A-A' will be referred to as a first direction, and a direction substantially parallel to the line B-B' intersecting the line A-A' will be referred to as a second direction.

[0025] Referring to FIGS. 1A-1C , a memory device based on some embodiments of the disclosed technology can include a substrate 100; a plurality of first line structures 110 disposed over the substrate 100 and extending in the first direction while being arranged to be spaced apart from each other in the second direction; a plurality of second line structures 150 disposed over the first line structures 110 and extending in the second direction while being arranged to be spaced apart from each other in the first direction; and a stack structure of a tunnel barrier layer 120, a free layer 130, and a selection element layer 140, which overlaps each of the intersection regions between the first line structures 110 and the second line structures 150.

[0026] The substrate 100 can include a semiconductor material such as silicon. Although not shown in FIGS. 1A-1C , the substrate 100 can include a lower structure including, for example, a driving circuit electrically connected to the first line structures 110 and / or the second line structures 150 to drive or apply a voltage or a current to the first line structures 110 and / or the second line structures 150.

[0027] The first line structure 110 can include at least a pinned layer, and thus can form a magnetic tunnel junction (MTJ) structure including the pinned layer, a tunnel barrier layer 120, and a free layer 130. In addition, the first line structure 110 can further include one or more material layers or structures having various functions to improve characteristics required for the MTJ structure. As will be described below with reference to FIGS. 2A and 2B, the first line structure 110 can include a seed layer 112, a buffer layer 114, the pinned layer 116, a capping layer 118, and the tunnel barrier layer 120. FIG. 1D As discussed, the disclosed technology can be implemented in some embodiments to provide the first line structure 110 and the MTJ structure including the first line structure 110.

[0028] FIG. 1D FIGS. 1A and 1B are views illustrating an MTJ structure based on some embodiments of the disclosed technology.

[0029] Referring to FIG. 1D , the MTJ structure can include a first line structure 110 having a multi-layer structure including a pinned layer 116, a tunnel barrier layer 120 disposed above the first line structure 110, and a free layer 130 disposed above the tunnel barrier layer 120.

[0030] The free layer 130 can exhibit a magnetization direction that can vary, i.e., a variable magnetization direction, and can store different data by changing the magnetization direction. In some implementations, the free layer 130 can be referred to as a data storage layer. The change in the magnetization direction in the free layer 130 can be attributed to a spin transfer torque from a spin-polarized current, in which a spin polarization of charge carriers, such as electrons, in the current can be transferred to the free layer 130. In some implementations, the free layer 130 can have a magnetization direction that is substantially perpendicular to a surface of the layer. For example, as indicated by the arrow in the free layer 130, the magnetization direction of the free layer 130 can change between an up-to-down direction and a down-to-up direction. However, the disclosed technology is not limited thereto, and in other implementations, the free layer 130 can have a magnetization direction that is substantially parallel to a surface of the layer. FIG. 1D

[0031] The pinned layer 116 can have a fixed magnetization direction, and thus the magnetization direction of the pinned layer 116 can contrast with the magnetization direction of the free layer 130. In some implementations, the pinned layer 116 can be referred to as a reference layer. When the free layer 130 has a magnetization direction that is substantially perpendicular to a surface of the layer, the pinned layer 116 can also have a magnetization direction that is substantially perpendicular to a surface of the layer. For example, as indicated by the arrow in the pinned layer 116, the magnetization direction of the pinned layer 116 can be fixed in a down-to-up direction. However, the disclosed technology is not limited thereto, and the magnetization direction of the pinned layer 116 can be fixed and can have an up-to-down direction. Alternatively, when the free layer 130 has a magnetization direction that is substantially parallel to a surface of the layer, the pinned layer 116 can also have a magnetization direction that is substantially parallel to a surface of the layer. ​

[0032] The tunnel barrier layer 120 can cause tunneling of electrons across the boundary between the free layer 130 and the pinned layer 116 according to a voltage or a current applied through the upper and lower portions of the MTJ structure, thereby changing the magnetization direction of the free layer 130.

[0033] Each of the free layer 130 and the pinned layer 116 can have a single-layer or multi-layer structure including a ferromagnetic material. For example, each of the free layer 130 and the pinned layer 116 can include an alloy including Fe, Ni, or Co as a main component, e.g., a Co-Fe-B alloy, a Co-Fe-B-X alloy (where X is Al, Si, or Ti, V, Cr, Ni, Ga, Ge, Zr, Nb, Mo, Pd, Ag, Hf, Ta, W, or Pt), a Fe-Pt alloy, a Fe-Pd alloy, a Co-Pd alloy, a Co-Pt alloy, a Fe-Ni-Pt alloy, a Co-Fe-Pt alloy, a Co-Ni-Pt alloy, etc. Alternatively, each of the free layer 130 and the pinned layer 116 can include a stacked structure such as Co / Pt, Co / Pd, or the like, or a structure of an alternating stack of a magnetic material and a non-magnetic material. The tunnel barrier layer 120 can include an insulating oxide, e.g., an oxide such as MgO, CaO, SrO, TiO, VO, or NbO.

[0034] In the above-described MTJ structure, the magnetization direction of the free layer 130 can be changed according to an applied voltage or current, so that different data can be stored. When the magnetization directions of the free layer 130 and the pinned layer 116 are parallel to each other, the MTJ structure can be in a low resistance state which can indicate data ‘1’. Conversely, when the magnetization directions of the free layer 130 and the pinned layer 116 are anti-parallel to each other, the MTJ structure can be in a high resistance state which indicates data ‘0’.

[0035] Further, the first line structure 110 can further include a magnetic correction layer 112, a separation layer 114, and an interface layer 118 in addition to the pinned layer 116.

[0036] The magnetic correction layer 112 can be disposed adjacent to the pinned layer 116 with the spacer layer 114 interposed therebetween. For example, the magnetic correction layer 112 can be disposed to face a lower surface of the pinned layer 116, which is opposite to an upper surface of the pinned layer 116 facing the free layer 130. The magnetic correction layer 112 can perform an action of canceling or reducing an effect of a stray magnetic field generated by the pinned layer 116. In this case, an effect of the stray magnetic field of the pinned layer 116 on the free layer 130 can be reduced, thereby reducing a deflected magnetic field of the free layer 130. The magnetic correction layer 112 can have a magnetization direction that is anti-parallel to a magnetization direction of the pinned layer 116. In some embodiments, when the pinned layer 116 has a lower-to-upper magnetization direction, the magnetic correction layer 112 can have an upper-to-lower magnetization direction. However, unlike as shown, when the pinned layer 116 has an upper-to-lower magnetization direction, the magnetic correction layer 112 can have a lower-to-upper magnetization direction. The magnetic correction layer 112 can have a single-layer structure or a multi-layer structure including a ferromagnetic material.

[0037] The spacer layer 114 can be interposed between the magnetic correction layer 112 and the pinned layer 116 to enable anti-ferromagnetic exchange coupling between the magnetic correction layer 112 and the pinned layer 116. The spacer layer 114 can include a non-magnetic conductive material. For example, the spacer layer 114 can include a metallic material such as Cr, Ru, Ir, or Rh.

[0038] The interface layer 118 can be interposed between the pinned layer 116 and the tunnel barrier layer 120 to block diffusion of a metal of the pinned layer 116 into the tunnel barrier layer 120, and can prevent a crystal growth of the tunnel barrier layer 120 from affecting the pinned layer 116. Further, the interface layer 118 can exchange couple with the pinned layer 116 to prevent a change in a magnetization direction of the pinned layer 116. The interface layer 118 can have a single-layer structure or a multi-layer structure including a ferromagnetic material. For example, the interface layer 118 can include Fe, Co, a B-based alloy, or an alloy based on a combination thereof, e.g., a Fe-Co-B alloy.

[0039] However, the first line structure 110 is not limited to as shown in the drawings, and at least one of the magnetic correction layer 112, the spacer layer 114, and the interface layer 118 can be omitted. When all of the magnetic correction layer 112, the spacer layer 114, and the interface layer 118 are omitted from the first line structure 110, the first line structure 110 can include only the pinned layer 116, and can have a single-layer structure. Alternatively, the first line structure 110 can further include one or more other layers (not shown) for improving characteristics of the MTJ structure.

[0040] Referring again to FIGS. 1A-1CA select element layer 140 can be disposed on top of the MTJ structure. The select element layer 140 can be used to prevent current leakage that can occur between MTJ structures sharing the first line structure 110 or the second line structure 150. To this end, the select element layer 140 can have a threshold switching characteristic, e.g., a small amount of current flows when an applied voltage is less than a predetermined threshold, and the amount of current rapidly increases when the applied voltage becomes greater than or equal to the predetermined threshold. The threshold can be referred to as a threshold voltage, and the select element layer 140 can be implemented in an on state or an off state based on the threshold voltage. The select element layer 140 can include a diode, a bidirectional threshold switch (OTS) material such as a chalcogenide-based material, a mixed ionic electronic conductive (MIEC) material such as a metal chalcogenide-based material, a metal insulator transition (MIT) material such as Nb02 or VO2, a tunneling insulating layer with a relatively wide bandgap such as Si02 or Al203 or others.

[0041] In some embodiments, the stack of the tunnel barrier layer 120, the free layer 130, and the select element layer 140 can be collectively patterned to have sidewalls aligned with each other. Further, the stack of the tunnel barrier layer 120, the free layer 130, and the select element layer 140 can have a rectangular columnar shape with two sidewalls aligned with two sidewalls of the second line structure 150 in a first direction and two sidewalls aligned with two sidewalls of the first line structure 110 in a second direction. However, the disclosed technology is not limited thereto, and the sidewalls of the tunnel barrier layer 120, the free layer 130, and the select element layer 140 can not be aligned with each other. Alternatively, the sidewalls of the tunnel barrier layer 120, the free layer 130, and the select element layer 140 can be aligned with each other without being aligned with the sidewalls of the first line structure 110 and / or the second line structure 150.

[0042] In the intersection region of the first line structure 110 and the second line structure 150, the MTJ structure including the first line structure 110, the tunnel barrier layer 120, and the free layer 130, and the select element layer 140 can form a memory cell MC. Although the first line structure 110 has a line shape extending in the first direction, the free layer 130 for storing data can have an island shape overlapping the intersection region of the first line structure 110 and the second line structure to be spaced apart from another free layer 130 adjacent thereto. Thus, the memory cell MC can be formed at each of the intersection regions of the first line structure 110 and the second line structure 150. The first line structure 110 can constitute part of the MTJ structure and also transmit a voltage or a current to one end (e.g., a lower end of the memory cell MC). For example, the first line structure 110 can function as both part of the MTJ structure and a voltage / current transmission line (e.g., a bit line, a word line). Since the ferromagnetic material and / or the non-magnetic material forming the first line structure 110 is a conductive material, the function of transmitting a voltage or a current can be sufficiently performed.

[0043] The second line structure 150 can be used to transmit a voltage or a current to the other end (e.g., an upper end of the memory cell MC). Thus, a current can be generated through the first line structure 110, the memory cell MC, and the second line structure 150, thereby writing data to the memory cell MC or reading data from the memory cell MC. Since the second line structure 150 does not constitute part of the MTJ structure unlike the first line structure 110, the second line structure 150 can have a single-layer structure or a multi-layer structure including a low-resistance conductive material. For example, the second line structure 150 can include a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), or titanium (Ti), a metal nitride such as titanium nitride (TiN) or tantalum nitride (TaN), or a combination thereof. However, the second line structure 150 can have substantially the same structure as the first line structure 110.

[0044] In some embodiments of the disclosed technology, the first line structure 110 can function as one of a word line and a bit line for driving the memory cell MC and reading or writing data from or to the memory cell MC, while constituting part of the MTJ structure, and the second line structure 150 can function as the other of the word line and the bit line. However, since the first line structure 110 includes a ferromagnetic material, the resistivity of the first line structure 110 can be greater than that of the second line structure 150 when the second line structure 150 includes a low-resistance conductive material. However, the resistance of the first line structure 110 can be reduced by relatively increasing the thickness T1 of the first line structure 110. For example, the thickness T1 of the first line structure can be greater than the thickness T2 of the second line structure 150.

[0045] A memory device implemented based on some embodiments of the disclosed technology can achieve the following effects.

[0046] In an example of a memory device in which a memory cell including an MTJ structure and a selection element layer is disposed between a word line and a bit line crossing each other, a patterning process using a mask and an etching process for forming each of the word line, the memory cell, and the bit line are required, resulting in a complicated and expensive manufacturing process. In addition, since the memory cell includes the multi-layered MTJ structure and the selection element layer, the difficulty of the etching process for forming the memory cell can increase. On the other hand, in some embodiments of the disclosed technology, since the first line structure 110 including the pinned layer 116 replaces the word line and / or the bit line, and the stack structure of the tunnel barrier layer 120, the free layer 130, and the selection element layer 140 is formed in an island shape, the manufacturing process is thus simplified and the manufacturing cost is reduced. In addition, since the memory cell MC is formed by the etching process of the first line structure 110 and the etching process of the stack structure of the tunnel barrier layer 120, the free layer 130, and the selection element layer 140, the difficulty of the etching process can be reduced.

[0047] In addition, the increase in the resistivity of the first line structure 110 including the pinned layer 116 when used can be addressed by increasing the thickness of the first line structure 110. Despite the increase in the thickness of the first line structure 110, since at least one of the conventional word line and the bit line is omitted, the overall thickness of the memory device can be reduced. For example, miniaturization of the memory device can be possible.

[0048] Further, when the pinned layer 116 is formed in a line shape, the stability of the pinned layer 116 can be improved, so that the magnetization of the pinned layer 116 can be more easily maintained. This is because the stability, particularly thermal stability, of a magnetic material is proportional to the volume of the magnetic material. Accordingly, the operating characteristics of the memory device can be improved.

[0049] Although FIGS. 1A-1C Although FIGS. 2A-2C is shown to arrange the memory cell between two upper and lower lines crossing each other, for example, the memory cell is shown to be arranged in a single layer. However, the disclosed technology is not limited thereto. In some embodiments, three or more lines can be stacked in a vertical direction over a substrate, and the memory cell can be arranged between two adjacent lines in the vertical direction. For example, as will be discussed with reference to

[0050] FIG. 2A is a plan view showing a memory device based on some embodiments of the disclosed technology, FIG. 2B is FIG. 2A is a cross-sectional view taken along the A-A' line, and FIG. 2C is FIG. 2A is a cross-sectional view taken along the B-B' line.

[0051] ReferenceFIGS. 2A-2C A memory device implemented based on some embodiments of the disclosed technology can include a substrate 200; a plurality of first line structures 210 disposed over the substrate 200 and extending in a first direction while being arranged to be spaced apart from each other in a second direction; a plurality of second line structures 250 disposed over the first line structures 210 and extending in the second direction while being arranged to be spaced apart from each other in the first direction; a plurality of third line structures 290 disposed over the second line 250 and extending in the first direction while being arranged to be spaced apart from each other in the second direction; a stack structure of a first tunnel barrier layer 220, a first free layer 230, and a first selection element layer 240, which overlaps each of intersection regions of the first line structures 210 and the second line structures 250; and a stack structure of a second tunnel barrier layer 260, a second free layer 270, and a second selection element layer 280, which overlaps each of intersection regions of the second line structures 250 and the third line structures 290.

[0052] The first line structures 210 can include at least a pinned layer, and thus can form a first MTJ structure including the pinned layer, the first tunnel barrier layer 220, and the first free layer 230. The first line structures 210 can have substantially the same layer structure as the first line structures 110 of the above-described embodiments. For example, the first line structures 210 can have substantially the same layer structure as the first line structures 110 shown in FIG. 1A. FIG. 1D The first line structures 210 can include at least a pinned layer, and thus can form a first MTJ structure including the pinned layer, the first tunnel barrier layer 220, and the first free layer 230. The first line structures 210 can have substantially the same layer structure as the first line structures 110 of the above-described embodiments. For example, the first line structures 210 can have substantially the same layer structure as the first line structures 110 shown in FIG. 1A.

[0053] The first selection element layer 240 can be disposed over the first MTJ structure. In some embodiments, the stack structure of the first tunnel barrier layer 220, the first free layer 230, and the first selection element layer 240 can be collectively patterned to have sidewalls aligned with each other. Further, the stack structure of the first tunnel barrier layer 220, the first free layer 230, and the first selection element layer 240 can have a rectangular column shape having two sidewalls aligned with two sidewalls of the second line structures 250 in the first direction and two sidewalls aligned with two sidewalls of the first line structures 210 in the second direction. However, the disclosed technology is not limited thereto, and the sidewalls of the first tunnel barrier layer 220, the first free layer 230, and the first selection element layer 240 can not be aligned with each other. Alternatively, the sidewalls of the first tunnel barrier layer 220, the first free layer 230, and the first selection element layer 240 can be aligned with each other without being aligned with the sidewalls of the first line structures 210 and / or the second line structures 250.

[0054] In the intersection region of the first line structure 210 and the second line structure 250, the first MTJ structure including the first line structure 210, the first tunnel barrier layer 220, and the first free layer 230 and the first select element layer 240 can form the first memory cell MC1. The first line structure 210 can constitute part of the first MTJ structure and also transmit a voltage or a current to one end (e.g., a lower end of the first memory cell MC1). For example, the first line structure 210 can serve as both part of the first MTJ structure and a voltage / current transmission line (e.g., a bit line, a word line).

[0055] The second line structure 250 can be used to transmit a voltage or a current to the other end (e.g., an upper end of the first memory cell MC1). Accordingly, a current can be generated through the first line structure 210, the first memory cell MC1, and the second line structure 250, thereby writing data to or reading data from the first memory cell MC1.

[0056] Further, the second line structure 250 can include at least a pinned layer, and thus a second MTJ structure including the pinned layer, the second tunnel barrier layer 260, and the second free layer 270 can be formed. The second line structure 250 can have substantially the same structure as the first line structure 210.

[0057] The second select element layer 280 can be disposed above the second MTJ structure. In some embodiments, a stack structure of the second tunnel barrier layer 260, the second free layer 270, and the second select element layer 280 can be collectively patterned to have sidewalls aligned with each other. Further, the stack structure of the second tunnel barrier layer 260, the second free layer 270, and the second select element layer 280 can have a rectangular column shape having two sidewalls aligned with two sidewalls of the second line structure 250 in a first direction and two sidewalls aligned with two sidewalls of the third line structure 290 in a second direction. However, the disclosed technology is not limited thereto, and the sidewalls of the second tunnel barrier layer 260, the second free layer 270, and the second select element layer 280 can not be aligned with each other. Alternatively, the sidewalls of the second tunnel barrier layer 260, the second free layer 270, and the second select element layer 280 can be aligned with each other without being aligned with the sidewalls of the second line structure 250 and / or the third line structure 290. The stack structure of the second tunnel barrier layer 260, the second free layer 270, and the second select element layer 280 can overlap the stack structure of the first tunnel barrier layer 220, the first free layer 230, and the first select element layer 240, and can have sidewalls aligned with sidewalls of the stack structure of the first tunnel barrier layer 220, the first free layer 230, and the first select element layer 240.

[0058] In the intersection region of the second line structure 250 and the third line structure 290, the second MTJ structure including the second line structure 250, the second tunnel barrier layer 260, and the second free layer 270, and the second select element layer 280 can form a second memory cell MC2. The second line structure 250 can constitute part of the second MTJ structure and also transmit a voltage or a current to one end (e.g., a lower end of the second memory cell MC2). For example, the second line structure 250 can function as both part of the MTJ structure and a voltage / current transmission line (e.g., a bit line, a word line).

[0059] The third line structure 290 can be used to transmit a voltage or a current to the other end (e.g., an upper end of the second memory cell MC2). Thus, a current can be generated through the second line structure 250, the second memory cell MC2, and the third line structure 290, thereby writing data to or reading data from the second memory cell MC2.

[0060] The third line structure 290 can be formed to overlap the first line structure 210 and can have a sidewall aligned with a sidewall of the first line structure 210. Since the third line structure 290 does not constitute part of the MTJ structure unlike the first line structure 210 and / or the second line structure 250, the third line structure 290 can have a single-layer structure or a multi-layer structure including a low-resistance conductive material. For example, the third line structure 290 can include a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), or titanium (Ti), a metal nitride such as titanium nitride (TiN) or tantalum nitride (TaN), or a combination thereof. However, the third line structure 290 can have substantially the same structure as the first line structure 210 and / or the second line structure 250.

[0061] In some embodiments of the disclosed technology, the first line structure 210 can function as one of a word line and a bit line for driving the first memory cell MC1 and reading or writing data from or to the memory cell MC, while constituting part of the first MTJ structure. The second line structure 250 can function as any one of the word line and the bit line for driving the first memory cell MC1, and can function as any one of the word line and the bit line for driving the second memory cell MC2, while constituting part of the second MTJ structure. The third line structure 290 can function as the other of the word line and the bit line for driving the second memory cell MC2. When the first line structure 210 and the second line structure 250 include a ferromagnetic material to have a larger resistivity than the third line structure 290, each of a thickness of the first line structure 210 and a thickness of the second line structure 250 can be greater than a thickness of the third line structure 290.

[0062] The memory device implemented based on some embodiments of the disclosed technology can achieve all the effects as described above and can also be highly integrated.

[0063] In some embodiments of the disclosed technology, three layers of the line structures 210, 250, and 290 are provided over the substrate 200 and two layers of the memory cells MC1 and MC2 can be provided therebetween, but the disclosed technology is not limited thereto. Four or more layers of the line structures and three or more layers of the memory cells can be provided over the substrate. In this case, the line structures other than the uppermost line structure can have the same line structure as each other and include at least the pinned layer. The uppermost line structure can have the same layer structure as the line structures other than the uppermost line structure or can have a different layer structure from the line structures other than the uppermost line structure. When the resistivity of the uppermost line structure is less than the resistivity of the line structures other than the uppermost line structure, the thickness of the uppermost line structure can be less than the thickness of each of the line structures other than the uppermost line structure.

[0064] In some embodiments of the disclosed technology, the free layer is provided over the pinned layer and the selection element layer is provided over the MTJ structure, but the disclosed technology is not limited thereto, and as will be described below with reference to FIG. 4, the vertical positions of the pinned layer and the free layer, and the vertical positions of the MTJ structure and the selection element layer can be changed. FIGS. 3A-3B

[0065] FIG. 3A is a plan view showing a memory device based on some embodiments of the disclosed technology. FIG. 3B may substantially correspond to FIG. 2A a cross-sectional view taken along the A-A' line.

[0066] Referring to FIG. 3A , the memory device implemented based on some embodiments of the disclosed technology can include a substrate 300; a plurality of first line structures 310 provided over the substrate 300 and extending in a first direction while being arranged to be spaced apart from each other in a second direction; a plurality of second line structures 350 provided over the first line structures 310 and extending in the second direction while being arranged to be spaced apart from each other in the first direction; a plurality of third line structures 390 provided over the second line structures 350 and extending in the first direction while being arranged to be spaced apart from each other in the second direction, a stack structure of a first selection element layer 320, a first free layer 330, and a first tunnel barrier layer 340, the stack structure overlapping each of intersection regions of the first line structures 310 and the second line structures 350 between the first line structures 310 and the second line structures 350; and a stack structure of a second selection element layer 360, a second free layer 370, and a second tunnel barrier layer 380, the stack structure overlapping each of intersection regions of the second line structures 350 and the third line structures 390 between the second line structures 350 and the third line structures 390.​

[0067] Since the first line structure 310 is adjacent to the first selection element layer 320, a pinned layer can not be included. For example, the first line structure 310 can include a low-resistance conductive material such as metal, and can have a single layer structure.

[0068] On the other hand, the second line structure 350 can include at least a pinned layer, and thus can form a first MTJ structure including the pinned layer, the first tunnel barrier layer 340, and the first free layer 330. The second line structure 350 can have substantially the same layer structure as the structure in which the upper and lower portions of the first line structure 110 of the above-described embodiment are inverted. The second line structure 350 and the MTJ structure including the second line structure 350 will be described below by referring to FIG. 3B FIG. 2.

[0069] FIG. 3B is a view illustrating a first MTJ structure based on some embodiments of the disclosed technology.

[0070] Referring to FIG. 3B , the first MTJ structure can include the first free layer 330; the first tunnel barrier layer 340 disposed above the first free layer 330; and the second line structure 350 disposed above the first tunnel barrier layer 340.

[0071] The second line structure 350 can include at least a pinned layer 354. In addition, the second line structure 350 can further include an interface layer 352, a magnetic correction layer 358, and a separation layer 356. The interface layer 352 can be interposed between the pinned layer 354 and the tunnel barrier layer 340. The magnetic correction layer 358 can be disposed to face an upper surface of the pinned layer 354, the upper surface of the pinned layer 354 being opposite to a lower surface of the pinned layer 354 facing the free layer 330. The separation layer 356 can be interposed between the magnetic correction layer 358 and the pinned layer 354.

[0072] Referring back to FIG. 3A , the third line structure 390 can include at least a pinned layer to form a second MTJ structure in common with the second tunnel barrier layer 380 and the second free layer 370. The third line structure 390 can have substantially the same layer structure as the second line structure 350.

[0073] Since the second line structure 350 forms part of the first MTJ structure, and the third line structure 390 forms part of the second MTJ structure, the first selection element layer 320 and the second selection element layer 360 can be disposed below the first MTJ structure and the second MTJ structure, respectively.

[0074] A memory device implemented based on some embodiments of the disclosed technology can achieve all the effects as described above and can also be highly integrated.

[0075] In some embodiments of the disclosed technology, three-layered line structures 310, 350, and 390 can be provided over the substrate 300 and two-layered memory cells MC1 and MC2 can be provided therebetween, but the disclosed technology is not limited thereto. Four or more layers of line structures and three or more layers of memory cells can be provided over the substrate. In this case, except for the lowermost line structure, the remaining line structures can have the same line structure as each other and include at least a pinned layer. The lowermost line structure can have the same layer structure as the remaining line structures or can have a different layer structure from the remaining line structures. When the resistivity of the lowermost line structure is less than the resistivity of the remaining line structures, the thickness of the lowermost line structure can be less than the thickness of each of the remaining line structures.

[0076] In some embodiments of the disclosed technology, the tunnel barrier layer has an island shape overlapping with the intersection region of the upper and lower lines. In an embodiment, it has been described that the tunnel barrier layer can be co-patterned with the free layer to have a sidewall aligned with the free layer. However, in another embodiment, the tunnel barrier layer located at the intersection region of either one of the upper and lower lines can not be spaced apart from the tunnel barrier layer located at the intersection region of the other one of the upper and lower lines. For example, the tunnel barrier layer can be formed in a line shape by being co-patterned with any one of the upper and lower lines, having a sidewall aligned with any one of the upper and lower lines. Alternatively, for example, the tunnel barrier layer can have a plate shape overlapping with all of the memory cells by not being patterned. This will be described exemplarily with reference to FIGS. 6A and 6B. FIGS. 4A-5C While being exemplarily described.

[0077] FIG. 4A is a plan view illustrating a memory device based on some embodiments of the disclosed technology, FIG. 4B is FIG. 4A a cross-sectional view taken along the line A-A', and FIG. 4C is FIG. 4A a cross-sectional view taken along the line B-B'.

[0078] Reference will be made to FIGS. 4A-4CThe memory device of some embodiments can include a substrate 400; a plurality of first line structures 410 disposed over the substrate 400 and extending in a first direction while being arranged to be spaced apart from each other in a second direction; a plurality of second line structures 450 disposed over the first line structures 410 and extending in the second direction while being arranged to be spaced apart from each other in the first direction; a plurality of third line structures 490 disposed over the second lines 450 and extending in the first direction while being arranged to be spaced apart from each other in the second direction; a stack structure of a first free layer 430 and a first select element layer 440 that overlaps with each of the intersection regions of the first line structures 410 and the second line structures 450 between the first line structures 410 and the second line structures 450; a stack structure of a second free layer 470 and a second select element layer 480 that overlaps with each of the intersection regions of the second line structures 450 and the third line structures 490 between the second line structures 450 and the third line structures 490; a first tunnel barrier layer 420 interposed between the first free layer 430 and the first line structures 410 and overlapping with the first line structures 410 to extend in the first direction; and a second tunnel barrier layer 460 interposed between the second free layer 470 and the second line structures 450 and overlapping with the second line structures 450 to extend in the second direction.

[0079] For example, the first tunnel barrier layer 420 can have sidewalls aligned with sidewalls of the first line structures 410 by being co-patterned with the first line structures 410. The second tunnel barrier layer 460 can have sidewalls aligned with sidewalls of the second line structures 450 by being co-patterned with the second line structures 450.

[0080] In some embodiments of the disclosed technology, the characteristics of the first MTJ structure and the second MTJ structure can be further improved due to the reduced potential etch damage to the first tunnel barrier layer 420 and the second tunnel barrier layer 460.

[0081] FIG. 5A is a plan view showing a memory device based on some embodiments of the disclosed technology, FIG. 5B is FIG. 5A is a cross-sectional view taken along the A-A' line, and FIG. 5C is FIG. 5A is a cross-sectional view taken along the B-B' line.

[0082] Reference is made to FIGS. 5A-5CThe memory device of some embodiments can include a substrate 500; a plurality of first line structures 510 disposed over the substrate 500 and extending in a first direction while being arranged to be spaced apart from each other in a second direction; a plurality of second line structures 550 disposed over the first line structures 510 and extending in the second direction while being arranged to be spaced apart from each other in the first direction; a plurality of third line structures 590 disposed over the second line structures 550 and extending in the first direction while being arranged to be spaced apart from each other in the second direction; a stack structure of a first free layer 530 and a first selection element layer 540 that overlaps with each of the intersection regions of the first line structures 510 and the second line structures 550 between the first line structures 510 and the second line structures 550; a stack structure of a second free layer 570 and a second selection element layer 580 that overlaps with each of the intersection regions of the second line structures 550 and the third line structures 590 between the second line structures 550 and the third line structures 590; a first tunnel barrier layer 520 interposed between the first free layer 530 and the first line structures 510 and having a plate shape, and a second tunnel barrier layer 560 interposed between the second free layer 570 and the second line structures 550 and having a plate shape.

[0083] For example, the first tunnel barrier layer 520 and the second tunnel barrier layer 560 can not be patterned. Thus, each of the first tunnel barrier layer 520 and the second tunnel barrier layer 560 can have a shape that overlaps with all of the first free layers 530 and all of the second free layers 570.

[0084] In some embodiments of the disclosed technology, potential etching damage to the first tunnel barrier layer 520 and the second tunnel barrier layer 560 can be avoided, such that the characteristics of the first MTJ structure and the second MTJ structure are further improved.

[0085] Although this patent document contains many details, this should not be interpreted to limit any application or claimed scope in any way, but rather to describe features that can be specific to a particular embodiment of a specific application. Some features that are described in the context of separate embodiments of this patent document can also be implemented in combination, within a single embodiment. Conversely, multiple features described in the context of a single embodiment can also be implemented separately or in any suitable subcombination. Also, although features can be described above as acting in particular combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination and the claimed combination can be directed to a subcombination or variation of a subcombination.

[0086] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring such an order, or that all illustrated operations be performed, to achieve desirable results. Further, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

[0087] Only a few implementations and examples are described and other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.

[0088] While multiple embodiments are described above, it should be understood that they have been described only by way of example and that many changes and modifications can be made to these embodiments by those skilled in the art without departing from the spirit and scope of the teachings as defined by the claims.

Claims

1. A semiconductor device comprising: a plurality of first line structures extending in a first direction, each of the plurality of first line structures including a first pinned layer exhibiting magnetization in a fixed magnetization direction; a plurality of second line structures spaced apart from the first line structures and extending in a second direction crossing the first direction; a plurality of first free layers each exhibiting magnetization having a variable magnetization direction, the first free layers overlapping with intersection regions of the first line structures and the second line structures, respectively, between the first line structures and the second line structures; and a first tunnel barrier layer interposed between the first line structures and the first free layers.

2. The semiconductor device of claim 1, wherein, The first tunnel barrier layer overlaps with the first free layers and has sidewalls aligned with sidewalls of the first free layers.

3. The semiconductor device of claim 1, wherein, The first tunnel barrier layer overlaps with the first line structures and has sidewalls aligned with sidewalls of the first line structures.

4. The semiconductor device of claim 1, wherein, The first tunnel barrier layer has a plate shape overlapping with all of the plurality of first free layers.

5. The semiconductor device of claim 1, wherein, The second line structures include a conductive material having a resistivity smaller than a resistivity of the first line structures.

6. The semiconductor device of claim 5, wherein, The first line structures have a thickness greater than a thickness of the second line structures.

7. The semiconductor device of claim 1, wherein, The first line structures and the second line structures have a same layer structure.

8. The semiconductor device of claim 1, further comprising: a plurality of third line structures spaced apart from the second line structures and extending in the first direction; a plurality of second free layers overlapping with intersection regions of the second line structures and the third line structures, respectively, between the second line structures and the third line structures, each of the plurality of second free layers having a variable magnetization direction; and a second tunnel barrier layer interposed between the second line structures and the second free layers, wherein the second line structures include a second pinned layer having a fixed magnetization direction.

9. The semiconductor device of claim 8, wherein, The second tunnel barrier layer overlaps with the second free layers and has sidewalls aligned with sidewalls of the second free layers.

10. The semiconductor device of claim 8, wherein, The second tunnel barrier layer overlaps with the second line structures and has sidewalls aligned with sidewalls of the second line structures.

11. The semiconductor device of claim 8, wherein, The second tunnel barrier layer has a plate shape overlapping with all of the plurality of second free layers.

12. The semiconductor device of claim 8, wherein, The third line structures include a conductive material having a resistivity smaller than a resistivity of each of the first line structures and the second line structures.

13. The semiconductor device of claim 12, wherein, Each of the first line structures and the second line structures has a thickness greater than a thickness of the third line structures.

14. The semiconductor device of claim 8, wherein, The first line structures, the second line structures, and the third line structures have a same layer structure.

15. The semiconductor device of claim 1, wherein, The first line structures further include a magnetic correction layer having a magnetization direction opposite to the magnetization direction of the first pinned layer and a separation layer interposed between the first pinned layer and the magnetic correction layer.

16. The semiconductor device of claim 1, wherein, The first line structures further include an interface layer interposed between the first pinned layer and the first tunnel barrier layer.

17. The semiconductor device of claim 1, wherein, An overlapping portion of the first line structure, the first free layer, and the first tunnel barrier layer forms a structure that stores data based on a relative direction between a magnetization direction of the first line structure and a magnetization direction of the first free layer.

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