Real-time caustic mapping

Abstract

Apparatus, systems, and techniques for ray tracing caustics in a scene using feedback of photon information between frames. In at least one embodiment, photon tracing (104, 202, 504) determines photon occupancy (406) in an individual frame as a result of individual photons interacting with one or more caustic-casting objects in that frame, and uses these photon occupancies (406) to facilitate photon tracing (104, 202, 504) in subsequent frames.

Description

Technical Field

[0001] At least one embodiment relates to processing resources for generating ray-traced caustic effects in a scene using feedback of photon information between frames. For example, at least one embodiment relates to a processor or computing system for determining photon patterns in a scene as a result of individual photons interacting with one or more objects that reflect or alter the photons' paths, and for using this information for subsequent frame rendering. Background Art

[0002] Caustics are a common phenomenon in both real-life and rendered scenes containing water, metallic materials, or transparent surfaces. Caustics occur when photons emitted by a light source interact with caustics-casting objects, such as opaque objects (including metallic materials) through which light cannot pass but reflects, or transparent / translucent surfaces (including water and glass) through which light can pass. This interaction (usually from reflection or refraction) causes the photons in the light to scatter, and the resulting scattering can sometimes become focused or have altered trajectories. Due to the complexity of calculating the photon data associated with caustics, many renderers either ignore caustics or handle them crudely using techniques such as static decal textures. However, the increased availability of ray tracing performed by graphics processing units has made it more feasible to calculate the photon data associated with caustics in real time. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a block diagram illustrating an improved technique for photon scattering to determine improved caustic information from ray / photon tracing associated with a scene, in accordance with at least one embodiment;

[0004] Figure 2 is a block diagram illustrating data flow between data storage buffers for facilitating determination of improved caustics information from photon tracing, according to at least one embodiment;

[0005] Figure 3 is a block diagram illustrating photon tracing (such as photon mapping) to determine caustic information in accordance with at least one embodiment;

[0006] Figure 4 is a block diagram illustrating determining ray occupancy from data in a photon buffer by photon scattering in accordance with at least one embodiment;

[0007] Figure 5 is a block diagram illustrating a feedback loop for improving caustics information determined by photon tracing using data from a task buffer, according to at least one embodiment;

[0008] Figure 6Ais a block diagram illustrating determining perturbed soft caustics information according to at least one embodiment;

[0009] Figure 6B is a block diagram illustrating the use of position and direction information associated with photons emitted by an area light to improve soft caustic information for determining disturbances in accordance with at least one embodiment;

[0010] Figure 7 A process for performing an improved technique for photon scattering to determine improved caustics information in a scene is shown in accordance with at least one embodiment;

[0011] Figure 8 An exemplary data center is shown in accordance with at least one embodiment;

[0012] Figure 9 A processing system according to at least one embodiment is shown;

[0013] Figure 10 A computer system according to at least one embodiment is shown;

[0014] Figure 11 A system according to at least one embodiment is shown;

[0015] Figure 12 An exemplary integrated circuit according to at least one embodiment is shown;

[0016] Figure 13 A computing system according to at least one embodiment is shown;

[0017] Figure 14 An APU is shown according to at least one embodiment;

[0018] Figure 15 A CPU according to at least one embodiment is shown;

[0019] Figure 16 An exemplary accelerator integrated slice is shown in accordance with at least one embodiment;

[0020] Figure 17A and Figure 17B An exemplary graphics processor is shown in accordance with at least one embodiment;

[0021] Figure 18A A graphics core according to at least one embodiment is shown;

[0022] Figure 18B GPGPU according to at least one embodiment is shown;

[0023] Figure 19A A parallel processor according to at least one embodiment is shown;

[0024] Figure 19B illustrates a processing cluster according to at least one embodiment;

[0025] Figure 19C A graphics multiprocessor is shown in accordance with at least one embodiment;

[0026] Figure 20 A graphics processor according to at least one embodiment is shown;

[0027] Figure 21 A processor according to at least one embodiment is shown;

[0028] Figure 22 A processor according to at least one embodiment is shown;

[0029] Figure 23 illustrates a graphics processor core according to at least one embodiment;

[0030] Figure 24 illustrates a PPU according to at least one embodiment;

[0031] Figure 25 shows a GPC according to at least one embodiment;

[0032] Figure 26 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0033] Figure 27 illustrates a software stack for a programming platform according to at least one embodiment;

[0034] Figure 28 According to at least one embodiment, Figure 27 CUDA implementation of the software stack;

[0035] Figure 29 According to at least one embodiment, Figure 27 ROCm implementation of the software stack;

[0036] Figure 30 According to at least one embodiment, Figure 27 OpenCL implementation of the software stack;

[0037] Figure 31 illustrates software supported by a programming platform according to at least one embodiment;

[0038] Figure 32 According to at least one embodiment, Figures 27-30 Compiled code executed on the programming platform;

[0039] Figure 33 According to at least one embodiment, Figures 27-30More detailed compiled code executed on the programming platform;

[0040] Figure 34 Transforming source code before compiling it according to at least one embodiment is shown;

[0041] Figure 35A A system configured to compile and execute CUDA source code using different types of processing units is shown in accordance with at least one embodiment;

[0042] Figure 35B A method configured to compile and execute a program using a CPU and a CUDA-enabled GPU according to at least one embodiment is shown. Figure 35A CUDA source code system;

[0043] Figure 35C A method configured to compile and execute using a CPU and a non-CUDA enabled GPU according to at least one embodiment is shown. Figure 35A CUDA source code system;

[0044] Figure 36 According to at least one embodiment, Figure 35C An example kernel converted by the CUDA to HIP conversion tool;

[0045] Figure 37 More details are shown according to at least one embodiment. Figure 35C a non-CUDA-enabled GPU; and

[0046] Figure 38 shows how threads of an exemplary CUDA grid are mapped to Figure 37 different computational units; and

[0047] Figure 39 It shows how to migrate existing CUDA code to data-parallel C++ code according to at least one embodiment. DETAILED DESCRIPTION

[0048] In the foregoing and following descriptions, various techniques are described. For purposes of explanation, specific configurations and details are set forth to provide a thorough understanding of possible ways to implement these techniques. However, it will also be apparent that the techniques described below can be practiced in different configurations without these specific details. Furthermore, well-known features may be omitted or simplified to avoid obscuring the techniques being described.

[0049] Figure 1The present invention is a block diagram illustrating an improved technique for photon scattering to determine improved caustic information for ray tracing (also referred to as photon tracing 104, hereinafter referred to as photon tracing) associated with a scene during graphics processing by a graphics processing unit (GPU), according to at least one embodiment. The improved technique for photon scattering includes an algorithm that implements adaptive anisotropic photon scattering 102. Adaptive anisotropic photon scattering 102 can be implemented as hardware operations and / or software instructions that, when executed, perform photon tracing or photon mapping 104 through a scene and determine caustics for any light particles that interact with a caustics caster (such as an opaque or transparent object) in the scene during photon tracing. In embodiments, a caustic caster is an opaque surface, such as a reflective surface that reflects light in different directions, or a transparent surface that changes the path of a photon through it. In embodiments, a caustic is a concentration of photons projected through a scene during graphics processing by a processor (such as, but not limited to, a GPU) that interacts with a caustics caster (such as an opaque or transparent object), thereby changing the trajectory of those photons. Traditionally, determining caustics in a scene is performed by photon mapping algorithms, which involve tracing photons through the scene via photon tracing, or photon mapping, and then performing density estimation. However, traditional algorithms only work in a fixed dimension and produce blurry or noisy results.

[0050] Adaptive anisotropic photon scattering 102 improves the traditional photon mapping algorithm by performing the step of adaptively refining the photon information between frames. To achieve this, in an embodiment, adaptive anisotropic photon scattering includes four buffers for storing photon data, as shown below in combination with Figure 2 First, in an embodiment, adaptive anisotropic photon scattering 102 includes using a task buffer implemented (for example, but not limited to) as a structured buffer containing data about photons or rays for tracking in the current rendered frame. Second, in an embodiment, adaptive anisotropic photon scattering 102 includes using a photon buffer to record photon data related to the photons or rays tracked in the current frame. The photon or ray data includes the location where the photon or ray hit the object or surface in the current frame in combination with the occupancy and intensity of the photon or ray, as described below in conjunction with Figure 4 Third, in an embodiment, adaptive anisotropic photon scattering 102 includes using a caustic buffer that indicates a render target to be rendered in screen space corresponding to a frame for photons, as described below in conjunction with Figure 2 Finally, adaptive anisotropic photon scattering 102 includes the use of one or more feedback buffers, as described below in conjunction with Figure 2 and Figure 5The one or more feedback buffers include information including ray or photon occupancy; intensity variance of individual photons or rays, and ray density associated with one or more projected or tracked photons or rays. In an embodiment, information stored in one feedback buffer is combined with information in another feedback buffer to update the task buffer with new photon or ray information, as described below in conjunction with Figure 5 As stated.

[0051] In an embodiment, using these data buffers, adaptive anisotropic photon scattering 102 performs photon tracing 104. In an embodiment, photon tracing 104 is hardware operations and / or software instructions that, when executed, trace rays of light carrying lighting information (photons) from a light source through a scene, reflecting or refracting the light due to the presence of caustics (such as opaque or transparent objects), and recording this information when the light hits an opaque, non-specular (rough) surface. In an embodiment, when emitting photons from a fixed resolution, a task buffer is not necessary and adaptive anisotropic photon scattering 102 is not performed. When a dynamic (non-fixed) resolution is used, adaptive anisotropic photon scattering 102 uses an adaptive method to emit photons in different areas of the scene based on the task buffer, and tracks these photons in the scene, as described below in conjunction with Figure 2 and Figure 3 During photon tracing 104, if any photon hits a caustic projectile (such as an opaque or transparent surface), the adaptive anisotropic photon scattering 102 creates a record in the photon buffer and adds the occupancy information to the feedback buffer, as described below in conjunction with Figure 2 and Figure 3 Further described.

[0052] In an embodiment, after photon tracing 104, adaptive anisotropic photon scattering 102 performs photon scattering 106. In an embodiment, photon scattering 106 is a hardware operation and / or software instruction that, when executed, plots each photon or ray indicated in the photon buffer as a data value that can be used to display an elliptical occupancy, and stores the elliptical occupancy information in a caustic buffer for each pixel indicated in the photon buffer, as described below in conjunction with Figure 2 and Figure 4As further described. In at least one embodiment, an elliptical occupancy, or occupancy of any other shape, may include data values indicating one or more pixels that a photon or ray hits or lands on. In an embodiment, occupancy is determined based at least in part on pixel position or position combined with intensity. During photon scattering 106, photons are "drawn" onto a screen space image, called a caustic buffer, where the pixel position of each photon is calculated and the corresponding pixel in the caustic buffer is lit. During photon tracing 104, the shape and intensity of each photon occupancy at each pixel is adjusted by the photon differential from interacting with a caustic projectile, such as an opaque or transparent object.

[0053] During compound caustics 108, adaptive anisotropic photon scattering 102 applies the data stored in the caustic buffer to the current scene. In embodiments, compound caustics 108 are hardware operations and / or software instructions that, when executed, apply the caustic pattern of photons traced during photon tracing 104 to screen space for rendering for the current frame. Because the caustic pattern is generated during photon scattering 106 and recorded in the caustic buffer, compound caustics 108 does not utilize photon information.

[0054] Adaptive anisotropic photon scattering 102 improves caustic rendering by applying feedback 110. In an embodiment, applying feedback 110 includes hardware operations and / or software instructions that, when executed, combine one or more feedback buffers associated with previously rendered frames and a feedback buffer generated for the current frame to generate a task buffer for the next frame to be rendered, as described below in conjunction with Figure 2 and Figure 5 During feedback 110, one or more data values in the task buffer are updated by combining the photon or ray density data for each pixel in the current frame determined during photon tracing 104 with the photon or ray density data for each pixel in the previous frame. The current and previous photon or ray density data are combined using the following Figure 5 The techniques described further below are combined.

[0055] Figure 2 is a block diagram illustrating the flow of data between data storage buffers for facilitating determination of improved caustics information from photon tracing, according to at least one embodiment. In an embodiment, a task buffer 204 is a data buffer that includes information about photons 208 or rays to be emitted by a light source 206 in a scene, the scene including a surface 212 on which the photons 208 or rays are to be traced and one or more caustics casters 230 that may interact with the photons 208 or rays. As described above in conjunction with Figure 1 As described above, a task buffer 204 is used during photon tracing 202. During photon tracing 202, photons 208 are emitted 210 from a light source 206 in a scene to be rendered 224, according to a ray density value for each pixel indicated in the task buffer 204. The ray density value in the task buffer 204 indicates how many photons 208 are to be emitted 210 or traced starting from each pixel corresponding to the light source 206.

[0056] In embodiments, light source 206 is one or more data values (such as pixels in a scene) indicating one or more locations from which one or more photons 208 are to be traced during photon tracing 202. In embodiments, photons 208 are data values that include position and direction information, as described below. During photon tracing 202, photons 208 are emitted 210 from light source 206 or traced to surface 212. In embodiments, surface 212 is a data value indicating an object that does not pass through or reflect photons 208 emitted 210 or traced from light source 206. Photons 208 emitted 210 or traced from light source 206 that strike or otherwise interact with surface 212 are photon hits 214. In embodiments, photon hits 214 are data values to be stored in photon buffer 218 indicating that photons 208 emitted from light source 206 landed on, struck, or otherwise interacted with surface 212 during photon tracing. In an embodiment, photon hits 214 include only photons 208 emitted 210 or traced from light source 206 that interacted with one or more caustic projectiles 230. In an embodiment, caustic projectiles 230 are data values indicating objects (such as three-dimensional (3D) shapes in a scene) through which one or more photons 208 passed during photon tracing 202, or which were reflected by one or more photons 208 during photon tracing 202. In an embodiment, caustic projectiles 230 are data values indicating solid three-dimensional shapes (such as metallic objects) through which light cannot pass. In another embodiment, caustic projectiles 230 are data values indicating transparent objects through which light can pass. Caustic projectiles 230 affect the occupancy of photons 208, as indicated in photon buffer 218 and one or more feedback buffers 228.

[0057] The photon density indicates the number of photons to be emitted near a specific u, v coordinate in light space. For point lights and spot lights, the photon density is the number of photons emitted near a given direction. For directional lights, the photon density indicates the number of photons emitted near a given point. The emitted photons that have hit 214 the rough opaque surface 212 are stored in a photon buffer 218. During photon tracing 202, photons 208 or rays emitted from a light source 206 have two position parameters for directional light from the light source 206:

[0058] p=p(u,v)

[0059] Or two directional parameters for a point light emitted 210 from a light source 206:

[0060] d=d(u,v)

[0061] After photon tracing 202 of a photon 208 emitted 210 or traced from a light source 206, the position p' of the photon 208 on the surface 212 is determined based on all parameters u, v such that:

[0062] p′=p′(u,v)

[0063] If a photon 208 or ray is perturbed during photon tracing 202, such as if it passes through a caustic projectile 230, the perturbation Δp' of the photon position of the photon 208 is determined as:

[0064]

[0065] in and is the ray differential at the intersection point where the photon 208 interacts with the caustic projectile 230 .

[0066] During photon tracing 202, a ray generation shader is dispatched to shoot or trace 210 photons 208 or rays according to the ray density indicated in the task buffer 204. Each compute thread in the ray generation shader only traces one photon 208 along one or more rays 210, where several rays are used and new rays are created and traced when a photon is reflected or refracted. If multiple light sources 206 are to be traced during photon tracing 202, each light is assigned a specific region in the photon density texture. Each light source 206 is assigned an identifier. Each compute thread in the ray generation shader then uses the u,v coordinates to determine which light source corresponds to the photon 208 or ray to shoot 210 or trace during photon tracing 202.

[0067] Data corresponding to photons 208 that have interacted with caustic projectiles 230 and struck 214 a surface 212 is stored in a photon buffer 218. In an embodiment, the photon buffer 218 is a set of data values that includes information about photons 208 or rays emitted 210 by light sources 206 in the scene that interacted with or otherwise intersected a caustic projectile 230 during photon tracing 202. In an embodiment, the photon buffer 218 stores the results of a set of photons striking one or more caustic projectiles 230. During photon scattering 216, the ray occupancy information for each pixel in the photon buffer 218 is used to draw the photons on a texture (such as an image) stored in the caustic buffer 220, as described below in conjunction with Figure 4 As described. Ray occupancy is calculated from the ray density for each pixel in the ray density texture by determining the area of the pixel in the photon buffer divided by the number of samples indicating the number of photons that landed on that pixel in the scene (as indicated by the ray density). A ray or photon density texture or buffer records ray density information in light space. Ray density information is data that indicates, for each pixel, a count or number indicating how many photons 208 emitted 210 from a light source 206 passed through or otherwise interacted with a caustic projectile 230 before hitting a surface 212 during photon tracing 202. In an embodiment, the ray density information does not distinguish between discarded photons and retained photons, and only indicates how many photons should be emitted to represent the photons 208 that hit 214 the surface 212 after interacting with the caustic projectile 230. The ray density information is in light space, and the pixels in the ray density information cover a small u, v coordinate range of pixels in screen space, or pixels that are actually displayed on the screen.

[0068] In an embodiment, the caustic buffer 220 is data including a normal texture representing a scene to be displayed on a screen, wherein the texture includes caustic patterns corresponding to the photons 208 emitted 210 by the light source 206 during photon tracing 202. Using the texture stored in the caustic buffer 220, caustics indicating the occupancy of the photons during caustic application are applied to screen space and transferred to the hardware and / or software operations responsible for rendering the scene 224.

[0069] To improve caustic rendering, one or more feedback buffers 228 facilitate integration of caustic information determined during the previous frame and the current frame into the next frame during feedback 226. In an embodiment, the feedback buffer 228 is a data buffer that includes a projected area indicating the average screen-space area of the photons 208 emitted during the photon tracing 202 and the average brightness of each screen pixel in the caustic buffer 220. During photon tracing 202 for each frame, the occupancy of each photon 208 is projected into screen space, and the projected area is accumulated in the feedback buffer along with the temporal intensity variance of the pixels hit by each photon 208. During feedback 226, the projected area and intensity variance stored in the feedback buffer for the current frame are combined to compute a ray density, which is blended with the ray density texture stored in the feedback buffer 228 for the previous frame and used to drive the photon emission indicated in the task buffer 204 for the next frame, as described below in conjunction with Figure 5 As stated.

[0070] Figure 3 is a block diagram illustrating photon tracing (such as photon tracing) to determine caustic information according to at least one embodiment. Figure 1 and Figure 2 The depicted task buffer 302 includes data for facilitating tracing one or more photons or rays 306, 314, 318 across a scene in a frame. Figure 2 As shown, photons or light rays 306 , 314 , 318 emitted from light source 304 are projected onto surface 310 .

[0071] Photons or rays 306, 314, 318 emitted from light source 304 interact with caustic projectiles (such as opaque / transparent object 316), as described above in conjunction with Figure 2 If one or more light rays 314, 318 pass through a caustic projectile (such as an opaque / transparent object 316), the photons corresponding to the one or more light rays 314, 318 are disturbed before intersecting or landing on the surface 310. Photons or light rays 306, 314, 318 that intersect or otherwise interact with a caustic projectile (such as an opaque / transparent object 316) have a disturbed trajectory, the position and density of which are recorded in the photon buffer 322, as described above in conjunction with Figure 1 and Figure 2 The projected area and brightness variance of the pixel associated with the surface 310 on which the photon falls are stored in one or more feedback buffers 322, as described above in conjunction with Figure 2 As stated.

[0072] One or more rays 306, 314, 318 or photons that pass through or otherwise interact with a caustic projector (such as an opaque / transparent object 316) are photon hits 320, and data associated with these rays 306, 314, 318 or photons is recorded or otherwise indicated in a photon and / or feedback buffer 322. One or more rays 306, 314, 318 or photons that do not pass through or otherwise interact with a caustic projector (such as an opaque / transparent object 316) are discarded 312 and do not contribute to caustics in that frame.

[0073] Figure 4 is a block diagram illustrating photon occupancy 406 determined from ray occupancy data in a photon buffer 406 by transforming 404, according to at least one embodiment. In an embodiment, photon occupancy 406 is one or more data values corresponding to a pixel in a light space ray density texture that includes information about one or more photons projected to each pixel. Figures 1 to 3 As described above, the photon buffer 402 includes light density or occupancy information for each pixel in the frame. Figure 1 As described, a transform 404 operation is performed. The transform 404 operation maps each photon indicated by the information in the photon buffer into an elliptical occupancy 410 for each pixel 408 in the frame.

[0074] The information stored in the photon buffer 402 indicates the number of photons or rays that interacted with the caustic projectile (as described above) and landed on (intersected) pixels corresponding to opaque, rough surfaces in the scene. The information stored in the photon buffer 402 includes integer or floating point values indicating the number of photons or rays that interacted with the caustic projectile and landed on (intersected) each pixel corresponding to the opaque, rough surface in the scene. For each entry in the photon buffer 402 corresponding to an individual pixel, one or more photon occupancies are calculated 410. The number of photon occupancies calculated or converted 404 is the nearest squared number less than the ray density in the ray density buffer determined for each pixel in the photon buffer 402.

[0075] During the conversion 404, the adaptive anisotropic photon scattering algorithm calculates a photon occupancy 406 for each photospace pixel 408 in the scene. Each pixel 408 includes one or more occupancies 410 corresponding to one or more photons or rays emitted or traced during photon tracing that fall within each pixel 408. The photon occupancies 410 are calculated using the above-described method in conjunction with Figure 2 The photon or light differential information and The calculated photon occupancy 406 is stored in the photon buffer 402 and then provided to the photon scattering 412 to be applied to the texture in the caustic buffer.

[0076] Figure 5 is a block diagram illustrating a feedback loop for improving caustics information determined by photon tracing 504 using data from task buffer 502, according to at least one embodiment. Figure 1-Figure 3 As described, the task buffer 502 includes photon information available during photon tracing 504 to trace or otherwise determine the paths of photons that may have interacted with one or more caustic projectors (such as opaque or transparent objects). Information about photons that interacted with one or more caustic projectors (such as opaque or transparent objects) is recorded in a feedback buffer for a particular frame or scene.

[0077] The feedback buffer for a particular frame or scene includes a projected area 506 texture and a luminance variance 508 texture. In an embodiment, the projected area 506 texture is a set of data values that indicates that pixels corresponding to the texture or image of the scene include the average screen-space area of photons emitted or traced during photon tracing 504. In an embodiment, the luminance variance 508 texture is a set of data values that indicates that pixels corresponding to the texture or image of the scene include the average luminance variance of pixels in the frame or scene that were hit by photons during photon tracing 504.

[0078] During photon tracing 504, the occupancy of each photon, as stored in or otherwise indicated by the task buffer 502, is projected into the screen space of the frame. The area of each traced photon, in pixels, is stored in the projected area 506 texture. During photon tracing 504, the temporal intensity variance between pixels over which photons were traced is also stored in the intensity variance 508 texture.

[0079] The proposed ray density d' 512 for each pixel in the current frame is determined by combining 510 the projected area 506 texture and the luminance variance 508 texture for each pixel. The projected area 506 texture and the luminance variance 508 texture in the current feedback buffer are combined 510 as:

[0080]

[0081] Where d′ is the proposed ray density 512, d is the previous ray density 516 stored in the feedback buffer for the previous frame 518, a is the average screen space projection size from the projection area, and a tis the target projection size, v is the brightness variance of photons emitted during photon tracing 504 , and g is the brightness gain. The proposed ray density d′ 512 is stored in the feedback buffer for the current frame 514 .

[0082] To improve the accuracy of the proposed light density d' 512, the proposed photon or light density for each pixel is updated 520 or blended between neighboring pixels of the proposed light density d' 512. In one embodiment, the equation for updating 520 the proposed light density d' 512 is:

[0083]

[0084] Among them, d new is the new ray density to be stored and updated in the ray density texture, d′ is the suggested ray density 512, and w t is the time mixing factor, w i is the spatial mixing factor, and d i is the light density in the current pixel and its neighborhood. In an embodiment, w t and w i Both are floating point values between 0 and 1. In the embodiment, w t A higher value of d new In an embodiment, the ray density indicated by the ray density texture is converted into ray tasks and stored in the task buffer 502.

[0085] In an embodiment, the task buffer 502 is updated with the new ray density d new In another embodiment, the task buffer 502 is updated based at least in part on the new light density d new The calculated light occupancy data is updated.

[0086] Figure 6A is a block diagram illustrating determining perturbed soft caustic information according to at least one embodiment. In embodiments, soft caustics are generated by photons or rays 604, 608 that are emitted from an area light 602 and that pass through or otherwise interact with a caustic projector (such as an opaque / transparent object 606) during photon tracing, as described above in conjunction with Figure 2 and Figure 3 In an embodiment, area light 602 is a light source and generates photon occupancy 612 on surface 610 .

[0087] In an embodiment, one or more photons or light rays 604, 608 emitted by an area light 602 passing through a caustic projector (such as an opaque / transparent object 606) are perturbed 614. Depending on the embodiment, the perturbation 614 may include a data value indicating a derivative, called a photon differential, calculated using the chain rule or other calculated metric, indicating one or more interactions between the one or more photons or light rays 604, 608 and an object or force that can alter the one or more photons or light rays 604, 608. In an embodiment, the perturbation 614 is a set of data indicating the derivative of the photon position with respect to the ray position and direction. In an embodiment, the perturbation 614 is photon-specific. In an embodiment, the calculation of the perturbation 614 for one photon does not require information from other photons. In an embodiment, adaptive anisotropic photon scattering records the photon perturbation 614 from the light source (such as the area light 602) and updates the perturbation using the chain rule as the photons interact with the caustic projector (such as the opaque / transparent object 606).

[0088] The perturbation 614 results in a change in the photon occupancy 612. In an embodiment, the photon occupancy 612 is determined using the above-mentioned Figure 2 and Figure 3 However, because the photons or rays from the area light 602 include position and direction information that can vary independently, the above combined Figure 2 and Figure 3 The technique described for direct light is not accurate for area light 602. Point light, spot light, directional light and other lights also have disturbances, and the disturbance affects the use of the above combined Figure 2 and Figure 3 The technique described is used for calculation.

[0089] Figure 6B is a block diagram illustrating the use of position and direction information associated with photons emitted by an area light 620 to improve the determination of soft caustic photon occupancy 648 of disturbances 632, 640, according to at least one embodiment. The area light 620 emits photons or rays 634, 636, 642, 644 during photon tracing that pass through or otherwise interact with a caustic projector (such as an opaque / transparent object 624), resulting in an occupancy 648 on a surface 628, as described above in conjunction with Figure 2 and Figure 3 In an embodiment, photons or light rays 634 , 636 , 642 , 644 emitted from the area light 620 may be perturbed 632 , 640 , resulting in a location 638 and direction 646 of the perturbation on the surface 628 .

[0090] Because the photons or rays 634, 636, 642, 644 include independent direction and position information, during photon tracing, both the position perturbation 632 and the direction perturbation 632 can be independently applied to the photons or rays 634, 636, 642, 644. If the position perturbation 632 is applied, the resulting position-perturbed photon or ray 634 will pass through or otherwise interact with a caustic projectile (such as an opaque / transparent object 624), thereby changing its path 636 and causing the perturbed position occupancy 638 to be different from the unperturbed photon occupancy. If the directional perturbation 640 is applied, the resulting directional perturbated photon or ray 642 will pass through a scattering projectile (such as an opaque / transparent object 624) or otherwise interact with a scattering projectile, thereby changing its path 644 and causing the perturbed directional occupancy 646 to be different from the occupancy of the unperturbed photon and different from the perturbed positional occupancy 638 of the photons or rays 634, 636, 642, 644.

[0091] To accurately render or otherwise determine soft caustics, such as Figure 6A and Figure 6B As shown, adaptive anisotropic photon scattering calculates the occupancy 648 of photons or rays 634, 636, 642, 644 based on independent changes in position and direction associated with each photon or ray 634, 636, 642, 644 during photon tracing. Figure 2 As described above, during photon tracing, photons or rays emitted from direct light have a position parameter p = p(u, v) or a direction parameter d = d(u, v). In contrast, photons or rays 634, 636, 642, 644 emitted or traced by area light 620 during photon tracing have two position parameters p = p(u, v) and two different direction parameters d = d(p, q). The resulting photon position p′ 648 is determined based on all the parameters p′ = p′(u, v, p, q).

[0092] Adaptive anisotropic photon scattering assumes that the perturbations 632, 640 of the photon or light parameters, Δu, Δv, Δp, and Δq, are independent random variables that follow a standard normal distribution. The photon occupancy 648 after these perturbations comprises the significant region of the resulting probability distribution. The resulting change in the photon position as a result of the perturbations 632, 640 is:

[0093] Δp′=Δp′ p +Δp′ d

[0094] in

[0095]

[0096]

[0097] Δp′ p and Δp′ a Both are the two-dimensional photon perturbation vectors in the local xy coordinate system of the photon caused by the position 632 and direction 640 perturbations respectively.

[0098] Δp′ p and Δp′ a Both follow a normal distribution:

[0099] Δp′ p ~N(0,∑ p )

[0100] Δp′ d ~N(0,∑ d )

[0101] in

[0102]

[0103]

[0104] Because Δp′ p and Δp′ a are independent, in the embodiment, the probability distribution of Δp′ is obtained by p and Δp′ a The convolution operation is performed to calculate. Because the result of the convolution of two normal distributions is a normal distribution, its mean and covariance are the sum of the two, respectively, then:

[0105] Δp′~N(0,∑)

[0106] in

[0107] ∑=∑ p +∑ d

[0108] To calculate the photon differential from Σ, find two vectors Δp1 and Δp2 such that:

[0109] ∑=(Δp1Δp2)(Δp1Δp2) T

[0110] By assuming that Δp1 is along the x-axis of the local coordinate system, Δp2 is solved accordingly.

[0111] In the embodiment, as described above in conjunction with Figure 1 and Figure 2The adaptive anisotropic photon scattering computes photon differentials in response to both position perturbations 632 and direction perturbations 640 of photons or rays emitted by one or more area lights 620 during photon tracing. In an embodiment, the adaptive anisotropic photon scattering then constructs a covariance matrix ∑ p and ∑ d , and these two matrices are added to obtain the covariance matrix ∑ for the composite occupancy. Then, the adaptive anisotropic photon scattering calculates the photon differentials Δp1 and Δp2 from ∑ and stores them in the task buffer associated with the photon, as described above in conjunction with Figure 1-Figure 3 As stated.

[0112] Figure 7 A process 700 is shown for performing an improved technique for photon scattering to determine improved caustic information in a scene according to at least one embodiment. The process 700 performs the above-described combined Figure 1 6 , wherein one or more photons or rays are emitted 702 by a ray tracer based on data in a task buffer 702 , as described above in conjunction with Figures 1 to 3 The ray tracer then traces photons or rays 704 through the scene for individual frames, as described above in conjunction with Figure 2 and Figure 3 As stated.

[0113] If a photon or ray passes through or otherwise interacts with a caustic projectile or hits a caustic projectile (such as an opaque / transparent surface 706), data about the photon or ray is recorded in a photon buffer, as described above in conjunction with Figures 2 to 4 If a photon or ray does not pass through or otherwise interact with a caustic projector (such as an opaque object 706), data about the photon or ray is discarded 708, as described above in conjunction with Figure 3 As stated.

[0114] In conjunction with the photon data recorded in the photon buffer 710 during photon tracing, information or data related to one or more photon occupancy is stored in the feedback buffer to facilitate generating or updating the task buffer for the next frame 720, as described above in conjunction with Figure 5 After the photon tracing completes the tracking of the photon 704 or the light ray through the scene in the frame, the Figure 7 The process of illustrating adaptive anisotropic photon scattering hardware or software creates occupancy data 714 from the light density information stored in the photon buffer, as described above in conjunction with Figure 1 and Figure 4 As stated.

[0115] The occupancy data calculated or created from the photon buffer 714 is written 716 or applied (mapped) to a texture (such as an image) and stored in the caustic buffer 716, and the texture (such as an image) is applied to the scene of the current frame 718 using a renderer or other hardware or software facility for applying graphics data to the scene to be rendered to the screen 718. After the caustic data from the caustic buffer is applied to the scene 718 by hardware or software implementing adaptive anisotropic photon scattering, the task buffer is updated 720 by the hardware or software based on the data stored in the feedback buffer, as described above in conjunction with Figure 2 and Figure 5 The updated task buffer utilizes the caustics information generated for the current frame to facilitate photon emission 702 and tracking 704 for the next frame.

[0116] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the present invention can be practiced without one or more of these specific details.

[0117] Data Center

[0118] Figure 8 An example data center 800 is shown in accordance with at least one embodiment. In at least one embodiment, the data center 800 includes, but is not limited to, a data center infrastructure layer 810, a framework layer 820, a software layer 830, and an application layer 840.

[0119] In at least one embodiment, Figure 8 As shown, the data center infrastructure layer 810 may include a resource coordinator 812, grouped computing resources 814, and node computing resources ("node CRs") 816(1)-816(N), where "N" represents any complete positive integer. In at least one embodiment, the node CRs 816(1)-816(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays ("FPGAs"), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node CRs 816(1)-816(N) may be servers having one or more of the above-mentioned computing resources.

[0120] In at least one embodiment, the grouped computing resources 814 may include separate groups of node CRs housed in one or more racks (not shown), or may include many racks (also not shown) housed in data centers at various geographic locations. The separate groups of node CRs within the grouped computing resources 814 may include computing, network, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0121] In at least one embodiment, resource coordinator 812 may configure or otherwise control one or more node CRs 816(1)-816(N) and / or grouped computing resources 814. In at least one embodiment, resource coordinator 812 may comprise a software design infrastructure ("SDI") management entity for data center 800. In at least one embodiment, resource coordinator 812 may comprise hardware, software, or some combination thereof.

[0122] In at least one embodiment, Figure 8 As shown, the framework layer 820 includes, but is not limited to, a job scheduler 832, a configuration manager 834, a resource manager 836, and a distributed file system 838. In at least one embodiment, the framework layer 820 may include a framework that supports the software 852 of the software layer 830 and / or one or more applications 842 of the application layer 840. In at least one embodiment, the software 852 or the application 842 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 820 may be, but is not limited to, a free and open source software web application framework, such as Apache Spark, which can utilize the distributed file system 838 to perform large-scale data processing (e.g., "big data"). TM(hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 832 may include a Spark driver to facilitate scheduling of workloads supported by the various layers of the data center 800. In at least one embodiment, the configuration manager 834 may be capable of configuring the different layers, such as the software layer 830 and the framework layer 820 including Spark and a distributed file system 838 for supporting large-scale data processing. In at least one embodiment, the resource manager 836 may be capable of managing the mapping or allocation of clustered or grouped computing resources used to support the distributed file system 838 and the job scheduler 832. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 814 on the data center infrastructure layer 810. In at least one embodiment, the resource manager 836 may coordinate with the resource coordinator 812 to manage these mapped or allocated computing resources.

[0123] In at least one embodiment, the software 852 included in the software layer 830 may include software used by at least a portion of the node CRs 816(1)-816(N), the grouped computing resources 814, and / or the distributed file system 838 of the framework layer 820. The one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0124] In at least one embodiment, the one or more applications 842 included in the application layer 840 may include one or more types of applications used by at least a portion of the node CRs 816(1)-816(N), the grouped computing resources 814, and / or the distributed file system 838 of the framework layer 820. The one or more types of applications may include, but are not limited to, CUDA applications.

[0125] In at least one embodiment, any of the configuration manager 834, the resource manager 836, and the resource coordinator 812 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve the data center operator of the data center 800 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0126] Computer-based systems

[0127] The following figures set forth, but are not limiting of, exemplary computer-based systems that can be used to implement at least one embodiment.

[0128] Figure 9A processing system 900 is shown in accordance with at least one embodiment. In at least one embodiment, system 900 includes one or more processors 902 and one or more graphics processors 908, and can be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 902 or processor cores 907. In at least one embodiment, processing system 900 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0129] In at least one embodiment, the processing system 900 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console, including a gaming and media console. In at least one embodiment, the processing system 900 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 900 may also include a device coupled to or integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 900 is a television or set-top box device having one or more processors 902 and a graphical interface generated by one or more graphics processors 908.

[0130] In at least one embodiment, one or more processors 902 each include one or more processor cores 907 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 907 is configured to process a specific instruction set 909. In at least one embodiment, the instruction set 909 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computed by very long instruction words (VLIW). In at least one embodiment, multiple processor cores 907 can each process a different instruction set 909, which can include instructions that contribute to emulating other instruction sets. In at least one embodiment, the processor core 907 can also include other processing devices, such as a digital signal processor (DSP).

[0131] In at least one embodiment, the processor 902 includes a cache memory (cache) 904. In at least one embodiment, the processor 902 can have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared among the various components of the processor 902. In at least one embodiment, the processor 902 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can use known cache coherence techniques to share this logic among the processor cores 907. In at least one embodiment, the processor 902 further includes a register file 906. The processor 902 may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, the register file 906 may include general purpose registers or other registers.

[0132] In at least one embodiment, one or more processors 902 are coupled to one or more interface buses 910 to transmit communication signals, such as address, data, or control signals, between the processors 902 and other components in the system 900. In at least one embodiment, the interface bus 910 can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 910 is not limited to a DMI bus and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 902 includes an integrated memory controller 916 and a platform controller hub 930. In at least one embodiment, the memory controller 916 facilitates communication between storage devices and other components of the processing system 900, while the platform controller hub (PCH) 930 provides connections to input / output (I / O) devices via a local I / O bus.

[0133] In at least one embodiment, the storage device 920 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or a device having suitable performance for use as processor memory. In at least one embodiment, the storage device 920 can be used as system memory for the processing system 900 to store data 922 and instructions 921 for use when one or more processors 902 execute applications or processes. In at least one embodiment, the memory controller 916 is also coupled to an optional external graphics processor 912, which can communicate with one or more graphics processors 908 in the processor 902 to perform graphics and media operations. In at least one embodiment, a display device 911 can be connected to the processor 902. In at least one embodiment, the display device 911 can include one or more internal display devices, such as in a mobile electronic device or portable computer device, or an external display device connected via a display interface (e.g., a DisplayPort, etc.). In at least one embodiment, the display device 911 can include a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0134] In at least one embodiment, the platform controller hub 930 enables peripheral devices to connect to the storage device 920 and the processor 902 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 946, a network controller 934, a firmware interface 928, a wireless transceiver 926, a touch sensor 925, and a data storage device 924 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 924 can be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 925 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 926 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 928 enables communication with the system firmware and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, the network controller 934 can enable network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 910. In at least one embodiment, the audio controller 946 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 900 includes an optional legacy I / O controller 940 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the processing system 900. In at least one embodiment, the platform controller hub 930 may also be connected to one or more universal serial bus (USB) controllers 942, which connect input devices such as a keyboard and mouse 943 combination, a camera 944, or other USB input devices.

[0135] In at least one embodiment, instances of memory controller 916 and platform controller hub 930 may be integrated into a discrete external graphics processor, such as external graphics processor 912. In at least one embodiment, platform controller hub 930 and / or memory controller 916 may be external to one or more processors 902. For example, in at least one embodiment, processing system 900 may include external memory controller 916 and platform controller hub 930, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with processor 902.

[0136] Figure 10A computer system 1000 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1000 can be a system of interconnected devices and components, a SOC, or some combination thereof. In at least one embodiment, the computer system 1000 is formed by a processor 1002, which can include an execution unit for executing instructions. In at least one embodiment, the computer system 1000 can include, but is not limited to, components such as the processor 1002, which employs an execution unit including logic to execute algorithms for processing data. In at least one embodiment, the computer system 1000 can include a processor such as the Intel® processor available from Intel Corporation of Santa Clara, California. Processor family, XeonTM, XScaleTM and / or StrongARMTM, Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1000 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0137] In at least one embodiment, computer system 1000 can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications can include microcontrollers, digital signal processors ("DSPs"), SoCs, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system that can execute one or more instructions according to at least one embodiment.

[0138] In at least one embodiment, computer system 1000 may include, but is not limited to, a processor 1002, which may include, but is not limited to, one or more execution units 1008, which may be configured to execute Compute Unified Device Architecture ("CUDA") ( Developed by NVIDIA Corporation of Santa Clara, California) program. In at least one embodiment, a CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 1000 is a single-processor desktop or server system. In at least one embodiment, computer system 1000 may be a multi-processor system. In at least one embodiment, processor 1002 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1002 may be coupled to a processor bus 1010 that may transmit data signals between processor 1002 and other components in computer system 1000.

[0139] In at least one embodiment, processor 1002 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1004. In at least one embodiment, processor 1002 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1002. In at least one embodiment, processor 1002 may include a combination of internal and external caches. In at least one embodiment, register file 1006 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0140] In at least one embodiment, an execution unit 1008, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 1002. The processor 1002 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 1008 may include logic for processing a packed instruction set 1009. In at least one embodiment, by including the packed instruction set 1009 in the instruction set of the general-purpose processor 1002, along with associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 1002. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0141] In at least one embodiment, execution unit 1008 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, or other types of logic circuits. In at least one embodiment, computer system 1000 may include, but is not limited to, memory 1020. In at least one embodiment, memory 1020 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. Memory 1020 may store instructions 1019 and / or data 1021 represented by data signals that may be executed by processor 1002.

[0142] In at least one embodiment, a system logic chip can be coupled to the processor bus 1010 and the memory 1020. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1016, and the processor 1002 can communicate with the MCH 1016 via the processor bus 1010. In at least one embodiment, the MCH 1016 can provide a high-bandwidth memory path 1018 to the memory 1020 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1016 can initiate data signals between the processor 1002, the memory 1020, and other components in the computer system 1000, and bridge data signals between the processor bus 1010, the memory 1020, and the system I / O 1022. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1016 may be coupled to the memory 1020 via a high-bandwidth memory path 1018 , and the graphics / video card 1012 may be coupled to the MCH 1016 via an Accelerated Graphics Port (“AGP”) interconnect 1014 .

[0143] In at least one embodiment, the computer system 1000 may use the system I / O 1022 as a proprietary hub interface bus to couple the MCH 1016 to the I / O controller hub ("ICH") 1030. In at least one embodiment, the ICH 1030 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1020, chipset, and processor 1002. Examples may include, but are not limited to, an audio controller 1029, a firmware hub ("Flash BIOS") 1028, a wireless transceiver 1026, a data store 1024, a legacy I / O controller 1023 including user input 1025 and a keyboard interface, a serial expansion port 1027 (e.g., USB), and a network controller 1034. The data store 1024 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0144] In at least one embodiment, Figure 10 A system comprising interconnected hardware devices or "chips" is shown. In at least one embodiment, Figure 10 An exemplary SoC may be shown. In at least one embodiment, Figure 10 The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1000 are interconnected using a Compute Express Link (CXL) interconnect.

[0145] Figure 11 A system 1100 is shown in accordance with at least one embodiment. In at least one embodiment, the system 1100 is an electronic device that utilizes a processor 1110. In at least one embodiment, the system 1100 can be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0146] In at least one embodiment, system 1100 may include, but is not limited to, a processor 1110 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1110 is coupled using a bus or interface, such as an I 2 C bus, System Management Bus ("SMBus"), Low Pin Count (LPC) bus, Serial Peripheral Interface ("SPI"), High Definition Audio ("HDA") bus, Serial Advanced Technology Attachment ("SATA") bus, USB (Revisions 1, 2, 3), or Universal Asynchronous Receiver / Transmitter ("UART") bus. In at least one embodiment, Figure 11 A system is shown that includes interconnected hardware devices or "chips". In at least one embodiment, Figure 11 An exemplary SoC may be shown. In at least one embodiment, Figure 11 The devices shown in can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 11 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0147] In at least one embodiment, Figure 11 The components may include a display 1124, a touch screen 1125, a touchpad 1130, a near field communication unit ("NFC") 1145, a sensor hub 1140, a thermal sensor 1146, a fast chipset ("EC") 1135, a trusted platform module ("TPM") 1138, a BIOS / firmware / flash memory ("BIOS, FW Flash") 1122, a DSP 1160, a solid-state disk ("SSD") or a hard disk drive ("HDD") 1120, a wireless local area network unit ("WLAN") 1150, a Bluetooth unit 1152, a wireless wide area network unit ("WWAN") 1156, a global positioning system (GPS) 1155, a camera ("USB 3.0 camera") 1154 (e.g., a USB 3.0 camera), or a low-power double data rate ("LPDDR") memory unit ("LPDDR3") 1115 implemented in, for example, the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0148] In at least one embodiment, other components may be communicatively coupled to processor 1110 via the components discussed above. In at least one embodiment, an accelerometer 1141, an ambient light sensor (“ALS”) 1142, a compass 1143, and a gyroscope 1144 may be communicatively coupled to sensor hub 1140. In at least one embodiment, a thermal sensor 1139, a fan 1137, a keyboard 1136, and a touchpad 1130 may be communicatively coupled to EC 1135. In at least one embodiment, a speaker 1163, an earpiece 1164, and a microphone (“mic”) 1165 may be communicatively coupled to an audio unit (“audio codec and class-D amplifier”) 1162, which in turn may be communicatively coupled to DSP 1160. In at least one embodiment, audio unit 1162 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, a SIM card (“SIM”) 1157 may be communicatively coupled to WWAN unit 1156. In at least one embodiment, components such as the WLAN unit 1150 and the Bluetooth unit 1152 and the WWAN unit 1156 may be implemented as a next generation form factor (NGFF).

[0149] Figure 12 An exemplary integrated circuit 1200 is shown in accordance with at least one embodiment. In at least one embodiment, the exemplary integrated circuit 1200 is a SoC, which may be manufactured using one or more IP cores. In at least one embodiment, the integrated circuit 1200 includes one or more application processors 1205 (e.g., CPUs), at least one graphics processor 1210, and may additionally include an image processor 1215 and / or a video processor 1220, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1200 includes peripheral or bus logic including a USB controller 1225, a UART controller 1230, an SPI / SDIO controller 1235, and an I / O controller. 2 S / I 2 IC controller 1240. In at least one embodiment, integrated circuit 1200 may include a display device 1245 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1250 and a Mobile Industry Processor Interface (MIPI) display interface 1255. In at least one embodiment, storage may be provided by a flash memory subsystem 1260, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1265 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1270.

[0150] Figure 13A computing system 1300 is shown in accordance with at least one embodiment. In at least one embodiment, computing system 1300 includes a processing subsystem 1301 having one or more processors 1302 and system memory 1304 communicating via an interconnect path that may include a memory hub 1305. In at least one embodiment, memory hub 1305 may be a separate component within a chipset assembly or integrated within one or more processors 1302. In at least one embodiment, memory hub 1305 is coupled to an I / O subsystem 1311 via a communication link 1306. In at least one embodiment, I / O subsystem 1311 includes an I / O hub 1307, which enables computing system 1300 to receive input from one or more input devices 1308. In at least one embodiment, I / O hub 1307 may enable a display controller, included in one or more processors 1302, to provide output to one or more display devices 1310A. In at least one embodiment, the one or more display devices 1310A coupled to the I / O hub 1307 may include local, internal, or embedded display devices.

[0151] In at least one embodiment, the processing subsystem 1301 includes one or more parallel processors 1312 coupled to the memory hub 1305 via a bus or other communication link 1313. In at least one embodiment, the communication link 1313 can be one of many standard-based communication link technologies or protocols, such as, but not limited to, PCIe, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 1312 form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 1312 form a graphics processing subsystem that can output pixels to one of one or more display devices 1310A coupled via the I / O hub 1307. In at least one embodiment, the one or more parallel processors 1312 can also include a display controller and display interface (not shown) to enable direct connection to the one or more display devices 1310B.

[0152] In at least one embodiment, system storage unit 1314 can be connected to I / O hub 1307 to provide a storage mechanism for computing system 1300. In at least one embodiment, I / O switch 1316 can be used to provide an interface mechanism to enable connections between I / O hub 1307 and other components, such as network adapter 1318 and / or wireless network adapter 1319 that can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 1320. In at least one embodiment, network adapter 1318 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1319 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices including one or more radios.

[0153] In at least one embodiment, computing system 1300 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 1307. Figure 13 The communication paths that interconnect the various components in the system can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect or interconnect protocol).

[0154] In at least one embodiment, one or more parallel processors 1312 include circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1312 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of computing system 1300 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1312, memory hub 1305, processor 1302, and I / O hub 1307 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 1300 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1300 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computing system. In at least one embodiment, I / O subsystem 1311 and display device 1310B are omitted from computing system 1300.

[0155] Processing system

[0156] The following figures illustrate, but are not limited to, exemplary processing systems that can be used to implement at least one embodiment.

[0157] Figure 14 An accelerated processing unit ("APU") 1400 is shown in accordance with at least one embodiment. In at least one embodiment, the APU 1400 was developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the APU 1400 can be configured to execute application programs, such as CUDA programs. In at least one embodiment, the APU 1400 includes, but is not limited to, a core complex 1410, a graphics complex 1440, a fabric 1460, an I / O interface 1470, a memory controller 1480, a display controller 1492, and a multimedia engine 1494. In at least one embodiment, the APU 1400 can include, but is not limited to, any combination of any number of core complexes 1410, any number of graphics complexes 1450, any number of display controllers 1492, and any number of multimedia engines 1494. For purposes of illustration, multiple instances of similar objects are referred to herein by reference numerals, where the reference numeral identifies the object and a number in parentheses identifies the desired instance.

[0158] In at least one embodiment, core complex 1410 is a CPU, graphics complex 1440 is a GPU, and APU 1400 is a processing unit that integrates 1410 and 1440 onto a single chip (without limitation). In at least one embodiment, some tasks may be assigned to core complex 1410, while other tasks may be assigned to graphics complex 1440. In at least one embodiment, core complex 1410 is configured to execute primary control software associated with APU 1400, such as an operating system. In at least one embodiment, core complex 1410 is the main processor of APU 1400, controlling and coordinating the operations of the other processors. In at least one embodiment, core complex 1410 issues commands that control the operations of graphics complex 1440. In at least one embodiment, core complex 1410 may be configured to execute host executable code derived from CUDA source code, and graphics complex 1440 may be configured to execute device executable code derived from CUDA source code.

[0159] In at least one embodiment, core complex 1410 includes, but is not limited to, cores 1420(1)-1420(4) and L3 cache 1430. In at least one embodiment, core complex 1410 may include, but is not limited to, any number of cores 1420 and any combination of any number and type of caches. In at least one embodiment, cores 1420 are configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 1420 is a CPU core.

[0160] In at least one embodiment, each core 1420 includes, but is not limited to, a fetch / decode unit 1422, an integer execution engine 1424, a floating-point execution engine 1426, and an L2 cache 1428. In at least one embodiment, the fetch / decode unit 1422 fetches instructions, decodes these instructions, generates micro-ops, and dispatches individual micro-ops to the integer execution engine 1424 and the floating-point execution engine 1426. In at least one embodiment, the fetch / decode unit 1422 can simultaneously dispatch one micro-op to the integer execution engine 1424 and another micro-op to the floating-point execution engine 1426. In at least one embodiment, the integer execution engine 1424 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1426 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1422 dispatches micro-ops to a single execution engine that replaces both the integer execution engine 1424 and the floating-point execution engine 1426.

[0161] In at least one embodiment, each core 1420(i) can access an L2 cache 1428(i) included in the core 1420(i), where i is an integer representing a specific instance of the core 1420. In at least one embodiment, each core 1420 included in a core complex 1410(j) is connected to the other cores 1420 included in the core complex 1410(j) via an L3 cache 1430(j) included in the core complex 1410(j), where j is an integer representing a specific instance of the core complex 1410. In at least one embodiment, a core 1420 included in a core complex 1410(j) can access all L3 caches 1430(j) included in the core complex 1410(j), where j is an integer representing a specific instance of the core complex 1410. In at least one embodiment, the L3 cache 1430 can include, but is not limited to, any number of slices.

[0162] In at least one embodiment, graphics complex 1440 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, graphics complex 1440 is configured to perform graphics pipeline operations, such as draw commands, pixel operations, geometry calculations, and other operations associated with rendering an image to a display. In at least one embodiment, graphics complex 1440 is configured to perform operations that are not graphics-related. In at least one embodiment, graphics complex 1440 is configured to perform both graphics-related operations and graphics-independent operations.

[0163] In at least one embodiment, graphics complex 1440 includes, but is not limited to, any number of compute units 1450 and L2 cache 1442. In at least one embodiment, compute units 1450 share L2 cache 1442. In at least one embodiment, L2 cache 1442 is partitioned. In at least one embodiment, graphics complex 1440 includes, but is not limited to, any number of compute units 1450 and any number (including zero) and type of cache. In at least one embodiment, graphics complex 1440 includes, but is not limited to, any amount of dedicated graphics hardware.

[0164] In at least one embodiment, each compute unit 1450 includes, but is not limited to, any number of SIMD units 1452 and shared memory 1454. In at least one embodiment, each SIMD unit 1452 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each compute unit 1450 can execute any number of thread blocks, but each thread block executes on a single compute unit 1450. In at least one embodiment, a thread block includes, but is not limited to, any number of threads of execution. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1452 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized and communicated via shared memory 1454.

[0165] In at least one embodiment, fabric 1460 is a system interconnect that facilitates data and control transfers across core complex 1410, graphics complex 1440, I / O interface 1470, memory controller 1480, display controller 1492, and multimedia engine 1494. In at least one embodiment, APU 1400 may include, in addition to or in lieu of fabric 1460, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to APU 1400. In at least one embodiment, I / O interface 1470 represents any number and type of I / O interfaces (e.g., PCI, PCI-Extended ("PCI-X"), PCIe, Gigabit Ethernet ("GBE"), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1470. In at least one embodiment, peripheral devices coupled to I / O interface 1470 may include, but are not limited to, a keyboard, mouse, printer, scanner, joystick or other type of game controller, media recording device, external storage device, network interface card, etc.

[0166] In at least one embodiment, display controller AMD92 displays images on one or more display devices, such as liquid crystal display (LCD) devices. In at least one embodiment, multimedia engine 240 includes, but is not limited to, any number and type of multimedia-related circuits, such as video decoders, video encoders, image signal processors, and the like. In at least one embodiment, memory controller 1480 facilitates data transfer between APU 1400 and unified system memory 1490. In at least one embodiment, core complex 1410 and graphics complex 1440 share unified system memory 1490.

[0167] In at least one embodiment, the APU 1400 implements a memory subsystem including, but not limited to, any number and type of memory controllers 1480 and memory devices that may be dedicated to a component or shared among multiple components (e.g., shared memory 1454). In at least one embodiment, the APU 1400 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 1528, L3 cache 1430, and L2 cache 1442), each of which may be private to a component or shared among any number of components (e.g., core 1420, core complex 1410, SIMD units 1452, compute units 1450, and graphics complex 1440).

[0168] Figure 15A CPU 1500 is shown according to at least one embodiment. In at least one embodiment, the CPU 1500 is developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the CPU 1500 can be configured to execute application programs. In at least one embodiment, the CPU 1500 is configured to execute host control software, such as an operating system. In at least one embodiment, the CPU 1500 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1500 can be configured to execute host executable code derived from CUDA source code, and the external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, the CPU 1500 includes, but is not limited to, any number of core complexes 1510, fabric 1560, I / O interfaces 1570, and memory controllers 1580.

[0169] In at least one embodiment, core complex 1510 includes, but is not limited to, cores 1520(1)-1520(4) and L3 cache 1530. In at least one embodiment, core complex 1510 may include, but is not limited to, any number of cores 1520 and any combination of any number and type of caches. In at least one embodiment, cores 1520 are configured to execute instructions of a specific ISA. In at least one embodiment, each core 1520 is a CPU core.

[0170] In at least one embodiment, each core 1520 includes, but is not limited to, a fetch / decode unit 1522, an integer execution engine 1524, a floating-point execution engine 1526, and an L2 cache 1528. In at least one embodiment, the fetch / decode unit 1522 fetches instructions, decodes these instructions, generates micro-ops, and dispatches individual micro-ops to the integer execution engine 1524 and the floating-point execution engine 1526. In at least one embodiment, the fetch / decode unit 1522 can simultaneously dispatch one micro-op to the integer execution engine 1524 and another micro-op to the floating-point execution engine 1526. In at least one embodiment, the integer execution engine 1524 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1526 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1522 dispatches micro-ops to a single execution engine that replaces both the integer execution engine 1524 and the floating-point execution engine 1526.

[0171] In at least one embodiment, each core 1520(i) can access an L2 cache 1528(i) included in the core 1520(i), where i is an integer representing a specific instance of the core 1520. In at least one embodiment, each core 1520 included in a core complex 1510(j) is connected to the other cores 1520 in the core complex 1510(j) via an L3 cache 1530(j) included in the core complex 1510(j), where j is an integer representing a specific instance of the core complex 1510. In at least one embodiment, a core 1520 included in a core complex 1510(j) can access all L3 caches 1530(j) included in the core complex 1510(j), where j is an integer representing a specific instance of the core complex 1510. In at least one embodiment, the L3 cache 1530 can include, but is not limited to, any number of slices.

[0172] In at least one embodiment, fabric 1560 is a system interconnect that facilitates data and control transfers across core complexes 1510(1)-1510(N) (where N is an integer greater than zero), I / O interface 1570, and memory controller 1580. In at least one embodiment, CPU 1500 may include, in addition to or in lieu of fabric 1560, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to CPU 1500. In at least one embodiment, I / O interface 1570 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1570. In at least one embodiment, peripheral devices coupled to I / O interface 1570 may include, but are not limited to, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, and the like.

[0173] In at least one embodiment, memory controller 1580 facilitates data transfers between CPU 1500 and system memory 1590. In at least one embodiment, core complex 1510 and graphics complex 1540 share system memory 1590. In at least one embodiment, CPU 1500 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 1580 and memory devices that can be dedicated to a component or shared among multiple components. In at least one embodiment, CPU 1500 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 1528 and L3 cache 1530), each of which can be private to a component or shared among any number of components (e.g., core 1520 and core complex 1510).

[0174] Figure 16 An exemplary accelerator integrated slice 1690 according to at least one embodiment is shown. As used herein, a "slice" includes a specified portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services on behalf of multiple graphics processing engines in multiple graphics acceleration modules. The graphics processing engines may each include a separate GPU. Optionally, the graphics processing engines may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip.

[0175] The application effective address space 1682 within system memory 1614 stores a process element 1683. In one embodiment, a process element 1683 is stored in response to a GPU call 1681 from an application 1680 executing on processor 1607. Process element 1683 contains the processing state of the corresponding application 1680. A work descriptor (WD) 1684 contained in process element 1683 may be a single job requested by the application or may contain a pointer to a job queue. In at least one embodiment, WD 1684 is a pointer to a job request queue in the application effective address space 1682.

[0176] Graphics acceleration module 1646 and / or each graphics processing engine can be shared by all or part of the processes in the system.In at least one embodiment, an infrastructure for establishing a processing state and sending WD 1684 to graphics acceleration module 1646 to start a job in a virtualized environment can be included.

[0177] In at least one embodiment, a dedicated process programming model is implemented. In this model, a single process owns a graphics acceleration module 1646 or individual graphics processing engine. Because the graphics acceleration module 1646 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owning partition, and the operating system initializes the accelerator integrated circuit for the owning partition when the graphics acceleration module 1646 is allocated.

[0178] In operation, the WD fetch unit 1691 in the accelerator integrated slice 1690 fetches the next WD 1684, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 1646. Data from the WD 1684 can be stored in registers 1645 for use by the memory management unit (MMU) 1639, the interrupt management circuit 1647, and / or the context management circuit 1648, as shown. For example, one embodiment of the MMU 1639 includes segment / page roaming circuitry for accessing the segment / page tables 1686 within the OS virtual address space 1685. The interrupt management circuit 1647 can process interrupt events (INT) 1692 received from the graphics acceleration module 1646. When executing graph operations, the effective addresses 1693 generated by the graphics processing engines are converted into real addresses by the MMU 1639.

[0179] In one embodiment, the same register set 1645 is replicated for each graphics processing engine and / or graphics acceleration module 1646 and can be initialized by the hypervisor or operating system. Each of these replicated registers can be included in the accelerator integration slice 1690. Table 1 shows exemplary registers that can be initialized by the hypervisor.

[0180] Table 1 – Registers initialized by the hypervisor

[0181] 1 Slice Control Register 2 Real address (RA) plan processing area pointer 3 Authorization Mask Override Register 4 Interrupt vector table input offset 5 Interrupt vector table entry restriction 6 Status Register 7 Logical partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0182] Example registers that may be initialized by the operating system are shown in Table 2.

[0183] Table 2 – Operating System Initialization Registers

[0184] 1 Process and thread identification 2 Effective Address (EA) environment save / restore pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) stores the segment table pointer 5 Mask of Authority 6 Job Descriptor

[0185] In one embodiment, each WD 1684 is specific to a particular graphics acceleration module 1646 and / or a particular graphics processing engine. It contains all the information the graphics processing engine needs to do its work or work, or it can be a pointer to a memory location where the application has set up a command queue for work to be done.

[0186] Figures 17A-17B An exemplary graphics processor according to at least one embodiment of the present disclosure is shown. In at least one embodiment, any exemplary graphics processor can be manufactured using one or more IP cores. In addition to the illustrated diagram, in at least one embodiment, other logic and circuitry can be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processor is used within a SoC.

[0187] Figure 17A An exemplary graphics processor 1710 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 17B An additional exemplary graphics processor 1740 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 17A The graphics processor 1710 is a low power graphics processor core. In at least one embodiment, Figure 17B The graphics processor 1740 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1710, 1740 can be Figure 12 A variant of the graphics processor 1210.

[0188] In at least one embodiment, the graphics processor 1710 includes a vertex processor 1705 and one or more fragment processors 1715A-1715N (e.g., 1715A, 1715B, 1715C, 1715D through 1715N-1 and 1715N). In at least one embodiment, the graphics processor 1710 can execute different shader programs via separate logic, such that the vertex processor 1705 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1715A-1715N perform fragment (e.g., pixel) shading operations for the fragment or pixel or shader program. In at least one embodiment, the vertex processor 1705 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the fragment processors 1715A-1715N use the primitives and vertex data generated by the vertex processor 1705 to generate a frame buffer for display on a display device. In at least one embodiment, fragment processors 1715A-1715N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0189] In at least one embodiment, graphics processor 1710 additionally includes one or more MMUs 1720A-1720B, caches 1725A-1725B, and circuit interconnects 1730A-1730B. In at least one embodiment, one or more MMUs 1720A-1720B provide a mapping of virtual to physical addresses for graphics processor 1710, including for vertex processor 1705 and / or fragment processors 1715A-1715N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1725A-1725B. In at least one embodiment, one or more MMUs 1720A-1720B may synchronize with other MMUs within the system, including with Figure 12 One or more MMUs associated with one or more application processors 1205, graphics processor 1215, and / or video processor 1220 enable each processor 1205-1220 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1730A-1730B enable graphics processor 1710 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0190] In at least one embodiment, graphics processor 1740 includes Figure 17A 1755N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores may vary. In at least one embodiment, the graphics processor 1740 includes an inter-core task manager 1745 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1755A-1755N and a tiling unit 1758 to accelerate tile-based rendering operations in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0191] Figure 18AFIGURE 1 shows a graphics core 1800 according to at least one embodiment. In at least one embodiment, the graphics core 1800 may include Figure 12 In at least one embodiment, the graphics core 1800 may be Figure 17B 1755N. In at least one embodiment, graphics core 1800 includes a shared instruction cache 1802, texture units 1818, and cache / shared memory 1820, which are common to execution resources within graphics core 1800. In at least one embodiment, graphics core 1800 may include multiple slices 1801A-1801N or partitions of each core, and a graphics processor may include multiple instances of graphics core 1800. Slices 1801A-1801N may include support logic including local instruction caches 1804A-1804N, thread schedulers 1806A-1806N, thread dispatchers 1808A-1808N, and a set of registers 1810A-1810N. In at least one embodiment, slices 1801A-1801N may include a set of additional function units (AFUs) 1812A-1812N, floating point units (FPUs) 1814A-1814N, integer arithmetic logic units (ALUs) 1816A-1816N, address calculation units (ACUs) 1813A-1813N, double precision floating point units (DPFPUs) 1815A-1815N, and matrix processing units (MPUs) 1817A-1817N.

[0192] In at least one embodiment, the FPUs 1814A-1814N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1815A-1815N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1816A-1816N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1817A-1817N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 1817A-1817N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 1812A-1812N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0193] Figure 18BA general purpose graphics processing unit (GPGPU) 1830 is shown in at least one embodiment. In at least one embodiment, GPGPU 1830 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU 1830 can be configured to enable highly parallel computational operations to be performed by an array of GPUs. In at least one embodiment, GPGPU 1830 can be directly linked to other instances of GPGPU 1830 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, GPGPU 1830 includes a host interface 1832 to enable connection to a host processor. In at least one embodiment, host interface 1832 is a PCIe interface. In at least one embodiment, host interface 1832 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 1830 receives commands from the host processor and dispatches execution threads associated with those commands to a set of compute clusters 1836A-1836H using a global scheduler 1834. In at least one embodiment, compute clusters 1836A-1836H share cache memory 1838. In at least one embodiment, cache memory 1838 can serve as a higher level cache for cache memories within compute clusters 1836A-1836H.

[0194] In at least one embodiment, GPGPU 1830 includes memory 1844A-1844B coupled to compute clusters 1836A-1836H via a set of memory controllers 1842A-1842B. In at least one embodiment, memory 1844A-1844B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0195] In at least one embodiment, computing clusters 1836A-1836H each include a set of graphics cores, such as Figure 18A The graphics core 1800, which may include multiple types of integer and floating-point logic units, may perform computational operations at various precisions, including computations suitable for use with CUDA programs. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 1836A-1836H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0196] In at least one embodiment, multiple instances of GPGPU 1830 can be configured to operate as a compute cluster. Compute clusters 1836A-1836H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 1830 communicate via host interface 1832. In at least one embodiment, GPGPU 1830 includes an I / O hub 1839 that couples GPGPU 1830 to GPU link 1840, enabling direct connections to other instances of GPGPU 1830. In at least one embodiment, GPU link 1840 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1830. In at least one embodiment, GPU link 1840 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1830 are located in separate data processing systems and communicate via a network device accessible via host interface 1832. In at least one embodiment, GPU link 1840 may be configured to connect to a host processor, in addition to or in place of host interface 1832. In at least one embodiment, GPGPU 1830 may be configured to execute CUDA programs.

[0197] Figure 19A A parallel processor 1900 in accordance with at least one embodiment is shown. In at least one embodiment, the various components of the parallel processor 1900 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or an FPGA.

[0198] In at least one embodiment, parallel processor 1900 includes parallel processing unit 1902. In at least one embodiment, parallel processing unit 1902 includes an I / O unit 1904 that enables communication with other devices, including other instances of parallel processing unit 1902. In at least one embodiment, I / O unit 1904 can be directly connected to other devices. In at least one embodiment, I / O unit 1904 connects to other devices using a hub or switch interface (e.g., memory hub 1905). In at least one embodiment, the connection between memory hub 1905 and I / O unit 1904 forms a communication link. In at least one embodiment, I / O unit 1904 is connected to a host interface 1906 and a memory crossbar switch 1916, where host interface 1906 receives commands for performing processing operations and memory crossbar switch 1916 receives commands for performing memory operations.

[0199] In at least one embodiment, when host interface 1906 receives command buffers via I / O unit 1904, host interface 1906 can direct work operations to execute those commands to front end 1908. In at least one embodiment, front end 1908 is coupled to scheduler 1910, which is configured to dispatch commands or other work items to processing array 1912. In at least one embodiment, scheduler 1910 ensures that processing array 1912 is properly configured and in a valid state before dispatching tasks to the processing array 1912. In at least one embodiment, scheduler 1910 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, a microcontroller-implemented scheduler 1910 can be configured to perform complex scheduling and work dispatch operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 1912. In at least one embodiment, host software can authenticate workloads for scheduling on processing array 1912 through one of multiple graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 1912 by scheduler 1910 logic within a microcontroller that includes scheduler 1910 .

[0200] In at least one embodiment, processing array 1912 can include up to "N" processing clusters (e.g., cluster 1914A, cluster 1914B, through cluster 1914N). In at least one embodiment, each cluster 1914A-1914N of processing array 1912 can execute a large number of concurrent threads. In at least one embodiment, scheduler 1910 can allocate work to clusters 1914A-1914N of processing array 1912 using various scheduling and / or work distribution algorithms, which can vary depending on the workload generated by each program or computation type. In at least one embodiment, scheduling can be handled dynamically by scheduler 1910 or can be partially assisted by compiler logic during the compilation of program logic configured to be executed by processing array 1912. In at least one embodiment, different clusters 1914A-1914N of processing array 1912 can be assigned to process different types of programs or to perform different types of computations.

[0201] In at least one embodiment, processing array 1912 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing array 1912 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing array 1912 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0202] In at least one embodiment, processing array 1912 is configured to perform parallel graphics processing operations. In at least one embodiment, processing array 1912 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing array 1912 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing units 1902 may transfer data from system memory via I / O units 1904 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1922) during processing and then written back to system memory.

[0203] In at least one embodiment, when parallel processing unit 1902 is used to perform graph processing, scheduler 1910 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 1914A-1914N of processing array 1912. In at least one embodiment, portions of processing array 1912 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 1914A-1914N can be stored in a buffer to allow the intermediate data to be transferred between clusters 1914A-1914N for further processing.

[0204] In at least one embodiment, the processing array 1912 can receive processing tasks to be executed via the scheduler 1910, which receives commands defining the processing tasks from the front end 1908. In at least one embodiment, the processing tasks can include an index of the data to be processed, which can include, for example, surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 1910 can be configured to obtain the index corresponding to the task, or can receive the index from the front end 1908. In at least one embodiment, the front end 1908 can be configured to ensure that the processing array 1912 is configured in a valid state before starting the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.).

[0205] In at least one embodiment, each of one or more instances of parallel processing unit 1902 can be coupled to parallel processor memory 1922. In at least one embodiment, parallel processor memory 1922 can be accessed via memory crossbar 1916, which can receive memory requests from processing array 1912 and I / O unit 1904. In at least one embodiment, memory crossbar 1916 can access parallel processor memory 1922 via memory interface 1918. In at least one embodiment, memory interface 1918 can include multiple partition units (e.g., partition unit 1920A, partition unit 1920B, through partition unit 1920N), which can each be coupled to a portion of parallel processor memory 1922 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 1920A-1920N are configured to be equal to the number of memory cells, such that the first partition unit 1920A has a corresponding first memory cell 1924A, the second partition unit 1920B has a corresponding memory cell 1924B, and the Nth partition unit 1920N has a corresponding Nth memory cell 1924N. In at least one embodiment, the number of partition units 1920A-1920N may not be equal to the number of memory devices.

[0206] In at least one embodiment, memory units 1924A-1924N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 1924A-1924N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 1924A-1924N, allowing partition units 1920A-1920N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 1922. In at least one embodiment, local instances of parallel processor memory 1922 may be eliminated in favor of a unified memory design that utilizes system memory in combination with local cache memory.

[0207] In at least one embodiment, any of the clusters 1914A-1914N of the processing array 1912 can process data to be written to any memory unit 1924A-1924N within the parallel processor memory 1922. In at least one embodiment, the memory crossbar 1916 can be configured to transmit the output of each cluster 1914A-1914N to any partition unit 1920A-1920N or another cluster 1914A-1914N, which can perform other processing operations on the output. In at least one embodiment, each cluster 1914A-1914N can communicate with a memory interface 1918 via the memory crossbar 1916 to read from or write to various external storage devices. In at least one embodiment, memory crossbar 1916 has connections to memory interface 1918 for communicating with I / O unit 1904, and connections to local instances of parallel processor memory 1922, thereby enabling processing units within different processing clusters 1914A-1914N to communicate with system memory or other memory that is not local to parallel processing unit 1902. In at least one embodiment, memory crossbar 1916 may use virtual channels to separate traffic flows between clusters 1914A-1914N and partition units 1920A-1920N.

[0208] In at least one embodiment, multiple instances of parallel processing unit 1902 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 1902 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 1902 can include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 1902 or parallel processor 1900 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0209] Figure 19B FIG2 shows a processing cluster 1994 according to at least one embodiment. In at least one embodiment, the processing cluster 1994 is included within a parallel processing unit. In at least one embodiment, the processing cluster 1994 is Figure 19AIn at least one embodiment, processing cluster 1994 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit that is configured to issue instructions to a group of processing engines within each processing cluster 1994.

[0210] In at least one embodiment, the operation of the processing cluster 1994 can be controlled by a pipeline manager 1932 that assigns processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 1932 Figure 19A Scheduler 1910 receives instructions and manages the execution of these instructions by graphics multiprocessor 1934 and / or texture unit 1936. In at least one embodiment, graphics multiprocessor 1934 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within processing cluster 1994. In at least one embodiment, one or more instances of graphics multiprocessor 1934 may be included within processing cluster 1994. In at least one embodiment, graphics multiprocessor 1934 may process data, and data crossbar 1940 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, pipeline manager 1932 may facilitate the distribution of processed data by specifying a destination for the processed data to be distributed via data crossbar 1940.

[0211] In at least one embodiment, each graphics multiprocessor 1934 within a processing cluster 1994 may include the same set of function execution logic (e.g., arithmetic logic unit, load store unit (LSU), etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where a new instruction may be issued before a previous instruction has completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0212] In at least one embodiment, instructions transmitted to processing cluster 1994 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 1934. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within graphics multiprocessor 1934. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the processing of a loop within the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within graphics multiprocessor 1934. In at least one embodiment, when a thread group includes more threads than the number of processing engines within graphics multiprocessor 1934, processing can be performed within consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 1934.

[0213] In at least one embodiment, the graphics multiprocessor 1934 includes internal cache memory to perform load and store operations. In at least one embodiment, the graphics multiprocessor 1934 can abandon the internal cache and use cache memory within the processing cluster 1994 (e.g., L1 cache 1948). In at least one embodiment, each graphics multiprocessor 1934 can also access a partition unit (e.g., Figure 19A L2 cache within partition units 1920A-1920N) of the graphics multiprocessor 1934 is shared across all processing clusters 1994 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 1934 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 1902 can be used as global memory. In at least one embodiment, processing cluster 1994 includes multiple instances of graphics multiprocessor 1934, which can share common instructions and data, which can be stored in L1 cache 1948.

[0214] In at least one embodiment, each processing cluster 1994 may include an MMU 1945 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 1945 may reside in Figure 19A1918. In at least one embodiment, the MMU 1945 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles (more on tiles below) and optionally to cache line indices. In at least one embodiment, the MMU 1945 may include a translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 1934 or L1 cache 1948 or processing cluster 1994. In at least one embodiment, the physical addresses are processed to assign surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0215] In at least one embodiment, the processing clusters 1994 can be configured such that each graphics multiprocessor 1934 is coupled to a texture unit 1936 to perform texture mapping operations, which may involve, for example, determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1934, and texture data is retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 1934 outputs processed tasks to a data crossbar 1940 to provide the processed tasks to another processing cluster 1994 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 1916. In at least one embodiment, a pre-raster operations unit (preROP) 1942 is configured to receive data from the graphics multiprocessor 1934 and direct the data to a ROP unit, which can communicate with a partitioning unit (e.g., a partitioning unit) as described herein. Figure 19A In at least one embodiment, the PreROP 1942 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0216] Figure 19C A graphics multiprocessor 1996 is shown according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 1996 is Figure 19B1934. In at least one embodiment, the graphics multiprocessor 1996 is coupled to the pipeline manager 1932 of the processing cluster 1994. In at least one embodiment, the graphics multiprocessor 1996 has an execution pipeline that includes, but is not limited to, an instruction cache 1952, an instruction unit 1954, an address mapping unit 1956, a register file 1958, one or more GPGPU cores 1962, and one or more LSUs 1966. The GPGPU cores 1962 and LSUs 1966 are coupled to cache memory 1972 and shared memory 1970 via a memory and cache interconnect 1968.

[0217] In at least one embodiment, the instruction cache 1952 receives a stream of instructions to be executed from the pipeline manager 1932. In at least one embodiment, the instructions are cached in the instruction cache 1952 and dispatched for execution by the instruction unit 1954. In at least one embodiment, the instruction unit 1954 can dispatch instructions as thread groups (e.g., warps), assigning each thread of the thread group to a different execution unit within the GPGPU core 1962. In at least one embodiment, the instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 1956 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the LSU 1966.

[0218] In at least one embodiment, register file 1958 provides a set of registers for the functional units of graphics multiprocessor 1996. In at least one embodiment, register file 1958 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 1962, LSU 1966) connected to graphics multiprocessor 1996. In at least one embodiment, register file 1958 is divided between each functional unit such that a dedicated portion of register file 1958 is allocated to each functional unit. In at least one embodiment, register file 1958 is divided between the different thread groups being executed by graphics multiprocessor 1996.

[0219] In at least one embodiment, the GPGPU cores 1962 may each include an FPU and / or ALU for executing instructions of the graphics multiprocessor 1996. The GPGPU cores 1962 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 1962 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 1996 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 1962 may also include fixed-function or special-function logic.

[0220] In at least one embodiment, the GPGPU core 1962 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 1962 can physically execute SIMD4, SIMD8, and SIMD9 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0221] In at least one embodiment, memory and cache interconnect 1968 is an interconnect network that connects each functional unit of graphics multiprocessor 1996 to register file 1958 and shared memory 1970. In at least one embodiment, memory and cache interconnect 1968 is a crossbar interconnect that allows LSU 1966 to implement load and store operations between shared memory 1970 and register file 1958. In at least one embodiment, register file 1958 can operate at the same frequency as GPGPU core 1962, resulting in very low latency for data transfers between GPGPU core 1962 and register file 1958. In at least one embodiment, shared memory 1970 can be used to enable communication between threads executing on functional units within graphics multiprocessor 1996. In at least one embodiment, cache memory 1972 can be used, for example, as a data cache to cache texture data communicated between functional units and texture unit 1936. In at least one embodiment, shared memory 1970 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 1972, threads executing on GPGPU core 1962 may programmatically store data in shared memory.

[0222] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0223] Figure 20A graphics processor 2000 is shown in accordance with at least one embodiment. In at least one embodiment, graphics processor 2000 includes a ring interconnect 2002, a pipeline front end 2004, a media engine 2037, and graphics cores 2080A-2080N. In at least one embodiment, ring interconnect 2002 couples graphics processor 2000 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2000 is one of many processors integrated within a multi-core processing system.

[0224] In at least one embodiment, graphics processor 2000 receives batches of commands via ring interconnect 2002. In at least one embodiment, the input commands are interpreted by command streamer 2003 in pipeline front end 2004. In at least one embodiment, graphics processor 2000 includes scalable execution logic to perform 3D geometry processing and media processing via graphics cores 2080A-2080N. In at least one embodiment, for 3D geometry processing commands, command streamer 2003 provides the commands to geometry pipeline 2036. In at least one embodiment, for at least some media processing commands, command streamer 2003 provides the commands to video front end 2034, which is coupled to media engine 2037. In at least one embodiment, media engine 2037 includes a video quality engine (VQE) 2030 for video and image post-processing, and a multi-format encoding / decoding (MFX) 2033 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2036 and the media engine 2037 each generate execution threads for thread execution resources provided by at least one graphics core 2080A.

[0225] In at least one embodiment, the graphics processor 2000 includes scalable thread execution resources featuring modular graphics cores 2080A-2080N (sometimes referred to as core slices), each of which has multiple sub-cores 2050A-2050N, 2060A-2060N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2000 can have any number of graphics cores 2080A-2080N. In at least one embodiment, the graphics processor 2000 includes a graphics core 2080A having at least a first sub-core 2050A and a second sub-core 2060A. In at least one embodiment, the graphics processor 2000 is a low-power processor having a single sub-core (e.g., 2050A). In at least one embodiment, the graphics processor 2000 includes multiple graphics cores 2080A-2080N, each of which includes a set of first sub-cores 2050A-2050N and a set of second sub-cores 2060A-2060N. In at least one embodiment, each of the first sub-cores 2050A-2050N includes at least a first set of execution units (EUs) 2052A-2052N and media / texture samplers 2054A-2054N. In at least one embodiment, each of the second sub-cores 2060A-2060N includes at least a second set of execution units 2062A-2062N and samplers 2064A-2064N. In at least one embodiment, each of the sub-cores 2050A-2050N, 2060A-2060N shares a set of shared resources 2070A-2070N. In at least one embodiment, the shared resources include a shared cache and pixel operation logic.

[0226] Figure 21 A processor 2100 is shown according to at least one embodiment. In at least one embodiment, the processor 2100 may include, but is not limited to, logic circuitry for executing instructions. In at least one embodiment, the processor 2100 may execute instructions including x86 instructions, ARM instructions, specialized instructions for ASICs, and the like. In at least one embodiment, the processor 2110 may include registers for storing packed data, such as the 64-bit wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. In at least one embodiment, the MMX registers, available in integer and floating-point form, may operate with packed data elements with SIMD and Streaming SIMD Extensions ("SSE") instructions. In at least one embodiment, the 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as "SSEx") technology may store such packed data operands. In at least one embodiment, the processor 2110 may execute instructions to accelerate CUAD programs.

[0227] In at least one embodiment, processor 2100 includes an in-order front end ("Front End") 2101 to fetch instructions for execution and prepare them for later use in the processor pipeline. In at least one embodiment, Front End 2101 may include several units. In at least one embodiment, instruction prefetcher 2126 retrieves instructions from memory and provides them to instruction decoder 2128, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2128 decodes received instructions into one or more operations, called "microinstructions" or "micro-operations" (also referred to as "micro-ops" or "micro-instructions"), for execution. In at least one embodiment, instruction decoder 2128 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform the operations. In at least one embodiment, trace cache 2130 can assemble the decoded microinstructions into a program-ordered sequence or trace in microinstruction queue 2134 for execution. In at least one embodiment, when trace cache 2130 encounters a complex instruction, microcode ROM 2132 provides the microinstructions necessary to complete the operation.

[0228] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions may require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2128 may access the microcode ROM 2132 to execute the instruction. In at least one embodiment, an instruction may be decoded into a smaller number of micro-ops for processing at the instruction decoder 2128. In at least one embodiment, if multiple micro-ops are required to complete the operation, the instruction may be stored in the microcode ROM 2132. In at least one embodiment, the trace cache 2130 references the entry point programmable logic array ("PLA") to determine the correct micro-op pointer for reading the microcode sequence from the microcode ROM 2132 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2132 completes the micro-op sequencing for the instruction, the front end 2101 of the machine may resume fetching micro-ops from the trace cache 2130.

[0229] In at least one embodiment, the out-of-order execution engine ("OOO engine") 2103 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions flow down the pipeline and are scheduled for execution. The OOO engine 2103 includes, but is not limited to, an allocator / register renamer 2140, a memory microinstruction queue 2142, an integer / floating-point microinstruction queue 2144, a memory scheduler 2146, a fast scheduler 2102, a slow / general floating-point scheduler ("slow / general FP scheduler") 2104, and a simple floating-point scheduler ("simple FP scheduler") 2106. In at least one embodiment, the fast scheduler 2102, the slow / general floating-point scheduler 2104, and the simple floating-point scheduler 2106 are also collectively referred to as "microinstruction schedulers 2102, 2104, 2106." The allocator / register renamer 2140 allocates the machine buffers and resources required for each microinstruction to execute in order. In at least one embodiment, the allocator / register renamer 2140 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 2140 also allocates an entry for each microinstruction in one of two microinstruction queues: a memory microinstruction queue 2142 for memory operations and an integer / floating point microinstruction queue 2144 for non-memory operations, preceding the memory scheduler 2146 and the microinstruction schedulers 2102, 2104, 2106. In at least one embodiment, the microinstruction schedulers 2102, 2104, 2106 determine when a microinstruction is ready to execute based on the readiness of its dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2102 of at least one embodiment can schedule on every half of the main clock cycle, while the slow / general floating point scheduler 2104 and the simple floating point scheduler 2106 can schedule once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 2102, 2104, 2106 arbitrate on dispatch ports to schedule microinstructions for execution.

[0230] In at least one embodiment, execution block 2111 includes, but is not limited to, integer register file / branch network 2108, floating point register file / branch network ("FP register file / branch network") 2110, address generation units ("AGUs") 2112 and 2114, fast arithmetic logic units ("fast ALUs") 2116 and 2118, slow ALU 2120, floating point ALU ("FP") 2122, and floating point move unit ("FP move") 2124. In at least one embodiment, integer register file / branch network 2108 and floating point register file / bypass network 2110 are also referred to herein as "register files 2108, 2110." In at least one embodiment, AGUS 2112 and 2114, fast ALUs 2116 and 2118, slow ALU 2120, floating-point ALU 2122, and floating-point move unit 2124 are also referred to herein as "execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124." In at least one embodiment, an execution block may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0231] In at least one embodiment, register files 2108 and 2110 may be arranged between microinstruction schedulers 2102, 2104, and 2106 and execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124. In at least one embodiment, integer register file / branch network 2108 performs integer operations. In at least one embodiment, floating-point register file / branch network 2110 performs floating-point operations. In at least one embodiment, each of register files 2108 and 2110 may include, but is not limited to, a branch network that can bypass or forward recently completed results that have not yet been written to the register file to new dependent objects. In at least one embodiment, register files 2108 and 2110 may communicate data with each other. In at least one embodiment, integer register file / branch network 2108 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / branch network 2110 may include, but is not limited to, 128-bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits wide.

[0232] In at least one embodiment, execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124 can execute instructions. In at least one embodiment, register files 2108 and 2110 store integer and floating-point data operand values required for microinstructions to execute. In at least one embodiment, processor 2100 can include, but is not limited to, any number of execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124, and combinations thereof. In at least one embodiment, floating-point ALU 2122 and floating-point move unit 2124 can execute floating-point, MMX, SIMD, AVX, SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2122 can include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2116 and 2118. In at least one embodiment, fast ALUs 2116 and 2118 can perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 2120, as slow ALU 2120 may include, but is not limited to, integer execution hardware for long-latency operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by ALUs 2112 and 2114. In at least one embodiment, fast ALU 2116, fast ALU 2118, and slow ALU 2120 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2116, fast ALU 2118, and slow ALU 2120 can be implemented to support various data bit sizes, including 16, 32, 128, 256, and the like. In at least one embodiment, the floating point ALU 2122 and floating point shift unit 2124 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, the floating point ALU 2122 and floating point shift unit 2124 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0233] In at least one embodiment, the microinstruction schedulers 2102, 2104, and 2106 schedule dependent operations before the parent load completes execution. In at least one embodiment, because microinstructions can be speculatively scheduled and executed in processor 2100, processor 2100 can also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations running in the pipeline that temporarily prevent the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor can also be designed to capture instruction sequences for text string comparison operations.

[0234] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using a variety of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, and the like. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0235] Figure 22 A processor 2200 is shown in accordance with at least one embodiment. In at least one embodiment, the processor 2200 includes, but is not limited to, one or more processor cores (cores) 2202A-2202N, an integrated memory controller 2214, and an integrated graphics processor 2208. In at least one embodiment, the processor 2200 may include additional cores, up to and including the additional processor core 2202N represented by the dashed box. In at least one embodiment, each processor core 2202A-2202N includes one or more internal cache units 2204A-2204N. In at least one embodiment, each processor core may also have access to one or more shared cache units 2206.

[0236] In at least one embodiment, the internal cache units 2204A-2204N and the shared cache unit 2206 represent a cache memory hierarchy within the processor 2200. In at least one embodiment, the cache memory units 2204A-2204N may include at least one level of instruction and data within each processor core and one or more levels of cache in a shared mid-level cache, such as an L2, L3, level 4 (L4), or other level of cache, with the highest level of cache being categorized as LLC before external memory. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2206 and 2204A-2204N.

[0237] In at least one embodiment, the processor 2200 may also include a set of one or more bus controller units 2216 and a system agent core 2210. In at least one embodiment, the one or more bus controller units 2216 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2210 provides management functions for various processor components. In at least one embodiment, the system agent core 2210 includes one or more integrated memory controllers 2214 to manage access to various external memory devices (not shown).

[0238] In at least one embodiment, one or more processor cores 2202A-2202N include support for simultaneous multithreading. In at least one embodiment, system agent core 2210 includes components for coordinating and operating processor cores 2202A-2202N during multithreaded processing. In at least one embodiment, system agent core 2210 may additionally include a power control unit (PCU) that includes logic and components to regulate one or more power states of processor cores 2202A-2202N and graphics processor 2208.

[0239] In at least one embodiment, the processor 2200 further includes a graphics processor 2208 to perform graphics processing operations. In at least one embodiment, the graphics processor 2208 is coupled to a shared cache unit 2206 and a system agent core 2210 including one or more integrated memory controllers 2214. In at least one embodiment, the system agent core 2210 also includes a display controller 2211 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 2211 may also be a separate module coupled to the graphics processor 2208 via at least one interconnect, or may be integrated within the graphics processor 2208.

[0240] In at least one embodiment, a ring-based interconnect 2212 is used to couple the internal components of the processor 2200. In at least one embodiment, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 2208 is coupled to the ring interconnect 2212 via an I / O link 2213.

[0241] In at least one embodiment, I / O link 2213 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2218 (e.g., an eDRAM module). In at least one embodiment, each of the processor cores 2202A-2202N and the graphics processor 2208 uses the embedded memory module 2218 as a shared LLC.

[0242] In at least one embodiment, the processor cores 2202A-2202N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2202A-2202N are heterogeneous in terms of ISA, where one or more processor cores 2202A-2202N execute a common instruction set, while one or more other processor cores 2202A-2202N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, the processor cores 2202A-2202N are heterogeneous in terms of microarchitecture, where one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 2200 can be implemented on one or more chips or as a SoC integrated circuit.

[0243] Figure 23 A graphics processor core 2300 is shown in accordance with at least one described embodiment. In at least one embodiment, graphics processor core 2300 is included within a graphics core array. In at least one embodiment, graphics processor core 2300 (sometimes referred to as a core slice) can be one or more graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 2300 is an example of a graphics core slice, and the graphics processors described herein can include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2300 can include fixed function blocks 2330 coupled to multiple sub-cores 2301A-2301F, also referred to as sub-slices, which include modular blocks of general purpose and fixed function logic.

[0244] In at least one embodiment, fixed function block 2330 includes a geometry / fixed function pipeline 2336, which, for example, in lower performance and / or lower power graphics processor implementations, may be shared by all sub-cores in graphics processor 2300. In at least one embodiment, geometry / fixed function pipeline 2336 includes a 3D fixed function pipeline, a video front end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0245] In at least one embodiment, fixed function block 2330 also includes a graphics SoC interface 2337, a graphics microcontroller 2338, and a media pipeline 2339. Graphics SoC interface 2337 provides an interface between graphics core 2300 and other processor cores in the SoC integrated circuit system. In at least one embodiment, graphics microcontroller 2338 is a programmable subprocessor that can be configured to manage various functions of graphics processor 2300, including thread dispatching, scheduling, and preemption. In at least one embodiment, media pipeline 2339 includes logic that facilitates decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline 2339 implements media operations via requests to computational or sampling logic within sub-cores 2301-2301F.

[0246] In at least one embodiment, the SoC interface 2337 enables the graphics core 2300 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2337 may also enable communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enable the use and / or implementation of global memory atomics that can be shared between the graphics core 2300 and the CPU within the SoC. In at least one embodiment, the SoC interface 2337 may also implement power management controls for the graphics core 2300 and enable interfaces between the clock domain of the graphics core 2300 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2337 enables the reception of command buffers from a command stream converter and a global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, commands and instructions may be dispatched to the media pipeline 2339 when media operations are to be performed, or may be assigned to the geometry and fixed function pipelines (e.g., geometry and fixed function pipeline 2336, geometry and fixed function pipeline 2314) when graph processing operations are to be performed.

[0247] In at least one embodiment, the graphics microcontroller 2338 can be configured to perform various scheduling and management tasks for the graphics core 2300. In at least one embodiment, the graphics microcontroller 2338 can perform graph and / or compute workload scheduling on various graphics parallel engines within the execution unit (EU) arrays 2302A-2302F, 2304A-2304F in the sub-cores 2301A-2301F. In at least one embodiment, host software executing on a CPU core of a SoC including the graphics core 2300 can submit a workload to one of multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operations include determining which workload to run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In at least one embodiment, the graphics microcontroller 2338 may also facilitate a low power or idle state for the graphics core 2300, thereby providing the graphics core 2300 with the ability to save and restore registers across low power state transitions within the graphics core 2300 independent of the operating system and / or graphics driver software on the system.

[0248] In at least one embodiment, graphics core 2300 may have more or fewer sub-cores than the sub-cores 2301A-2301F shown, up to N modular sub-cores. For each set of N sub-cores, in at least one embodiment, graphics core 2300 may also include shared function logic 2310, shared and / or cache memory 2312, geometry / fixed function pipelines 2314, and additional fixed function logic 2316 to accelerate various graphics and compute processing operations. In at least one embodiment, shared function logic 2310 may include logic units (e.g., samplers, math, and / or inter-thread communication logic) that may be shared by each of the N sub-cores within graphics core 2300. Shared and / or cache memory 2312 may be LLC for the N sub-cores 2301A-2301F within graphics core 2300 and may also serve as shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 2314 may be included in place of geometry / fixed function pipeline 2336 within fixed function block 2330 and may include the same or similar logic units.

[0249] In at least one embodiment, graphics core 2300 includes additional fixed-function logic 2316, which may include various fixed-function acceleration logic for use by graphics core 2300. In at least one embodiment, additional fixed-function logic 2316 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines, and within geometry / fixed-function pipelines 2316, 2336, there are at least two geometry pipelines, including a full geometry pipeline and a culling pipeline, which may be included in additional fixed-function logic 2316. In at least one embodiment, the culling pipeline is a modified version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of an application, each with a separate context. In at least one embodiment, position-only shading can hide long culling runs for discarded triangles, allowing shading to complete earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed function logic 2316 can execute position shaders in parallel with the main application and generally generate critical results faster than the full pipeline because the culling pipeline obtains and masks the position attributes of the vertices without having to perform rasterization and render the pixels to the frame buffer. In at least one embodiment, the culling pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether those triangles are culled. In at least one embodiment, the full pipeline (which in this case may be called a replay pipeline) can consume visibility information to skip culled triangles to mask only visible triangles that are ultimately passed to the rasterization stage.

[0250] In at least one embodiment, the additional fixed function logic 2316 may also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, for implementing slowed down CUAD routines.

[0251] In at least one embodiment, a set of execution resources is included within each graphics sub-core 2301A-2301F that can be used to execute graphics, media, and compute operations in response to requests from the graphics pipeline, media pipeline, or shader programs. In at least one embodiment, the graphics sub-core 2301A-2301F includes a plurality of EU arrays 2302A-2302F, 2304A-2304F, thread dispatch and inter-thread communication (TD / IC) logic 2303A-2303F, 3D (e.g., texture) samplers 2305A-2305F, media samplers 2306A-2306F, shader processors 2307A-2307F, and shared local memory (SLM) 2308A-2308F. Each EU array 2302A-2302F, 2304A-2304F includes multiple execution units, which are GU GPUs capable of servicing graphics, media, or compute operations, executing floating-point and integer / fixed-point logic operations, including graphics, media, or compute shader programs. In at least one embodiment, TD / IC logic 2303A-2303F performs local thread dispatch and thread control operations for execution units within a sub-core and facilitates communication between threads executing on execution units within the sub-core. In at least one embodiment, 3D samplers 2305A-2305F can read texture or other 3D graphics-related data into memory. In at least one embodiment, 3D samplers can read texture data differently based on the configured sampling state and texture format associated with a given texture. In at least one embodiment, media samplers 2306A-2306F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 2301A-2301F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each sub-core 2301A-2301F may utilize shared local memory 2308A-2308F within each sub-core, enabling threads executing within a thread group to execute using a common pool of on-chip memory.

[0252] Figure 24A parallel processing unit ("PPU") 2400 is shown in accordance with at least one embodiment. In at least one embodiment, PPU 2400 is configured with machine-readable code that, if executed by PPU 2400, causes PPU 2400 to perform some or all of the processes and techniques described herein. In at least one embodiment, PPU 2400 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multithreading as a latency hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a group of instructions configured to be executed by PPU 2400. In at least one embodiment, PPU 2400 is a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device, such as an LCD device. In at least one embodiment, PPU 2400 is configured to perform computations, such as linear algebra operations and machine learning operations. Figure 24 The example parallel processor is shown for illustrative purposes only and should be construed as a non-limiting example of a processor architecture implemented in at least one embodiment.

[0253] In at least one embodiment, one or more PPUs 2400 are configured to accelerate high-performance computing ("HPC"), data center, and machine learning applications. In at least one embodiment, one or more PPUs 2400 are configured to accelerate CUDA programs. In at least one embodiment, PPU 2400 includes, but is not limited to, an I / O unit 2406, a front-end unit 2410, a scheduler unit 2412, a work distribution unit 2414, a hub 2416, a crossbar switch ("Xbar") 2420, one or more general processing clusters ("GPCs") 2418, and one or more partitioning units ("memory partitioning units") 2422. In at least one embodiment, PPU 2400 is connected to a host processor or other PPUs 2400 via one or more high-speed GPU interconnects ("GPU interconnects") 2408. In at least one embodiment, PPU 2400 is connected to a host processor or other peripheral devices via a system bus or interconnect 2402. In one embodiment, PPU 2400 is connected to local memory including one or more memory devices ("memory") 2404. In at least one embodiment, the memory device 2404 includes, but is not limited to, one or more dynamic random access memory ("DRAM") devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as a high bandwidth memory ("HBM") subsystem, with multiple DRAM dies stacked within each device.

[0254] In at least one embodiment, the high-speed GPU interconnect 2408 may refer to a wire-based, multi-lane communication link that a system uses to scale and includes one or more PPUs 2400 ("CPUs") in conjunction with one or more CPUs, supporting cache coherency between the PPU 2400 and the CPUs and CPU mastering. In at least one embodiment, the high-speed GPU interconnect 2408 transmits data and / or commands to other units of the PPU 2400, such as one or more copy engines, video encoders, video decoders, power management units, and / or other processors, via the hub 2416. Figure 24 Other components that may not be explicitly shown.

[0255] In at least one embodiment, the I / O unit 2406 is configured to receive data from the host processor ( Figure 242406). In at least one embodiment, the I / O unit 2406 communicates with the host processor directly via the system bus 2402 or through one or more intermediate devices (e.g., a memory bridge). In at least one embodiment, the I / O unit 2406 can communicate with one or more other processors (e.g., one or more PPUs 2400) via the system bus 2402. In at least one embodiment, the I / O unit 2406 implements a PCIe interface for communicating over the PCIe bus. In at least one embodiment, the I / O unit 2406 implements an interface for communicating with external devices.

[0256] In at least one embodiment, the I / O unit 2406 decodes packets received via the system bus 2402. In at least one embodiment, at least some of the packets represent commands configured to cause the PPU 2400 to perform various operations. In at least one embodiment, the I / O unit 2406 sends the decoded commands to various other units of the PPU 2400 as specified by the commands. In at least one embodiment, the commands are sent to the front end unit 2410 and / or to the hub 2416 or other units of the PPU 2400, such as one or more replication engines, video encoders, video decoders, power management units, etc. Figure 24 In at least one embodiment, I / O unit 2406 is configured to route communications between the various logical units of PPU 2400.

[0257] In at least one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to the PPU 2400 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory that is accessible (e.g., read / write) by both the host processor and the PPU 2400—the host interface unit can be configured to access the buffer in system memory connected to the system bus 2402 via memory requests transmitted via the I / O unit 2406 over the system bus 2402. In at least one embodiment, the host processor writes a command stream to the buffer and then sends a pointer indicating the beginning of the command stream to the PPU 2400, so that the front end unit 2410 receives pointers to one or more command streams and manages the one or more command streams, reading commands from the command streams and forwarding the commands to the various units of the PPU 2400.

[0258] In at least one embodiment, the front end unit 2410 is coupled to a scheduler unit 2412, which configures the various GPCs 2418 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 2412 is configured to track state information associated with the various tasks managed by the scheduler unit 2412, where the state information may indicate which GPC 2418 the task is assigned to, whether the task is active or inactive, a priority associated with the task, and the like. In at least one embodiment, the scheduler unit 2412 manages multiple tasks that execute on one or more GPCs 2418.

[0259] In at least one embodiment, the scheduler unit 2412 is coupled to a work distribution unit 2414, which is configured to dispatch tasks for execution on the GPCs 2418. In at least one embodiment, the work distribution unit 2414 tracks a plurality of scheduled tasks received from the scheduler unit 2412 and manages a pending task pool and an active task pool for each GPC 2418. In at least one embodiment, the pending task pool includes a plurality of time slots (e.g., 32 time slots) containing tasks assigned to be processed by a particular GPC 2418; the active task pool may include a plurality of time slots (e.g., 4 time slots) for tasks actively being processed by the GPC 2418, such that as a task in a GPC 2418 completes execution, the task is evicted from the active task pool of the GPC 2418, and one of the other tasks is selected from the pending task pool and scheduled for execution on the GPC 2418. In at least one embodiment, if an active task is idle on a GPC 2418, such as while waiting for data dependencies to be resolved, the active task is evicted from the GPC 2418 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on the GPC 2418.

[0260] In at least one embodiment, work distribution unit 2414 communicates with one or more GPCs 2418 via XBar 2420. In at least one embodiment, XBar 2420 is an interconnect network that couples many units of PPU 2400 to other units of PPU 2400 and can be configured to couple work distribution unit 2414 to a specific GPC 2418. In at least one embodiment, one or more other units of PPU 2400 can also be connected to XBar 2420 through hub 2416.

[0261] In at least one embodiment, tasks are managed by a scheduler unit 2412 and assigned to one of the GPCs 2418 by a work distribution unit 2414. The GPC 2418 is configured to process the tasks and produce results. In at least one embodiment, the results can be consumed by other tasks in the GPC 2418, routed to a different GPC 2418 via an XBar 2420, or stored in memory 2404. In at least one embodiment, the results can be written to memory 2404 via a partition unit 2422, which implements a memory interface for writing data to or reading data from memory 2404. In at least one embodiment, the results can be transferred to another PPU 2400 or CPU via a high-speed GPU interconnect 2408. In at least one embodiment, the PPU 2400 includes, but is not limited to, U partition units 2422, which equal the number of separate and distinct memory devices 2404 coupled to the PPU 2400.

[0262] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 2400. In at least one embodiment, multiple computing applications are executed simultaneously by the PPU 2400, and the PPU 2400 provides isolation, quality of service ("QoS"), and independent address spaces for the multiple computing applications. In at least one embodiment, the application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 2400, and the driver core outputs the tasks to one or more streams processed by the PPU 2400. In at least one embodiment, each task includes one or more related thread groups, which may be referred to as warps. In at least one embodiment, a warp includes multiple related threads (e.g., 32 threads) that can execute in parallel. In at least one embodiment, a cooperative thread may refer to multiple threads that include instructions for executing tasks and exchanging data through shared memory.

[0263] Figure 25 FIG2 shows a GPC 2500 according to at least one embodiment. In at least one embodiment, the GPC 2500 is Figure 242418. In at least one embodiment, each GPC 2500 includes, but is not limited to, multiple hardware units for processing tasks, and each GPC 2500 includes, but is not limited to, a pipeline manager 2502, a pre-raster operations unit ("PROP") 2504, a raster engine 2508, a work distribution crossbar ("WDX") 2516, a memory management unit ("MMU") 2518, one or more data processing clusters ("DPCs") 2506, and any suitable combination of components.

[0264] In at least one embodiment, the operation of the GPC 2500 is controlled by a pipeline manager 2502. In at least one embodiment, the pipeline manager 2502 manages the configuration of one or more DPCs 2506 to process tasks assigned to the GPC 2500. In at least one embodiment, the pipeline manager 2502 configures at least one of the one or more DPCs 2506 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, a DPC 2506 is configured to execute vertex shader programs on a programmable streaming multiprocessor ("SM") 2514. In at least one embodiment, the pipeline manager 2502 is configured to route packets received from a work distribution unit to appropriate logic within the GPC 2500, and in at least one embodiment, some packets may be routed to fixed-function hardware units in the PROP 2504 and / or raster engine 2508, while other packets may be routed to a DPC 2506 for processing by a primitive engine 2512 or an SM 2514. In at least one embodiment, pipeline manager 2502 configures at least one of DPCs 2506 to implement a neural network model and / or a computational pipeline. In at least one embodiment, pipeline manager 2502 configures at least one of DPCs 2506 to execute at least a portion of a CUDA program.

[0265] In at least one embodiment, PROP unit 2504 is configured to route data generated by raster engine 2508 and DPC 2506 to a raster operations ("ROP") unit in a partition unit, such as described above in conjunction with Figure 24Memory partitioning unit 2422, etc., described in more detail. In at least one embodiment, PROP unit 2504 is configured to perform optimizations for color blending, organize pixel data, perform address translation, and the like. In at least one embodiment, raster engine 2508 includes, but is not limited to, a plurality of fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, raster engine 2508 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are passed to the coarse raster engine to generate coverage information for the primitives (e.g., an x, y coverage mask for the tile); the output of the coarse raster engine is passed to the culling engine, where fragments associated with primitives that fail the z test are culled, and to the clipping engine, where fragments outside the viewing frustum are clipped. In at least one embodiment, the clipped and culled fragments are passed to a fine raster engine to generate properties for the pixel fragments based on a plane equation generated by the setup engine. In at least one embodiment, the output of the raster engine 2508 includes fragments to be processed by any appropriate entity (e.g., by a fragment shader implemented within the DPC 2506).

[0266] In at least one embodiment, each DPC 2506 included in a GPC 2500 includes, but is not limited to, an M-pipeline controller ("MPC") 2510; a primitive engine 2512; one or more SMs 2514; and any suitable combination thereof. In at least one embodiment, the MPC 2510 controls the operation of the DPC 2506, routing packets received from the pipeline manager 2502 to appropriate units within the DPC 2506. In at least one embodiment, packets associated with vertices are routed to the primitive engine 2512, which is configured to fetch vertex attributes associated with the vertices from memory; conversely, packets associated with shader programs may be sent to the SM 2514.

[0267] In at least one embodiment, SM 2514 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, SM 2514 is multithreaded and configured to simultaneously execute multiple threads (e.g., 32 threads) from a particular thread group, and implements a single instruction, multiple data ("SIMD") architecture, in which each thread in a group of threads (e.g., a warp) is configured to process a different data set based on the same instruction set. In at least one embodiment, all threads in a thread group execute the same instructions. In at least one embodiment, SM 2514 implements a single instruction, multiple thread ("SIMT") architecture, in which each thread in a group of threads is configured to process a different data set based on the same instruction set, but in which individual threads in a thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp, thereby enabling concurrency between warps and serial execution within a warp when threads in the warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby enabling equal concurrency between all threads within a warp and between warps. In at least one embodiment, execution state is maintained for each individual thread, and threads executing the same instruction can be converged and executed in parallel to improve efficiency. Figure 26 At least one embodiment of SM 2514 is described in more detail.

[0268] In at least one embodiment, the MMU 2518 provides a communication channel between the GPC 2500 and the memory partition unit (e.g., Figure 24 The MMU 2518 provides an interface between the memory and the partition unit 2422, and provides virtual to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, the MMU 2518 provides one or more translation lookaside buffers ("TLBs") for performing translation of virtual addresses to physical addresses in memory.

[0269] Figure 26 Streaming Multiprocessor ("SM") 2600 is shown in accordance with at least one embodiment. In at least one embodiment, SM 2600 is Figure 25SM 2514. In at least one embodiment, SM 2600 includes, but is not limited to, an instruction cache 2602; one or more scheduler units 2604; a register file 2608; one or more processing cores ("cores") 2610; one or more special function units ("SFUs") 2612; one or more load / store units ("LSUs") 2614; an interconnect network 2616; a shared memory / level 1 ("L1") cache 2618; and any suitable combination thereof. In at least one embodiment, a work distribution unit schedules tasks for execution on a general processing cluster ("GPC") of a parallel processing unit ("PPU"), with each task being assigned to a specific data processing cluster ("DPC") within the GPC, and if the task is associated with a shader program, the task is assigned to one of SMs 2600. In at least one embodiment, scheduler unit 2604 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM 2600. In at least one embodiment, the scheduler unit 2604 schedules thread blocks for execution as warps of parallel threads, where each thread block is assigned at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, the scheduler unit 2604 manages a plurality of different thread blocks, assigns warps to different thread blocks, and then dispatches instructions from a plurality of different cooperating groups to various functional units (e.g., processing cores 2610, SFUs 2612, and LSUs 2614) during each clock cycle.

[0270] In at least one embodiment, "cooperative groups" may refer to a programming model for organizing groups of communicating threads, allowing developers to express the granularity at which threads are communicating, thereby enabling the expression of richer, more efficient decompositions of parallelism. In at least one embodiment, a cooperative launch API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, conventional programming model APIs provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., the syncthreads() function). However, in at least one embodiment, programmers can define thread groups at a granularity smaller than a thread block and synchronize within the defined group to achieve higher performance, design flexibility, and software reuse in the form of a collective group-wide function interface. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at sub-block and multi-block granularity and perform collective operations, such as synchronizing threads within a cooperative group. In at least one embodiment, the sub-block granularity is as small as a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, allowing libraries and utility functions to safely synchronize within their local environment without making assumptions about convergence. In at least one embodiment, the cooperation group primitive enables new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.

[0271] In at least one embodiment, the dispatch unit 2606 is configured to send instructions to one or more of the functional units, and the scheduler unit 2604 includes, but is not limited to, two dispatch units 2606 that enable two different instructions from the same warp to be dispatched per clock cycle. In at least one embodiment, each scheduler unit 2604 includes a single dispatch unit 2606 or additional dispatch units 2606.

[0272] In at least one embodiment, each SM 2600 includes, but is not limited to, a register file 2608 that provides a set of registers for the functional units of SM 2600. In at least one embodiment, register file 2608 is partitioned between each functional unit, allocating a dedicated portion of register file 2608 to each functional unit. In at least one embodiment, register file 2608 is partitioned between the different warps executed by SM 2600, and register file 2608 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM 2600 includes, but is not limited to, a plurality of L processing cores 2610. In at least one embodiment, SM 2600 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 2610. In at least one embodiment, each processing core 2610 includes, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, processing core 2610 includes, but is not limited to, 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

[0273] In at least one embodiment, the tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing core 2610. In at least one embodiment, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiplication and accumulation operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

[0274] In at least one embodiment, the matrix multiplication inputs A and B are 16-bit floating-point matrices, and the accumulation matrices C and D are 16-bit floating-point or 32-bit floating-point matrices. In at least one embodiment, the tensor core performs a 32-bit floating-point accumulation operation on the 16-bit floating-point input data. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations and obtains a full-precision product, which is then accumulated with other intermediate products using 32-bit floating-point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the tensor core is used to perform larger two-dimensional or higher-dimensional matrix operations composed of these smaller elements. In at least one embodiment, an API (such as the CUDA-C++ API) exposes specialized matrix load, matrix multiplication and accumulation, and matrix store operations to efficiently use the tensor cores from a CUDA-C++ program. In at least one embodiment, at the CUDA level, the warp-level interface assumes a 16×16 matrix size across all 32 warp threads.

[0275] In at least one embodiment, each SM 2600 includes, but is not limited to, M SFUs 2612 that perform specialized functions (e.g., attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFUs 2612 include, but are not limited to, tree traversal units configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFUs 2612 include, but are not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture units are configured to load texture maps (e.g., 2D arrays of texels) from memory and sample the texture maps to generate sampled texture values for use by shader programs executed by the SM 2600. In at least one embodiment, the texture maps are stored in shared memory / L1 cache 2618. In at least one embodiment, the texture units implement texture operations (such as filtering operations) using mip-maps (e.g., texture maps with different levels of detail). In at least one embodiment, each SM 2600 includes, but is not limited to, two texture units.

[0276] In at least one embodiment, each SM 2600 includes, but is not limited to, N LSUs 2614 that implement load and store operations between the shared memory / L1 cache 2618 and the register file 2608. In at least one embodiment, each SM 2600 includes, but is not limited to, an interconnection network 2616 that connects each functional unit to the register file 2608, and the LSUs 2614 connect to the register file 2608 and the shared memory / L1 cache 2618. In at least one embodiment, the interconnection network 2616 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 2608, and to connect the LSUs 2614 to memory locations in the register file 2608 and the shared memory / L1 cache 2618.

[0277] In at least one embodiment, shared memory / L1 cache 2618 is an array of on-chip memory that, in at least one embodiment, allows for data storage and communication between the SM 2600 and the primitive engines, as well as between threads within the SM 2600. In at least one embodiment, shared memory / L1 cache 2618 includes, but is not limited to, 128KB of storage capacity and is located in the path from the SM 2600 to the partition unit. In at least one embodiment, shared memory / L1 cache 2618 is used to cache reads and writes in at least one embodiment. In at least one embodiment, one or more of shared memory / L1 cache 2618, L2 cache, and memory is a backing store.

[0278] In at least one embodiment, data cache and shared memory functionality are combined into a single memory block, providing improved performance for both types of memory accesses. In at least one embodiment, capacity is used by programs that do not use the shared memory or as a cache. For example, if the shared memory is configured to use half of its capacity, texture and load / store operations can use the remaining capacity. According to at least one embodiment, integration within the shared memory / L1 cache 2618 enables the shared memory / L1 cache 2618 to function as a high-throughput pipeline for streaming data, while providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, when configured for general-purpose parallel computing, a simpler configuration can be used compared to graphics processing. In at least one embodiment, the fixed-function GPU is bypassed, creating a simpler programming model. In at least one embodiment, in a general-purpose parallel computing configuration, the work distribution unit directly allocates and distributes blocks of threads to DPCs. In at least one embodiment, threads in a block execute the same program, use unique thread IDs in computations to ensure each thread generates unique results, use SM 2600 to execute the program and perform computations, use shared memory / L1 cache 2618 to communicate between threads, and use LSU 2614 to read and write global memory through shared memory / L1 cache 2618 and a memory partitioning unit. In at least one embodiment, when configured for general-purpose parallel computation, SM 2600 writes commands to scheduler unit 2604 that can be used to start new work on a DPC.

[0279] In at least one embodiment, the PPU is included in or coupled to a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld device), PDA, digital camera, vehicle, head-mounted display, handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system-on-chip ("SoC") along with one or more other devices (e.g., additional PPUs, memory, a RISC CPU, an MMU, a digital-to-analog converter ("DAC"), etc.).

[0280] In at least one embodiment, the PPU can be included on a graphics card that includes one or more storage devices. The graphics card can be configured to connect to a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU can be an integrated GPU ("iGPU") included in a chipset on the motherboard.

[0281] Software Construction for General Computing

[0282] The following figures illustrate, but are not limited to, exemplary software architectures for implementing at least one embodiment.

[0283] Figure 27 A software stack for a programming platform according to at least one embodiment is shown. In at least one embodiment, a programming platform is a platform for utilizing hardware on a computing system to accelerate computing tasks. In at least one embodiment, a software developer can access the programming platform through libraries, compiler directives, and / or extensions to a programming language. In at least one embodiment, the programming platform can be, but is not limited to, CUDA, Radeon Open Compute Platform ("ROCm"), OpenCL (OpenCL developed by Khronos group), TM ), SYCL, or Intel One API.

[0284] In at least one embodiment, the programming platform's software stack 2700 provides an execution environment for applications 2701. In at least one embodiment, applications 2701 may include any computer software capable of being launched on the software stack 2700. In at least one embodiment, applications 2701 may include, but are not limited to, artificial intelligence ("AI") / machine learning ("ML") applications, high performance computing ("HPC") applications, virtual desktop infrastructure ("VDI"), or data center workloads.

[0285] In at least one embodiment, application 2701 and software stack 2700 run on hardware 2707. In at least one embodiment, hardware 2707 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices that support a programming platform. In at least one embodiment, for example, using CUDA, software stack 2700 may be vendor-specific and only compatible with devices from a specific vendor. In at least one embodiment, for example, using OpenCL, software stack 2700 can be used with devices from different vendors. In at least one embodiment, hardware 2707 includes a host connected to one or more devices that can be accessed via application programming interface (API) calls to perform computing tasks. In at least one embodiment, compared to the host within hardware 2707, which may include but is not limited to a CPU (but may also include a computing device) and its memory, the devices within hardware 2707 may include but are not limited to a GPU, FPGA, AI engine, or other computing device (but may also include a CPU) and its memory.

[0286] In at least one embodiment, the programming platform's software stack 2700 includes, but is not limited to, a plurality of libraries 2703, a runtime 2705, and device kernel drivers 2706. In at least one embodiment, each of the libraries 2703 may include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, the libraries 2703 may include, but are not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the libraries 2703 include functions optimized for execution on one or more types of devices. In at least one embodiment, the libraries 2703 may include, but are not limited to, functions for performing mathematical, deep learning, and / or other types of operations on the devices. In at least one embodiment, the libraries 2703 are associated with corresponding APIs 2702, which may include one or more APIs that expose the functions implemented in the libraries 2703.

[0287] In at least one embodiment, the application 2701 is written as source code that is compiled into executable code as follows: Figures 32-34 2701. In at least one embodiment, the executable code of application 2701 can run at least in part on an execution environment provided by software stack 2700. In at least one embodiment, during the execution of application 2701, code that needs to run on the device (as opposed to the host) can be obtained. In this case, in at least one embodiment, runtime 2705 can be called to load and start the necessary code on the device. In at least one embodiment, runtime 2705 can include any technically feasible runtime system capable of supporting the execution of application 2701.

[0288] In at least one embodiment, runtime 2705 is implemented as one or more runtime libraries associated with a corresponding API (shown as API 2704). In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization, among others. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, deallocating, and copying device memory, and for transferring data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for launching a function on the device (sometimes referred to as a "kernel" when the function is a global function callable from the host), and functions for setting property values in buffers maintained by the runtime library for a given function to be executed on the device.

[0289] In at least one embodiment, the runtime library and corresponding API 2704 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs can expose a low-level set of functions for fine-grained control of a device, while another (or any number of) APIs can expose such a higher-level set of functions. In at least one embodiment, a high-level runtime API can be built on top of the low-level APIs. In at least one embodiment, one or more runtime APIs can be language-specific APIs layered on top of a language-independent runtime API.

[0290] In at least one embodiment, the device kernel driver 2706 is configured to facilitate communication with the underlying device. In at least one embodiment, the device kernel driver 2706 can provide APIs such as API 2704 and / or low-level functions that other software relies on. In at least one embodiment, the device kernel driver 2706 can be configured to compile intermediate representation ("IR") code into binary code at runtime. In at least one embodiment, for CUDA, the device kernel driver 2706 can compile non-hardware-specific parallel thread execution ("PTX") IR code into binary code for a specific target device at runtime (caching the compiled binary code), which is sometimes also referred to as "final" code. In at least one embodiment, doing so can allow the final code to run on a target device that may not have existed when the source code was originally compiled into PTX code. Alternatively, in at least one embodiment, the device source code can be compiled into binary code offline without the device kernel driver 2706 compiling the IR code at runtime.

[0291] Figure 28 According to at least one embodiment, Figure 27 2801. In at least one embodiment, the CUDA software stack 2800, on which the application 2801 can be launched, includes a CUDA library 2803, a CUDA runtime 2805, a CUDA driver 2807, and a device kernel driver 2808. In at least one embodiment, the CUDA software stack 2800 executes on hardware 2809, which may include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0292] In at least one embodiment, the application 2801, the CUDA runtime 2805, and the device kernel driver 2808 can perform similar functions as the application 2701, the runtime 2705, and the device kernel driver 2706, respectively. Figure 27. In at least one embodiment, the CUDA driver 2807 includes a library (libcuda.so) that implements the CUDA driver API 2806. In at least one embodiment, similar to the CUDA runtime API 2804 implemented by the CUDA runtime library (cudart), the CUDA driver API 2806 may expose, but is not limited to, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, the CUDA driver API 2806 differs from the CUDA runtime API 2804 in that the CUDA runtime API 2804 simplifies device code management by providing implicit initialization, context (similar to process) management, and module (similar to dynamically loaded libraries) management. In contrast to the high-level CUDA runtime API 2804, in at least one embodiment, the CUDA driver API 2806 is a low-level API that provides finer-grained control over the device, particularly with respect to context and module loading. In at least one embodiment, the CUDA driver API 2806 may expose functions for context management that are not exposed by the CUDA runtime API 2804. In at least one embodiment, the CUDA driver API 2806 is also language-independent and supports, for example, OpenCL in addition to the CUDA runtime API 2804. Furthermore, in at least one embodiment, the development libraries, including the CUDA runtime 2805, can be considered separate from the driver components, including the user-mode CUDA driver 2807 and the kernel-mode device driver 2808 (sometimes also referred to as a "display" driver).

[0293] In at least one embodiment, the CUDA libraries 2803 may include, but are not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries, which can be utilized by parallel computing applications (e.g., application 2801). In at least one embodiment, the CUDA libraries 2803 may include mathematical libraries, such as the cuBLAS library, which is an implementation of the Basic Linear Algebra Subroutines ("BLAS") for performing linear algebra operations; the cuFFT library for computing fast Fourier transforms ("FFTs"), and the cuRAND library for generating random numbers, among others. In at least one embodiment, the CUDA libraries 2803 may include deep learning libraries, such as the cuDNN library for primitives for deep neural networks and the TensorRT platform for high-performance deep learning inference, among others.

[0294] Figure 29 According to at least one embodiment, Figure 27In at least one embodiment, the ROCm software stack 2900, on which an application 2901 can be launched, includes a language runtime 2903, a system runtime 2905, thunks 2907, and a ROCm kernel driver 2908. In at least one embodiment, the ROCm software stack 2900 executes on hardware 2909, which may include a ROCm-enabled GPU developed by AMD, Inc. of Santa Clara, California.

[0295] In at least one embodiment, application 2901 may execute a combination of the above Figure 27 In addition, in at least one embodiment, the language runtime 2903 and the system runtime 2905 can perform functions similar to those described above in conjunction with the application 2701. Figure 27 The language runtime 2903 and the system runtime 2905 are similar in functionality to the runtime 2705 discussed above. In at least one embodiment, the language runtime 2903 differs from the system runtime 2905 in that the system runtime 2905 is a language-agnostic runtime that implements the ROCr system runtime API 2904 and leverages the Heterogeneous System Architecture ("HSA") runtime API. In at least one embodiment, the HSA runtime API is a thin user-mode API that exposes interfaces for accessing and interacting with the AMDGPU, including functions for memory management, execution control of kernels dispatched by the architecture, error handling, system and agent information, and runtime initialization and shutdown. In at least one embodiment, compared to the system runtime 2905, the language runtime 2903 is an implementation of a language-specific runtime API 2902 layered on top of the ROCr system runtime API 2904. In at least one embodiment, the language runtime API may include, but is not limited to, a portable heterogeneous compute interface ("HIP") language runtime API, a heterogeneous compute compiler ("HCC") language runtime API, or an OpenCL API, among others. In particular, the HIP language is an extension of the C++ programming language with a functionally similar version of the CUDA mechanism, and in at least one embodiment, the HIP language runtime API includes a Figure 28 Similar functions to the CUDA runtime API 2804 are discussed, such as those used for memory management, execution control, device management, error handling, and synchronization.

[0296] In at least one embodiment, thunk (ROCt) 2907 is an interface 2906 that can be used to interact with the underlying ROCm driver 2908. In at least one embodiment, the ROCm driver 2908 is a ROCk driver, which is a combination of the AMDGPU driver and the HSA kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for GPUs developed by AMD that performs the above combined Figure 27 The HSA kernel driver 2706 may be used to provide similar functionality to the discussed device kernel driver 2706. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to more efficiently share system resources via hardware features.

[0297] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 2900 above the language runtime 2903 and provide Figure 28 The various libraries may include, but are not limited to, math, deep learning, and / or other libraries, such as a hipBLAS library that implements functions similar to CUDA cuBLAS, a rocFFT library similar to CUDA cuFFT for computing FFTs, and the like.

[0298] Figure 30 According to at least one embodiment, Figure 27 3001. In at least one embodiment, the OpenCL software stack 3000, on which the application 3001 can be launched, includes an OpenCL framework 3010, an OpenCL runtime 3006, and a driver 3007. In at least one embodiment, the OpenCL software stack 3000 executes on hardware 2809 that is not vendor-specific. In at least one embodiment, because devices developed by different vendors support OpenCL, specific OpenCL drivers may be required to interoperate with hardware from such vendors.

[0299] In at least one embodiment, the application 3001, the OpenCL runtime 3006, the device kernel driver 3007 and the hardware 3008 can each execute in conjunction with the above Figure 27 Similar functionality is discussed for application 2701, runtime 2705, device kernel driver 2706, and hardware 2707. In at least one embodiment, application 3001 also includes an OpenCL kernel 3002 having code to be executed on the device.

[0300] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides a platform layer API and a runtime API, shown as platform API 3003 and runtime API 3005. In at least one embodiment, runtime API 3005 uses contexts to manage the execution of kernels on devices. In at least one embodiment, each identified device can be associated with a respective context, which runtime API 3005 can use to manage the device's command queue, program and kernel objects, shared memory objects, and the like. In at least one embodiment, platform API 3003 exposes functions that allow device contexts to be used to select and initialize devices, submit work to devices via command queues, and enable data transfer to and from devices. Additionally, in at least one embodiment, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, image processing functions, and the like.

[0301] In at least one embodiment, a compiler 3004 is also included in the OpenCL framework 3010. In at least one embodiment, source code can be compiled offline before executing the application or compiled online during execution of the application. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment can be compiled online by compiler 3004, which is included to represent any number of compilers that can be used to compile source code and / or IR code (e.g., Standard Portable Intermediate Representation ("SPIR-V") code) into binary code. Alternatively, in at least one embodiment, OpenCL applications can be compiled offline before executing such applications.

[0302] Figure 31 Software supported by a programming platform according to at least one embodiment is shown. In at least one embodiment, programming platform 3104 is configured to support various programming models 3103, middleware and / or libraries 3102, and frameworks 3101 that applications 3100 can rely on. In at least one embodiment, application 3100 can be an AI / ML application implemented using, for example, a deep learning framework (e.g., MXNet, PyTorch, or TensorFlow), which can rely on libraries such as cuDNN, NVIDIA Collective Communications Library ("NCCL"), and / or NVIDIA Developer Data Loading Library ("DALI") CUDA libraries to provide accelerated computation on the underlying hardware.

[0303] In at least one embodiment, the programming platform 3104 can be a combination of the above Figure 28 、 Figure 29 and Figure 30 In at least one embodiment, the programming platform 3104 supports one of the CUDA, ROCm, or OpenCL platforms described herein. In at least one embodiment, the programming platform 3104 supports multiple programming models 3103, which are abstractions of the underlying computing system that allow the expression of algorithms and data structures. In at least one embodiment, the programming model 3103 can expose features of the underlying hardware to improve performance. In at least one embodiment, the programming model 3103 can include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism ("C++AMP"), Open Multiprocessing ("OpenMP"), Open Accelerators ("OpenACC"), and / or Vulcan Compute.

[0304] In at least one embodiment, the library and / or middleware 3102 provides an abstract implementation of the programming model 3104. In at least one embodiment, such a library includes data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, in addition to those that can be obtained from the programming platform 3104, such middleware also includes software that provides services to the application. In at least one embodiment, the library and / or middleware 3102 may include but is not limited to cuBLAS, cuFFT, cuRAND and other CUDA libraries, or rocBLAS, rocFFT, rocRAND and other ROCm libraries. In addition, in at least one embodiment, the library and / or middleware 3102 may include NCCL and ROCm communication collection libraries ("RCCL") libraries that provide communication routines for GPUs, MIOpen libraries for deep learning acceleration and / or intrinsic libraries for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0305] In at least one embodiment, application framework 3101 relies on libraries and / or middleware 3102. In at least one embodiment, each application framework 3101 is a software framework for implementing a standard structure for application software. Returning to the AI / ML example discussed above, in at least one embodiment, AI / ML applications can be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning framework.

[0306] Figure 32 Compiled code is shown in accordance with at least one embodiment to Figures 27-30In at least one embodiment, compiler 3201 receives source code 3200, which includes both host code and device code. In at least one embodiment, compiler 3201 is configured to convert source code 3200 into host executable code 3202 for execution on the host and device executable code 3203 for execution on the device. In at least one embodiment, source code 3200 can be compiled offline before executing the application, or compiled online during execution of the application.

[0307] In at least one embodiment, source code 3200 may include code in any programming language supported by compiler 3201, such as C++, C, Fortran, etc. In at least one embodiment, source code 3200 may be included in a single-source file having a mixture of host code and device code, with the location of the device code indicated therein. In at least one embodiment, the single-source file may be a .cu file including CUDA code or a .hip.cpp file including HIP code. Alternatively, in at least one embodiment, source code 3200 may include multiple source code files, rather than a single source file, in which host code and device code are separated.

[0308] In at least one embodiment, compiler 3201 is configured to compile source code 3200 into host executable code 3202 for execution on a host and device executable code 3203 for execution on a device. In at least one embodiment, compiler 3201 performs operations including parsing source code 3200 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment where source code 3200 comprises a single source file, compiler 3201 may separate device code from host code in such a single source file, compile the device code and host code into device executable code 3203 and host executable code 3202, respectively, and link device executable code 3203 and host executable code 3202 together in a single file, as described below with respect to Figure 33 discussed in more detail.

[0309] In at least one embodiment, host executable code 3202 and device executable code 3203 may be in any suitable format, such as binary code and / or IR code. In the case of CUDA, in at least one embodiment, host executable code 3202 may include native object code, while device executable code 3203 may include code in a PTX intermediate representation. In at least one embodiment, in the case of ROCm, both host executable code 3202 and device executable code 3203 may include target binary code.

[0310] Figure 33 is compiled code according to at least one embodiment to Figures 27-30 33. In at least one embodiment, the compiler 3301 is configured to receive source code 3300, compile the source code 3300, and output an executable file 3310. In at least one embodiment, the source code 3300 is a single source file, such as a .cu file, a .hip.cpp file, or a file in another format, which includes both host code and device code. In at least one embodiment, the compiler 3301 can be, but is not limited to, the NVIDIA CUDA compiler ("NVCC") for compiling CUDA code in .cu files, or the HCC compiler for compiling HIP code in .hip.cpp files.

[0311] In at least one embodiment, compiler 3301 includes a compiler front end 3302, a host compiler 3305, a device compiler 3306, and a linker 3309. In at least one embodiment, compiler front end 3302 is configured to separate device code 3304 from host code 3303 in source code 3300. In at least one embodiment, device code 3304 is compiled by device compiler 3306 into device executable code 3308, which, as described, may include binary code or IR code. In at least one embodiment, host code 3303 is separately compiled by host compiler 3305 into host executable code 3307. In at least one embodiment, for NVCC, host compiler 3305 may be, but is not limited to, a general-purpose C / C++ compiler that outputs native object code, while device compiler 3306 may be, but is not limited to, a Low-Level Virtual Machine ("LLVM")-based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, for HCC, both the host compiler 3305 and the device compiler 3306 can be, but are not limited to, LLVM-based compilers that output target binary code.

[0312] In at least one embodiment, after source code 3300 is compiled into host executable code 3307 and device executable code 3308, linker 3309 links host and device executable code 3307 and 3308 together in executable file 3310. In at least one embodiment, native object code for the host and PTX or binary code for the device may be linked together in an Executable and Linkable Format ("ELF") file, which is a container format for storing object code.

[0313] Figure 343. The conversion of source code before compiling it is shown in accordance with at least one embodiment. In at least one embodiment, source code 3400 is passed through a conversion tool 3401, which converts the source code 3400 into converted source code 3402. In at least one embodiment, a compiler 3403 is used to compile the converted source code 3402 into a host executable code 3404 and a device executable code 3305, similar to the process by which compiler 3201 compiles source code 3200 into a host executable code 3202 and a device executable code 3203, as described above in conjunction with Figure 32 discussed.

[0314] In at least one embodiment, the conversion performed by the conversion tool 3401 is used to port the source code 3400 for execution in an environment different from that on which it was originally intended to run. In at least one embodiment, the conversion tool 3401 may include, but is not limited to, a HIP converter for "hipifying" CUDA code for a CUDA platform into HIP code that can be compiled and executed on a ROCm platform. In at least one embodiment, the conversion of the source code 3400 may include parsing the source code 3400 and converting calls to APIs provided by one programming model (e.g., CUDA) to corresponding calls to APIs provided by another programming model (e.g., HIP), as described below in conjunction with Figure 35A and Figure 36 Returning to the example of porting CUDA code, in at least one embodiment, calls to the CUDA runtime API, the CUDA driver API, and / or the CUDA library can be converted to corresponding HIP API calls. In at least one embodiment, the automatic conversion performed by the conversion tool 3401 may sometimes be incomplete, requiring additional manual effort to fully port the source code 3400.

[0315] Configuring GPUs for general computing

[0316] The following figures illustrate, but are not limited to, exemplary architectures for compiling and executing computing source code in accordance with at least one embodiment.

[0317] Figure 35AA system 3500 is shown configured to compile and execute CUDA source code 3510 using different types of processing units in accordance with at least one embodiment. In at least one embodiment, the system 3500 includes, but is not limited to, CUDA source code 3510, a CUDA compiler 3550, a host executable 3570(1), a host executable 3570(2), a CUDA device executable 3584, a CPU 3590, a CUDA-enabled GPU 3594, a GPU 3592, a CUDA to HIP conversion tool 3520, HIP source code 3530, a HIP compiler driver 3540, an HCC 3560, and an HCC device executable 3582.

[0318] In at least one embodiment, CUDA source code 3510 is a collection of human-readable code in the CUDA programming language. In at least one embodiment, CUDA code is human-readable code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language that includes, but is not limited to, mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, device code is source code that can be executed in parallel on a device after compilation. In at least one embodiment, the device can be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU 3590, GPU 3592, or another GPGPU. In at least one embodiment, host code is source code that can be executed on a host after compilation. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU 3590.

[0319] In at least one embodiment, CUDA source code 3510 includes, but is not limited to, any number (including zero) of global functions 3512, any number (including zero) of device functions 3514, any number (including zero) of host functions 3516, and any number (including zero) of host / device functions 3518. In at least one embodiment, global functions 3512, device functions 3514, host functions 3516, and host / device functions 3518 can be intermixed within CUDA source code 3510. In at least one embodiment, each global function 3512 is executable on the device and callable from the host. Thus, in at least one embodiment, one or more of the global functions 3512 can serve as an entry point for the device. In at least one embodiment, each global function 3512 is a kernel. In at least one embodiment, and in a technique known as dynamic parallelism, one or more global functions 3512 define a kernel that is executable on and callable from a device. In at least one embodiment, the kernel is executed N times (where N is any positive integer) in parallel by N different threads on the device during execution.

[0320] In at least one embodiment, each device function 3514 executes on a device and can only be called from such a device. In at least one embodiment, each host function 3516 executes on a host and can only be called from such a host. In at least one embodiment, each host / device function 3516 defines both a host version of the function that is executable on the host and can only be called from such a host, and a device version of the function that is executable on a device and can only be called from such a device.

[0321] In at least one embodiment, CUDA source code 3510 may also include, but is not limited to, any number of calls to any number of functions defined by the CUDA runtime API 3502. In at least one embodiment, the CUDA runtime API 3502 may include, but is not limited to, any number of functions executed on the host for allocating and deallocating device memory, transferring data between host and device memory, managing systems with multiple devices, and the like. In at least one embodiment, CUDA source code 3510 may also include, but is not limited to, any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API designed for use by CUDA code. In at least one embodiment, CUDA APIs include, but are not limited to, the CUDA runtime API 3502, the CUDA driver API, APIs for any number of CUDA libraries, and the like. In at least one embodiment, and relative to the CUDA runtime API 3502, the CUDA driver API is a lower-level API that provides finer-grained control over the device. In at least one embodiment, examples of CUDA libraries include, but are not limited to, cuBLAS, cuFFT, cuRAND, cuDNN, and the like.

[0322] In at least one embodiment, the CUDA compiler 3550 compiles input CUDA code (e.g., CUDA source code 3510) to generate host executable code 3570(1) and CUDA device executable code 3584. In at least one embodiment, the CUDA compiler 3550 is NVCC. In at least one embodiment, the host executable code 3570(1) is a compiled version of the host code included in the input source code that is executable on the CPU 3590. In at least one embodiment, the CPU 3590 can be any processor optimized for sequential instruction processing.

[0323] In at least one embodiment, the CUDA device executable code 3584 is a compiled version of the device code included in the input source code that is executable on the CUDA-enabled GPU 3594. In at least one embodiment, the CUDA device executable code 3584 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3584 includes, but is not limited to, IR code, such as PTX code, which is further compiled by a device driver at runtime into binary code for a specific target device (e.g., a CUDA-enabled GPU 3594). In at least one embodiment, the CUDA-enabled GPU 3594 can be any processor that is optimized for parallel instruction processing and supports CUDA. In at least one embodiment, the CUDA-enabled GPU 3594 was developed by NVIDIA Corporation of Santa Clara, California.

[0324] In at least one embodiment, the CUDA to HIP conversion tool 3520 is configured to convert the CUDA source code 3510 into functionally similar HIP source code 3530. In at least one embodiment, the HIP source code 3530 is a collection of human-readable code in the HIP programming language. In at least one embodiment, the HIP code is human-readable code in the HIP programming language. In at least one embodiment, the HIP programming language is an extension of the C++ programming language and includes, but is not limited to, a functionally similar version of the CUDA mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, the HIP programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, for example, the HIP programming language includes, but is not limited to, mechanisms for defining global functions 3512. However, such a HIP programming language may lack support for dynamic parallelism, and therefore, global functions 3512 defined in the HIP code are only callable from the host.

[0325] In at least one embodiment, HIP source code 3530 includes, but is not limited to, any number (including zero) of global functions 3512, any number (including zero) of device functions 3514, any number (including zero) of host functions 3516, and any number (including zero) of host / device functions 3518. In at least one embodiment, HIP source code 3530 may also include any number of calls to any number of functions specified in the HIP runtime API 3532. In at least one embodiment, the HIP runtime API 3532 includes, but is not limited to, functionally similar versions of a subset of the functions included in the CUDA runtime API 3502. In at least one embodiment, HIP source code 3530 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, a HIP API may be any API designed for use by HIP code and / or ROCm. In at least one embodiment, HIP APIs include, but are not limited to, the HIP runtime API 3532, a HIP driver API, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, and the like.

[0326] In at least one embodiment, the CUDA to HIP conversion tool 3520 converts each kernel call in the CUDA code from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in the CUDA API, and a HIP call is a call to a function specified in the HIP API. In at least one embodiment, the CUDA to HIP conversion tool 3520 converts any number of calls to functions specified in the CUDA runtime API 3502 to any number of calls to functions specified in the HIP runtime API 3532.

[0327] In at least one embodiment, the CUDA to HIP conversion tool 3520 is a tool called hipify-perl, which performs a text-based conversion process. In at least one embodiment, the CUDA to HIP conversion tool 3520 is a tool called hipify-clang, which performs a more complex and robust conversion process than hipify-perl, which involves parsing the CUDA code using clang (a compiler front end) and then converting the resulting symbols. In at least one embodiment, in addition to those modifications performed by the CUDA to HIP conversion tool 3520, correctly converting the CUDA code to HIP code may require modifications (e.g., manual editing).

[0328] In at least one embodiment, the HIP compiler driver 3540 is a front end that determines the target device 3546 and then configures a compiler compatible with the target device 3546 to compile the HIP source code 3530. In at least one embodiment, the target device 3546 is a processor optimized for parallel instruction processing. In at least one embodiment, the HIP compiler driver 3540 can determine the target device 3546 in any technically feasible manner.

[0329] In at least one embodiment, if the target device 3546 is CUDA compatible (e.g., a CUDA-enabled GPU 3594), the HIP compiler driver 3540 generates HIP / NVCC compile commands 3542. In at least one embodiment and in conjunction with Figure 35B As described in more detail, HIP / NVCC compile commands 3542 configure CUDA compiler 3550 to use, but not limited to, HIP to CUDA translation headers and CUDA runtime libraries to compile HIP source code 3530. In at least one embodiment and in response to HIP / NVCC compile commands 3542, CUDA compiler 3550 generates host executable code 3570(1) and CUDA device executable code 3584.

[0330] In at least one embodiment, if the target device 3546 is not CUDA compatible, the HIP compiler driver 3540 generates HIP / HCC compilation commands 3544. In at least one embodiment and as in conjunction with Figure 35C As described in more detail, the HIP / HCC compile command 3544 configures the HCC 3560 to compile the HIP source code 3530 using the HCC headers and the HIP / HCC runtime library. In at least one embodiment and in response to the HIP / HCC compile command 3544, the HCC 3560 generates a host executable code 3570(2) and an HCC device executable code 3582. In at least one embodiment, the HCC device executable code 3582 is a compiled version of the device code contained in the HIP source code 3530 that can be executed on the GPU 3592. In at least one embodiment, the GPU 3592 can be any processor that is optimized for parallel instruction processing, is not CUDA-compatible, and is compatible with HCC. In at least one embodiment, the GPU 3592 is developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the GPU 3592 is a non-CUDA-enabled GPU 3592.

[0331] For illustrative purposes only, Figure 35A35. In at least one embodiment, three different flows that can be implemented to compile CUDA source code 3510 for execution on a CPU 3590 and different devices are depicted. In at least one embodiment, the direct CUDA flow compiles CUDA source code 3510 for execution on the CPU 3590 and a CUDA-enabled GPU 3594 without converting the CUDA source code 3510 into HIP source code 3530. In at least one embodiment, the indirect CUDA flow converts the CUDA source code 3510 into HIP source code 3530 and then compiles the HIP source code 3530 for execution on the CPU 3590 and a CUDA-enabled GPU 3594. In at least one embodiment, the CUDA / HCC flow converts the CUDA source code 3510 into HIP source code 3530 and then compiles the HIP source code 3530 for execution on the CPU 3590 and a GPU 3592.

[0332] A direct CUDA flow that can be implemented in at least one embodiment can be depicted by a dashed line and a series of bubble annotations A1-A3. In at least one embodiment, and as indicated by bubble annotation A1, a CUDA compiler 3550 receives a CUDA source code 3510 and a CUDA compile command 3548 that configures the CUDA compiler 3550 to compile the CUDA source code 3510. In at least one embodiment, the CUDA source code 3510 used in the direct CUDA flow is written in the CUDA programming language, which is based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to the CUDA compile command 3548, the CUDA compiler 3550 generates a host executable code 3570 (1) and a CUDA device executable code 3584 (indicated by bubble annotation A2). In at least one embodiment and as indicated by bubble annotation A3, the host executable code 3570 (1) and the CUDA device executable code 3584 can be executed on a CPU 3590 and a CUDA-enabled GPU 3594, respectively. In at least one embodiment, the CUDA device executable code 3584 includes but is not limited to binary code. In at least one embodiment, the CUDA device executable code 3584 includes but is not limited to PTX code and is further compiled into binary code for a specific target device at runtime.

[0333] The indirect CUDA flow that can be implemented in at least one embodiment can be depicted by the dashed line and a series of bubble notes B1-B6. In at least one embodiment and as indicated by bubble note B1, a CUDA to HIP conversion tool 3520 receives CUDA source code 3510. In at least one embodiment and as indicated by bubble note B2, the CUDA to HIP conversion tool 3520 converts the CUDA source code 3510 into HIP source code 3530. In at least one embodiment and as indicated by bubble note B3, a HIP compiler driver 3540 receives the HIP source code 3530 and determines whether the target device 3546 is CUDA-enabled.

[0334] In at least one embodiment and as indicated by bubble note B4, the HIP compiler driver 3540 generates HIP / NVCC compile commands 3542 and sends both the HIP / NVCC compile commands 3542 and the HIP source code 3530 to the CUDA compiler 3550. Figure 35B As described in more detail, the HIP / NVCC compile command 3542 configures the CUDA compiler 3550 to compile the HIP source code 3530 using, but not limited to, the HIP to CUDA translation header and the CUDA runtime library. In at least one embodiment and in response to the HIP / NVCC compile command 3542, the CUDA compiler 3550 generates host executable code 3570 (1) and CUDA device executable code 3584 (indicated by bubble note B5). In at least one embodiment and as indicated by bubble note B6, the host executable code 3570 (1) and the CUDA device executable code 3584 can be executed on a CPU 3590 and a CUDA-enabled GPU 3594, respectively. In at least one embodiment, the CUDA device executable code 3584 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3584 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0335] The CUDA / HCC process that can be implemented in at least one embodiment can be described by a solid line and a series of bubble comments C1-C6. In at least one embodiment and as indicated by bubble comment C1, a CUDA to HIP conversion tool 3520 receives CUDA source code 3510. In at least one embodiment and as indicated by bubble comment C2, the CUDA to HIP conversion tool 3520 converts the CUDA source code 3510 into HIP source code 3530. In at least one embodiment and as indicated by bubble comment C3, a HIP compiler driver 3540 receives the HIP source code 3530 and determines that the target device 3546 is not CUDA-enabled.

[0336] In at least one embodiment, the HIP compiler driver 3540 generates HIP / HCC compile commands 3544 and sends both the HIP / HCC compile commands 3564 and the HIP source code 3530 to the HCC 3560 (indicated by bubble comment C4). In at least one embodiment and as in conjunction with Figure 35C As described in more detail, HIP / HCC compile command 3564 configures HCC 3560 to compile HIP source code 3530 using, but not limited to, HCC headers and HIP / HCC runtime libraries. In at least one embodiment and in response to HIP / HCC compile command 3544, HCC 3560 generates host executable code 3570(2) and HCC device executable code 3582 (indicated by bubble comment C5). In at least one embodiment and as indicated by bubble comment C6, host executable code 3570(2) and HCC device executable code 3582 can be executed on CPU 3590 and GPU 3592, respectively.

[0337] In at least one embodiment, after converting the CUDA source code 3510 to the HIP source code 3530, the HIP compiler driver 3540 can then be used to generate executable code for the CUDA-enabled GPU 3594 or GPU 3592 without having to re-implement the CUDA to HIP conversion tool 3520. In at least one embodiment, the CUDA to HIP conversion tool 3520 converts the CUDA source code 3510 to the HIP source code 3530 and then stores it in memory. In at least one embodiment, the HIP compiler driver 3540 then configures the HCC 3560 to generate the host executable code 3570 (2) and the HCC device executable code 3582 based on the HIP source code 3530. In at least one embodiment, the HIP compiler driver 3540 then configures the CUDA compiler 3550 to generate the host executable code 3570 (1) and the CUDA device executable code 3584 based on the stored HIP source code 3530.

[0338] Figure 35B 3590 and a CUDA-enabled GPU 3594 configured to compile and execute Figure 35A In at least one embodiment, the system 3504 includes, but is not limited to, the CUDA source code 3510, a CUDA to HIP conversion tool 3520, a HIP source code 3530, a HIP compiler driver 3540, a CUDA compiler 3550, a host executable 3570(1), a CUDA device executable 3584, a CPU 3590, and a CUDA-enabled GPU 3594.

[0339] In at least one embodiment and as previously incorporated herein Figure 35A As depicted, CUDA source code 3510 includes, but is not limited to, any number (including zero) of global functions 3512, any number (including zero) of device functions 3514, any number (including zero) of host functions 3516, and any number (including zero) of host / device functions 3518. In at least one embodiment, CUDA source code 3510 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0340] In at least one embodiment, the CUDA to HIP conversion tool 3520 converts the CUDA source code 3510 into HIP source code 3530. In at least one embodiment, the CUDA to HIP conversion tool 3520 converts each kernel call in the CUDA source code 3510 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA source code 3510 into any number of other functionally similar HIP calls.

[0341] In at least one embodiment, the HIP compiler driver 3540 determines that the target device 3546 is CUDA-enabled and generates HIP / NVCC compile commands 3542. In at least one embodiment, the HIP compiler driver 3540 then configures the CUDA compiler 3550 via the HIP / NVCC compile commands 3542 to compile the HIP source code 3530. In at least one embodiment, as part of configuring the CUDA compiler 3550, the HIP compiler driver 3540 provides access to a HIP to CUDA translation header 3552. In at least one embodiment, the HIP to CUDA translation header 3552 translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs into any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, the CUDA compiler 3550 uses the HIP to CUDA translation header 3552 in conjunction with a CUDA runtime library 3554 corresponding to the CUDA runtime API 3502 to generate host executable code 3570(1) and CUDA device executable code 3584. In at least one embodiment, the host executable code 3570(1) and the CUDA device executable code 3584 can then be executed on the CPU 3590 and the CUDA-enabled GPU 3594, respectively. In at least one embodiment, the CUDA device executable code 3584 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3584 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0342] Figure 35C A system 3506 is shown that is configured to compile and execute using a CPU 3590 and a non-CUDA enabled GPU 3592, according to at least one embodiment. Figure 35A CUDA source code 3510. In at least one embodiment, system 3506 includes, but is not limited to, CUDA source code 3510, CUDA to HIP conversion tool 3520, HIP source code 3530, HIP compiler driver 3540, HCC 3560, host executable code 3570(2), HCC device executable code 3582, CPU 3590, and GPU 3592.

[0343] In at least one embodiment, and as previously incorporated herein Figure 35AAs depicted, CUDA source code 3510 includes, but is not limited to, any number (including zero) of global functions 3512, any number (including zero) of device functions 3514, any number (including zero) of host functions 3516, and any number (including zero) of host / device functions 3518. In at least one embodiment, CUDA source code 3510 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0344] In at least one embodiment, the CUDA to HIP conversion tool 3520 converts the CUDA source code 3510 into HIP source code 3530. In at least one embodiment, the CUDA to HIP conversion tool 3520 converts each kernel call in the CUDA source code 3510 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the source code 3510 into any number of other functionally similar HIP calls.

[0345] In at least one embodiment, the HIP compiler driver 3540 then determines that the target device 3546 is not CUDA-enabled and generates HIP / HCC compile commands 3544. In at least one embodiment, the HIP compiler driver 3540 then configures the HCC 3560 to execute the HIP / HCC compile commands 3544, thereby compiling the HIP source code 3530. In at least one embodiment, the HIP / HCC compile commands 3544 configure the HCC 3560 to use, but are not limited to, a HIP / HCC runtime library 3558 and an HCC header 3556 to generate a host executable code 3570(2) and an HCC device executable code 3582. In at least one embodiment, the HIP / HCC runtime library 3558 corresponds to the HIP runtime API 3532. In at least one embodiment, the HCC header 3556 includes, but is not limited to, any number and type of interoperability mechanisms for the HIP and HCC. In at least one embodiment, host executable code 3570(2) and HCC device executable code 3582 may execute on CPU 3590 and GPU 3592, respectively.

[0346] Figure 36 According to at least one embodiment, Figure 35C35. In at least one embodiment, the CUDA source code 3510 divides the overall problem that a given kernel is designed to solve into relatively coarse-grained sub-problems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, but is not limited to, an arbitrary number of threads. In at least one embodiment, each sub-problem is divided into relatively small pieces that can be solved in parallel by the threads in the thread block in a cooperative manner. In at least one embodiment, threads within a thread block can collaborate by sharing data through shared memory and by synchronizing execution to coordinate memory access.

[0347] In at least one embodiment, the CUDA source code 3510 organizes the thread blocks associated with a given kernel into a one-dimensional, two-dimensional, or three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes, but is not limited to, any number of threads, and the grid includes, but is not limited to, any number of thread blocks.

[0348] In at least one embodiment, a kernel is a function in device code that is defined using the "__global__" declaration specifier. In at least one embodiment, the CUDA kernel launch syntax 3610 is used to specify the size of the grid on which the kernel is executed and the associated streams for a given kernel call. In at least one embodiment, the CUDA kernel launch syntax 3610 is specified as "KernelName<<<GridSize,BlockSize,SharedMemorySize,Stream> >>(KernelArguments);". In at least one embodiment, the execution configuration syntax is a "<<< ... >>>" construct that is inserted between the kernel name ("KernelName") and the bracketed list of kernel arguments ("KernelArguments"). In at least one embodiment, the CUDA kernel launch syntax 3610 includes, but is not limited to, CUDA launch function syntax rather than execution configuration syntax.

[0349] In at least one embodiment, "GridSize" is of type dim3 and specifies the dimensions and size of the grid. In at least one embodiment, type dim3 is a CUDA-defined structure that includes, but is not limited to, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, z defaults to 1. In at least one embodiment, if y is not specified, y defaults to 1. In at least one embodiment, the number of thread blocks in the grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, "BlockSize" is of type dim3 and specifies the dimensions and size of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread executing the kernel is given a unique thread ID that can be accessed within the kernel via a built-in variable (e.g., "threadIdx").

[0350] In at least one embodiment, with respect to CUDA kernel launch syntax 3610, "SharedMemorySize" is an optional parameter that specifies the number of bytes in shared memory that are dynamically allocated for each thread block for a given kernel call, in addition to statically allocated memory. In at least one embodiment and with respect to CUDA kernel launch syntax 3610, SharedMemorySize defaults to zero. In at least one embodiment and with respect to CUDA kernel launch syntax 3610, "stream" is an optional parameter that specifies the associated stream and defaults to zero to specify the default stream. In at least one embodiment, a stream is a sequence of commands that are executed in order (which may be issued by different host threads). In at least one embodiment, different streams may execute commands out of order or concurrently with respect to each other.

[0351] In at least one embodiment, the CUDA source code 3510 includes, but is not limited to, a kernel definition and a main function for an exemplary kernel "MatAdd". In at least one embodiment, the main function is host code executed on the host and includes, but is not limited to, a kernel call that causes the kernel MatAdd to be executed on the device. In at least one embodiment, as shown, the kernel MatAdd adds two matrices A and B of size NxN, where N is a positive integer, and stores the result in a matrix C. In at least one embodiment, the main function defines the threadsPerBlock variable as 16x16 and the numBlocks variable as N / 16 x N / 16. In at least one embodiment, the main function then specifies the kernel call "MatAdd<<<numBlocks,threadsPerBlock> >>(A, B, C);". In at least one embodiment, and in accordance with CUDA kernel launch syntax 3610, kernel MatAdd is executed using a grid of thread blocks of size N / 16×N / 16, where each thread block has a size of 16×16. In at least one embodiment, each thread block includes 256 threads, a grid is created with enough blocks to have one thread per matrix element, and each thread in the grid executes kernel MatAdd to perform one pairwise addition.

[0352] In at least one embodiment, while converting CUDA source code 3510 to HIP source code 3530, CUDA-to-HIP conversion tool 3520 converts each kernel call in CUDA source code 3510 from CUDA kernel launch syntax 3610 to HIP kernel launch syntax 3620, and converts any number of other CUDA calls in source code 3510 to any number of other functionally similar HIP calls. In at least one embodiment, HIP kernel launch syntax 3620 is specified as "hipLaunchKernelGGL(KernelName, GridSize, BlockSize, SharedMemorySize, Stream, KernelArguments);". In at least one embodiment, each of KernelName, GridSize, BlockSize, SharedMemorySize, Stream, and KernelArguments has the same meaning in HIP kernel launch syntax 3620 as in CUDA kernel launch syntax 3610 (described previously herein). In at least one embodiment, the parameters SharedMemorySize and Stream are required in the HIP kernel launch syntax 3620 and optional in the CUDA kernel launch syntax 3610.

[0353] In at least one embodiment, in addition to the kernel call to cause the kernel MatAdd to execute on the device, Figure 36 A portion of the HIP source code 3530 depicted in Figure 36 3510 is identical to a portion of the CUDA source code 3510 depicted in FIG. In at least one embodiment, kernel MatAdd is defined in HIP source code 3530 with the same “__global__” declaration specifier as kernel MatAdd is defined in CUDA source code 3510. In at least one embodiment, the kernel call in HIP source code 3530 is “hipLaunchKernelGGL(MatAdd, numBlocks, threadsPerBlock, 0, 0, A, B, C);”, while the corresponding kernel call in CUDA source code 3510 is “MatAdd<<<numBlocks,threadsPerBlock> >>(A, B, C);".

[0354] Figure 37 More details are shown according to at least one embodiment. Figure 35C 35. In at least one embodiment, the GPU 3592 is a non-CUDA-enabled GPU 3592. In at least one embodiment, the GPU 3592 is developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the GPU 3592 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, the GPU 3592 is configured to perform graphics pipeline operations, such as draw commands, pixel operations, geometry calculations, and other operations associated with rendering an image to a display. In at least one embodiment, the GPU 3592 is configured to perform operations unrelated to graphics. In at least one embodiment, the GPU 3592 is configured to perform both graphics-related operations and operations unrelated to graphics. In at least one embodiment, the GPU 3592 can be configured to execute device code included in the HIP source code 3530.

[0355] In at least one embodiment, the GPU 3592 includes, but is not limited to, any number of programmable processing units 3720, a command processor 3710, an L2 cache 3722, a memory controller 3770, a DMA engine 3780(1), a system memory controller 3782, a DMA engine 3780(2), and a GPU controller 3784. In at least one embodiment, each programmable processing unit 3720 includes, but is not limited to, a workload manager 3730 and any number of compute units 3740. In at least one embodiment, the command processor 3710 reads commands from one or more command queues (not shown) and dispatches the commands to the workload manager 3730. In at least one embodiment, for each programmable processing unit 3720, the associated workload manager 3730 dispatches work to the compute units 3740 included in the programmable processing unit 3720. In at least one embodiment, each compute unit 3740 can execute any number of thread blocks, but each thread block executes on a single compute unit 3740. In at least one embodiment, a work group is a thread block.

[0356] In at least one embodiment, each compute unit 3740 includes, but is not limited to, any number of SIMD units 3750 and shared memory 3760. In at least one embodiment, each SIMD unit 3750 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each SIMD unit 3750 includes, but is not limited to, a vector ALU 3752 and a vector register file 3754. In at least one embodiment, each SIMD unit 3750 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, prediction can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 3760.

[0357] In at least one embodiment, programmable processing units 3720 are referred to as "shader engines." In at least one embodiment, each programmable processing unit 3720 includes, but is not limited to, any number of specialized graphics hardware in addition to compute units 3740. In at least one embodiment, each programmable processing unit 3720 includes, but is not limited to, any number (including zero) of geometry processors, any number (including zero) of rasterizers, any number (including zero) of rendering backends, a workload manager 3730, and any number of compute units 3740.

[0358] In at least one embodiment, the compute units 3740 share an L2 cache 3722. In at least one embodiment, the L2 cache 3722 is partitioned. In at least one embodiment, all compute units 3740 in a GPU 3592 can access GPU memory 3790. In at least one embodiment, a memory controller 3770 and a system memory controller 3782 facilitate data transfers between the GPU 3592 and a host, and a DMA engine 3780(1) enables asynchronous memory transfers between the GPU 3592 and the host. In at least one embodiment, a memory controller 3770 and a GPU controller 3784 facilitate data transfers between a GPU 3592 and other GPUs 3592, and a DMA engine 3780(2) enables asynchronous memory transfers between a GPU 3592 and other GPUs 3592.

[0359] In at least one embodiment, the GPU 3592 includes, but is not limited to, any number and type of system interconnects that facilitate data and control transfers between any number and type of directly or indirectly linked components within or external to the GPU 3592. In at least one embodiment, the GPU 3592 includes, but is not limited to, any number and type of I / O interfaces (e.g., PCIe) coupled to any number and type of peripheral devices. In at least one embodiment, the GPU 3592 may include, but is not limited to, any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, the GPU 3592 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers (e.g., memory controller 3770 and system memory controller 3782) and memory devices (e.g., shared memory 3760) that are dedicated to a component or shared between multiple components. In at least one embodiment, GPU3592 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 3722), each of which can be private or shared among any number of components (e.g., SIMD units 3750, compute units 3740, and programmable processing units 3720).

[0360] Figure 38 shows how threads of an exemplary CUDA grid 3820 are mapped to Figure 373740. In at least one embodiment, and for illustration purposes only, the grid 3820 has a GridSize of BX times BY times 1 and a BlockSize of TX times TY times 1. Thus, in at least one embodiment, the grid 3820 includes, but is not limited to, (BX*BY) thread blocks 3830, and each thread block 3830 includes, but is not limited to, (TX*TY) threads 3840. Threads 3840 are Figure 38 Depicted as a curved arrow.

[0361] In at least one embodiment, the grid 3820 is mapped to programmable processing units 3720(1), which include, but are not limited to, compute units 3740(1)-3740(C). In at least one embodiment and as shown, the (BJ*BY) thread blocks 3830 are mapped to compute unit 3740(1), and the remaining thread blocks 3830 are mapped to compute unit 3740(2). In at least one embodiment, each thread block 3830 may include, but are not limited to, any number of warps, and each warp is mapped to Figure 37 3750 of different SIMD units.

[0362] In at least one embodiment, the warps in a given thread block 3830 may synchronize together and communicate via shared memory 3760 included in the associated compute unit 3740. For example, and in at least one embodiment, the warps in thread block 3830(BJ, 1) may synchronize together and communicate via shared memory 3760(1). For example, and in at least one embodiment, the warps in thread block 3830(BJ+1, 1) may synchronize together and communicate via shared memory 3760(2).

[0363] Figure 39The present invention illustrates how to migrate existing CUDA code to data parallel C++ code according to at least one embodiment. Data Parallel C++ (DPC++) may refer to an open, standards-based alternative to single-architecture proprietary languages that allows developers to reuse code across hardware targets (CPUs and accelerators such as GPUs and FPGAs) and also perform custom tuning for specific accelerators. DPC++ uses similar and / or identical C and C++ constructs to ISO C++ that developers may be familiar with. DPC++ incorporates the Khronos Group's standard SYCL to support data parallelism and heterogeneous programming. SYCL refers to a cross-platform abstraction layer that builds on the underlying concepts, portability, and efficiency of OpenCL, which enables code for heterogeneous processors to be written in a "single-source" style using standard C++. SYCL enables single-source development, where C++ template functions can contain both host code and device code to build complex algorithms accelerated using OpenCL, and then reuse them throughout the source code for different types of data.

[0364] In at least one embodiment, a DPC++ compiler is used to compile DPC++ source code that can be deployed across various hardware targets. In at least one embodiment, the DPC++ compiler is used to generate DPC++ applications that can be deployed across various hardware targets, and the DPC++ compatibility tool can be used to migrate CUDA applications to multi-platform programs in DPC++. In at least one embodiment, the DPC++ base toolkit includes: a DPC++ compiler for deploying applications across various hardware targets; a DPC++ library for improving productivity and performance on CPUs, GPUs, and FPGAs; a DPC++ compatibility tool for migrating CUDA applications to multi-platform applications; and any suitable combination thereof.

[0365] In at least one embodiment, the DPC++ programming model is used to simplify one or more aspects related to programming CPUs and accelerators by using modern C++ features to express parallelism with a programming language called Data Parallel C++. The DPC++ programming language can be used to reuse code for hosts (e.g., CPUs) and accelerators (e.g., GPUs or FPGAs) using a single source language and clearly communicate execution and memory dependencies. Mappings within the DPC++ code can be used to convert an application to run on the hardware or set of hardware devices that best accelerate the workload. The host can also be used to simplify the development and debugging of device code even on platforms without available accelerators.

[0366] In at least one embodiment, CUDA source code 3900 is provided as input to a DPC++ compatibility tool 3902 to generate human-readable DPC++ 3904. In at least one embodiment, human-readable DPC++ 3904 includes inline comments generated by the DPC++ compatibility tool 3902 that guide the developer on how and / or where to modify the DPC++ code to complete the coding and tuning to the desired performance 3906, thereby generating DPC++ source code 3908.

[0367] In at least one embodiment, the CUDA source code 3900 is or includes a collection of human-readable source code in the CUDA programming language. In at least one embodiment, the CUDA source code 3900 is human-readable source code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language that includes, but is not limited to, mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, device code is source code that, after compilation, is executable on a device (e.g., a GPU or FPGA) and may include one or more parallelizable workflows that are executable on one or more processor cores of the device. In at least one embodiment, the device may be a processor that is optimized for parallel instruction processing, such as a CUDA-enabled GPU, a GPU, or another GPGPU, among others. In at least one embodiment, host code is source code that, after compilation, is executable on a host. In at least one embodiment, some or all of the host code and device code may be executed in parallel across a CPU and a GPU / FPGA. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU. In conjunction Figure 39 The CUDA source code 3900 described may be consistent with that discussed elsewhere in this document.

[0368] In at least one embodiment, DPC++ compatibility tool 3902 refers to an executable tool, program, application, or any other suitable type of tool for facilitating the migration of CUDA source code 3900 to DPC++ source code 3908. In at least one embodiment, DPC++ compatibility tool 3902 is a command-line-based code migration tool that can be used as part of the DPC++ toolkit for porting existing CUDA source code to DPC++. In at least one embodiment, DPC++ compatibility tool 3902 converts some or all of a CUDA application's source code from CUDA to DPC++ and generates a resulting file written at least partially in DPC++, referred to as human-readable DPC++ 3904. In at least one embodiment, human-readable DPC++ 3904 includes comments generated by DPC++ compatibility tool 3902 to indicate where user intervention may be required. In at least one embodiment, user intervention is necessary when CUDA source code 3900 calls a CUDA API for which there is no equivalent DPC++ API; other examples of requiring user intervention are discussed in more detail below.

[0369] In at least one embodiment, a workflow for migrating CUDA source code 3900 (e.g., an application or portion thereof) includes creating one or more compilation database files; migrating CUDA to DPC++ using the DPC++ compatibility tool 3902; completing the migration and verifying correctness to generate DPC++ source code 3908; and compiling the DPC++ source code 3908 using the DPC++ compiler to generate a DPC++ application. In at least one embodiment, the compatibility tool provides a utility that intercepts commands used during Makefile execution and stores them in the compilation database file. In at least one embodiment, the file is stored in JSON format. In at least one embodiment, the interception of build commands converts Makefile commands into DPC++ compatibility commands.

[0370] In at least one embodiment, intercept-build is a utility script that intercepts the build process to capture compile options, macro definitions, and include paths, and writes that data to a compile database file. In at least one embodiment, the compile database file is a JSON file. In at least one embodiment, the DPC++ compatibility tool 3902 parses the compile database and applies options when migrating input sources. In at least one embodiment, the use of intercept-build is optional but highly recommended for Make or CMake-based environments. In at least one embodiment, the migration database includes commands, directories, and files: commands may include necessary compile flags; directories may include paths to header files; and files may include paths to CUDA files.

[0371] In at least one embodiment, DPC++ compatibility tool 3902 migrates CUDA code (e.g., applications) written in CUDA to DPC++ by generating DPC++ whenever possible. In at least one embodiment, DPC++ compatibility tool 3902 is available as part of a toolkit. In at least one embodiment, the DPC++ toolkit includes an intercept-build tool. In at least one embodiment, the intercept-build tool creates a compilation database that captures compilation commands to migrate CUDA files. In at least one embodiment, DPC++ compatibility tool 3902 uses the compilation database generated by the intercept-build tool to migrate CUDA code to DPC++. In at least one embodiment, non-CUDA C++ code and files are migrated intact. In at least one embodiment, DPC++ compatibility tool 3902 generates human-readable DPC++ 3904, which may be DPC++ code, as generated by DPC++ compatibility tool 3902, that cannot be compiled by the DPC++ compiler and requires additional pipeline to verify the incorrectly migrated code portions, and may involve manual intervention, such as intervention by the developer. In at least one embodiment, DPC++ compatibility tool 3902 provides hints or tools embedded in the code to help developers manually migrate additional code that cannot be automatically migrated.In at least one embodiment, migration is a one-time activity for a source file, project, or application.

[0372] In at least one embodiment, DPC++ compatibility tool 39002 is capable of successfully migrating all portions of CUDA code to DPC++, and there may simply be an optional step for manually verifying and tuning the performance of the generated DPC++ source code. In at least one embodiment, DPC++ compatibility tool 3902 directly generates DPC++ source code 3908 that is compiled by the DPC++ compiler, without requiring or utilizing manual intervention to modify the DPC++ code generated by DPC++ compatibility tool 3902. In at least one embodiment, DPC++ compatibility tool generates compilable DPC++ code that developers can selectively tune based on performance, readability, maintainability, and various other considerations, or any combination thereof.

[0373] In at least one embodiment, one or more CUDA source files are migrated to DPC++ source files using, at least in part, the DPC++ compatibility tool 3902. In at least one embodiment, the CUDA source code includes one or more header files, which may include CUDA header files. In at least one embodiment, the CUDA source file includes a header file that can be used to print text.<cuda.h> header files and<stdio.h> In at least one embodiment, a portion of a vector addition kernel CUDA source file may be written as or related to:

[0374]

[0375]

[0376] In at least one embodiment, and in conjunction with the CUDA source files presented above, DPC++ compatibility tool 3902 parses the CUDA source code and replaces the header files with the appropriate DPC++ and SYCL header files. In at least one embodiment, the DPC++ header files include helper declarations. In CUDA, there is the concept of a thread ID, and correspondingly, in DPC++ or SYCL, there is a local identifier for each element.

[0377] In at least one embodiment, and in relation to the CUDA source file presented above, there are two vectors A and B that are initialized and the result of the vector addition is placed into vector C as part of VectorAddKernel(). In at least one embodiment, as part of migrating the CUDA code to DPC++ code, the DPC++ compatibility tool 3902 converts the CUDA thread ID used to index the work elements to the SYCL standard addressing of the work elements via the local ID. In at least one embodiment, the DPC++ code generated by the DPC++ compatibility tool 3902 can be optimized—for example, by reducing the dimensionality of nd_item, thereby increasing memory and / or processor utilization.

[0378] In at least one embodiment and in conjunction with the CUDA source files presented above, memory allocation is migrated. In at least one embodiment, cudaMalloc() is migrated to a unified shared memory SYCL call malloc_device() to which the device and context are passed, relying on SYCL concepts such as platform, device, context, and queue. In at least one embodiment, a SYCL platform can have multiple devices (e.g., host and GPU devices); a device can have multiple queues to which jobs can be submitted; each device can have a context; and a context can have multiple devices and manage shared memory objects.

[0379] In at least one embodiment and in conjunction with the CUDA source file presented above, the main() function invokes or calls VectorAddKernel() to add two vectors A and B and store the result in vector C. In at least one embodiment, the CUDA code that calls VectorAddKernel() is replaced by DPC++ code to submit the kernel to the command queue for execution. In at least one embodiment, the command group handler cgh passes data, synchronization, and computations submitted to the queue, and parallel_for is called for multiple global elements and multiple work items in the work group that called VectorAddKernel().

[0380] In at least one embodiment and in conjunction with the CUDA source files presented above, the CUDA calls that copy device memory and then free memory for vectors A, B, and C are migrated to corresponding DPC++ calls. In at least one embodiment, the C++ code (e.g., standard ISO C++ code for printing a vector of floating-point variables) is migrated intact without modification by the DPC++ compatibility tool 3902. In at least one embodiment, the DPC++ compatibility tool 3902 modifies the CUDA API for memory setup and / or host calls to execute the kernel on the acceleration device. In at least one embodiment and in conjunction with the CUDA source files presented above, the corresponding human-readable DPC++ 3904 (e.g., compilable) is written as or in association with:

[0381]

[0382]

[0383] In at least one embodiment, human-readable DPC++ 3904 refers to the output generated by DPC++ compatibility tool 3902 and can be optimized in one way or another. In at least one embodiment, the human-readable DPC++ 3904 generated by DPC++ compatibility tool 3902 can be manually edited by the developer after migration to make it easier to maintain, for performance, or for other reasons. In at least one embodiment, the DPC++ code generated by DPC++ compatibility tool 39002 (e.g., the public DPC++) can be optimized by removing duplicate calls to get_current_device() and / or get_default_context() for each malloc_device() call. In at least one embodiment, the DPC++ code generated above uses a three-dimensional nd_range, which can be refactored to use only a single dimension, thereby reducing memory usage. In at least one embodiment, the developer can manually edit the DPC++ code generated by DPC++ compatibility tool 3902 to replace the use of unified shared memory with accessors. In at least one embodiment, DPC++ compatibility tool 3902 has the option to change how it migrates CUDA code to DPC++ code. In at least one embodiment, DPC++ compatibility tool 3902 is verbose because it uses generic templates to migrate CUDA code to DPC++ code, which is applicable to a large number of cases.

[0384] In at least one embodiment, the CUDA to DPC++ migration workflow includes the following steps: preparing for migration using an intercept-build script; performing the migration of the CUDA project to DPC++ using the DPC++ compatibility tool 3902; manually reviewing and editing the migrated source files to ensure their completeness and correctness; and compiling the final DPC++ code to generate a DPC++ application. In at least one embodiment, manual review of the DPC++ source code may be required in one or more scenarios, including but not limited to: the migrated API does not return an error code (CUDA code can return an error code that can later be used by the application, but SYCL uses exceptions to report errors, so the error code is not exposed); DPC++ does not support CUDA compute capability-related logic; statements cannot be deleted. In at least one embodiment, scenarios where manual intervention is required in the DPC++ code may include but are not limited to: error code logic is replaced with (*,0) code or commented out; equivalent DPC++ APIs are unavailable; CUDA compute capability-related logic; hardware-related APIs (clock()); missing APIs with unsupported features; execution time measurement logic; handling built-in vector type conflicts; migration of the cuBLAS API; and more.

[0385] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described above in detail. However, it should be understood that there is no intention to limit the disclosure to one or more specific forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the present disclosure as defined by the appended claims.

[0386] Unless otherwise noted or clearly contradicted by the context, the use of the terms "a" and "an" and "the" and similar references in the context of describing the disclosed embodiments (particularly in the context of the appended claims) should be interpreted as covering the singular and plural, rather than as definitions of terms. Unless otherwise noted, the terms "include," "have," "include," and "contain" should be interpreted as open-ended terms (meaning "including but not limited to"). The term "connected" (when unmodified, refers to a physical connection) should be interpreted as partially or completely contained within, attached to, or connected together, even if there is some intervention. Unless otherwise noted herein, references to numerical ranges herein are intended only to be used as a shorthand method of referring to each individual value falling within the range, and each individual value is incorporated into the specification as if it were separately recited herein. Unless otherwise noted or contradicted by the context, the use of the term "set" (e.g., "item set") or "subset" should be interpreted as a non-empty set comprising one or more members. Furthermore, unless otherwise indicated or contradicted by context, the term "subset" of a corresponding set does not necessarily mean a proper subset of the corresponding set, but rather a subset and a corresponding set may be equivalent.

[0387] Unless expressly indicated otherwise or clearly contradicted by context, conjunctions such as phrases of the form "at least one of A, B, and C" or "at least one of A, B, and C" are understood in context to generally refer to an item, clause, or the like that may be A or B or C, or any non-empty subset of the set A, B, and C. For example, in the illustrative example of a set having three members, the conjunctions "at least one of A, B, and C" and "at least one of A, B, and C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctions are not generally intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C. Additionally, unless expressly indicated otherwise or contradicted by context, the term "plurality" refers to plurality (e.g., "a plurality of items" means a plurality of items). The number of items in a plurality of items is at least two, but may be more if expressly indicated or indicated by context. Further, unless stated otherwise or clear from context, the phrase "based on" means "based at least in part on" rather than "based solely on."

[0388] Unless otherwise indicated herein or clearly contradicted by the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are performed under the control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that are collectively executed on one or more processors by hardware or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of, for example, a computer program that includes a plurality of instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transient signals (e.g., propagated transient electrical or electromagnetic transmissions) but includes non-transitory data storage circuits (e.g., buffers, caches, and queues). In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) having executable instructions stored thereon, which, when executed by one or more processors of a computer system (i.e., as a result of being executed), causes the computer system to perform the operations described herein. In at least one embodiment, the set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media in the plurality of non-transitory computer-readable storage media lacks all of the code, but rather the plurality of non-transitory computer-readable storage media collectively store all of the code. In at least one embodiment, the executable instructions are executed so that different instructions are executed by different processors, for example, a non-transitory computer-readable storage medium stores instructions, and a main central processing unit ("CPU") executes some instructions, while a graphics processing unit ("GPU") executes other instructions. In at least one embodiment, different components of the computer system have separate processors, and different processors execute different subsets of instructions.

[0389] Thus, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such a computer system is configured with applicable hardware and / or software that enables the implementation of the operations. Furthermore, the computer system implementing at least one embodiment of the present disclosure is a single device, and in another embodiment is a distributed computer system comprising multiple devices operating in different ways such that the distributed computer system performs the operations described herein and such that no single device performs all of the operations.

[0390] The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended merely to better illuminate embodiments of the present disclosure and does not limit the scope of the disclosure unless otherwise required. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

[0391] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0392] In the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms may not be intended as synonyms for each other. Rather, in specific examples, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0393] Unless expressly stated otherwise, it is understood that throughout this specification, terms such as “process,” “calculate,” “compute,” “determine,” etc., refer to the actions and / or processes of a computer or computing system or similar electronic computing device that processes and / or converts data represented as physical quantities (e.g., electronic) in the registers and / or memories of the computing system into other data similarly represented as physical quantities in the memories, registers, or other such information storage, transmission, or display devices of the computing system.

[0394] In a similar manner, the term "processor" may refer to any device or portion of a memory that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. As non-limiting examples, a "processor" may be a CPU or a GPU. A "computing platform" may include one or more processors. As used herein, a "software" process may include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Likewise, each process may refer to multiple processes to execute instructions continuously or intermittently, sequentially, or in parallel. The terms "system" and "method" may be used interchangeably herein, as long as a system may embody one or more methods, and a method may be considered a system.

[0395] In this document, reference may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, computer system, or computer-implemented machine. The process of obtaining, acquiring, receiving, or inputting analog and digital data can be accomplished in a variety of ways, such as by receiving data as parameters of a function call or a call to an application programming interface. In some implementations, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data via a serial or parallel interface. In another implementation, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. Reference may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by transmitting the data as input or output parameters of a function call, an application programming interface, or an interprocess communication mechanism.

[0396] Although the above discussion sets forth example implementations of the described technology, other architectures may be used to implement the described functionality and are intended to fall within the scope of this disclosure. In addition, although specific responsibilities are defined above for discussion purposes, the various functions and responsibilities may be allocated and divided in different ways depending on the circumstances.

[0397] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims.

Claims

1. A processor, comprising: One or more circuits for: For a current frame, tracking a path of one or more particles in the scene based at least in part on the information indicated in the task buffer; storing position information about the one or more particles in a feedback buffer and a photon buffer; determining occupancy information to apply to a texture stored in a caustic buffer based at least in part on the photon buffer; applying the texture in the caustic buffer to the scene; as well as The information in the task buffer is updated based at least in part on the position information in the feedback buffer. 2 . The processor of claim 1 , wherein the position information comprises one or more position values and one or more intensity values associated with each of the one or more particles projected into the scene.

3. The processor of claim 1 , wherein the occupancy information applied to the texture in the caustic buffer is determined by combining, for each of a plurality of data items in the photon buffer, the position information with one or more intensity values determined by projecting the one or more particles into the scene.

4. The processor of claim 1 , wherein the information in the task buffer is updated with the position information of the feedback buffer by combining position information from a second feedback buffer for a second frame with the position information of the feedback buffer for the frame.

5. A system comprising: one or more processors; a memory storing computer-executable instructions that, if executed, cause the one or more processors to: calculating projection information based at least in part on the particle information in the first buffer; storing position information calculated as a result of the interaction of the projection information with one or more objects in the scene in a second buffer and a third buffer; storing occupancy information applied to the texture in a fourth buffer, the occupancy information calculated at least in part based on the position information of the third buffer; applying the texture stored in the fourth buffer to the scene; as well as The particle information of the first buffer is updated based at least in part on the position information of the second buffer. The system of claim 5 , wherein the projection information indicates location and intensity. 7 . The system of claim 5 , wherein the position information is calculated by determining, for one or more pixels in the scene, one or more particles interacting with the one or more objects and hitting each of the one or more pixels.

8. The system of claim 5, wherein the occupancy information applied to the texture is calculated, for each of a plurality of entries in the third buffer, using a position value of the entry from the position information and an intensity value of the entry from the projection information. 9 . The system of claim 5 , wherein the particle information of the first buffer is updated by combining the position information of the second buffer with position information of a fifth buffer.

10. A machine-readable medium having stored thereon a set of instructions that, if executed by one or more processors, cause the one or more processors to at least: determining one or more projection paths in the scene corresponding to the particle information stored in the first buffer; calculating position information to be stored in a second buffer and a third buffer as a result of the one or more projection paths interacting with one or more objects in the scene; calculating occupancy information to be applied to a texture stored in a fourth buffer based at least in part on the position information of the third buffer; as well as The particle information of the first buffer is updated based at least in part on the position information of the second buffer.

11. The machine-readable medium of claim 10, wherein the instructions further comprise instructions that, as a result of execution by the one or more processors, cause the occupancy information to be calculated by multiplying the position information with intensity information determined as a result of the one or more projection paths.

12. The machine-readable medium of claim 10 , wherein the instructions causing the one or more processors to update the particle information in the first buffer further comprise instructions that, as a result of being executed, cause the one or more processors to: The position information is combined with one or more past position information data to calculate one or more projected position data, and the particle information of the first buffer is updated with the one or more projected position data.

13. The machine-readable medium of claim 10 , wherein the instructions further comprise instructions that, as a result of execution by the one or more processors, cause the occupancy information to be applied to the texture stored in the fourth buffer and cause the texture stored in the fourth buffer to be applied to the scene.

14. The machine-readable medium of claim 10, wherein the instructions that cause the one or more processors to calculate the occupancy information further comprise instructions that, as a result of being executed, cause the one or more processors to: creating two or more covariance matrices corresponding to direction information and position information from the particle information as a result of the one or more projection paths originating from the area light; and The occupancy information is calculated based at least in part on a combination of the two or more covariance matrices.

15. A method comprising: calculating a projected path of one or more light particles in the scene based at least in part on the first particle information; As a result of the interaction of the projection path with one or more objects in the scene: calculating second particle information indicating occupancy of each of the one or more light particles; generating a caustic effect including one or more light ray occupancy corresponding to the one or more light particles; applying the caustic effect to the image; and The first particle information is updated based at least in part on the second particle information. 16 . The method of claim 15 , wherein the first particle information comprises one or more data values corresponding to a position and an intensity of each of the one or more light particles.

17. The method of claim 15 , wherein the occupancy of each of the one or more light particles is calculated at least in part based on a position value associated with each of the one or more light particles and an intensity value associated with each of the one or more light particles, the position value and the intensity value being determined as a result of the projection path interacting with the one or more objects in the scene.

18. The method of claim 15, wherein the first particle information is updated based at least in part on a current position value and one or more previous position values determined as a result of the projected path interacting with the one or more objects.

19. The method of claim 15, wherein the second particle information is applied to a texture based at least in part on the occupancy of each of the one or more light particles, and the texture is applied to the scene.

20. The method of claim 15, wherein as a result of the one or more light particles originating from an area light source, the second particle information is calculated by: creating two or more covariance matrices corresponding to direction information and position information from the first particle information; and The occupancy is calculated based at least in part on a combination of the two or more covariance matrices.

Images